Sub-EUV patterning of heater for Burr Mushroom Cell PCM

Abstract

A phase change material (PCM) memory cell includes a sub-EUV metallic heater element. The PCM memory cell includes a bottom electrode made of a metal-containing material; a memory cell structure including a phase change material; and a sub-extreme ultraviolet (sub-EUV) metallic heater element positioned between the bottom electrode and the PCM memory cell structure and electrically connecting the bottom electrode and the PCM memory cell structure. The metallic heater element is formed in a sub-EUV circular via structure and includes a seamless metal nitride fill material. The sub-extreme ultraviolet (sub-EUV) circular via structure further includes a sub-EUV metal nitride liner, the sub-EUV metal nitride liner having a thick bottom portion and thin sidewall portions. The thick bottom portion of the metal nitride liner improves thermal insulation, resulting in high-resistance / low-power switching and reduced amorphous phase change material volume.

Description

[Background technology]

[0001] The present disclosure relates to mushroom cell phase change devices, and more particularly to an integration and patterning approach that enables metallization of sub-EUV bottom electrode heaters for use with mushroom cell phase change devices.

[0002] Even with the advent of extreme ultraviolet (EUV) lithography, which enables print resolution of sub-40 nm pitch, the lack of robustness of organic materials and integration schemes means that pattern transfer is accompanied by mask erosion, leading to pattern collapse and line edge roughness defects.

[0003] In mushroom cell phase-change devices, the "mushroom size" (and therefore the energy required for switching) is determined by the bottom electrode (heater) area. Various sublithographic techniques have been proposed for heater definition, including the sidewall spacer approach, the use of carbon nanotubes as heaters, and the formation of nanoscale conductive filaments in the oxide layer above the heater by dielectric breakdown (oxide breakdown).

[0004] EUV limitations hinder the efficient scaling of ultra-small heater dimensions, necessitating multi-layer ALD / CVD deposition to produce thin heater filaments. Summary of the Invention

[0005] In one aspect, an integration and semiconductor device patterning approach is provided that allows sub-EUV bottom electrode heaters to be metallized exclusively with CVD metals and metal nitrides, resulting in high resistance / low power switching and reduced amorphous volume.

[0006] A further embodiment provides a multi-mushroom crossbar-like array, enabled by sub-EUV heaters.

[0007] By minimizing the heater dimensions, the amorphous switching volume of the PCM cell is minimized, and the reduced contact area more effectively reduces the programming current of the PCM cell, thus providing the GST volume of the PCM cell free from damage, resulting in reduced current draw (lower power) and improved device density.

[0008] According to a first embodiment, a phase change material (PCM) memory cell is provided, comprising: a bottom electrode made of a metal-containing material; a memory cell structure including a phase change material; and a sub-extreme ultraviolet (sub-EUV) metallic heater element having a sub-EUV circular via structure including a seamless fill material, the sub-EUV metallic heater element being located between and electrically connecting the bottom electrode and the PCM memory cell structure.

[0009] In one embodiment, the seamless filler material comprises a metal nitride filler material.

[0010] In one embodiment, the sub-extreme ultraviolet (sub-EUV) circular via structure further comprises a sub-EUV metal nitride liner.

[0011] In one embodiment, the sub-EUV metal nitride liner has a thick bottom portion and a thin sidewall portion. The thick bottom portion of the metal nitride liner provides better heat rejection and improved thermal insulation. Furthermore, the sub-EUV metal heater element with a circular via structure provides high resistance / low power switching and reduced amorphous phase change material volume.

[0012] In one embodiment, a metallic heater element having a circular via structure with sub-EUV dimensions has an outer metal nitride liner of a first metal nitride material and an inner metal nitride filament layer of a second metal nitride material.

[0013] According to a further embodiment, a phase change material (PCM) memory cell array is provided, the PCM memory cell array comprising: a first insulating material layer having a plurality of bottom electrodes made of a metal-containing material; a plurality of memory cell structures made of a phase change material; and a plurality of sub-extreme ultraviolet (sub-EUV) metallic heater elements, each having a sub-EUV circular via structure containing a seamless fill material, each positioned between and electrically connecting a respective bottom electrode and a respective PCM memory cell structure.

[0014] In a PCM memory cell array, the seamless fill material includes a metal nitride fill material.

[0015] In a further embodiment, the metallic heater element having a circular via structure with sub-extreme ultraviolet (sub-EUV) dimensions further includes a metal nitride liner with sub-EUV dimensions. The sub-EUV metal nitride liner has a thick bottom portion and a thin sidewall portion. The thick bottom portion of the metal nitride liner provides better heat rejection and improved thermal insulation. The metallic heater element with a circular via structure with sub-EUV dimensions provides high resistance / low power switching and a reduced volume of amorphous phase change material.

[0016] In a further embodiment, each metallic heater element having a circular via structure with sub-EUV dimensions includes an outer metal nitride liner of a first metal nitride material and an inner metal nitride filament layer of a second metal nitride material.

[0017] According to one aspect of the present disclosure, a method for forming a phase change material (PCM) memory cell is provided. The method includes an integrated multi-step approach, including at least one tapered reactive ion etching (RIE) process, which provides a topological profile and aspect ratio of an insulating layer that allows for filling of a metal material into a circular via at sub-EUV dimensions with minimal or no voids / gaps / seams at sub-EUV dimensions, resulting in a unique structure. [Brief explanation of the drawings]

[0018] [Figure 1] 1A-1G illustrate one embodiment of a method for fabricating a PCM memory cell device to create sub-EUV via features in accordance with one aspect of the present disclosure.

[0019] [Figure 2] 2A-2C illustrate alternative embodiments of steps in a method for fabricating a PCM memory device to create sub-EUV via features according to further aspects of the present disclosure.

[0020] [Figure 3] 1 illustrates a memory cell structure having a bottom heater electrode structure formed in accordance with embodiments described herein.

[0021] [Figure 4] 4A-4C depict various views of a 2D or 3D PCM cell memory array including a stencil structure with a bottom line heater metal structure of sub-EUV dimensions, according to an embodiment herein.

[0022] [Figure 5] 5A-5C show various views of a further embodiment of a 2D or 3D PCM cell memory array including PCM memory cells formed on a stencil structure having a bottom heater metal structure with sub-EUV dimensions, according to a further embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0023] The present application will now be described in more detail by reference to the following discussion and the drawings that accompany this application. It should be noted that the drawings herein are provided for illustrative purposes only, and therefore the drawings are not drawn to scale. It should also be noted that like and corresponding elements are referred to by like reference numerals.

[0024] In the following description, numerous specific details are set forth, such as particular structures, components, materials, dimensions, processing steps, and techniques, to provide an understanding of various embodiments of the present application. However, it will be understood by those skilled in the art that various embodiments of the present application may be practiced without these specific details. In other instances, well-known structures or processing steps have not been described in detail to avoid obscuring the present application.

[0025] When an element, such as a layer, region, or substrate, is referred to as being "on" or "over" another element, it is understood that the element can be directly on the other element, or that intervening elements may also be present. In contrast, when an element is referred to as being "directly on" or "directly over" another element, there are no intervening elements present. When an element is referred to as being "beneath" or "under" another element, it is understood that the element can be directly below or directly under the other element, or that intervening elements may be present. In contrast, when an element is referred to as being "directly beneath" or "directly under" another element, there are no intervening elements present.

[0026] In one embodiment, the present disclosure provides a method and structure for forming PCM memory cells on a semiconductor wafer.

[0027] Specifically, an integration and patterning approach is provided that enables sub-EUV (i.e., critical dimension <25 nm) bottom electrode heaters to be metallized entirely with CVD metal and metal nitride, enabling high resistance / low power switching and reduced amorphous volume.

[0028] The present disclosure is directed to a multi-mushroom crossbar-like array and fabrication method enabled by sub-EUV heaters. By minimizing the heater dimensions, the amorphous switching volume is minimized and the contact area is reduced, thereby more effectively reducing the programming current of the PCM cells.

[0029] Advantageously, this method provides a PCM cell with a GST volume that is free from damage, thereby reducing current draw (lower power) and increasing device density.

[0030] 1A-1G illustrate one embodiment of a method for manufacturing a memory device to create sub-EUV via features in accordance with one aspect of the present disclosure.

[0031] As shown in FIG. 1A, a cross-sectional view of an initial semiconductor structure 100 is shown. The initial structure 10 is formed after performing MOL or BEOL semiconductor fabrication processes to fabricate conductive lines, contacts, insulating material layers, metal levels, etc., that interconnect previously formed individual devices, such as transistors, capacitors, resistors, etc. (not shown). As shown in FIG. 1A, the exemplary structure 100 includes, from bottom to top: a first interlayer dielectric layer 12 of a low-k dielectric material (e.g., SiN); an upper dielectric material cap layer 15 (e.g., TiN) formed above the interlayer dielectric material layer 12; a second interlayer dielectric material layer 20 (e.g., a low-k dielectric material such as an oxide dielectric material (e.g., SiO), or a silicon-doped oxide) formed above the dielectric material cap layer 15; and an upper developable OPL (organic planarization material) layer 25. In an embodiment, the first interlayer dielectric layer 12 of SiN dielectric material is formed to a thickness of approximately 75 nm. An upper TiN cap layer 15, which functions as a hard mask, is formed above the interlevel dielectric material layer 12 and is formed to a thickness of approximately 10 to 30 nm. A second interlevel dielectric material layer 20 made of SiO formed above the dielectric material cap layer 15 may be a tetraethyl orthosilicate (TEOS) dielectric material layer formed to a thickness in the range of approximately 100 to 300 nm.

[0032] Furthermore, a top anti-reflective coating layer 30, such as a silicon-containing anti-reflective coating (SiARC), is provided on top of the interlayer dielectric material layer 20. Furthermore, a patterned mask layer, for example, a photoresist material layer 40 formed as a result of applying a photolithographic imaging and development process, is formed on the top SiARC layer 30 to form a mask pattern 35.

[0033] That is, to create the initial structure 100 of Figure 1A, a photolithography system is used to expose a mask layer 40 to an image pattern (not shown), which is then developed in a developer solution, as shown in Figure 1A, to form a pattern 35 in the photoresist layer 40. The resist pattern 35 includes a series of openings, forming resist structures 38 in a periodic pattern. In one embodiment, the period, calculated as the distance d between adjacent resist pattern layer structures 38, is in the range of approximately 32 nm to 40 nm.

[0034] FIG. 1B shows a cross-sectional view of structure 101 resulting from transferring pattern 35 of photoresist layer 40 in structure 100 of FIG. 1A to the underlying OPL layer 25 using a dry etching process. That is, a reactive ion etching (RIE) step selective to the surface of dielectric layer level 20 results in etching through SiARC layer 38 and OPL layer 25 to form a pattern 55 in the OPL layer defined by resist structures 38, including a series of slightly tapered openings 56, with the remaining OPL structures 58 having a period equal to the periodic distance d of structures 38 in original resist layer pattern 35. In one embodiment, a tapered RIE etch is performed such that each of structures 58 has slightly sloped sidewalls 57. In one embodiment, the etch defines the aspect ratio of the resulting structures 58; that is, structures 58 have edges that form angles less than 90 degrees, e.g., angles in the range of 86 to 89.5 degrees relative to vertical. Structure 101 in FIG. 1B shows the result of further removing any remaining resist layer 35 and removing SiARC layer 30.

[0035] 1C shows a cross-sectional view of a structure 102 resulting from a first RIE etch to transfer the pattern 55 of the OPL layer 25 in the structure 101 of FIG. 1B to the underlying hard mask layer 15 using a further tapered dry etch process, and a second pattern transfer using hard mask (HM) metal RIE through the hard mask layer 15. That is, as a result of the further tapered RIE etch step selective to the surface of the hard mask layer 15, etching through the SiO layer 20 forms a pattern 65 of funnel-shaped vias 66 in the dielectric material, e.g., the SiO layer 20, defined by tapered openings 56 between the upper OPL layer structures 58. This formed pattern 65 includes a series of funnel-shaped via openings 66, and the remaining dielectric layer structures 68 have a periodicity equivalent to the periodicity distance d of the structures 38 of the original resist layer pattern 35. In one embodiment, a first tapered RIE etch is performed such that each of the remaining dielectric layer structures 68 in the pattern 65 has sidewalls 67 that are sloped relative to the slope of the sidewalls 57 of the structures 58 of the overlying OPL patterned layer 55. In one embodiment, a capacitively coupled plasma chamber using a N / H polymerization plasma chemistry can be tuned to achieve the desired profile of the opening 56 in the patterned layer 55. In one embodiment, the tapered etch in the capacitively coupled plasma chamber using a C / O / Ar polymerization plasma chemistry is tuned to achieve the sloped sidewall structures 68 with a defined aspect ratio. That is, the structures 68 have edges that form an angle less than (<) 90° with respect to vertical, e.g., in the range of 86 to 89.5°, resulting in the desired profile of the opening 66 in the patterned layer 65. As shown in FIG. 1C , the formed funnel-shaped via opening 66 exposes a portion of the top surface of the hard mask layer 15 over the length 1 between the sloped sidewall structures 68. In one embodiment, the length 1 of this exposed hard mask top surface is approximately 10 nm to 20 nm. Two successive plasma RIE conditions can be used to reduce the initially defined critical dimension (CD) by 20 to 30 nm, defining a final CD of less than 20 nm (a highly reduced RIE process).

[0036] 1C further shows the resulting structure 102 formed after performing a further isotropic etch selective to the bottom interlayer dielectric layer 12 to transfer the dielectric material layer pattern 65 to the hard mask layer 15 using a standard hard mask metal RIE etch. This results in a hard mask layer pattern 75 with vertical circular vias or openings 76 periodically spaced between remaining hard mask structures 78, each having a diameter length 1, e.g., approximately 8 nm in diameter. The resulting hard mask structures 78 have straight edge sidewalls and are approximately 28 + / - 0.1 nm in length.

[0037] FIG. 1D illustrates a cross-sectional view of a structure 103 resulting from transferring the pattern 75 defined in the hard mask layer 15 in the structure 102 of FIG. 1C to the underlying dielectric layer 12 using a dry etching process. That is, a further RIE step and an etch bias technique performed through the defined circular via openings 76 result in a final pattern 85 in the dielectric layer 12, which includes a series of vertically oblong circular via openings 86 aligned with the circular via openings 76 in the hard mask layer 15. In one embodiment, an etch bias of −10 nm results in openings 86 with a sub-EUV feature size of approximately 8 nm. The resulting pattern 85 includes residual SiN layer structures 88 with a periodicity equivalent to the periodicity distance d of the structures 38 in the original resist layer pattern 35. The resulting structure 103 of FIG. 1D illustrates the result of further removing any remaining overlying OPL layer structures 58. In one embodiment, the etch bias is applied according to the following formula: DCD(LTH)-FCD(SiN)=10nm where DCD represents the developed critical dimension, LTH represents the lithographically printed, and FCD(ILD) represents the final critical dimension (e.g., the final CD printed in SiN or any interlayer dielectric). As an example, assume a starting pitch d=36 nm, the lithographically printed CD achieved is 18 nm, and the highly reduced RIE reduces the CD further to 10 nm, resulting in a final CD=8 nm for opening 76 in layer 75, while maintaining a pitch of d=36 nm that matches the initial pitch.

[0038] 1E shows a cross-sectional view of structure 104 resulting from a metallization step to deposit a metal material on structure 103 of FIG. 1D when formed above a bottom electrode layer (not shown). Specifically, a heater metal material, including but not limited to TiN, W, TaN, Al, or AlN, is deposited using a chemical vapor deposition (CVD) or physical vapor deposition (PVD) process. This deposition process results in the formation of a thin heater metal material layer 89 that conforms to the top surface and sloped sidewall edge surfaces of the patterned dielectric material 65 layer, and in a heater electrode or heater filament structure 95 made of heater metal material that seamlessly fills the elongated, aligned circular via openings 76, 86 defined in hard mask 75 and dielectric material pattern 85, respectively.

[0039] FIG. 1F shows a close-up view of an alternative structure in which a liner material 92 is first deposited into the funnel-shaped via opening 66 and the aligned vertical circular via openings 76, 86 in the structure 103 of FIG. 1D prior to core filling with heater metal material. That is, as shown in FIG. 1D , tapered RIE results in a patterned dielectric material layer 65 whose surface structure 68 defines the funnel-shaped via opening 66 with an aspect ratio that allows for material filling with minimal or no seams. As shown in FIG. 1F , at sub-EUV dimensions, this defined surface topology of FIG. 1D first allows for seamless PVD of a metal nitride material liner 89 in which the via bottom liner portion 93 is thicker than the sidewall metal nitride liner portion 94. In one embodiment, the PVD deposition process can deposit a liner 89 of a liner material, including, but not limited to, TaN, TiN, AlN, WN, amorphous carbon (α-C), cobalt, ruthenium, etc. As shown in FIG. 1F, the funnel-shaped via opening 66 allows for the deposition of a metal nitride liner and core fill material, avoiding pinch-off. The initial conductive PVD metal nitride material deposition results in a continuous layer with a thick bottom liner 93 and less sidewall deposition 94 due to the straight sidewalls. As a result, the heater structure 90 is formed with an increased thickness of the TaN liner bottom 93, providing better thermal insulation and improved thermal insulation. Furthermore, the final PVD-deposited metal nitride heater core fill material 95, e.g., TaN, is free of any voids / gaps / seams due to the tapered RIE profile and aspect ratio of the funnel-shaped opening 66 achieved in the patterned dielectric material layer 65.

[0040] FIG. 1G shows a cross-sectional view of a stencil structure 105 obtained by applying a chemical mechanical planarization (CMP) step to the structure 104 of FIG. 1E. The CMP step removes the remaining patterned dielectric material 65 layer and the remaining patterned hard mask metal layer 75, ensuring that the sub-EUV lined metal heater features 95 formed in the patterned dielectric layer 85 are void / seam / gap-free. The formed sub-EUV metal heater structures 95 each have a width l1 of approximately 8 nm and are spaced apart according to a distance l2 of approximately 28 nm, as determined, for example, by the DCD(LTH)-FCD(SiN) equation. In a non-limiting example, this results in a pitch range of approximately 32 nm to 40 nm. The resulting patterned dielectric layer 85 of the structure 105 with the sub-EUV lined metal heater features 95 formed therein can be a precursor or stencil for further patterning. For example, each of these formed sub-EUV lined metal heater structures 95 is aligned with a subsequently formed memory cell, i.e., a phase change memory cell, formed in a subsequent process step (not shown).

[0041] 2A-2C illustrate alternative embodiments of steps in a method of manufacturing a PCM memory device to create sub-EUV via features according to further aspects of the present disclosure.

[0042] Specifically, Figure 2A shows a further cross-sectional view of the second embodiment structure 204 resulting from a metallization step to deposit a metal material liner 189 on the structure 103 of Figure 1D when formed above a bottom electrode layer (not shown). Specifically, a heater metal material, such as TiN, W, TaN, Al, or AlN, is deposited using a CVD or PVD process to line the surfaces of the sloped sidewalls 67 of the defined funnel-shaped opening 66 in the patterned dielectric layer 65 and to form a liner on the interior surfaces of the aligned etched holes 76, 86 in the patterned hard mask 75 and the patterned first dielectric layer 85, respectively. As shown in the embodiment of Figure 1F, the funnel-shaped via opening 66 allows for the deposition of a metal nitride liner and core fill material to avoid pinch-off. The CVD or PVD deposition of the metal nitride liner material forms a heater metal material liner 189 approximately 2 to 3 nm thick. Additionally, optional bias etch (e.g., bias in situ sputter etch) and dielectric fill steps can be performed after forming liner 189. Figure 2A shows tapered opening 66 in patterned dielectric layer 65 lined with metal nitride liner material, and lined etched circular via holes 76, 86 in patterned hard mask layer 75 and patterned dielectric layer 85, respectively.

[0043] In an alternative embodiment, the resulting structure 190 shown in FIG. 2B illustrates the result of depositing a first liner material 189 into the funnel-shaped via opening 66 and the aligned vertically oblong circular via openings 76, 86 of the structure 204 of FIG. 2A and depositing a core heater metal material 195 into the vertically oblong circular via opening 86. That is, using tapered RIE to create the funnel-shaped via opening of FIG. 1D results in a patterned dielectric material layer 65 whose surface structure 68 defines the funnel-shaped opening 66 with an aspect ratio that allows for metal fill with minimal or no seams. At sub-EUV dimensions, this defined surface topology of FIG. 1D first enables the PVD of a metallic material outer liner 189, e.g., TaN, with a seamless, continuous thick bottom liner portion 193 that is thicker than the sidewall liner portion 194. Other metallic material liners can include TiN, AlN, WN, α-C, etc. As shown in FIG. 2B , the funnel-shaped via opening 66 allows for the deposition of a metal nitride material liner 189 (e.g., TaN) and core fill material 195 to avoid pinch-off. The initial conductive PVD metal nitride material deposition results in a continuous outer layer, but due to the straight sidewalls, the bottom liner 193 is thicker and the sidewall metal nitride material deposition 194 is less. The resulting heater structure 190 has an increased thickness of the bottom metal nitride material liner 193, resulting in better thermal insulation and improved thermal insulation. An additional deposition step of a metal nitride material, such as TiN, can be used to form an additional inner metal nitride filament layer 192 that conforms to the inner surfaces of the outer liner portions 193, 194. This filament layer can be a TiN layer deposited by an atomic layer deposition (ALD) process. Furthermore, the metal nitride core fill material 195 (e.g., TaN) deposited by performing the final PVD step does not have any voids / gaps / seams due to the tapered RIE profile and aspect ratio of the realized funnel-shaped opening 66, which avoids pinch-off in the patterned dielectric material layer 65.

[0044] Alternatively, rather than depositing a metal nitride core fill material 195, an interlayer dielectric material fill 195 including, but not limited to, SiO2 or SiN can be deposited, for example, by an ALD / CVD process, in the final PVD deposition step.

[0045] FIG. 2C shows a cross-sectional view of a second embodiment stencil structure 205 resulting from applying a CMP step to the structure 204 of FIG. 2A. The CMP step removes the remaining patterned dielectric material 65 layer and the remaining patterned hard mask metal layer 75, forming a patterned dielectric layer 85 with spaced-apart sub-EUV metal heater structures 190. Each of the formed sub-EUV metal heater structures 190 includes a circular via opening having a liner 189, a diameter l1 of approximately 8 nm, and is filled with either a metal nitride or a dielectric material 195. Adjacent sub-EUV metal heater liner structures 190 are spaced apart by a distance l2 of approximately 28 nm. In one embodiment, the opening diameter l1 may range from 6 nm to 10 nm, and the distance l2 may range from 26 nm to 30 nm. The resulting patterned dielectric layer 85 of the stencil structure 205 with the sub-EUV metal heater structures 190 formed thereon can be a precursor or stencil for further patterning, for example, each of these formed sub-EUV dimension metal heater structures 190 can be aligned with a memory cell, i.e., a phase change memory cell, to be formed in a subsequent process step (not shown).

[0046] 3 shows a memory cell structure 200 having a bottom heater electrode structure 300 formed thereon according to embodiments described herein. For example, in one embodiment, a PCM mushroom cell memory element 150 including an active volume of Ge2Sb2Te5 (GST) material is formed on each sub-EUV heater metal filament of the stencil structure 105 of FIG. 1G. In another design, a PCM mushroom cell memory element 150 including an active volume of GST material is formed on each sub-EUV heater metal filament of the stencil structure 205 of FIG. 2B.

[0047] That is, as shown in FIG. 3 , the PCM cell memory element 150 is formed in electrical contact with a lithographically aligned and defined bottom heater metal electrode 300, whether consisting of a sub-EUV dimensioned bottom heater metal filament structure 95 as shown in FIG. 1G or a sub-EUV dimensioned metal heater liner feature 190 as shown in FIG. 2B. An electrical connection is shown between a corresponding aligned active amorphous GST (α-GST) phase change material portion 151 of the memory element 150. The defined dimensions of the sub-EUV dimensioned bottom heater metal filament structure 95 as shown in FIG. 1G or the sub-EUV dimensioned metal heater liner feature 190 as shown in FIG. 2B determine the size of the switching volume of the α-GST material portion 151 of the cell 150. The sub-EUV dimensioned bottom heater electrode 300 enables the PCM cell 200 to undergo amorphous-to-crystalline state transitions in response to voltage and current applied to the bottom electrode 300.

[0048] 4A-4C depict various views of a 2D or 3D PCM cell memory array including a stencil structure having a heater metal structure with a bottom liner of sub-EUV dimensions, according to an embodiment herein.

[0049] Specifically, Figures 4A-4C show various views of a 2D or 3D PCM cell memory array 400 including either a stencil structure 105 having a bottom lined heater metal structure 95 of sub-EUV dimensions as shown in Figure 1F or a stencil structure 205 having a lined heater metal structure 190 of sub-EUV dimensions as shown in Figure 2B.

[0050] 4A shows a cross-sectional view of a 2D or 3D PCM cell memory array 400 in which a series of memory elements 410 are formed on a formed stencil, i.e., a dielectric layer stencil 105 having a bottom heater metal filament 95 with sub-EUV dimensions as shown in FIG. 1G or a stencil 205 having a metal heater liner feature 190 with sub-EUV dimensions as shown in FIG. 4A. As shown in FIG. 4A, a respective PCM mushroom cell memory element 410 is aligned with each of the bottom heater metal filaments 95 or metal heater liner features 190, and each cell has a GST material, e.g., crystalline GST or c-GST, and a corresponding α-GST switching material portion 411. As shown in FIG. 4A , in one embodiment, memory cell array 400 is formed on an interlevel low-k dielectric (ILD) or tetraethyl orthosilicate (TEOS) material layer 415 overlying either a dielectric layer stencil 105 having sub-EUV bottom heater metal filaments 95 as shown in FIG. 1G or a stencil 205 having sub-EUV metal heater liner features 190 as shown in FIG. 2B . Formed in the patterned TEOS material layer 415 are respective metal conductors (metal lines or wires) 420, each electrically connected to a respective sub-EUV bottom heater metal filament 95 as shown in FIG. 1G or, alternatively, to a respective sub-EUV metal heater liner feature 190 as shown in FIG. 2B . In an embodiment, the respective metal conductor lines or wires 420 receive voltage or current signals used to program the resistance states of the respective PCM memory cells 410. As further shown in FIG. 4A, each PCM memory cell is electrically connected to a single upper metal electrode 425 formed in an upper interlevel dielectric layer and aligned with the line or memory cell 410 for electrical connection to each cell 410.

[0051] In one embodiment, each line or wire is formed of a metallic material such as copper, tungsten, a copper alloy, cobalt, or any suitable conductive metal, and is lined with a barrier layer (not shown), for example, Ta, TaN, Ti, TiN, or any suitable liner material.

[0052] FIG. 4B is a cross-sectional view of the 2D or 3D PCM cell memory array 400 array structure of FIG. 4A rotated 90 degrees. The cross-sectional view of the 90° rotated 2D or 3D PCM cell memory array structure of FIG. 4B shows a series of memory elements 410, each with a corresponding aligned top electrode 425 formed in an upper interlayer dielectric layer 435 of a dielectric material such as TEOS. The series of memory elements 410 shown in the rotated orientation in the cross-sectional view of the rotated 2D or 3D PCM cell memory array structure of FIG. 4B are further electrically connected to individual single metal conductor lines or wires 420 that receive voltage or current signals for programming the individual memory cells 410. Although not shown, an exemplary current can be applied from the bottom individual metal conductor lines or wires 420, pass through either the sub-EUV dimension bottom heater metal filament 95 or metal heater liner feature 190 of the stencil 105 and the respective memory cell elements, and be read or sensed via the top metal electrode 425.

[0053] Figure 4C shows a top view 450 of the 2D or 3D PCM cell crossbar memory array 400 of Figures 4A and 4B, with a linear series of PCM memory cells 410 formed on either a stencil 105 with a bottom heater metal filament 95 of sub-EUV dimensions as shown in Figure 1G or a stencil 205 with a metal heater liner feature 190 of sub-EUV dimensions as shown in Figure 2C. Figure 4A specifically shows a cross section of the structure 450 along line Y-Y' in Figure 4C, with the linear series of cells 410 in the 2D array connected to respective top conductors 425. Figure 4B shows a cross section of the structure 450 along line XX in Figure 4C, with the linear series of cells 410 in the 2D array connected to respective bottom metal conductors 420.

[0054] 5A-5C show various views of a further embodiment of a 2D or 3D PCM cell memory array including PCM memory cells formed on a stencil structure having a bottom heater metal structure with sub-EUV dimensions, according to a further embodiment.

[0055] Specifically, Figures 5A-5C depict various views of a further embodiment 2D or 3D PCM cell memory array 500 including PCM memory cells formed on either a stencil structure 105 having a bottom heater metal filament structure 95 with sub-EUV dimensions as shown in Figure 1G or a stencil structure 205 having a metal heater liner feature 190 with sub-EUV dimensions as shown in Figure 2C.

[0056] 5A illustrates a cross-sectional view of a 2D or 3D PCM cell memory array 500 in which a series of multiple individual memory elements 410 are formed on a formed stencil, i.e., a dielectric layer stencil 105 having a bottom heater metal filament 95 with sub-EUV dimensions as shown in FIG. 1G or a stencil 205 having a metal heater liner feature 190 with sub-EUV dimensions as shown in FIG. 2C. The difference between the memory cell array 500 of FIG. 5A and the memory cell array 400 embodiment of FIG. 4A is that each PCM memory cell in the PCM cell memory array 500 embodiment of FIG. 5A is isolated and separated from adjacent PCM memory cells 510 by dielectric material spacers 512. That is, in one embodiment, when the PCM memory cell elements 510 are fabricated, a spacer between each memory cell is formed, each spacer comprising SiO2 or a similar dielectric material spacer fill 512.

[0057] As shown in Figure 5A, a respective PCM mushroom cell memory element 510 is aligned with a bottom heater metal filament 95 or metal heater liner feature 190, and each cell has a GST material (e.g., poly-GST or c-GST) and a corresponding α-GST switching material portion 511. As shown in Figure 5A, in one embodiment, the memory cell array 500 is formed on an interlayer low-k dielectric (ILD) or tetraethyl orthosilicate (TEOS) material layer 515, overlying which is formed either a dielectric layer stencil 105 having a bottom heater metal filament 95 with sub-EUV dimensions as shown in Figure 1G or a stencil 205 having a metal heater liner feature 190 with sub-EUV dimensions as shown in Figure 2C. Formed in the patterned TEOS material layer 515 are respective metal conductors (metal lines or wires) 520, each electrically connected to an individual sub-EUV sized bottom heater metal filament 95 shown in FIG. 1G or, alternatively, to an individual sub-EUV sized metal heater liner feature 190 as shown in FIG. 2C. In an embodiment, the individual metal conductor lines or wires 520 receive voltage or current signals used to program the resistance states of individual PCM memory cells 510. As further shown in FIG. 5A, each PCM memory cell is electrically connected to a single top metal electrode 525 formed in an overlying interlevel dielectric layer and aligned with the line or memory cell 510 for electrical connection to each cell 510.

[0058] In one embodiment, each line or wire is formed of a metallic material such as copper, tungsten, a copper alloy, cobalt, or any suitable conductive metal, and is lined with a barrier layer, for example, Ta, TaN, Ti, TiN, or any suitable liner material (not shown).

[0059] Figure 5B shows a cross-sectional view of the array structure of the 2D or 3D PCM cell memory array 500 of Figure 5A rotated 90 degrees. The cross-sectional view of the 2D or 3D PCM cell memory array structure of Figure 5B shows a series of memory elements 510, with the individual memory elements separated and isolated by spacers 512. Each memory cell element has an associated top electrode 525 formed in and aligned with an upper interlayer dielectric layer 535 of a dielectric material, such as TEOS. The series of memory elements 510, shown in the rotated orientation in the cross-sectional view of the rotated 2D or 3D PCM cell memory array structure of Figure 5B, are further electrically connected to individual single metal conductor lines or wires 520 that receive voltage or current signals for programming the individual memory cells 510. Although not shown, an exemplary current can be applied from the bottom individual metal conductor line or wire 520, passed through either the sub-EUV bottom heater metal filament 95 or the sub-EUV metal heater liner feature 190 of the stencil 105 and the respective memory cell element, and read or sensed via the top metal electrode 525.

[0060] Figure 5C shows a top view 550 of the 2D or 3D PCM cell crossbar memory array 500 of Figures 5A and 5B, in which a linear series of PCM memory cells 510 are formed on either a stencil 105 having a bottom heater metal filament 95 with sub-EUV dimensions as shown in Figure 1G or a stencil 205 having a metal heater liner feature 190 with sub-EUV dimensions as shown in Figure 2C, each separated and individually isolated by dielectric material spacers 512. Figure 5A specifically shows a cross section of the structure 550 along line Y-Y' in Figure 5C, in which the linear series of cells 510 in the 2D array are connected to respective top conductors 525. Figure 5B shows a cross section of the structure 550 along line XX in Figure 5C, in which the linear series of cells 510 in the 2D array are connected to respective bottom metal conductors 520.

[0061] The methods of Figures 1A-1G and 2A-2C propose a new integration and patterning approach, enabling the sub-EUV bottom electrode heater of a PCM cell to be metallized solely with CVD metal and metal nitride, enabling high-resistance / low-power switching and reduced amorphous volume. Specifically, EUV lithography processes utilizing etch bias enable further reduction in via size, even with large top CD apertures, enabling PVD / ALD metallization. These methods also enable improved heater via sidewall verticality. Further embodiments include multi-mushroom crossbar-like PCM cell arrays enabled by sub-EUV heaters. Minimizing heater dimensions minimizes the amorphous switching volume of the PCM cell and spares the provided GST volume from damage, reducing current draw (operating at lower power) and improving device density. The reduced heater size enhances PCM device performance efficiency.

[0062] The methods of FIGS. 1A-1G and 2A-2C are applicable to PCM device technology in heater modules, and the methods are scalable to enable higher density PCM architectures.

[0063] While the present disclosure has been described with respect to specific embodiments, it is evident that numerous alternatives, modifications, and variations will become apparent to those skilled in the art in light of the foregoing description. Unless expressly stated otherwise or otherwise clearly compatible with one another, the various embodiments of the present disclosure can be used either alone or in combination with any other embodiment. Accordingly, the present disclosure is intended to embrace all alternatives, modifications, and variations that fall within the scope of this disclosure and the following claims.

Claims

1. a bottom electrode made of a metal-containing material; A memory cell structure including a phase change material; and a sub-extreme ultraviolet (sub-EUV) metal heater element having a sub-EUV vertical circular via structure with a seamless fill material, the sub-EUV metal heater element being positioned between and electrically connecting the bottom electrode and the PCM memory cell structure; A phase change material (PCM) memory cell comprising:

2. The PCM memory cell of claim 1 , wherein the seamless fill material comprises a metal nitride fill material.

3. The PCM memory cell of claim 2 , wherein the sub-extreme ultraviolet (sub-EUV) vertical circular via structure further comprises a sub-EUV metal nitride liner.

4. The PCM memory cell of claim 3 , wherein the sub-EUV metal nitride liner is thick at the bottom and thin at the sidewalls.

5. 10. The PCM memory cell of claim 1, wherein the metallic heater element with the sub-EUV vertical circular via structure includes an outer metal nitride liner made of a first metal nitride material and an inner metal nitride filament layer made of a second metal nitride material.

6. The PCM memory cell of claim 5 , wherein the sub-EUV outer metal nitride liner is thick at its bottom and thin at its sidewalls.

7. The PCM memory cell of claim 6 , wherein the seamless fill material comprises a material selected from a metal nitride fill material or a dielectric fill material.

8. 2. The PCM memory cell of claim 1, wherein the sub-EUV metallic heater element via structure is formed in a first dielectric material layer directly below the PCM memory cell structure, and the bottom electrode is formed in a second dielectric material layer below the first dielectric material layer.

9. a first insulating material layer including a plurality of bottom electrodes made of a metal-containing material; a plurality of memory cell structures made of a phase change material, each memory cell structure being aligned with a respective bottom electrode; and a plurality of sub-extreme ultraviolet (sub-EUV) dimensioned metal heater elements, each having a sub-EUV dimensioned vertical circular via structure including a seamless fill material, each positioned between a respective bottom electrode and a respective PCM memory cell structure and electrically connecting the respective bottom electrode and the respective PCM memory cell structure; A phase change material (PCM) memory cell array comprising:

10. The PCM memory cell array of claim 9 , wherein the seamless fill material comprises a metal nitride fill material.

11. The PCM memory cell array of claim 10 , wherein the sub-extreme ultraviolet (sub-EUV) vertical circular via structure further comprises a sub-EUV metal nitride liner.

12. The PCM memory cell array of claim 11 , wherein the sub-EUV metal nitride liner is thick at the bottom and thin at the sidewalls.

13. 10. The PCM memory cell array of claim 9, wherein each of the metallic heater elements having the sub-EUV vertical circular via structures includes an outer metal nitride liner made of a first metal nitride material and an inner metal nitride filament layer made of a second metal nitride material.

14. 14. The PCM memory cell array of claim 13, wherein the sub-EUV outer metal nitride liner is thick at its bottom portion and thin at its sidewall portion.

15. 15. The PCM memory cell array of claim 14, wherein the seamless fill material comprises a material selected from a metal nitride fill material or a dielectric fill material.

16. 10. The PCM memory cell array of claim 9, wherein the plurality of sub-EUV dimension metallic heater elements are formed in a first dielectric material layer directly below the PCM memory cell structure, and the plurality of bottom electrodes are formed in a second dielectric material layer below the first dielectric material layer.

17. 1. A method of forming a phase change material (PCM) memory cell, comprising: forming a first insulating material layer having a bottom electrode made of a metal-containing material; and forming a second insulating material layer having a metallic heater element with sub-extreme ultraviolet (sub-EUV) dimensions; the sub-EUV metallic heater element is aligned with and includes a sub-EUV vertical circular via structure in electrical communication with the bottom electrode, the vertical circular via structure having a seamless fill material; The method further comprises: forming a PCM memory cell structure above the sub-EUV metallic heater element and in electrical communication with the sub-EUV metallic heater element; A method comprising:

18. forming a second insulating material layer containing the sub-EUV metallic heater element; forming the second layer of insulating material above the first layer of insulating material; forming a hard mask dielectric material layer above the second insulating material layer; forming an intermediate dielectric material layer above the hard mask dielectric material layer; etching the intermediate dielectric material layer using a tapered etch process to achieve a topographic profile that defines one or more funnel-shaped openings; performing a further etching process within the defined funnel-shaped opening to form a circular via opening aligned with the funnel-shaped opening and extending through the hard mask dielectric material layer and the second insulating material layer; performing a vapor deposition process to seamlessly deposit the fill material within the vertical circular via opening; and removing the interlayer dielectric material and removing the hardmask dielectric material. Equipped with 18. The method of claim 17.

19. 20. The method of claim 18, wherein the fill material seamlessly deposited within the vertical circular via opening comprises a metal nitride fill material.

20. Prior to performing the vapor deposition process to seamlessly deposit the fill material, depositing a sub-EUV metal nitride liner in the vertical circular via opening; the sub-EUV metal nitride liner has a thick bottom portion and a thin sidewall portion; 20. The method of claim 19.

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