Low-loss traveling-wave parametric device using planar capacitors.

Abstract

A method for fabricating a traveling wave parametric amplifier (TWPA) includes forming a superconducting junction on a substrate. Trenches are etched through a metal surface and into a layer of dielectric material. The trenches define a plurality of fingers positioned in an interdigitated arrangement of a capacitor defined by the metal and dielectric material remaining from the etched-away metal surface and layer of dielectric material.

Description

[Technical Field]

[0001] The present disclosure relates generally to electrical devices, and more particularly to low-loss traveling-wave parametric devices that use planar capacitors. [Background technology]

[0002] In general, parametric devices use a time-varying parameter to couple multiple modes. In Josephson parametric devices, the Josephson inductance acts as the time-varying parameter. Josephson traveling-wave parametric devices are typically amplifiers, isolators, or frequency converters and are commonly used in readout circuits of superconducting quantum computing systems. More specifically, Josephson traveling-wave parametric devices rely on a non-resonant construction of a series Josephson junction with a lumped-element capacitance to ground, thereby creating an artificial transmission line. The non-resonant construction overcomes the bandwidth limitations associated with resonant devices at the expense of requiring hundreds to thousands of series elements.

[0003] Some traveling wave parametric devices (TWPDs) are designed in a fabrication process called the tri-layer process. This superconducting thin-film process is available at a variety of commercial and academic foundries and allows for the fabrication of multilayer superconducting circuits with thousands of Josephson junctions within a single die. This process is also compatible with passive radio frequency (RF) circuits (e.g., transmission lines, inductors, etc.). A variety of circuits can be constructed with this process, including amplifiers, logic circuits, single flux quantum (SFQ) circuits, detectors, etc. Unlike fabrication processes used to realize qubits, the tri-layer process relies on the use of dielectric materials with relatively high loss tangents, which represents a significant tradeoff in junction yield. The tri-layer process is beneficial for creating high-yield TWPDs with thousands of junctions in series.

[0004] A typical tri-layer process can involve multiple thin-film superconductors on alternating dielectric layers. An exemplary process for fabricating a TWPD may require only two metal layers. The dielectric material between the two metal layers has a typical loss tangent on the order of 0.001. This results in an inherently lossy Josephson transmission line. This loss can be captured in both simulations and measurements. For some current representative devices, the loss can be approximately 2-3 dB per device.

[0005] 1 and 2 show an example of a conventional TWPD device unit cell. The source of losses in a conventional TWPD can be determined from a circuit model and the process used to fabricate the device. Because the majority of the series wiring is part of the superconducting stack, losses are minimal in that portion of the circuit. However, as can be seen, the unit cell shown in FIGS. 1 and 2 uses a parallel plate capacitor 50 coupled to a junction 60. The parallel plate capacitor includes a lossy SiO2 dielectric deposited by a plasma-enhanced chemical vapor deposition (PECVD) process.

[0006] Losses in current TWPD fabrication processes affect the operation of quantum computers. In one way, the losses translate into the signal-to-noise ratio, and therefore the fidelity, of qubit state measurements in quantum computing systems. Extremely low power, corresponding to a single microwave photon populating the readout resonator, is used to interrogate the qubit to minimize undesired perturbations of the qubit state. Given the desire to minimize measurement power, it is important to maintain the signal-to-noise ratio of the qubit state measurement while the signal is transferred from the quantum processor to the higher-temperature digitizing electronics. This signal-to-noise ratio can be quantified as quantum efficiency, which normalizes the signal-to-noise of the measurement to the limit set by noise associated with vacuum fluctuations of electromagnetic fields in cryogenic environments. TWPDs can be used as amplifiers, whereby additional noise from downstream components, such as HEMT amplifiers, adversely affects the overall quantum efficiency of the measurement. In contrast, losses before amplification typically have a larger impact because they proportionally degrade the quantum efficiency of the qubit measurement. Therefore, minimizing losses in the components from the qubit chip up to and including the TWPD can help maintain high quantum efficiency in the readout chain. Summary of the Invention

[0007] According to one embodiment of the present disclosure, a traveling wave parametric device (TWPD) is provided. The TWPD comprises a dielectric substrate and a periodic array of Josephson junctions located in a tri-layer structure. The tri-layer structure includes a common electrode layer, a base electrode layer, and an aluminum oxide layer positioned between the common electrode layer and the base electrode layer. The tri-layer structure is supported by the dielectric substrate. An interlayer dielectric layer is supported by the tri-layer structure. A metal layer is supported by the interlayer dielectric layer. The TWPD also comprises a plurality of capacitors coupled to the Josephson junctions arranged in an interdigitated configuration in the tri-layer structure.

[0008] In one embodiment that may be combined with the preceding embodiments, a first set of the plurality of capacitors is positioned on a first side of the Josephson junction and a second set of the plurality of capacitors is positioned on a second side of the Josephson junction. By positioning capacitors on both sides of the junction, the overall footprint available for capacitance can be increased while maintaining the same period as a conventional TWPD. The use of interdigitated capacitors can reduce losses while maintaining the overall capacitance for the TWPD.

[0009] In one embodiment that may be combined with the preceding embodiment, a first set of the plurality of capacitors is positioned on a first side of the Josephson junction, and a second set of the plurality of capacitors is positioned on a second side of the Josephson junction.

[0010] In one embodiment that may be combined with the preceding embodiments, the plurality of capacitors are positioned in any layer of the three-layer structure.

[0011] In one embodiment that may be combined with the preceding embodiments, the plurality of capacitors are positioned on the base electrode layer.

[0012] In one embodiment, which may be combined with the preceding embodiments, the capacitors are positioned in the same plane as the plane of the Josephson junctions.

[0013] In one embodiment that may be combined with the preceding embodiments, the plurality of capacitors are positioned on the common electrode layer.

[0014] In one embodiment that may be combined with the preceding embodiments, the interlayer dielectric material is a thermal film.

[0015] In one embodiment that may be combined with the preceding embodiments, the interlayer dielectric material is an epitaxial film.

[0016] In one embodiment, the TWPD is an amplifier.

[0017] In one embodiment, the TWPD is a frequency converter.

[0018] According to one embodiment of the present disclosure, a qubit system is provided. The qubit system includes a qubit, a resonator coupled to the qubit, and a traveling wave parametric device (TWPD) coupled to the resonator. The TWPD includes a dielectric substrate and a periodic array of Josephson junctions located in a tri-layer structure. The tri-layer structure includes a common electrode layer, a base electrode layer, and an aluminum oxide layer positioned between the common electrode layer and the base electrode layer. The tri-layer structure is supported by the dielectric substrate. An interlayer dielectric layer is supported by the tri-layer structure. A metal layer is supported by the interlayer dielectric layer. The TWPD also includes a plurality of capacitors coupled to the Josephson junctions arranged in an interdigitated configuration in the tri-layer structure.

[0019] In one embodiment that may be combined with the preceding embodiments, each capacitor of the plurality of capacitors is positioned on the same plane as each other capacitor in the plurality of capacitors. The use of coplanar interdigitated capacitors can preserve capacitance for TWPD while reducing losses in dielectric levels that may be seen when using parallel plate capacitors.

[0020] In one embodiment, the plurality of capacitors are positioned in the same plane as the plane of the Josephson junctions.

[0021] In one embodiment that may be combined with the preceding embodiments, the interlayer dielectric material is a thermal film.

[0022] In one embodiment that may be combined with the preceding embodiments, the interlayer dielectric material is an epitaxial film.

[0023] In one embodiment that may be combined with the preceding embodiment, a first set of the plurality of capacitors is positioned on a first side of the Josephson junction and a second set of the plurality of capacitors is positioned on a second side of the Josephson junction.

[0024] According to one embodiment of the present disclosure, there is provided a method for fabricating a traveling wave parametric device (TWPD), the method comprising forming Josephson junctions in a tri-layer structure on a dielectric substrate, the method further comprising patterning capacitors in an interdigitated arrangement on a metal surface of the tri-layer structure, and etching away trenches in an interlayer dielectric material between the capacitors.

[0025] In one embodiment that may be combined with the preceding embodiments, the method includes using a thermal film or epitaxial film as the interlayer dielectric material. The interlayer dielectric dominates losses in conventional TWPDs having a three-layer structure. By increasing the capacitor footprint and using a thermal film or epitaxial film for the interlayer dielectric material, the interlayer dielectric section of the device produces a lower loss tangent in the circuit.

[0026] In one embodiment, which may be combined with the preceding embodiments, the arrangement of interdigitated capacitors is formed on a single plane.

[0027] In one embodiment, which may be combined with the preceding embodiments, the arrangement of interdigitated capacitors is formed in sets positioned on either side of the Josephson junction.

[0028] In one embodiment that may be combined with the preceding embodiments, the arrangement of interdigitated capacitors is formed in any layer of the three-layer structure.

[0029] The techniques described herein may be implemented in several ways. Example implementations are provided below with reference to the following figures. [Brief explanation of the drawings]

[0030] The drawings are of exemplary embodiments. They do not depict all embodiments. Other embodiments may be used in addition or instead. To save space or for a more effective illustration, details that may be obvious or unnecessary may be omitted. Some embodiments may be practiced with additional components or steps and / or without all of the components or steps shown. When the same numeral appears in different drawings, it refers to the same or similar components or steps.

[0031] [Figure 1]FIG. 1 is a schematic top view of a prior art traveling wave parametric device unit cell.

[0032] [Figure 2] FIG. 2 is a schematic top perspective view of the traveling wave parametric device of FIG. 1.

[0033] [Figure 3] 1 is a block diagram of a quantum computing system according to one embodiment.

[0034] [Figure 4] FIG. 1 is a schematic diagram of a traveling wave parametric device according to one embodiment.

[0035] [Figure 5] 5A is a schematic top view of a section of a traveling wave parametric device according to an exemplary embodiment, and FIG. 5A is an enlarged view of circle 5A in FIG.

[0036] [Figure 6] FIG. 1 is a schematic top view of a traveling wave parametric device unit cell according to an exemplary embodiment.

[0037] [Figure 7] FIG. 1 is a top perspective view of a traveling wave parametric device according to an exemplary embodiment.

[0038] [Figure 8] 8A and 8B are top perspective and enlarged inset views of the traveling wave parametric device of FIG. 7 according to an exemplary embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0039] [Summary] In the following detailed description, by way of example, numerous specific details are set forth in order to provide a thorough understanding of the relevant teachings. It will be apparent, however, that the present teachings may be practiced without such details. In other instances, well-known methods, procedures, components, and / or circuits have been described in relatively general terms, without detail, in order to avoid unnecessarily obscuring aspects of the present teachings.

[0040] In one aspect, spatially related terminology such as "front," "back," "top," "bottom," "lower," "belower," "upper," "upper," "side," "left," "right," and the like, is used with reference to the orientation of the figures being described. Because components of embodiments of the present disclosure can be positioned in many different orientations, directional terminology is used for illustrative purposes and in no way limiting. It will therefore be understood that spatially relative terminology is intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if a device in the figures were inverted, elements described as "below" or "below" other elements or features would then be oriented "above" such other elements or features. Thus, for example, the term "below" can encompass both an orientation of above and below. A device may be oriented differently (rotated 90 degrees or viewed or referenced in another orientation), and the spatially relative descriptors used herein should be interpreted accordingly.

[0041] As used herein, the terms "lateral," "planar," and "horizontal" describe an orientation parallel to a first surface of a chip or substrate.

[0042] As used herein, the term "vertical" describes an orientation that is disposed perpendicular to the first surface of a chip, chip carrier, chip substrate, or semiconductor body.

[0043] As used herein, the terms "coupled" and / or "electrically coupled" are not intended to imply that elements must be directly coupled together; intervening elements may be provided between the "coupled" or "electrically coupled" elements. In contrast, when an element is referred to as being "directly connected" or "directly coupled" to another element, there are no intervening elements present. The term "electrically connected" refers to a low resistance electrical connection between the elements that are electrically connected together.

[0044] Terms such as first, second, etc. may be used herein to describe various elements, and these elements should not be limited by these terms. These terms are merely used to distinguish elements from one another. For example, a first element may be referred to as a second element, and similarly, a second element may be referred to as a first element, without departing from the scope of the example embodiments. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0045] Example embodiments are described herein with reference to cross-sectional illustrations that are schematic illustrations of idealized or simplified embodiments (and intermediate structures). As such, variations from the shapes of the illustrations due, for example, to manufacturing techniques and / or tolerances, can be expected. Thus, the regions illustrated in the figures are schematic in nature and their shapes do not necessarily illustrate the actual shapes of regions of a device and are not limiting in scope. It should be understood that the figures and / or drawings accompanying this disclosure are illustrative, non-limiting, and not necessarily drawn to scale.

[0046] It is to be understood that other embodiments may be utilized and structural or logical changes may be made without departing from the spirit and scope as defined by the claims. The description of the embodiments is not intended to be limiting. In particular, elements of the embodiments described below may be combined with elements of different embodiments.

[0047] With reference to the figures, embodiments of the subject device provide an unconventional structure for mitigating or reducing losses in quantum computing systems. In some applications, a TWPD is used as a Josephson traveling-wave parametric amplifier (TWPA). Because losses occur before (or during) the first stage of amplification, the losses are approximately linearly proportional to its effect on the overall quantum efficiency of the system. Because losses in TWPAs are primarily dominated by dielectric losses, the challenge becomes how to reduce these losses to improve efficiency. Embodiments of the subject technology generally provide TWPDs with reduced losses in the capacitor section of the device. It will be appreciated that in one aspect of the subject devices, losses in a quantum computing device are reduced in the dielectric elements, and that the reduction in losses translates into a substantially linearly proportional improvement to the quantum efficiency of the quantum computing device. While the following description is largely described in terms of an amplifier as an example of one embodiment, TWPDs may be used in other applications and configured accordingly in circuits, including, for example, as frequency converters.

[0048] Referring now to FIG. 3, FIG. 3 is an exemplary block diagram of a quantum computing system 200 consistent with illustrative embodiments. Quantum computing system 200 comprises a quantum processor including a plurality of qubits. As illustrated by way of example and not limitation by block 220(N), each qubit system 220(1)-220(N) may comprise a readout resonator 206 coupled to qubit 202. For example, readout resonator 206 impinges on an incoming pulse from control / measurement device 216 at the readout resonator frequency (e.g., 7 GHz). The pulse acts as a measurement to decoherently measure qubit 202, collapsing it into one or zero states, thereby imparting a phase shift to the measurement pulse. The measurement of each readout resonator of each qubit system 220(1)-220(N) may be spread in frequency (e.g., 7.00 GHz, 7.05 GHz, 7.10 GHz, 7.15 GHz, etc.), as previously mentioned.

[0049] Readout resonator 206 may be coupled to filter 210. Measurement fidelity is limited in part by energy relaxation of qubit 202 through resonator 206 into the transmission line, also known as the Purcell effect. One way to suppress this energy relaxation is to use filter 210, which blocks microwave propagation at the qubit frequency. Circulator 214 routes input from control / measurement device 216 to filter 210 and to qubit 202, where reflection measurements tagged with the decohered qubit state are returned to circulator 214 and routed to the input of isolator 218 and to measurement device 240 (e.g., mixer, amplifier, digitizer). This is one embodiment of a reflection measurement. Measurements may also be made in transmission, where circulator 214 is not required.

[0050] In one embodiment, each qubit system 220(1)-220(N) receives its corresponding control signal from control / measurement equipment block 216. There is an isolator 218 coupled to the output of circulator 214. Isolator 218 is a two-port device with unidirectional transmission characteristics. In other words, isolator 218 allows signals to propagate from circulator 214 to TWPD 222 but not from TWPD 222 to circulator 214. In some applications, TWPD 222 may be an amplifier (such as a TWPA). Any power reflected from the load will be absorbed by isolator 218 rather than being reflected back to TWPD 222. For example, isolator 218 may have approximately 40 dB of suppression in the reverse direction. Various embodiments can use different types of isolators that can be integrated. Note that an isolator may be constructed from the circulator and examples therein by terminating one of the three ports with an appropriate resistor (e.g., a 50 Ohm resistor).

[0051] Qubit system 220(N) may include a frequency multiplexer (MUX) 230 operable to receive the output signals of multiple (or all) qubit systems 220(1) through 220(N). MUX 230 combines the signals and provides them to measurement device 240. Measurement device 240 provides an output representative of the state of each qubit from the corresponding qubit system 220(1) through 220(N).

[0052] 4-8, a traveling wave parametric device (TWPD) 100 is shown. FIG. 4 illustrates the architecture of the TWPD 100 according to one embodiment. The TWPD 100 may include a dielectric substrate 135 supporting a layer of thermal oxide 119. The TWPD generally includes a periodic array of Josephson junctions 160 and a plurality of capacitors 150 coupled to at least one of the Josephson junctions 160. The capacitors 150 and the Josephson junctions 160 may be located in a tri-layer structure. The tri-layer structure includes a base (or back) electrode layer 114, a common electrode layer 117, and a layer of aluminum oxide 116 positioned between the base electrode layer 114 and the common electrode layer 117. The tri-layer structure may be positioned on a layer of silicon dioxide 111. The tri-layer structure is supported by the dielectric substrate 135. In some embodiments, the TWPD 100 architecture includes an interlayer dielectric layer 112 supported by the tri-layer structure. The embodiment may include a metal layer 113 supported by an interlevel dielectric layer 112. In an exemplary embodiment, the plurality of capacitors 150 are arranged in an interdigitated configuration in a three-layer structure.

[0053] 5 and 5A, TWPD 100 includes unit cells 140 of junctions 160 and capacitors 150. For illustrative purposes, only a section of TWPD 100 is shown because, in some embodiments, thousands of unit cells 140 may be connected in series, and the illustration would exceed what can be shown on the page. The embodiment shown includes a distributed resonator 120 (which may be similar to resonator 206 of FIG. 3) and a coupling capacitor 130 coupled to the remainder of the circuit.

[0054] As shown in FIGS. 6-8 , each TWPD unit cell 140 includes a capacitor 150 coupled to a Josephson junction 160. The TWPD unit cell 140 may be formed on a top surface 170 of a dielectric substrate 135 (e.g., the interlayer dielectric 113 shown in FIG. 4 ). The capacitor 150 may include a plurality of interdigitated fingers 165 that provide an interdigitated capacitor. For example, the fingers 165 may include a proximal base end 175 that may be connected to a bus 190 and a free distal end 180 that may not be connected to anything. See, for example, FIG. 6 . The fingers 165 may be arranged such that the free end 180 of one finger 165 may be positioned between or midway between the two base ends 175 of adjacent fingers 165 in an alternating manner. Gaps or trenches 155 may separate adjacent fingers 165 from one another. The term "comb" is used to describe the interleaving of fingers 165 similar to the fingers of clasped hands, although it will be understood that adjacent fingers 165 do not necessarily touch each other.

[0055] In an exemplary embodiment, the TWPD unit cell 140 may include a set of interdigitated fingers 165 on one or both sides of the junction 160. Positioning the fingers 165 on both sides of the junction 160 may provide a wider unit cell 140 with approximately the same period as other TWPD cells, thereby maintaining a capacitance value similar to other TWPD cells, but without the losses. The fingers 165 may be formed on or flush with the top surface 170. The set of interdigitated fingers 165 on one side of the junction 160 may be positioned on the same plane as the set of interdigitated fingers 165 on the other side of the junction 160.

[0056] In one embodiment, the interdigitated fingers 165 may be formed in a process that etches away the dielectric material 145, which may be, for example, a thermal film or an epitaxial film. The etch may form trenches 155 between the metal fingers 165. The dielectric 145 between the fingers 165 may be etched away or trenched to reduce the fields present in the dielectric 145. The etch may also further reduce the field participation rate in the capacitor 150, thereby reducing losses. In some embodiments, the etch may provide a consistent width for each finger 165. The width of the new unit cell 140 is typically wider than a conventional TWPA cell (e.g., 20 μm to about 120 μm in the exemplary design shown) to accommodate the capacitor fingers 165 of the target device.

[0057] [Conclusion] It may be surprising that TWPD construction with interdigitated capacitors in a three-layer process offers significant benefits. In such constructions, a lossy dielectric is still present to separate the two metal layers, and many quantum devices, such as qubit processors, target effective loss tangents that are orders of magnitude lower than can be achieved with such a dielectric present. However, in TWPAs, where gain and loss are distributed throughout an extended array of lumped-element components, significant improvements to quantum efficiency can still be achieved with a factor of 2–3 reduction in the loss tangent.

[0058] The results below in Table 1 show that the disclosed structure using interdigitated capacitors does indeed reduce losses by drawing the field out of the lossy dielectric. [Table 1]

[0059] Table 1

[0060] The quantum efficiency of the TWPD increases from 90.8% for conventional designs to 95.5% for the disclosed TWPD structure. Reducing losses in the TWPD can improve the quantum efficiency of the entire readout chain, which is a measure of how much quantum information is retrieved when the qubit state is read out.

[0061] The description of various embodiments of the present teachings has been presented for purposes of illustration, but is not intended to be exhaustive or limited to the disclosed embodiments. Many modifications and variations will be apparent to those skilled in the art without departing from the scope and spirit of the described embodiments. The terminology used herein has been selected to best explain the principles of the embodiments, practical applications, or technical improvements over commercially available technologies, or to enable others skilled in the art to understand the embodiments disclosed herein.

[0062] While the foregoing describes what is believed to be the best mode and / or other examples, it is understood that various modifications may be made therein, that the subject matter disclosed herein may be implemented in a variety of forms and examples, and that the teachings may be applied in numerous applications, only a few of which are described herein. It is intended that the following claims claim any and all applications, modifications, and variations that fall within the true scope of the present teachings.

[0063] The components, steps, features, objects, benefits, and advantages discussed herein are merely exemplary. Neither they nor any discussions related thereto are intended to limit the scope of protection. While various advantages have been discussed herein, it will be understood that not all embodiments necessarily include all advantages. Unless otherwise stated, all measurements, values, ratings, positions, dimensions, sizes, and other specifications set forth in this specification, including the following claims, are approximate and not precise. They are intended to have a reasonable range consistent with the functions to which they relate and that which is customary in the technical field to which they pertain.

[0064] Numerous other embodiments are contemplated, including embodiments having fewer, additional, and / or different components, steps, features, objects, benefits, and advantages, including embodiments in which components and / or steps are arranged and / or ordered differently.

[0065] While the foregoing has been described in conjunction with exemplary embodiments, it is understood that the term "exemplary" is intended as an example only, and not as best or optimal. Except as noted immediately above, nothing mentioned or shown is intended to, or should be construed to, provide the public with any component, step, feature, object, benefit, advantage, or equivalent, whether claimed or not.

[0066] It will be understood that the terms and expressions used herein have the ordinary meanings ascribed to such terms and expressions with respect to their respective fields of inquiry and study, unless a specific meaning is otherwise stated herein. Relative terms such as first and second, and the like, may be used solely to distinguish one entity or action from another, without necessarily requiring or implying any actual relationship or order between such entities or actions. The terms "comprises," "comprising," or any other variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that includes a list of elements may include not only those elements, but other elements not expressly listed or inherent in such process, method, article, or apparatus. An element preceded by "a" or "an" does not, in the absence of further constraints, exclude the presence of additional identical elements in the process, method, article, or apparatus that includes that element.

[0067] This Abstract of the Disclosure is provided to allow the reader to quickly ascertain the nature of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims. Additionally, in the foregoing Detailed Description, it can be seen that various features are grouped together in various embodiments for the purpose of streamlining the disclosure. This method of disclosure is not to be interpreted as reflecting an intention that the claimed embodiments have more features than are expressly recited in each claim. Rather, as the following claims reflect, inventive subject matter lies in less than all features of a single disclosed embodiment. Thus, the following claims are hereby incorporated into the Detailed Description, with each claim standing on its own as separately claimed subject matter.

Claims

1. A traveling wave parametric device (TWPD), comprising: dielectric substrate; A periodic array of Josephson junctions located in a three-layer structure, where: the three-layer structure comprising a common electrode layer, a base electrode layer, and a layer of aluminum oxide positioned between the common electrode layer and the base electrode layer; The three-layer structure is supported by the dielectric substrate; an interlayer dielectric layer supported by said three-layer structure; a metal layer supported by the interlevel dielectric layer; and a plurality of capacitors coupled to the Josephson junctions and arranged in an interdigitated configuration in the three-layer structure; TWPD is equipped with:

2. a first set of the plurality of capacitors positioned on a first side of the Josephson junction; and a second set of the plurality of capacitors positioned on a second side of the Josephson junction; The TWPD of claim 1 further comprising:

3. The TWPD of claim 1 , wherein the plurality of capacitors are positioned in any layer of the three-layer structure.

4. The TWPD of claim 1 , wherein the plurality of capacitors are positioned in the base electrode layer.

5. The TWPD of claim 1 , wherein the plurality of capacitors are positioned in the same plane as the plane of the Josephson junctions.

6. The TWPD of claim 1 , wherein the plurality of capacitors are positioned on the common electrode layer.

7. The TWPD of claim 1 , wherein the interlayer dielectric material is a thermal film.

8. The TWPD of claim 1 , wherein the interlayer dielectric material is an epitaxial film.

9. The TWPD of claim 1 , wherein the TWPD is an amplifier.

10. The TWPD of claim 1 , wherein the TWPD is a frequency converter.

11. 1. A qubit system comprising: Cubitt; a resonator coupled to the qubit; and a traveling wave parametric device (TWPD) coupled to the resonator; The TWPD comprises: dielectric substrate; A periodic array of Josephson junctions located in a three-layer structure, where: the three-layer structure includes a common electrode layer, a base electrode layer, and a layer of aluminum oxide positioned between the common electrode layer and the base electrode layer; The three-layer structure is supported by the dielectric substrate; an interlayer dielectric layer supported by said three-layer structure; a metal layer supported by the interlevel dielectric layer; and a plurality of capacitors coupled to the Josephson junctions and arranged in an interdigitated configuration in the three-layer structure; A qubit system having

12. 12. The qubit system of claim 11 , wherein each capacitor of the plurality of capacitors is positioned on the same plane as each other capacitor in the plurality of capacitors.

13. The qubit system of claim 11 , wherein the plurality of capacitors are positioned in the same plane as the plane of the Josephson junctions.

14. The qubit system of claim 11 , wherein the interlayer dielectric material is a thermal film.

15. The qubit system of claim 11 , wherein the interlayer dielectric material is an epitaxial film.

16. a first set of the plurality of capacitors positioned on a first side of the Josephson junction; and a second set of the plurality of capacitors positioned on a second side of the Josephson junction; The qubit system of claim 11 further comprising:

17. 1. A method for fabricating a traveling wave parametric device (TWPD), comprising: forming Josephson junctions in a three-layer structure on a dielectric substrate; patterning capacitors on the metal surface of the three-layer structure in an interdigitated arrangement; and etching away trenches in the interlayer dielectric material present between the capacitors; A method comprising:

18. 18. The method of claim 17, further comprising forming the arrangement of interdigitated capacitors on a single plane.

19. 20. The method of claim 18, further comprising forming the arrangement of the interdigitated capacitors in sets positioned on either side of the Josephson junction.

20. 20. The method of claim 17, further comprising forming the arrangement of interdigitated capacitors in any layer of the three-layer structure.

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