Highly selective silicon oxide removal method

Abstract

A semiconductor processing method may include delivering a fluorine-containing precursor to a processing region of a semiconductor processing chamber. A substrate may be disposed within the processing region. The substrate may include an exposed region of silicon- and oxygen-containing material. The substrate may include an exposed region of liner material. The method may include delivering a hydrogen-containing precursor to the semiconductor processing region. The method may include contacting the substrate with the fluorine-containing precursor and the hydrogen-containing precursor. The method may include selectively removing at least a portion of the exposed silicon- and oxygen-containing material.

Description

[Technical Field]

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0001] This application claims priority to U.S. patent application Ser. No. 17 / 944,540, filed Sep. 14, 2022, the entire disclosure of which is incorporated herein by reference for all purposes.

[0002]

[0002] The present technology relates to semiconductor systems, processes, and apparatus, and more particularly to systems and methods for selectively etching material layers on semiconductor devices. [Background technology]

[0003] Integrated circuits are made possible by processes that create intricately patterned layers of material on substrate surfaces. Creating patterned materials on a substrate requires a controlled method for removing exposed material. Chemical etching is used for a variety of purposes, including transferring a photoresist pattern to an underlying layer, thinning a layer, or narrowing the lateral dimensions of features already present on a surface. It is often desirable to have an etching process that etches some materials faster than others, facilitating, for example, a pattern transfer process or individual material removal. Such an etching process is said to be selective to the first material. As a result of the diversity of materials, circuits, and processes, etching processes have been developed that are selective to a variety of materials. However, deposition processes continue to be performed across a substrate, typically utilizing a blanket coat or conformal fill.

[0004] As device sizes continue to shrink in next-generation devices, selectivity may play a larger role when forming only a few nanometers of material in a particular layer, especially when the material is critical in transistor formation. While many different etch process selectivities have been developed between different materials, standard selectivities may no longer be adequate at the scale of current and future devices. In addition, process queue times continue to increase based on the number of masking, formation, and removal steps required to form and protect various critical dimensions of features across a device, while patterning and formation occurs elsewhere on the substrate.

[0005]

[0005] Therefore, there is a need for improved systems and methods that can be used to manufacture high quality devices and structures. These and other needs are addressed by the present technology. Summary of the Invention

[0006] An exemplary semiconductor processing method may include delivering a fluorine-containing precursor to a processing region of a semiconductor processing chamber. A substrate may be disposed within the processing region. The substrate may include exposed regions of silicon- and oxygen-containing material. The substrate may include exposed regions of liner material. The method may include delivering a hydrogen-containing precursor to the semiconductor processing region. The method may include contacting the substrate with the fluorine-containing precursor and the hydrogen-containing precursor. The method may include selectively removing at least a portion of the exposed silicon- and oxygen-containing material.

[0007] In some embodiments, the fluorine-containing precursor can be or include hydrogen fluoride. The hydrogen-containing precursor can be or include ammonia. The exposed region of the silicon- and oxygen-containing material can be an oxidized surface of the substrate. The exposed region of the liner material can be a spacer material having a low dielectric constant. A temperature within the semiconductor processing chamber can be maintained at or below about 200° C. A pressure within the semiconductor processing chamber can be maintained at or below about 20 Torr. The method can include performing a thermal anneal after contacting the substrate with the fluorine-containing precursor and the hydrogen-containing precursor. The thermal anneal can selectively remove a portion of the exposed region of the silicon- and oxygen-containing material by sublimation.

[0008] Some embodiments of the present technology include a semiconductor processing method. The method may include: i) delivering a fluorine-containing precursor and a hydrogen-containing precursor to a processing region of a semiconductor processing chamber. A substrate including an exposed region of a silicon- and oxygen-containing material may be disposed within the processing region. The method may include: ii) contacting the exposed region of the silicon- and oxygen-containing material with a fluorine-containing precursor and a hydrogen-containing precursor. The method may include iii) forming silicon- and oxygen-containing by-products on the substrate. The method may include iv) annealing the substrate. The annealing may sublimate at least a portion of the silicon- and oxygen-containing by-products.

[0009] In some embodiments, steps i) through iv) can be one cycle. The semiconductor processing method can include at least two cycles. Each cycle can be performed for a time period of about 200 seconds or less. A portion of the silicon- and oxygen-containing by-products can be removed with a selectivity ratio of about 3:1 or greater relative to the exposed areas of the liner material. The flow rate of the fluorine-containing precursor can be about 500 sccm or less. The flow rate of the hydrogen-containing precursor can be about 100 sccm or less.

[0010] Some embodiments of the present technology include a semiconductor processing method. The method may include delivering a fluorine-containing precursor to a processing region of a semiconductor processing chamber. A substrate is positioned within the processing region. The substrate may include an exposed region of a silicon- and oxygen-containing material. The substrate may include an exposed region of a liner material. The method may include delivering a hydrogen-containing precursor to the semiconductor processing region. The method may include contacting the substrate with the fluorine-containing precursor and the hydrogen-containing precursor. The method may include annealing the substrate. Annealing the substrate may sublimate at least a portion of the exposed region of the silicon- and oxygen-containing material relative to the exposed region of the liner material.

[0011] In some embodiments, annealing the substrate can include positioning the substrate proximate to a showerhead of a semiconductor processing chamber. A selectivity between the exposed region of the silicon- and oxygen-containing material relative to the exposed region of the liner material can be about 3:1 or greater. A flow rate ratio of the fluorine-containing precursor to the hydrogen-containing precursor can be about 10:1 or less. A removal rate of the exposed region of the silicon- and oxygen-containing material can be about 0.3 Å / sec or greater. The processing region can be maintained plasma-free during the semiconductor processing method.

[0012] The techniques described herein may provide many advantages over conventional systems and techniques. For example, the techniques described herein may enable removal while protecting other features or materials on the substrate. Additionally, the process may selectively remove silicon-oxygen materials relative to other exposed materials on the substrate. These and other embodiments, along with many of their advantages and features, are described in more detail in the following specification and accompanying drawings.

[0013] A further understanding of the nature and advantages of the disclosed technology may be realized by reference to the remaining portions of the specification and the drawings. [Brief explanation of the drawings]

[0014] [Figure 1] 1 illustrates a top view of an exemplary processing system, in accordance with an embodiment of the present technique. [Figure 2A]

[0015] 1 shows a schematic cross-sectional view of an exemplary processing chamber, in accordance with an embodiment of the present technique; [Figure 2B]

[0016] 1 shows a detailed view of an exemplary showerhead in accordance with an embodiment of the present technique. [Figure 3]

[0017] FIG. 1 illustrates a bottom view of an exemplary showerhead, in accordance with embodiments of the present technique. [Figure 4]

[0018] 1 illustrates selected steps in a method of forming a semiconductor structure, according to an embodiment of the present technique. [Figure 5A]

[0019] 1 shows a schematic cross-sectional view of an exemplary substrate, in accordance with an embodiment of the present technique; [Figure 5B] 1 shows a schematic cross-sectional view of an exemplary substrate, in accordance with an embodiment of the present technique; [Figure 5C] 1 shows a schematic cross-sectional view of an exemplary substrate, in accordance with an embodiment of the present technique;

[0015]

[0020] Some of the drawings are included as schematic diagrams. It should be understood that the drawings are for illustrative purposes and should not be considered to scale unless specifically stated to be to scale. Furthermore, as schematic diagrams, the drawings are provided to aid in understanding and may not include all aspects or information compared to realistic depictions and may include material that is emphasized for illustrative purposes.

[0016]

[0021] In the accompanying figures, similar components and / or features may have the same reference numerals. Furthermore, various components of the same type may be distinguished according to the reference numeral, with a letter distinguishing between the similar components. When only a first reference numeral is used in this specification, the description is applicable to any of the similar components having the same first reference numeral, regardless of the letter. DETAILED DESCRIPTION OF THE INVENTION

[0017]

[0022] Dilute acids can be used in many different semiconductor processes to clean substrates or remove materials from such substrates. For example, dilute hydrofluoric acid can be an effective etchant for silicon oxide and other materials and can be used to remove materials from the substrate surface. After the etching or cleaning process is complete, the acid can be dried and removed from the wafer or substrate surface. The use of dilute hydrofluoric acid (DHF) is sometimes referred to as "wet" etching, and the diluent is often water. Additional etching processes can be used that utilize precursors delivered to the substrate. For example, plasma-enhanced processes can also selectively etch materials by enhancing precursors through a plasma, and dry etching, including reactive ion etching, can be performed.

[0018]

[0023] While wet etchants using aqueous solutions or processes may work effectively for certain substrate structures, these processes may not selectively remove silicon oxide and other materials from the substrate surface. For example, utilizing water during an etching process can cause problems when placed on a substrate containing metallic materials. For example, certain subsequent manufacturing processes (e.g., deepening gaps, removing oxide dielectrics, or other processes for removing oxygen-containing materials) may be performed after some metallization has formed on the substrate. If water is used during etching, an electrolyte may be generated, and if the electrolyte comes into contact with the metallic material, galvanic corrosion may occur between the dissimilar metals, and the metal may be corroded or displaced in various processes. In addition, conventional techniques using dilute acids may have selectivity performance issues, for example, when removing silicon oxide from the substrate surface, and may result in undesirable removal of liner and / or spacer materials.

[0019]

[0024] The present technology overcomes the above-mentioned problems by developing a selective etching process for removal or cleaning. By utilizing a selective etching process performed in a specific apparatus, the described process may overcome problems associated with the prior art by performing a reaction that may enhance the removal of the target material while performing a dry etching process that may reduce the impact on the surface. Additionally, the materials and conditions used may enable improved material removal compared to conventional techniques.

[0020]

[0025] While the remainder of the disclosure will routinely identify specific etching processes utilizing the disclosed technology, it will be readily understood that the systems and methods are equally applicable to a variety of other etching and cleaning processes that may occur in the described chambers. Thus, the present technology should not be considered limited for use with only the described etching processes. This disclosure will describe one possible system and chamber that can be used with the present technology to perform a particular removal step, before describing an exemplary process sequence steps according to the present technology.

[0021]

[0026] 1 shows a top view of one embodiment of a deposition, etch, bake, and cure chamber processing system 100, according to an embodiment. In this figure, a pair of front opening unified pods (FOUPs) 102 supply substrates of various sizes. These substrates are received by a robotic arm 104 and positioned in a low-pressure holding area 106, which is then positioned in one of the substrate processing chambers 108a-f and placed in tandem sections 109a-c. A second robotic arm 110 can be used to transfer substrate wafers from the holding area 106 to the substrate processing chambers 108a-f and back. Each substrate processing chamber 108a-108f can be equipped to perform numerous substrate processing steps, including cyclical layer deposition (CLD), atomic layer deposition (ALD), chemical vapor deposition (CVD), physical vapor deposition (PVD), wet etching, pre-cleaning, degassing, alignment, and other substrate processing, as well as the dry etching processes and selective deposition described herein.

[0022]

[0027] The substrate processing chambers 108a-f may include one or more system components for depositing, annealing, curing, and / or etching a dielectric film on a substrate wafer. In one configuration, two pairs of processing chambers (e.g., 108c-108d and 108e-108f) may be used to deposit a dielectric or metal-containing material on a substrate, and a third pair of processing chambers (e.g., 108a-108b) may be used to etch the deposited dielectric. In another configuration, all three pairs of chambers (e.g., 108a-108f) may be configured to etch a dielectric film on a substrate. Any one or more of the processes described may be performed in chambers separate from the fabrication systems shown in various embodiments.

[0023]

[0028] In some embodiments, the chambers specifically include at least one etch chamber and at least one deposition chamber. The combined inclusion of these chambers on the processing side of the factory interface allows all etching and deposition processes described below to be performed in a controlled environment. For example, a vacuum environment can be maintained on the processing side of the holding area 106, thereby, in embodiments, maintaining all chambers and transfers under vacuum. This also prevents water vapor and other air components from contacting the substrate being processed. It will be understood that additional configurations of deposition chambers, etch chambers, annealing chambers, and curing chambers for dielectric films are contemplated by the system 100.

[0024]

[0029] 2A shows a cross-sectional view of an exemplary processing chamber system 200 having separate plasma generation regions within the processing chamber. During etching of a film (e.g., titanium nitride, tantalum nitride, tungsten, cobalt, aluminum oxide, tungsten oxide, silicon, polysilicon, silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, etc.), process gases can flow through gas injection assembly 205 into first plasma region 215. A remote plasma system (RPS) 201 may optionally be included in the system and can process a first gas, which then travels through gas injection assembly 205. Injection assembly 205 can include two or more separate gas delivery channels, and if a second channel (not shown) is included, can bypass RPS 201.

[0025]

[0030] Shown are a cooling plate 203, a faceplate 217, an ion suppressor 223, a showerhead 225, and a pedestal 265 upon which a substrate 255 is disposed, each of which may be included according to an embodiment. The pedestal 265 or substrate support may have heat exchange channels through which a heat exchange fluid flows to control the temperature of the substrate, and the heat exchange channels may operate to heat and / or cool the substrate or wafer during processing. The wafer support platter of the pedestal 265, which may comprise aluminum, ceramic, or a combination thereof, may also be resistively heated to reach relatively high temperatures (e.g., from about 100° C. or less to about 1100° C. or more) using embedded resistive heating elements.

[0026]

[0031] The faceplate 217 may be pyramidal, conical, or another similar structure that is narrow at the top and widens toward the bottom. Additionally, the faceplate 217 may be flat, as shown, and may include multiple through-channels used to distribute process gases. Plasma-generating gases and / or plasma-excited species may pass through multiple holes in the faceplate 217, as shown in FIG. 2B, for more uniform distribution into the first plasma region 215, depending on the use of the RPS 201.

[0027]

[0032] An exemplary configuration may include gas inject assembly 205 communicating with gas feed region 258 separated from first plasma region 215 by faceplate 217, allowing gases / species to flow into first plasma region 215 through holes in faceplate 217. Structural and operational features may be selected to prevent bulk backflow of plasma from first plasma region 215 into feed region 258, gas inject assembly 205, and fluid delivery system 210. Faceplate 217, or the conductive top of the chamber, and showerhead 225 are shown with an insulating ring 220 disposed between these components, allowing an AC potential to be applied to faceplate 217 relative to showerhead 225 and / or ion suppressor 223. Insulating ring 220 may be positioned between faceplate 217 and showerhead 225 and / or ion suppressor 223, allowing for the formation of a capacitively coupled plasma (CCP) in the first plasma region. Additionally, baffles (not shown) may be positioned within first plasma region 215 or otherwise coupled to gas injector assembly 205 to affect the flow of fluid through gas injector assembly 205 and into the region.

[0028]

[0033] The ion suppressor 223 may include a plate or other shape defining a plurality of apertures across its structure, configured to suppress the migration of ionic-charged species exiting the first plasma region 215 while allowing uncharged neutral or radical species to pass through the ion suppressor 223 and into the activated gas supply region between the suppressor and the showerhead. In embodiments, the ion suppressor 223 may include a perforated plate with various aperture configurations. These uncharged species may include highly reactive species that are carried with a less reactive carrier gas through the apertures. As discussed above, the migration of ionic species through the apertures can be reduced, and in some cases, completely suppressed. Controlling the amount of ionic species that pass through the ion suppressor 223 advantageously provides improved control over the gas mixture that is brought into contact with the underlying wafer substrate, thereby providing improved control over the deposition and / or etching characteristics of the gas mixture. For example, adjusting the ion concentration of the gas mixture can affect etch selectivity (e.g., SiN). x :SiO x Etching ratio, Si:SiO x The etching ratio, etc. can be significantly changed. In alternative embodiments where deposition is performed, it is also possible to change the balance of conformal to flowable deposition on the dielectric material.

[0029]

[0034] The plurality of apertures in the ion suppressor 223 can be configured to control the passage of activated gas (i.e., ionic, radical, and / or neutral species) through the ion suppressor 223. For example, the aspect ratio of the apertures, i.e., the diameter to length of the apertures, and / or the geometry of the apertures can be controlled to reduce the rate of ionic charged species in the activated gas passing through the ion suppressor 223. The apertures in the ion suppressor 223 can include a tapered portion facing the plasma excitation region 215 and a cylindrical portion facing the showerhead 225. The cylindrical portion can be shaped and sized to control the rate of ionic species passing to the showerhead 225. An adjustable electrical bias can be applied to the ion suppressor 223, which is an additional means of controlling the rate of ionic species passing through the suppressor.

[0030]

[0035] The ion suppressor 223 can function to reduce or eliminate the amount of ionic charged species that travel from the plasma generation region to the substrate. Uncharged neutral and radical species can still pass through the ion suppressor openings and react with the substrate. Note that complete elimination of ionic charged species within the reaction region around the substrate may not be performed in some embodiments. In certain cases, ionic species are intended to reach the substrate to perform etching and / or deposition processes. In such cases, the ion suppressor can help control the concentration of ionic species within the reaction region at a constant level that is process-supportive.

[0031]

[0036] The showerhead 225, in combination with the ion suppressor 223, can enable the plasma present in the first plasma region 215 to avoid direct excitation of gases in the substrate processing region 233, while still allowing excited species to migrate from the chamber plasma region 215 into the substrate processing region 233. In this manner, the chamber can be configured to prevent the plasma from contacting the substrate 255 being etched. This advantageously protects various intricate structures and films patterned on the substrate, which may be damaged, misaligned, or distorted if the generated plasma directly contacts them. Furthermore, if the plasma is allowed to contact or approach the substrate level, the rate at which oxide species etch may increase. Thus, if the exposed region of material is an oxide, keeping the plasma remote from the substrate can further protect this material.

[0032]

[0037] The processing system may further include a power supply 240 electrically connected to the processing chamber, which supplies power to the faceplate 217, the ion suppressor 223, the showerhead 225, and / or the pedestal 265 to generate a plasma in the first plasma region 215 or the processing region 233. The power supply may be configured to supply an adjustable amount of power to the chamber depending on the process being performed. Such a configuration may enable the use of an adjustable plasma in the process being performed. Unlike remote plasma units, which often exhibit an on or off function, an adjustable plasma may be configured to supply a specific amount of power to the plasma region 215. This may enable the development of specific plasma characteristics, which may separate precursors in specific ways and enhance the etch profile produced by those precursors.

[0033]

[0038] Plasma may be ignited in either the chamber plasma region 215 above the showerhead 225 or the substrate processing region 233 below the showerhead 225. In embodiments, the plasma formed in the substrate processing region 233 may be a DC-biased plasma formed with the pedestal acting as an electrode. The plasma exists in the chamber plasma region 215 and may generate radical precursors, for example, from the inflow of a fluorine-containing precursor or other precursor. An AC voltage, typically in the radio frequency (RF) range, may be applied between a conductive top portion of the processing chamber, such as the faceplate 217, and the showerhead 225 and / or ion suppressor 223 to ignite plasma in the chamber plasma region 215 during deposition. The RF power supply may generate a high RF frequency of 13.56 MHz, but may also generate other frequencies, either alone or in combination with the 13.56 MHz frequency.

[0034]

[0039] 2B is a detailed view 253 of features that affect the distribution of process gas through faceplate 217. As shown in FIGS. 2A and 2B, the intersection of faceplate 217, cooling plate 203, and gas inject assembly 205 defines gas delivery region 258, which can be supplied with process gas from gas inject assembly 205. Gas can fill gas delivery region 258 and flow through apertures 259 in faceplate 217 to first plasma region 215. Apertures 259 can be configured to direct flow in a substantially single direction, which can allow process gas to enter processing region 233 but can partially or completely prevent backflow into gas delivery region 258 after traversing faceplate 217.

[0035]

[0040] The gas distribution assembly, such as showerhead 225, used in processing chamber section 200 is referred to as a dual channel showerhead (DCSH), and is shown in more detail in the embodiment depicted in Figure 2B. A dual channel showerhead can accommodate etching processes that allow for separation of etchants outside of processing region 233, limiting their interaction with chamber components and with each other before being delivered into the processing region.

[0036]

[0041] The showerhead 225 may include an upper plate 214 and a lower plate 216. The plates may be coupled together to define a space 218 between the plates. The plates may be coupled to provide a first fluid channel 219 through the upper and lower plates and a second fluid channel 221 through the lower plate 216. The formed channel may be configured to provide fluid access from the space 218 through the lower plate 216 only via the second fluid channel 221, and the first fluid channel 219 may be fluidically isolated from the space 218 between the plates and the second fluid channel 221. The space 218 may be fluidically accessible through a side of the showerhead 225.

[0037]

[0042] 3 illustrates a bottom view of a showerhead 325 for use in a processing chamber, according to an embodiment. The showerhead 325 may correspond to the showerhead 225 illustrated in FIG. 2A. The through-holes 365, which represent the first fluid channels 219, may have multiple shapes and configurations to control and influence the flow rate of precursors through the showerhead 225. Small holes 375, which represent the second fluid channels 221, may be more evenly distributed over the surface of the showerhead, even among the through-holes 365, and may help to provide more uniform mixing of the precursors as they exit the showerhead than other configurations.

[0038]

[0043] FIG. 4 illustrates a method 400 for forming a semiconductor structure, many of the steps of which may be performed, for example, in chamber 200, as described above. Method 400 may include one or more steps prior to the start of the method, including front-end processing, polishing, cleaning, deposition, etching, or any other steps that may be performed before the described steps. The method may include numerous optional steps, as illustrated in the figures, that may or may not be particularly relevant to methods according to the present technology. For example, many of the steps are described to provide greater scope for structural configurations, but are not critical to the present technology or may be implemented by alternative methods, as described further below. Method 400 describes the steps illustrated generally in FIGS. 5A-5C, which will be described in connection with the steps of method 400. It should be understood that FIGS. 5A-5C illustrate only partial schematic views, and that a substrate may include any number of transistor sections having the configurations shown in the figures. The steps of method 400 may be performed to form a bottom insulating layer to prevent current leakage through the bottom nanowire channel. The steps of method 400 may also be performed to limit or eliminate RIE and / or ion implantation processes and to prevent damage to silicon-containing surfaces for defect-free source or drain formation. The steps of method 400 may further be performed to limit or eliminate masking steps and / or RIE processes and to reduce process queue times.

[0039]

[0044] As shown in FIG. 5A , method 400 can begin in optional step 405 by forming a multi-layer structure on a substrate 505 and performing post-processing of structure 500. Substrate 505 can be made of or include silicon or some other semiconductor substrate material. The multi-layer structure can include layers of various silicon-containing materials. The multi-layer structure can include polysilicon material 510. Polysilicon material 510 can be formed on substrate 505. Silicon nitride material 515 can be formed on polysilicon material 510. Oxide material 520 can be formed on silicon nitride material 515. Oxide material 520 can include, for example, silicon oxide or any other oxide material. A liner material 525, or spacer material, can be formed on substrate 505, polysilicon material 510, silicon nitride material 515, and oxide material 520. Liner material 525 can be, for example, a material containing silicon and nitrogen. In an embodiment, the liner material can be silicon nitride. In other embodiments, the liner material 525 may be a low dielectric constant material such as silicon oxynitride (SiON) or silicon oxycarbonitride (SiOCN). As described in more detail below, the multilayer structure may be subsequently developed into various transistor structures.

[0040]

[0045] Also in optional step 405, post-formation processes may be performed on structure 500. As previously described, front-end processes, polishing, cleaning, deposition, etching, or any other steps may be performed. For example, as shown in FIG. 5B, an etching step (such as a reactive ion etching step) may be performed to form a recess in substrate 505. The reactive ion etching step, which may use an oxygen-containing precursor, may form silicon- and oxygen-containing material 530 on substrate 505. In embodiments, silicon- and oxygen-containing material 530 may be an oxidized surface of substrate 505. The reactive ion etching step may also remove a portion of liner material 525 (such as liner material 525 overlying substrate 505). The reactive ion etching step may also damage or remove a portion of liner material 525 overlying oxide material 520.

[0041]

[0046] In step 410, method 400 may include delivering a fluorine-containing precursor to a processing region of a semiconductor processing chamber (such as chamber 200), as previously described. In step 410, as shown in FIG. 5B, substrate 505 may include exposed regions of silicon- and oxygen-containing material 530 and exposed regions of liner material 525. An exemplary fluorine-containing precursor may be hydrogen fluoride (HF). Other fluorine sources may be used in combination with or as an alternative to hydrogen fluoride. In some embodiments, the fluorine-containing precursor may be or include atomic fluorine, diatomic fluorine, hydrogen fluoride, nitrogen trifluoride, carbon tetrafluoride, xenon difluoride, and various other fluorine-containing precursors used or available in semiconductor processing.

[0042]

[0047] The flow rate of the fluorine-containing precursor can be about 500 sccm or less, and can be about 450 sccm or less, about 400 sccm or less, about 350 sccm or less, about 300 sccm or less, about 250 sccm or less, about 200 sccm or less, about 150 sccm or less, about 100 sccm or less, about 75 sccm or less, about 50 sccm or less, or less.

[0043]

[0048] In step 415, the method 400 can include delivering a hydrogen-containing precursor to a processing region of a semiconductor processing chamber. The hydrogen-containing precursor can also contain nitrogen. Thus, the hydrogen-containing precursor can include an amine group. An amine group is defined as having a nitrogen with a lone pair of electrons (typically designated N:). For example, the hydrogen-containing precursor can be or include ammonia, methylamine, ethylamine, diethylamine, methylethyldiamine, and various other hydrogen-containing precursors used or available in semiconductor processing.

[0044]

[0049] The flow rate of the hydrogen-containing precursor can be about 100 sccm or less, and can be about 90 sccm or less, about 80 sccm or less, about 70 sccm or less, about 60 sccm or less, about 50 sccm or less, about 40 sccm or less, about 30 sccm or less, about 20 sccm or less, about 15 sccm or less, about 10 sccm or less, or less. The flow rates of the fluorine-containing precursor and the hydrogen-containing precursor can be low enough to minimize etching or removal of other materials in the structure 500, while etching and / or forming by-products that sublimate in exposed areas of the silicon- and oxygen-containing material 530.

[0045]

[0050] As mentioned above, the flow rate of the fluorine-containing precursor can be, for example, about 500 sccm or less, and the flow rate of the hydrogen-containing precursor can be, for example, about 100 sccm or less. The flow rate ratio of the fluorine-containing precursor to the hydrogen-containing precursor is about 10:1 or less. If the flow rate ratio is about 10:1 or more, the partial pressure of the fluorine-containing material increases, which can reach a stage where the selectivity for removing silicon- and oxygen-containing materials decreases. Therefore, the flow rate ratio of the fluorine-containing precursor to the hydrogen-containing precursor can be about 9:1 or less, and can be about 8:1 or less, about 7:1 or less, about 6:1 or less, about 5:1 or less, about 4:1 or less, about 3:1 or less, about 2:1 or less, or less. However, increasing the flow rate of the fluorine-containing precursor to the hydrogen-containing precursor can increase the etch rate of silicon- and oxygen-containing materials. Therefore, the flow rate ratio of the fluorine-containing precursor to the hydrogen-containing precursor can be about 2:1 or more, about 3:1 or more, about 4:1 or more, about 5:1 or more, or even higher.

[0046]

[0051] The fluorine-containing precursor and the hydrogen-containing precursor may be delivered to the processing region separately, or in embodiments, may be mixed or combined before being delivered to the processing region. The fluorine-containing precursor and the hydrogen-containing precursor may also be delivered using any number of carrier gases, which may include nitrogen, helium, argon, or other inert gases.

[0047]

[0052] In step 420, the method 400 may include contacting the substrate 505 and the multilayer structure with a fluorine-containing precursor and a hydrogen-containing precursor. By contacting the substrate 505 with the fluorine-containing precursor and the hydrogen-containing precursor, by-products may be formed from exposed regions of the silicon- and oxygen-containing material 530 on the substrate 505. The fluorine-containing precursor and the hydrogen-containing precursor may interact with the exposed regions of the silicon- and oxygen-containing material 530 on the substrate 505 to form solid by-products, which may include ammonium silicofluoride ((NH4)2SiF6). Gaseous by-products may be formed, which may include silicon tetrafluoride (SiF4) and hydrogen (such as diatomic hydrogen (H2)), which may outgas. As described below, solid by-products, such as ammonium silicofluoride ((NH4)2SiF6), may be removed, for example, by sublimation.

[0048]

[0053] Process conditions can affect the steps performed in method 400. Each step of method 400 can, in embodiments, be performed at a constant temperature, while in some embodiments, the temperature can be adjusted between various steps. In some embodiments of the present technology, method 400 can be performed at substrate, pedestal, and / or chamber temperatures of about 200°C or less, and can be performed at temperatures of about 180°C or less, about 160°C or less, about 140°C or less, about 120°C or less, about 100°C or less, about 80°C or less, about 60°C or less, about 40°C or less, about 30°C or less, about 20°C or less, about 15°C or less, about 10°C or less, or lower. Temperatures can be maintained within these ranges, narrower ranges included in these ranges, or any temperature between any of these ranges.

[0049]

[0054] The pressure within the semiconductor processing chamber can also affect the processes performed. Thus, in some embodiments, the pressure may be maintained at about 20 Torr or less, about 15 Torr or less, about 10 Torr or less, about 9 Torr or less, about 8 Torr or less, about 7 Torr or less, about 6 Torr or less, about 5 Torr or less, about 4 Torr or less, about 3 Torr or less, about 2 Torr or less, about 1 Torr or less, about 0.8 Torr or less, about 0.6 Torr or less, about 0.4 Torr or less, about 0.2 Torr or less, or less. The pressure may also be maintained at any pressure within these ranges, within narrower ranges encompassed by these ranges, or between any of these ranges. Adding further control to the process, the partial pressure of the fluorine-containing precursor may be adjusted to adjust selectivity. For example, as the partial pressure of the fluorine-containing precursor increases, the selectivity of removal of silicon- and oxygen-containing material 530 may decrease. Thus, the partial pressure of the fluorine-containing precursor can be maintained at about 0.05 Torr or less to maintain selectivity for removal of silicon and oxygen-containing material 530. For example, the partial pressure of the fluorine-containing precursor can be maintained at about 0.045 Torr or less, about 0.04 Torr or less, about 0.035 Torr or less, about 0.03 Torr or less, about 0.025 Torr or less, about 0.02 Torr or less, about 0.015 Torr or less, about 0.01 Torr, or less.

[0050]

[0055] In embodiments, method 400 may be a purely thermal process. In some embodiments, the processing region is maintained plasma-free during method 400. It is also contemplated that a plasma may be formed from a fluorine-containing precursor and / or a hydrogen-containing precursor. The plasma of one or both of the precursors may be formed within the processing region of a semiconductor processing chamber, or alternatively, may be formed within a remote plasma system. However, unlike conventional techniques, the present technique may not require the formation of a plasma to effectively remove silicon- and oxygen-containing materials selectively exposed to other materials described herein.

[0051]

[0056] In optional step 425, method 400 can include performing a thermal anneal after contacting substrate 505 with the fluorine-containing precursor and the hydrogen-containing precursor. The thermal anneal can selectively remove exposed portions of silicon- and oxygen-containing material (e.g., byproducts formed during contacting substrate 505 and silicon- and oxygen-containing material 530 with the fluorine-containing precursor and the hydrogen-containing precursor) by sublimation. During step 425, substrate 505 can be elevated, for example, using lift pins in the substrate support, and positioned near a showerhead of the semiconductor processing chamber. The showerhead can be at a higher temperature than the substrate support, thereby increasing the temperature of the substrate during step 425. Step 425 can increase the temperature of the substrate to about 80° C. or higher, about 90° C. or higher, about 100° C. or higher, about 110° C. or higher, about 120° C. or higher, about 130° C. or higher, about 140° C. or higher, about 150° C. or higher, or higher. One or more inert gases may be supplied to the processing chamber to facilitate sublimation of the by-products during step 425. For example, one or more hydrogens (e.g., diatomic hydrogen, argon, neon, or xenon) may be supplied during step 425.

[0052]

[0057] 5C , in step 430, the method 400 may include selectively removing at least a portion of the exposed silicon- and oxygen-containing material 530. The removal rate of the exposed regions of the silicon- and oxygen-containing material 530 may be about 0.3 Å / sec or greater, about 0.4 Å / sec or greater, about 0.5 Å / sec or greater, about 0.6 Å / sec or greater, about 0.7 Å / sec or greater, about 0.8 Å / sec or greater, about 0.9 Å / sec or greater, about 1.0 Å / sec or greater, or greater. However, to maintain high selectivity, the flow rate of the fluorine-containing precursor and / or the hydrogen-containing precursor is provided to maintain the removal rate of the exposed regions of the silicon- and oxygen-containing material 530 at about 1.5 Å / sec or less (e.g., about 1.3 Å / sec or less, or about 1.0 Å / sec or less).

[0053]

[0058] In optional step 435, method 400 may include repeating steps 410-430 for one or more additional cycles. Steps 410-430 may define one cycle of method 400. If the removal time is greater than or equal to about 200 seconds, selectivity may begin to decrease due to prolonged contact between the precursor and the liner material 525. Thus, each cycle may be less than or equal to about 200 seconds, less than or equal to about 190 seconds, less than or equal to about 180 seconds, less than or equal to about 170 seconds, less than or equal to about 160 seconds, less than or equal to about 150 seconds, less than or equal to about 140 seconds, less than or equal to about 130 seconds, less than or equal to about 120 seconds, less than or equal to about 110 seconds, less than or equal to about 100 seconds, less than or equal to about 90 seconds, less than or equal to about 80 seconds, less than or equal to about 70 seconds, less than or equal to about 60 seconds, less than or equal to about 50 seconds, less than or equal to about 40 seconds, less than or equal to about 30 seconds, less than or equal to about 20 seconds, less than or equal to about 10 seconds, or may be shorter. Steps 410-430 may be repeated at least two, at least three, at least four, at least five, at least six, or more times to remove a desired amount of exposed silicon- and oxygen-containing material 530. The cyclic etching and by-product sublimation process may suppress etching or removal of liner material 525 and allow for highly selective etching or removal of silicon- and oxygen-containing material 530.

[0054]

[0059] By performing processes according to embodiments of the present technology, silicon- and oxygen-containing materials can be selectively etched relative to other materials, including any of the materials previously described. As previously described, for example, the present technology can selectively etch silicon- and oxygen-containing materials relative to exposed regions of low-k materials, including SiON, SiOCN, or other dielectrics and / or silicon nitride. Embodiments of the present technology may etch silicon- and oxygen-containing materials relative to low-k materials at a ratio of at least about 1.5:1, and may etch silicon- and oxygen-containing materials relative to exposed low-k materials at a selectivity ratio of about 2.0:1 or greater, about 2.5:1 or greater, about 3.0:1 or greater, about 3.5:1 or greater, about 4.0:1 or greater, about 4.5:1 or greater, about 5.0:1 or greater, or greater. Embodiments of the present technology may etch silicon and oxygen-containing materials relative to silicon nitride at a ratio of at least about 30:1, and may etch silicon and oxygen-containing materials relative to exposed silicon nitride at selectivity ratios of about 35:1 or greater, about 40:1 or greater, about 45:1 or greater, about 50:1 or greater, about 55:1 or greater, about 60:1 or greater, or greater. For example, etches performed according to some embodiments of the present technology may etch silicon and oxygen-containing materials while substantially or essentially preserving any of the other silicon-containing materials described above.

[0055]

[0060] In the foregoing description, for purposes of explanation, numerous details are presented in order to facilitate an understanding of various embodiments of the present technology. However, it will be apparent to one skilled in the art that particular embodiments may be practiced without some of these details, or with additional details.

[0056]

[0061] While several embodiments have been disclosed, those skilled in the art will recognize that various modifications, alternative constructions, and equivalents may be used without departing from the spirit of the embodiments. Additionally, many well-known processes and elements have not been described to avoid unnecessarily obscuring the technology. Therefore, the foregoing description should not be deemed to limit the scope of the technology.

[0057]

[0062] Where a range of values ​​is provided, unless the context clearly dictates otherwise, each intervening value between the upper and lower limit of that range is specifically disclosed to the smallest unit of the lower limit. Any narrower range between a stated value or an unstated intervening value in a stated range and any other stated or intervening value in that stated range is encompassed. The upper and lower limits of such narrower ranges may individually be included or excluded from that range. Each range where either, neither, or both limits are included in this narrower range is also encompassed within the technology, provided that there is a specifically excluded limit in the stated range. When a stated range includes one or both of the limits, ranges excluding either or both of those included limits are also included.

[0058]

[0063] As used in this specification and claims, the singular forms "a," "an," and "the" include plural referents unless the context clearly dictates otherwise. Thus, for example, a reference to "a material" includes a plurality of such materials, a reference to "the precursor" includes a reference to one or more precursors and equivalents thereof known to those skilled in the art, and so forth.

[0059]

[0064] Additionally, the terms "comprise(s)", "comprising", "contain(s)", "containing", "include(s)", and "including", when used in this specification and claims, are intended to specify the presence of stated features, integers, components, or steps, but do not exclude the presence or addition of one or more other features, integers, components, steps, operations, or groups.

Claims

1. 1. A semiconductor processing method comprising: providing a fluorine-containing precursor to a processing region of a semiconductor processing chamber, delivering a fluorine-containing precursor to a processing region of a semiconductor processing chamber, wherein a substrate is disposed in the processing region, the substrate including exposed regions of a silicon and oxygen-containing material, the substrate including exposed regions of a liner material; delivering a hydrogen-containing precursor to a semiconductor processing region; contacting the substrate with the fluorine-containing precursor and the hydrogen-containing precursor; selectively removing at least a portion of the exposed area of ​​the silicon and oxygen containing material; A semiconductor processing method comprising:

2. The semiconductor processing method of claim 1 , wherein the fluorine-containing precursor comprises hydrogen fluoride.

3. The semiconductor processing method of claim 1 , wherein the hydrogen-containing precursor comprises ammonia.

4. 10. The semiconductor processing method of claim 1, wherein said exposed area of ​​said silicon and oxygen containing material is an oxidized surface of said substrate.

5. 10. The semiconductor processing method of claim 1, wherein the exposed areas of the liner material comprise a spacer material having a low dielectric constant.

6. 10. The semiconductor processing method of claim 1, wherein the temperature within the semiconductor processing chamber is maintained at about 200°C or less.

7. 10. The semiconductor processing method of claim 1, wherein the pressure within the semiconductor processing chamber is maintained at about 20 Torr or less.

8. 10. The semiconductor processing method of claim 1, further comprising performing a thermal anneal after contacting the substrate with the fluorine-containing precursor and the hydrogen-containing precursor, wherein the thermal anneal selectively removes the portions of the exposed regions of the silicon- and oxygen-containing material by sublimation.

9. 1. A semiconductor processing method comprising: i) delivering a fluorine-containing precursor and a hydrogen-containing precursor to a processing region of a semiconductor processing chamber; delivering a fluorine-containing precursor and a hydrogen-containing precursor to a processing region of a semiconductor processing chamber, wherein a substrate including exposed regions of silicon and oxygen-containing material is disposed in the processing region; ii) contacting the exposed area of ​​the silicon and oxygen containing material with the fluorine-containing precursor and the hydrogen-containing precursor; iii) forming silicon and oxygen containing by-products on the substrate; iv) annealing the substrate, annealing the substrate to sublimate at least a portion of the silicon and oxygen containing by-products; A semiconductor processing method comprising:

10. 10. The semiconductor processing method of claim 9, wherein steps i)-iv) comprise one cycle, and wherein the semiconductor processing method comprises at least two cycles.

11. 11. The semiconductor processing method of claim 10, wherein each cycle occurs for a time period of about 200 seconds or less.

12. 10. The semiconductor processing method of claim 9, wherein said portion of said silicon and oxygen containing by-products are removed with a selectivity ratio of about 3:1 or greater relative to exposed areas of liner material.

13. 10. The semiconductor processing method of claim 9, wherein the flow rate of the fluorine-containing precursor is less than or equal to about 500 sccm.

14. 10. The semiconductor processing method of claim 9, wherein the flow rate of the hydrogen-containing precursor is about 100 sccm or less.

15. 1. A semiconductor processing method comprising: providing a fluorine-containing precursor to a processing region of a semiconductor processing chamber, providing a fluorine-containing precursor to a processing region of a semiconductor processing chamber, the processing region including a substrate positioned within the processing region, the substrate including exposed regions of a silicon and oxygen-containing material, the substrate including exposed regions of a liner material; delivering a hydrogen-containing precursor to a semiconductor processing region; contacting the substrate with the fluorine-containing precursor and the hydrogen-containing precursor; annealing the substrate, annealing the substrate to sublimate at least a portion of the exposed area of ​​the silicon and oxygen containing material relative to the exposed area of ​​the liner material; A semiconductor processing method comprising:

16. 16. The semiconductor processing method of claim 15, wherein annealing the substrate comprises positioning the substrate near a showerhead of the semiconductor processing chamber.

17. 16. The semiconductor processing method of claim 15, wherein a selectivity between said exposed areas of said silicon and oxygen containing material to said exposed areas of said liner material is greater than or equal to about 3:

1.

18. 16. The semiconductor processing method of claim 15, wherein the flow ratio of the fluorine-containing precursor to the hydrogen-containing precursor is about 10:1 or less.

19. 16. The semiconductor processing method of claim 15, wherein the removal rate of the exposed regions of the silicon and oxygen containing material is greater than or equal to about 0.3 Å / sec.

20. 16. The semiconductor processing method of claim 15, wherein the processing region is maintained plasma-free during the semiconductor processing method.

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