Circuit for integrating current from high density sensors

Abstract

The circuit (300) includes a plurality of first-stage integrators (106(1,1)-106(2,1)). Each of the plurality of first-stage integrators includes a first input (324), a second input (326), a third input (322), and an output (328). The first input (324) of each of the plurality of first-stage integrators is coupled to a different one of the circuit inputs (304), the second input (326) is coupled to a first reference input, and the third input (322) is coupled to a second reference input, and the output (328) of each of the plurality of first-stage integrators is coupled to the first input (324) of such first-stage integrator. The circuit (300) includes a second stage integrator (108(1)) including a first input (386) coupled to each of the first inputs of the plurality of first stage integrators, a second input (388) coupled to a first reference input, and an output (392) coupled to the second stage integrator first input (386).

Description

[Technical Field]

[0001] The present description generally relates to a circuit for integrating current from a sensor. [Background technology]

[0002] Image sensors are used to convert optical image information into electrical signals. Image sensors generate an electrical current depending on the amount of light incident on the sensor. Image sensors are used, for example, in electronic imaging devices, medical imaging devices, and thermal imaging devices.

[0003] Optical nanopore sensors are used in the detection and characterization of clinical biomarkers and for DNA / RNA sequencing. Optical nanopore sensors generally operate by detecting changes in ionic current through a nanopore.

[0004] A sensor system may include hundreds or thousands of individual sensors (e.g., sensor elements). The individual sensors may be arranged, for example, in a two-dimensional array. Each sensor may be coupled to an electronic processing circuit via a conductor (e.g., a signal trace, a channel, a wire). The electronic processing circuit converts the current generated by the sensor into a voltage. The electronic processing circuit may include an amplifier that integrates the current and provides an output voltage representative of the current. A drawback of many amplifiers is that noise signals (e.g., flicker noise signals or thermal noise signals) that may be present at the amplifier's input may be amplified and generated at the amplifier's output. Additionally, parasitic capacitances of the sensors and signal traces increase the noise signals.

[0005] As the noise signal increases, the signal-to-noise ratio (SNR) of the amplifier decreases. To reduce the noise signal and increase the SNR, a precision amplifier can be used to convert the current to a voltage. A precision amplifier can have a wide bandwidth, high gain, and low noise and can be implemented using multiple gain stages, each having several transistors. Therefore, a precision amplifier requires a relatively large area to implement on an integrated circuit or semiconductor die and draws a higher current. Because a sensor system can include thousands of sensors densely fabricated on an integrated circuit or semiconductor die, and each individual sensor can be coupled to its own precision amplifier, a high-density sensor system can occupy a relatively large area on the integrated circuit or semiconductor die and draw a higher current, which can increase power consumption. Summary of the Invention

[0006] In one aspect, a circuit includes multiple circuit inputs, at least one of which is adapted to receive an input current. The circuit includes a first reference input adapted to receive a first reference voltage and a second reference input adapted to receive a second reference voltage. The circuit includes multiple first-stage integrators, each of which includes a first input, a second input, a third input, and an output. The first input of each of the multiple first-stage integrators is coupled to a different one of the circuit inputs, the second input is coupled to the first reference input, and the third input is coupled to the second reference input, and the output of each of the multiple first-stage integrators is coupled to the first input of the first-stage integrator by a first feedback path for that first-stage integrator. The circuit includes a second-stage integrator including a first input, a second input, and an output. A first input of the second stage integrator is coupled to each of the first inputs of the plurality of first stage integrators, a second input of the second stage integrator is coupled to the first reference input, and an output of the second stage integrator is coupled to the first input of the second stage integrator by a second feedback path.

[0007] In an additional aspect, a circuit includes a plurality of transfer switches, each of the plurality of transfer switches including a first terminal and a second terminal, wherein the first terminal of each of the plurality of transfer switches is coupled to a different one of the first inputs of the plurality of first stage integrators, and the second terminal of each of the plurality of transfer switches is coupled to the first input of the second stage integrator.

[0008] In an additional aspect, the first feedback path of each of the plurality of first stage integrators includes a first switch having a first terminal coupled to the output of such first stage integrator and a second terminal, and the first feedback path of each of the plurality of first stage integrators includes a first feedback capacitor having a first terminal coupled to the first input of such first stage integrator and a second terminal coupled to the second terminal of the first switch.

[0009] In an additional aspect, each of the plurality of first stage integrators further includes a second switch including a first terminal coupled to the second terminal of the first feedback capacitor of such first stage integrator and a second terminal adapted to receive a second reference voltage.

[0010] In an additional aspect, a circuit includes a circuit input adapted to receive an input current, a first reference input adapted to receive a first reference voltage, and a second reference input adapted to receive a second reference voltage. The circuit includes a first stage integrator having a first input coupled to the circuit input, a second input coupled to the first reference input, a third input coupled to the second reference input, and an output coupled to the first input of the first stage integrator by a first feedback path. The circuit includes a transfer switch having a first terminal coupled to the first input of the first stage integrator and a second terminal. The circuit includes a second stage integrator having a first input coupled to the second terminal of the transfer switch, a second input coupled to the first reference input, and an output coupled to the first input of the second stage integrator by a third feedback path.

[0011] In an additional aspect, a circuit includes a circuit input adapted to receive an input current, a first reference input adapted to receive a first reference voltage, and a second reference input adapted to receive a second reference voltage. The circuit includes a first amplifier having a first input coupled to the circuit input, a second input coupled to the first reference input, and an output. The circuit includes a first switch having a first terminal coupled to the output of the first amplifier and a second terminal. The circuit includes a first feedback capacitor having a first terminal coupled to the first input of the first amplifier and a second terminal coupled to the second terminal of the first switch. The circuit includes a second switch having a first terminal coupled to the second terminal of the first feedback capacitor and a second terminal coupled to the second reference input. The circuit includes a transfer switch having a first terminal coupled to the first input of the first amplifier and a second terminal, a second amplifier having a first input coupled to the second terminal of the transfer switch and a second input coupled to the first reference input and an output, and a second feedback capacitor having a first terminal coupled to the first input of the second amplifier and a second terminal coupled to the output of the second amplifier. [Brief explanation of the drawings]

[0012] [Figure 1] FIG. 1 is a block diagram illustrating an example sensor system.

[0013] [Figure 2] FIG. 10 is a block diagram illustrating multiple sensors coupled to respective first stage integrators coupled to second stage integrators.

[0014] [Figure 3A] FIG. 1 is a schematic diagram illustrating an example circuit. [Figure 3B]FIG. 1 is a schematic diagram illustrating an example circuit. [Figure 3C] FIG. 1 is a schematic diagram illustrating an example circuit.

[0015] [Figure 4] FIG. 4 is a timing diagram illustrating timing signals and voltages in the circuit of FIGS. 3A-3C.

[0016] In the drawings, the same reference numerals or other reference signs are used to denote identical or similar (functional and / or structural) features. DETAILED DESCRIPTION OF THE INVENTION

[0017] FIG. 1 is a block diagram illustrating an example system 100. System 100 includes multiple sensors 104(1,1) through 104(M,N) arranged in a two-dimensional array of M rows and N columns. Sensor 104(1,1) refers to the sensor in row number 1 and column number 1, and sensor 104(M,N) refers to the sensor in row number M and column number N. The sensors may be, for example, photodiodes, nanopores, or other types of sensors. The sensors may be used in electronic, medical, and thermal imaging devices, and / or systems for detection and / or characterization of clinical biomarkers and DNA / RNA sequencing.

[0018] When energy (e.g., light) is incident on the sensors 104(1,1) through 104(M,N), the sensors generate an electric charge according to the amount of incident energy. In some examples, the sensors 104(1,1) through 104(M,N) are coupled to respective first-stage integrators 106(1,1) through 106(M,N), which may be incorporated with the corresponding sensor (as shown in FIG. 1). Thus, each sensor may be coupled to a corresponding first-stage integrator. The electric charge generated by each sensor is integrated by the corresponding first-stage integrator.

[0019] System 100 includes second-stage integrators 108(1) through 108(N). Each second-stage integrator may be coupled to a corresponding group of first-stage integrators (e.g., a column or a row as shown in FIG. 1). For example, second-stage integrator 108(1) may be coupled to the first-stage integrator in column number 1, and second-stage integrator 108(N) may be coupled to the first-stage integrator in column number N. Charge integrated by the first-stage integrator in column number 1 is transferred to second-stage integrator 108(1), and similarly, charge integrated by the first-stage integrator in column number N is transferred to second-stage integrator 108(N). In response to the charge transferred by the first stage integrator of column number 1, the second stage integrator 108(1) provides an output voltage representative of the transferred charge, for example, to one input of multiplexer 110. Similarly, in response to the charge transferred by the first stage integrator of column N, the second stage integrator 108(N) provides an output voltage representative of the transferred charge, for example, to another input of multiplexer 110.

[0020] In some examples, the output voltages provided by the second-stage integrators 108(1)-108(N) are multiplexed by a multiplexer 110, and the multiplexed output voltage is provided to an analog-to-digital converter (ADC) 112. The ADC 112 digitizes the output voltages and provides digital information (e.g., a digital code) representing the output voltages to circuitry (such as a processor, a state machine, logic circuitry, memory, and / or combinations thereof), which may include software. The switching of the MUX 110 may be controlled by a processor, logic circuitry, and / or control circuitry, which may be on the same integrated circuit as the MUX 110 or may be external to the integrated circuit.

[0021] 2 is a block diagram illustrating column number 1 sensors 104(1,1) through 104(M,1) coupled to respective first stage integrators 106(1,1) through 106(M,1), which are coupled to second stage integrators 108(1). Sensors 104(1,1) generate an input current I in response to incident energy (e.g., light) received. S1The first stage integrator 106(1,1) converts the charge output by the sensor 104(1,1) (e.g., the charge generated by the sensor 104(1,1) in response to the received incident energy) into an input current I S1 and outputs the resulting integrated charge CH1. Similarly, in response to incident energy, the sensor 104(M,1) outputs an input current I SM The first stage integrator 106(M,1) converts the charge output by the sensor 104(M,1) into an input current I SM and integrate as follows: M The second stage integrator 108(1) generates an output voltage based on the current / integrated charge provided by the first stage integrators 106(1,1) through 106(M,1).

[0022] In some examples, first-stage integrators 106(1,1) through 106(M,1) integrate charge over respective integration periods and output the resulting integrated charge over respective transfer periods to second-stage integrator 108(1). The integration periods may be different and may overlap in time. The transfer periods may be different and may overlap in time. A transfer period may be delayed from its corresponding integration period to allow adequate time for integration of the charge by the first-stage integrator. As described in more detail below, the number of transfer periods (which may also be referred to as "transfer phases") may be any integer value (e.g., 2), and the number of integration periods (which may also be referred to as "integration phases") may be any integer value (e.g., 2).

[0023] 3A is a schematic diagram of an example circuit 300. Circuit 300 includes example sensors 104(1,1) and 104(2,1), first stage integrators 106(1,1) and 106(2,1), and second stage integrator 108(1). Circuit 300 is configured to receive input currents from multiple sensors (e.g., sensors 104(1,1) and 104(2,1)) and provide an output voltage based on the input currents.

[0024] Circuit 300 includes a first stage integrator 106(1,1) coupled to sensor 104(1,1) and a first stage integrator 106(2,1) coupled to sensor 104(2,1). Circuit 300 includes a second stage integrator 108(1) coupled to first stage integrators 106(1,1) and 106(2,1). Circuit 300 includes a first circuit input 304 adapted to be coupled to sensor 104(1,1) and a second circuit input 306 adapted to be coupled to sensor 104(2,1).

[0025] The sensor 104(1,1) is connected to a current source I S1 and a parallel resistor R S1 and the current is generated by the charge collected by the energy incident on the sensor. S1 (e.g., on the order of nanoamperes to on the order of picoamperes) includes a first terminal 310 coupled to a first circuit input 304 and a second terminal 312 coupled to a common potential 314 (e.g., ground). S1 (For example, about 1M ohm to about 1G ohm) is I S1 and a second terminal 318 coupled to a common potential 314. The sensor 104(1,1) is coupled to an input of the first circuit via a signal trace T1 (e.g., a conductor, wire, channel, and / or circuit board trace). PAR_1 may exist between the signal trace T1 and the common potential 314. PAR_1 may represent the sum of the sensor parasitic capacitance, the signal trace parasitic capacitance, and any other parasitic capacitance.

[0026] The circuit 300 is connected to a first reference voltage V REF1 a first reference input 320 adapted to receive a second reference voltage V REF2 A second reference input 322 adapted to receive a reference voltage (eg, about 0V to about 1.5V).

[0027] The first stage integrator 106(1,1) includes a first operational amplifier A1, which includes a first input 324 (e.g., an inverting input), a second input 326 (e.g., a non-inverting input), and an output 328. The first input 324 of A1 is coupled to the first circuit input 304, and the second input 326 of A1 is coupled to the first reference input 320.

[0028] The first stage integrator 106(1,1) is connected to the switch S 11 (also referred to as the first switch), and a switch S 11 includes a first terminal 330 coupled to the output 328 of the first operational amplifier A1 and includes a second terminal 332. A feedback capacitor C1 is connected via a switch S1 between the output 328 of A1 and the first input 324 of A1. 11 A feedback capacitor C1 includes a first terminal 334 that is coupled to the first terminal 324 of A1 and is coupled via a switch S 11 The second terminal 336 is coupled to the second terminal 332 of the first electrode 332 .

[0029] The first stage integrator 106(1,1) is connected to the switch S 12 (also referred to as the second switch), and a switch S 12 includes a first terminal 340 coupled to the second terminal 336 of the feedback capacitor C1 and a second reference voltage V REF2 The first stage integrator 106(1,1) includes a second terminal 342 coupled to a second reference input 322 configured to receive a transfer switch S T1 and a transfer switch S T1 includes a first terminal 344 coupled to the first input 324 of the first operational amplifier A1, and includes a second terminal 346.

[0030] The model of the sensor 104(2,1) is a current source I S2 and current source I S2 includes a first terminal 350 and a second terminal 352 coupled to a common potential 314. The model of the sensor 104(2,1) also includes a sensor resistor R S2(e.g., about 1 M ohm to about 1 G ohm), and a sensor resistor R S2 I S2 1 and includes a first terminal 354 coupled to a first terminal 350 of the sensor 104(2,1) and a second terminal 356 coupled to a common potential 314. The sensor 104(2,1) is coupled to a second circuit input 306 via a signal trace T2 (e.g., a conductor, wire, channel, and / or printed circuit board trace). A parasitic capacitance C PAR_2 There may be a parasitic capacitance C PAR_2 may represent the sum of the sensor parasitic capacitance, the signal trace parasitic capacitance, and any other parasitic capacitance.

[0031] The first stage integrator 106(2,1) includes a second operational amplifier A2 having a first input 360 (e.g., an inverting input) coupled to the second circuit input 306, a second input 362 (e.g., a non-inverting input) coupled to a third reference input 364, and an output 366. The third reference input 364 is coupled to a first reference voltage V REF1 The first stage integrator 106(2,1) is adapted to receive a signal from a switch S 21 (also referred to as the third switch), and switch S 21 includes a first terminal 368 coupled to the output 366 of the second operational amplifier A2, and includes a second terminal 370. A feedback capacitor C2 is coupled between the output 366 of A2 and the first input 360 of A2. The feedback capacitor C2 has a first terminal 372 coupled to the first terminal 360 of A2, and a switch S 21 The second terminal 374 is coupled to the second terminal 370 of the first electrode 372 .

[0032] The first stage integrator 106(2,1) is connected to the switch S 22 (also referred to as the fourth switch), and switch S 22 includes a first terminal 376 coupled to a second terminal 374 of the feedback capacitor C2 and a second reference voltage V REF2The first stage integrator 106(2,1) includes a second terminal 378 coupled to a second reference input 380 configured to receive a transfer switch S T2 and a transfer switch S T2 includes a first terminal 382 coupled to a first input 360 of a second operational amplifier A2, and includes a second terminal 384.

[0033] The circuit 300 includes a second stage integrator 108(1), which is connected to first and second transfer switches S T1 and S T2 The third operational amplifier A3 is coupled to the first and second operational amplifiers A1 and A2 via respective transfer switches S T1 and S T2 The third operational amplifier A3 includes a first input 386 (e.g., an inverting input) coupled to the second terminals 346 and 384 of the first reference voltage V REF1 The third operational amplifier A3 includes a second input 388 (e.g., a non-inverting input) coupled to a fifth reference input 390 adapted to receive the input signal Vout. The third operational amplifier A3 includes an output 392 that may be coupled to the ADC 112 via the multiplexer 110. A feedback capacitor C3 is coupled between the output 392 of A3 and the first input 386 of A3. The feedback capacitor C3 includes a first terminal 393 coupled to the first input 386 of A3 and a second terminal 394 coupled to the output 392 of A3. The second stage integrator 108(1) includes a reset switch S connected between the first terminal 393 and the second terminal 394 of C3. RST Includes:

[0034] In some examples, the circuit 300 includes a switch S 11 , S 12 , S T1、 S 21 , S 22 , and S T23. The timing control circuit CTRL may include a clock (not shown in FIG. 3) that provides a clock signal. In response, the timing control circuit CTRL provides first, second, and third timing signals, φ1, φ2, φ3, at respective outputs 395, 396, and 397. The timing signal φ1 is coupled to a switch S 11 , S 12 , and S T1 , and timing signal φ2 is applied to control (e.g., cause the applicable switch to open (non-conducting) or close (conducting)) switch S 21 , S 22 , and S T2 and timing signal φ3 is applied to control switch S RST is applied to control

[0035] In some examples, the circuit 300 operates in two phases: (1) an integration phase and (2) a transfer phase. During the integration phase, an input current from a sensor (e.g., sensor 104(1,1)) is received by a corresponding first-stage integrator (e.g., first-stage integrator 106(1,1)), and the sensor charge forming the input current is integrated over an integration period. During the transfer phase, the first-stage integrator (e.g., first-stage integrator 106(1,1)) transfers the resulting integrated charge to a second-stage integrator (e.g., second-stage integrator 108(1)) over a transfer period. The second-stage integrator (e.g., second-stage integrator 108(1)) provides an output voltage representative of the transferred charge.

[0036] Similarly, during the integration phase, an input current from sensor 104(2,1) is received by first-stage integrator 106(2,1), which integrates the charge forming the input current over an integration period. During the transfer phase, first-stage integrator 106(2,1) transfers the resulting integrated charge over a transfer period to second-stage integrator 108(1). Second-stage integrator 108(1) provides an output voltage representative of the transferred charge.

[0037] 3B illustrates circuit 300 during the first and second integration phases. During the first integration phase, charge is integrated by first stage integrator 106(1,1), and during the second integration phase, charge is integrated by first stage integrator 106(2,1).

[0038] During the first integration phase, the first timing signal φ1 is asserted LOW (e.g., logic “0”, a low voltage such as around ground). In response, the switch S 11 is closed (e.g., conducting), but switch S 12 and S T1 is open (e.g., not conducting). Therefore, the output 328 of the first operational amplifier A1 is coupled to the first input 324 of A1 through a feedback capacitor C1, thereby forming a feedback path. The feedback path keeps the first input 324 of A1 at virtual ground with respect to the second input 326 of A1. The input current I from the sensor 104(1,1) S1 flows into the feedback capacitor C1, and I S1 The charge on the feedback capacitor C1 is integrated over the first integration period. During the first integration phase, switch S T1 remains open, decoupling the first stage integrator 106(1,1) from the second stage integrator 108(1).

[0039] Similarly, during the second integration phase, the second timing signal φ2 is asserted LOW. In response, the switch S 21 is closed, but switch S 22 and S T2is open. Therefore, the output 366 of the second operational amplifier A2 is coupled to the first input 360 of A2 through the feedback capacitor C2, thus forming a feedback path. The feedback path keeps the first input 360 of A2 at virtual ground with respect to the second input 362 of A2. The input current I from the sensor 104(2,1) S2 flows to the feedback capacitor C2, and I S2 The charge on the feedback capacitor C2 is integrated over the second integration period. During the second integration phase, switch S T2 remains open, thus decoupling the first stage integrator 106(2,1) from the second stage integrator 108(1).

[0040] In some examples, the first and second integration periods may have different durations and / or start times, while in other examples, the first and second integration periods may overlap (at least partially) in time.

[0041] 3C illustrates circuit 300 during the first and second transfer phases. During the first transfer phase, the first timing signal φ1 is asserted HIGH. In response, switch S 11 is opened, but switch S 12 and S T1 is closed. S 11 is opened, the output 328 of the first operational amplifier A1 is disconnected from the first input 324 of A1, thus disconnecting the feedback path. 21 and S T1 are both closed, the feedback capacitor C1 is connected to the second reference voltage V REF2 and the first input 324 of A1 is coupled to a first input 386 of a third operational amplifier A3. As a result, the charge integrated on feedback capacitor C1 is transferred to feedback capacitor C3 over a first transfer period.

[0042] Similarly, during the second transfer phase, the second timing signal φ2 is asserted HIGH. In response, the switch S 21is opened, but switch S 22 and S T2 is closed. S 21 is opened, the output 366 of the second operational amplifier A2 is disconnected from the first input 360 of A2, thus disconnecting the feedback path. 22 and S T2 are both closed, the feedback capacitor C2 is connected to the second reference voltage V REF2 and a first input 360 of A2 is coupled to a first input 386 of a third operational amplifier A3. Therefore, the charge integrated on feedback capacitor C2 is transferred to feedback capacitor C3 over a second transfer period.

[0043] During the first transfer period, the feedback path formed by feedback capacitor C1 is broken. Therefore, during the first transfer period, there is no virtual ground at the first input 324 of the first operational amplifier A1 relative to the second input 326 of A1, and the output potential V O1 is no longer capacitively coupled to the first input 324 of A1. Therefore, any noise that may be present at the second input 326 of A1 is not present at the first input 324 of A1 because there is no virtual ground, and any noise that may be present at the output 328 of A1 is not capacitively coupled to the first input 324 of A1. Therefore, during the first transfer phase, no noise from the first input 324 of A1 or any noise from the output 328 of A1 is transferred to the third operational amplifier A3. Similarly, during the second transfer phase, no noise from the first input 360 of A2 or any noise from the output 366 of A2 is transferred to the third operational amplifier A3.

[0044] In some examples, the first and second transfer periods may have different durations and / or start times. In other examples, the first and second transfer periods may overlap (at least partially) in time.

[0045] During the integration phase, the first stage integrator 106(1,1) integrates the input current I S1During the transfer phase, the first stage integrator 106(1,1) temporarily stores charge from the parasitic capacitor C PAR_1 However, the first stage integrator 106(1,1) transfers charge from V to the second stage integrator 108(1). O1 Therefore, any noise that may be present at the output 328 of A1 (e.g., the output voltage V 01 The noise signal (signal) is not transferred to the second-stage integrator 108(1) and does not degrade the performance of the second-stage integrator 108(1). Therefore, the first operational amplifier A1 can be implemented as a low-gain, low-bandwidth amplifier, requiring fewer gain stages and fewer transistors than would be required by a high-gain, high-bandwidth amplifier. Similarly, the first-stage integrator 106(2,1) can be implemented as a low-gain, low-bandwidth amplifier. In this manner, the described example allows A1 and A2 to be realized as low-gain, low-bandwidth amplifiers without degrading the accuracy of data acquisition. Using a low-gain, low-bandwidth amplifier instead of a high-gain, high-bandwidth amplifier has several advantages. A low-gain, low-bandwidth amplifier consumes significantly less power than a high-gain, high-bandwidth amplifier due to its relaxed noise specification. Also, a low-gain, low-bandwidth amplifier has fewer transistors and is therefore less expensive and requires less area to implement on an integrated circuit or semiconductor die. These advantages can be significant if the system requires a very large number of sensors or pixels (eg, 10K or 100K) and therefore an increased number of first stage integrators.

[0046] In some examples, the third operational amplifier A3 may be implemented as a high-gain, large-bandwidth amplifier with low noise (also referred to as a precision amplifier). A3 controls the output voltage V OF in response to the charge transferred from A1 and A2, so that any noise generated by A3 does not affect the output voltage V OFIt is therefore beneficial to implement A3 as a low noise, high gain, large bandwidth amplifier.

[0047] A3 output voltage V OF To ensure that σ is a measure of the charge transferred by the first stage integrators (e.g., 106(1,1) and 106(2,1) in FIG. 3C), feedback capacitor C3 is connected to switch S RST In some examples, the switch state S RST A timing signal (φ) is used to control the transfer period. Before the transfer period, φ3 is asserted high, which causes S RST is closed. Therefore, the feedback capacitor C3 is shorted and discharged or reset. When C3 is reset, φ3 is asserted low, which causes S RST Thus, during the next transfer period, the feedback capacitor C3 is charged only by the transferred charge from the first stage integrator, and therefore the output voltage V of A3 OF represents the transferred charge. In some examples, the feedback capacitor C3 may be reset to a known potential by coupling C3 to a known reference potential.

[0048] In some examples, charge is transferred from the first operational amplifier A1 to the third operational amplifier A3 or from the second operational amplifier A2 to A3, and the output voltage V OF After a predetermined duration, which is necessary for the output voltage V to stabilize, OF may be sampled and digitized by an analog-to-digital converter (not shown in FIGS. 3A-3C).

[0049] In some examples, charge from sensors 104(1,1) through 104(M,N) may be transferred sequentially in a frame. Thus, for example, charge may be transferred sequentially from sensors in column number 1, starting with sensor 104(1,1). After charge from the last sensor in column number 1 (e.g., sensor 104(M,1)) is transferred, the next frame (e.g., column number 2) begins and the process repeats.

[0050] In some examples, the sensors 104(1,1)-104(M,N), the first-stage integrators 106(1,1)-106(M,N), and the second-stage integrators 108(1)-108(N) may be implemented within an integrated circuit or semiconductor die. In some examples, the first-stage integrators 106(1,1)-106(M,N) and the second-stage integrators 108(1)-108(N) may be implemented within an integrated circuit, and the integrated circuit may be coupled to the sensors 104(1,1)-104(M,N) via external connections, signal traces, wires, or conductors. Other variations are possible within the scope of this description.

[0051] 4 illustrates timing signals and voltages in example circuit 300. The x-axis represents time and the y-axis represents voltage. First, at time T0, timing signals (φ1) (indicated by reference numeral 404) and (φ2) (indicated by reference numeral 408) are LOW, and timing signal (φ3) (indicated by reference numeral 409) is LOW. 12 At time T0, the feedback capacitor C3 of the third operational amplifier A3 is reset. In some examples, C3 is reset to a known voltage (e.g., VR). At time T0, the switch S 11 and S 21 is closed, but the feedback capacitors C1 and C2 are not yet fully charged, so the output V of the operational amplifier A1 O1 At time T0, the output V of operational amplifier A3 (indicated by reference numeral 416) and the output V of operational amplifier A2 (indicated by reference numeral 420) are both zero. OF (indicated by reference numeral 424) is V R, which means that the feedback capacitor C3 is R This is because it has been reset to

[0052] At time T1, φ1 is asserted HIGH. Therefore, switch S 11 is opened and switch S 21 and S T1 Therefore, C1 is connected to the second reference voltage V REF2 , and the first input 324 of the first operational amplifier A1 is coupled to the first input 386 of the third operational amplifier A3. Therefore, at time T1, charge from C1 is transferred to C3, and the output V OF begins to decrease. At time T2, V OF is allowed to settle, sampled (indicated by reference numeral 428) and digitized by the ADC.

[0053] At time T3, the charge transfer from C1 to C3 is complete, φ1 is asserted LOW, and φ3 is asserted HIGH. Therefore, C3 is connected to V R and switch S 11 is closed. In this way, the output voltage V OF rises and V R Return to.

[0054] At time T4, φ2 is asserted HIGH. Therefore, switch S 22 and S T2 is closed, but switch S 21 is opened. This starts the transfer of charge from C2 to C3 at time T4. At time T5, the output V OF settles, the ADC samples, and V OF At time T6, the charge transfer from C2 to C3 is completed and φ2 is asserted low. Therefore, V OF rises and V R Return to.

[0055] Circuits described herein may include one or more semiconductor elements (e.g., transistors), one or more passive elements (e.g., resistors, capacitors, and / or inductors), and / or one or more sources (e.g., voltage and / or current sources). A circuit may include only semiconductor elements in a single physical device (e.g., a semiconductor die and / or integrated circuit (IC) package) and may be coupled to at least some of the passive elements and / or sources to form the described structure either during or after manufacture, such as by an end user and / or a third party. Some examples may include certain elements implemented within an integrated circuit and other elements external to the integrated circuit, while in other examples, additional or fewer features may be incorporated into the integrated circuit. Also, some or all of the features illustrated as being external to the integrated circuit may be included in the integrated circuit, and / or some features illustrated as being internal to the integrated circuit may be incorporated external to the integrated circuit. As used herein, the term "integrated circuit" means one or more circuits that are (1) integrated in / on a semiconductor substrate, (2) integrated in a single semiconductor package, (3) integrated in the same module, and / or (4) integrated in / on the same printed circuit board.

[0056] In this description, the term "couple" may encompass a connection, communication, or signal path that enables a functional relationship consistent with this description. For example, (A) in a first example, device A is coupled to device B when device A provides a signal to control device B to perform a certain action; or (B) in a second example, device A is coupled to device B through an intervening component C when intervening component C does not substantially change the functional relationship between device A and device B, such that device B is controlled by device A through a control signal provided by device A. Also, in this description, a device that is "configured" to perform a certain task or function may be configured (e.g., programmed and / or hardwired) at the time of manufacture by a manufacturer to perform that function and / or be configurable (or reconfigurable) by a user after manufacture to perform that function and / or other additional or alternative functions. Such configuration may be via firmware and / or software programming of the device, via the configuration and / or layout of hardware components, via the device's interconnections, or via a combination thereof. Also, herein, circuits or devices including certain components may instead be adapted to be coupled to those components to form the described circuit or device. For example, a structure described as including one or more semiconductor elements (e.g., transistors), one or more passive elements (e.g., resistors, capacitors, and / or inductors), and / or one or more sources (e.g., voltage and / or current sources) may instead include only semiconductor elements within a single physical device (e.g., a semiconductor die and / or integrated circuit (IC) package) and may be adapted to be coupled to at least some of the passive elements and / or sources, either during or after manufacture, by an end user, a third party, etc., to form the described structure.

[0057] As used herein, the terms "terminal," "node," "interconnect," and "pin" are used interchangeably. Unless otherwise noted, these terms are used generally to refer to an interconnection between, or termination of, a device element, circuit element, integrated circuit, device, or other electronic or semiconductor component.

[0058] While some examples suggest that certain elements are included in an integrated circuit and other elements are external to the integrated circuit, in other examples, additional or fewer features may be incorporated into the integrated circuit. Also, some or all of the features illustrated as being external to the integrated circuit may be included in the integrated circuit, and / or some features illustrated as being internal to the integrated circuit may be incorporated outside the integrated circuit. As used herein, the term "integrated circuit" means one or more circuits that are (1) incorporated within / on a semiconductor substrate, (2) incorporated within a single semiconductor package, (3) incorporated within the same module, and / or (4) incorporated within / on the same printed circuit board.

[0059] Although the use of particular transistors is described herein, other transistors (or equivalent devices) can be substituted with little or no change to the remaining circuit elements. For example, metal-oxide-silicon FETs ("MOSFETs") (e.g., n-channel MOSFETs, nMOSFETs, or p-channel MOSFETs, pMOSFETs), bipolar junction transistors (BJTs—e.g., NPN or PNP), insulated-gate bipolar transistors (IGBTs), and / or junction field-effect transistors (JFETs) can be used in place of or in conjunction with the devices described herein. The transistors can be depletion-mode devices, drain-extension devices, enhancement-mode devices, natural transistors, or other types of device structure transistors. Additionally, the devices can be implemented in / on silicon substrates (Si), silicon carbide substrates (SiC), gallium nitride substrates (GaN), or gallium arsenide substrates (GaAs).

[0060] While some elements of the described examples are included in the integrated circuit and others are external to the integrated circuit, in other examples, additional or fewer features may be incorporated into the integrated circuit. Also, some or all of the features illustrated as being external to the integrated circuit may be included in the integrated circuit, and / or some features illustrated as being internal to the integrated circuit may be incorporated external to the integrated circuit. As used herein, the term "integrated circuit" means one or more circuits that are (1) incorporated within / on a semiconductor substrate, (2) incorporated within a single semiconductor package, (3) incorporated within the same module, and / or (4) incorporated within / on the same printed circuit board.

[0061] Although certain components may be described herein as being of a particular process technology, these components may be replaced with components of other process technologies. Circuits described herein are reconfigurable to include the replaced component to provide functionality at least partially similar to that available before the component replacement. A component shown as a resistor, unless otherwise specified, generally represents any one or more elements coupled in series and / or parallel to provide the amount of impedance represented by the depicted resistor. For example, a resistor or capacitor shown and described herein as a single component may instead be multiple resistors or capacitors coupled in series or parallel between the same two nodes as a single resistor or capacitor, respectively. Additionally, the use of the phrase “ground terminal” herein includes chassis ground, earth ground, floating ground, virtual ground, digital ground, common ground, and / or any other form of ground connection applicable to or suitable for the teachings herein. Unless otherwise specified, “about,” “approximately,” or “substantially” preceding a value means + / - 10% of the stated value, or, if the value is zero, a reasonable range of values ​​around zero.

[0062] Modifications may be made to the exemplary embodiments described, and other embodiments are possible, within the scope of the claims of the invention.

Claims

1. 1. A circuit having a plurality of circuit inputs, comprising: at least one of the plurality of circuit inputs is adapted to receive an input current, the circuit having a first reference input adapted to receive a first reference voltage and a second reference input adapted to receive a second reference voltage; The circuit a plurality of first stage integrators, each including a first input, a second input, a third input, and an output; a second stage integrator including a first input, a second input, and an output; Including, the first input of each of the plurality of first stage integrators is coupled to a different one of the circuit inputs, the second input is coupled to the first reference input, the third input is coupled to the second reference input, and the output of each of the plurality of first stage integrators is coupled to the first input of such first stage integrator by a first feedback path for such first stage integrator; coupled to a first input of the first stage integrator; the first stage of the second stage integrator is coupled to each of the first inputs of the plurality of first stage integrators, the second input of the second stage integrator is coupled to the first reference input, and the output of the second stage integrator is coupled to the first input of the second stage integrator by a second feedback path; circuit.

2. 2. The circuit of claim 1, further comprising a plurality of transfer switches, each of the plurality of transfer switches including a first terminal and a second terminal, the first terminal of each of the plurality of transfer switches being coupled to a different one of the first inputs of the plurality of first stage integrators, and the second terminal of each of the plurality of transfer switches being coupled to the first input of the second stage integrator.

3. 2. The circuit of claim 1, wherein the first feedback path comprises: a first switch including a first terminal coupled to the output of the first stage integrator and a second terminal; a first feedback capacitor having a first terminal coupled to the first input of the first stage integrator and a second terminal coupled to the second terminal of the first switch; The circuit includes:

4. 4. The circuit of claim 3, wherein each of the plurality of first stage integrators further includes a second switch, the second switch including a first terminal coupled to the second terminal of the first feedback capacitor of such first stage integrator and a second terminal adapted to receive the second reference voltage.

5. 2. The circuit of claim 1, wherein each of the plurality of first stage integrators further includes a transfer switch, the transfer switch including a first terminal coupled to the first input of such first stage integrator and a second terminal coupled to the first input of the second stage integrator.

6. 2. The circuit of claim 1, wherein the second feedback path includes a second feedback capacitor, the second feedback capacitor including a first terminal coupled to the first input of the second stage integrator and a second terminal coupled to the output of the second stage integrator.

7. 2. The circuit of claim 1, wherein the second stage integrator includes a reset switch, the reset switch including a first terminal coupled to the first input of the second stage integrator and a second terminal coupled to the output of the second stage integrator.

8. 8. The circuit of claim 7, wherein the reset switch is configured to reset the second feedback capacitor.

9. 1. A circuit having a circuit input adapted to receive an input current, the circuit having a first reference input adapted to receive a first reference voltage, and a second reference input adapted to receive a second reference voltage, The circuit a first stage integrator including a first input coupled to the circuit input, a second input coupled to the first reference input, a third input coupled to the second reference input, and an output coupled to the first input of the first stage integrator via a first feedback path; a transfer switch including a first terminal coupled to the first input of the first stage integrator and a second terminal; a second stage integrator; and Including, the second stage integrator including a first input coupled to the second terminal of the transfer switch, a second input coupled to the first reference input, and an output coupled to the first input of the second stage integrator by a third feedback path. circuit.

10. 10. The circuit of claim 9, wherein the first feedback path comprises: a first switch including a first terminal coupled to the output of the first stage integrator and a second terminal; a first feedback capacitor having a first terminal coupled to the first input of the first stage integrator and a second terminal coupled to the second terminal of the first switch; The circuit includes:

11. 10. The circuit of claim 9, wherein the second feedback path includes a second feedback capacitor, the second feedback capacitor including a first terminal coupled to the first input of the second stage integrator and a second terminal coupled to the output of the second stage integrator.

12. 10. The circuit of claim 9, wherein the second stage integrator includes a reset switch, the reset switch including a first terminal coupled to the first input of the second stage integrator and a second terminal coupled to the output of the second stage integrator.

13. A circuit having a circuit input adapted to receive an input current, a first reference input adapted to receive a first reference voltage, and a second reference input adapted to receive a second reference voltage, The circuit a first amplifier including a first input coupled to the circuit input, a second input coupled to the first reference input, and an output; a first switch including a first terminal coupled to the output of the first amplifier and including a second terminal; a first feedback capacitor including a first terminal coupled to the first input of the first amplifier and a second terminal coupled to the second terminal of the first switch; a second switch including a first terminal coupled to the second terminal of the first feedback capacitor and a second terminal coupled to the second reference input; a transfer switch including a first terminal coupled to the first input of the first amplifier and a second terminal; a second amplifier including a first input coupled to the second terminal of the transfer switch, a second input coupled to the first reference input, and an output; a second feedback capacitor including a first terminal coupled to the first input of the second amplifier and a second terminal coupled to the output of the second amplifier; The circuit includes:

14. 14. The circuit of claim 13, further comprising a reset switch, the reset switch comprising a first terminal coupled to the first terminal of the second feedback capacitor and a second terminal coupled to the second terminal of the second feedback capacitor.

15. 1. A circuit having a plurality of circuit inputs, at least one of the plurality of circuit inputs adapted to receive an input current, the circuit having a first reference input adapted to receive a first reference voltage and a second reference input adapted to receive a second reference voltage; The circuit a plurality of first stage integrators, each first stage integrator of the plurality of first stage integrators including a first input coupled to a different one of the circuit inputs, a second input coupled to the first reference input, a third input coupled to the second reference input, and an output coupled to the first input of such first stage integrator by a first feedback path; a second stage integrator including: a first input coupled to a first input of each of the plurality of first stage integrators; a second input coupled to the first reference input; and an output coupled to the first input of the second stage integrator by the second feedback path; The circuit includes:

16. 16. The circuit of claim 15, wherein each of the plurality of first stage integrators further includes a transfer switch, the transfer switch including a first terminal coupled to the first input of such first stage integrator and a second terminal coupled to the first input of the second stage integrator.

17. 16. The circuit of claim 15, further comprising a reset switch, the reset switch comprising a first terminal coupled to the first terminal of the second stage integrator and a second terminal coupled to the output of the second stage integrator.

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