Synthetic Voltage Signal

Abstract

Methods, systems, and apparatus for injecting a composite voltage signal, including a computer program encoded on a computer storage medium. One of the methods includes initiating a transition by a processing core from executing in a low power state to executing in a high power state. The device injects the composite voltage signal into a voltage feedback line of a power manager to cause the power manager to react more quickly to the transition by increasing the current supplied to the processing core. The power manager uses the composite voltage signal to increase the current supplied to the processing core after the processing core transitions from the low power state to the high power state.

Description

[Background technology]

[0001] TECHNICAL FIELD This specification relates to power management for computing devices. Computing devices, particularly battery-powered computing devices such as mobile phones, laptops, and tablets, employ many strategies to provide high computational performance with long battery life. To do so, such devices reduce power consumption when computational demands are low. For example, some devices attempt to conserve power by entering a higher power state when there is computational work to be done, and then entering a lower power state when the computational work is completed.

[0002] The power efficiency of entering and exiting these different power states is highly dependent on the speed at which the device can transition between states. However, there are real physical constraints on how quickly a device can enter a higher power state. One reason for this is that there are usually physical electronic components, such as inductors, located between the current regulator and the computational core, which impose physical limits on how quickly the current can increase.

[0003] Due to physical constraints on this current increase, devices can employ mitigation strategies to ensure that a spike in computational workload before the current is fully increased does not cause an unacceptable voltage drop that could cause the device to crash or malfunction. Devices can employ several strategies to help control such undesirable outcomes.

[0004] One example is a voltage droop detector that monitors a device's core voltage. When the voltage drops below a certain threshold, for example due to a spike in computational workload, the system slows down the clock frequency to prevent the voltage from dropping too much. However, slowing down the clock frequency has the disadvantage of reducing the device's computational power because it causes the device to operate more slowly.

[0005] Another example is an architectural relaxation that uses a mapping between desired voltage drops and instruction types or sequences. If a future instruction sequence has an undesired desired voltage drop, the system can execute the instructions more slowly. This approach also has the undesirable characteristic of throttling computing power to prevent unsafe voltage drops. Summary of the Invention

[0006] This specification describes how a system can use a composite voltage signal to improve power performance of a computing device having a power manager that uses a voltage feedback signal to control current increases. Injecting the composite voltage signal into the voltage feedback signal has the effect of allowing the power manager to react faster to power consumption spikes while reducing the adverse impact of frequency mitigation measures on computational performance.

[0007] Particular embodiments of the subject matter described herein can be implemented to achieve one or more of the following advantages: The use of a composite voltage signal improves the computational performance and power efficiency of a computing device in several ways. First, the composite voltage signal improves the computational performance of the device by allowing the computing device to transition from a low power state to a high power state more quickly. The composite voltage signal also reduces the adverse effects of frequency throttling. Furthermore, the use of a composite voltage signal generated by the processing cores makes it possible to implement these performance and efficiency improvements without redesigning or modifying the power manager.

[0008] The details of one or more embodiments of the subject matter herein are set forth in the accompanying drawings and the description below. Other features, aspects, and advantages of the subject matter will become apparent from the description, drawings, and claims. [Brief explanation of the drawings]

[0009] [Figure 1A] FIG. 1 illustrates an exemplary system using architectural relaxation. [Figure 1B] FIG. 1 illustrates an exemplary system using mitigation of clock frequency throttling. [Figure 2A] 10 shows how a composite voltage signal allows for faster voltage recovery. [Figure 2B] 1 shows how a synthesized voltage signal allows for faster frequency recovery. [Figure 3] We show how the power manager reacts to architectural relaxations but not to the composite voltage signal. [Figure 4] It is shown that the power supply manager has a faster reaction time when using a composite voltage signal. [Figure 5] It shows how a composite voltage signal can be used to compensate for both architectural and frequency relaxation in the same system. DETAILED DESCRIPTION OF THE INVENTION

[0010] Like reference symbols and designations in the various drawings refer to like elements. This specification describes how a system can use a composite voltage signal to improve power performance of a computing device having a power manager that uses a voltage feedback signal to control current increases. Injecting the composite voltage signal into the voltage feedback signal has the effect of allowing the power manager to react faster to power consumption spikes while reducing the adverse impact of frequency mitigation measures on computational performance.

[0011] 1A illustrates an exemplary system 100a employing architectural relaxation. System 100a is an example of a system that can use synthesized voltage signals to improve power supply performance.

[0012] System 100a includes a power manager 110 and an application processor 120 having a computational core 130. System 100a can be part of any suitable mobile or stationary computing device. For example, the system can be part of a mobile phone, a wearable device, a tablet, a laptop computer, a desktop computer, or a server. Computational core 130 can be any suitable computing device that executes instructions.

[0013] Power supply manager 110 can be any suitable power supply manager that uses voltage feedback to regulate the current supplied to compute core 130. For example, power supply manager 110 can be a buck-down converter. Power supply manager 110 receives a voltage feedback signal "Vout_sns" using voltage feedback line 112 to regulate the amount of current being supplied to application processor 120.

[0014] To generate the voltage feedback signal, system 100a uses a series resistor 127 in combination with a controlled current source 129 that draws current across series resistor 127. Because there is current in front of series resistor 127, changes to the current consumed by computational core 130 cause corresponding changes in voltage drop across resistor 127. These voltages are fed through voltage buffer 131 and then converted into a voltage feedback signal.

[0015] System 100a has at least two computing modes: a low power mode and a high power mode. When transitioning from the low power mode to the high power mode, power supply manager 110 can detect a voltage drop from the voltage feedback signal received on voltage feedback line 112.

[0016] FIG. 1A includes an inset plot 105 that illustrates the behavior of components with architectural relaxation relative to the current supplied by the power supply manager 110 .

[0017] The x-axis of inset plot 105 is time, and the y-axis is current at two locations on the device, 111 and 114. Inset plot 105 therefore shows the relationship between 1) the current consumed by compute core 130 at location 114 where power is supplied to the compute core, and 2) the current supplied by power supply manager 110, referred to as the "buck current," measured at point 111 just beyond buck inductor 113.

[0018] The current consumed from transitioning from a low power state to a high power state without any mitigation is shown by dotted line 102. As explained above, this may not actually be an option as doing so could cause an unsafe voltage drop.

[0019] The current consumed under architectural relaxation when transitioning from a low power state to a high power state is shown by dashed line 104. As compute core 130 performs this relaxation, the current consumed is boosted twice over time, as represented by dashed line 104.

[0020] Finally, the current supplied by power manager 110 during the architectural relaxation transition is shown by solid line 106. Because power manager 110 has no visibility into what compute cores 130 are doing, power manager 110 relies on a voltage feedback signal to initiate a power increase. In this example, power manager 110 senses a voltage drop only after a first boost in current consumption, shown by dashed line 104. Power manager 110 then steadily increases the current until the computing device reaches a steady state after performing a second boost in current consumption.

[0021] Compute core 130 has functional circuitry for implementing architectural mitigation. The effect of the architectural mitigation is that compute core 130 executes instructions more slowly during a transition from low power to high power until the power manager has had a chance to fully increase the available current. In some implementations, the components that implement the architectural mitigation do not actually measure the current supplied by power manager 110. Rather, they use calculations or lookup tables, or some combination of these, to calculate an estimate of the current that each instruction or instruction sequence is expected to consume when executed.

[0022] The compute core 130 has a digital power estimator 132 that calculates an estimate of the power consumed for a particular instruction or sequence of instructions. The di / dt instruction throttling module 134 can then use the digital power estimate produced by the digital power estimator 132 to control how fast an instruction should be executed or throttled.

[0023] The di / dt digital-to-analog converter (DAC) 136 can calculate the difference between the amount of power expected to be consumed and the amount of power being supplied to the compute core 130. For example, an architectural relaxation might inject three NOP instructions per actual payload instruction. Next, there is a power cost prediction performed with only the actual payload, including the NOP instructions. A NOP may have a power cost of, for example, 1 unit, and a payload instruction may have a power cost of 10 units. These costs may be summed over an instruction window, for example, 5, 50, or 100 instructions, with the difference between the summed costs representing the delta. The delta signal may then be calculated as the unthrottled power cost compared to the throttled power cost, possibly using a pre-calculated scaling factor.

[0024] System 100a can then use the calculated delta 133 to modify controlled current source 129 in a manner that produces a proportional voltage shift across series resistor 127. For example, delta can be used to decrease the current of controlled current source 129, thereby decreasing the voltage across series resistor 127, so as to effectively subtract from the voltage feedback signal on voltage feedback signal line 112. This, in effect, creates a composite voltage signal that is provided to voltage feedback signal line 112. In some implementations, computation core 130 can use a programmable GM amplifier to inject delta signal 133 as a current that affects the operation of controlled current source 129.

[0025] 1A includes another inset plot 115 showing the shape of the composite voltage signal. In inset plot 115, the x-axis is time and the y-axis is voltage. Due to compute core 130 entering a high power state, there is a voltage drop at location 116 before the current reaches compute core 130. Therefore, to cause power supply manager 110 to react more quickly, composite voltage signal 117 is provided on voltage feedback line 112.

[0026] In some implementations, the computational core generates a trajectory-matched resultant voltage signal 117 that matches the trajectory of the desired voltage drop 116. In other words, the resultant voltage signal has a shape designed to match the physical properties of the system, so that it substantially matches the desired voltage drop. As shown in inset plot 115, while the shape is substantially similar, the resultant voltage signal has an artificially lower magnitude. In effect, the resultant voltage signal tells power supply manager 110 that the conditions of the power being supplied are worse than they actually are, stimulating power supply manager 110 to react sooner and more aggressively than it would otherwise.

[0027] 1B illustrates an example system 100b that uses mitigated clock frequency throttling. System 100b has many similarities to system 100a, but system 100b uses a frequency lock loop (FLL) module 138 to throttle the clock frequency of compute core 130b until power regulator 110 can increase the current to compute core 130b.

[0028] In this case, however, the system uses the frequency reduction value calculated by the FLL 138 to generate a delta signal 135 that influences the controlled current source 129 to produce a composite voltage signal. The computation core 130b may, for example, use a programmable GM amplifier to inject the delta signal calculated from the frequency reduction value, optionally with a scaling factor.

[0029] 2A illustrates how the composite voltage signal 204 allows for faster voltage recovery. At transition point 210, which may be a transition from a low power state to a high power state, the voltage of the compute core drops as it consumes more power.

[0030] At transition point 210, the system can inject the composite voltage signal 204, and the resulting regulated voltage 206 recovers more quickly than the normal voltage 202 would have without the composite voltage signal. As noted above, this is because the composite error signal causes the power supply manager to react sooner, and potentially more aggressively.

[0031] 2B illustrates how a composite voltage signal can enable faster frequency recovery. At transition point 211, a compute core can implement frequency throttling due to increased power demand. Thus, frequency mitigation techniques lower the frequency. Without the composite voltage signal, core frequency 212 recovers more slowly than core frequency 214 when the composite voltage signal is used.

[0032] FIG. 3 shows how the power supply manager reacts to architectural relaxations but not to the composite voltage signal.

[0033] In Figure 3, there are three plots on the same time axis: The top plot 310 shows how the current consumption of the core changes upon power-up and how the power manager spikes the current supply to meet the increasing demand.

[0034] At 1 microsecond, the core begins to enter a high power state, which causes a first spike 312 in the core's current consumption and a corresponding first voltage drop 322.

[0035] To avoid unsafe voltage drops, the core's architectural mitigation subsystem throttles the instructions being executed to allow the power manager to keep up with the amount of current it is supplying.

[0036] The power supply manager uses the voltage feedback signal to detect the first voltage drop 322 and responds by increasing the supply of current. However, due to inherent delays due to physical components and wire lengths, the power supply manager cannot respond with an increase in current until 1.025 microseconds, at which point the current steadily increases.

[0037] When the supplied current finally matches the consumed current, the architectural relaxation becomes ineffective, resulting in a second current spike 314 and a corresponding second voltage drop 324 at 1.05 microseconds.

[0038] The power supply manager again senses the second voltage drop 324 but takes time to respond, steadily increasing the supply draw until it is sufficient to meet the current demand of the high power state.

[0039] As shown in the middle plot 320, the voltage in the core had two drop events 322 and 324 corresponding to the current spikes 312 and 314, respectively.

[0040] And even though the buck power manager was able to increase its current supply to match the current draw for approximately 1.12 microseconds, it took much longer for the core voltage to return to the voltage before the first current spike 312. Overall, the peak voltage excursion was 60 mV compared to the voltage before entering the high power state.

[0041] As shown in plot 330 below, even when using architectural relaxation, the FLL clock frequency reduction system still had to reduce the frequency by 15% to keep the voltage safe.

[0042] 4 shows that the power manager's reaction time is faster when using a composite voltage signal. In this example, the compute core uses architectural relaxation to slow down its execution frequency, resulting in two current spikes 512 and 514.

[0043] As shown in the top plot 410, as soon as the first current spike 412 is detected, the system generates a composite voltage signal 426 and provides the composite voltage signal 426 to the power supply manager.

[0044] As a result, the power supply manager begins a more aggressive increase in current that continues even after the architectural relaxation is released just before the second spike 414 .

[0045] As a result, the power manager achieves a current supply that exceeds the core's current consumption in the high power state more quickly than the example shown in Figure 3. When using the composite voltage signal, the power manager achieved the target current with fewer boosts than without the composite voltage signal. In this example, the power manager used only one boost, taking less than 0.5 microseconds. The example in Figure 3 required two current increases, taking more than 1 microsecond.

[0046] As shown in the bottom plot 420, the core voltage 424 had two voltage drops 422 and 424 corresponding to the first spike 412 and the second spike 414, respectively, but the voltage drops 422 and 424 were smaller than the voltage drops 322 and 324 that occurred without using the composite voltage signal shown in FIG. 3.

[0047] Furthermore, the FLL clock frequency reduction is also small, resulting in a frequency reduction of only 6% and a peak voltage fluctuation of only 40mV.

[0048] Figure 5 shows how a composite voltage signal can be used to compensate for both architectural and frequency throttling in the same system. In this example, the compute core first uses architectural throttling. Then, when the voltage is still low, the system uses frequency throttling to further mitigate the increase in power demand. Similar to Figures 3-4, architectural throttling results in two current spikes 512 and 514.

[0049] As shown in FIG. 5, the initial transition to a high power state causes a first current spike 512, at which point the compute core implements architectural relaxations.

[0050] The system can then generate a trajectory-matched composite voltage signal 526 to cause the power supply manager to more aggressively increase the current supplied to the processing core.

[0051] When the current supplied by the power manager catches up with the current consumed by the processing core, there is a second current spike 514. At this point, the processing core may inject a second synthesized voltage signal 528 to attempt to compensate for frequency throttling, such as implemented by a FLL system.

[0052] As a result, the current supplied by the power supply manager is more constant than in the example shown in Figure 4. In other words, even when using a synthesized voltage signal to compensate for frequency throttling, the power supply manager will swing less between local high and low current values.

[0053] Therefore, overall frequency throttling is reduced, resulting in lower peak voltage fluctuations. As shown in Figure 5, the frequency reduction rate was only 4.5%, and the peak voltage fluctuation was only 30mV, compared to 40mV in Figure 4 and 60mV in Figure 3.

[0054] Embodiments of the subject matter and functional operations described herein can be implemented in digital electronic circuitry, tangibly embodied computer software or firmware, computer hardware, such as the structures disclosed herein and their structural equivalents, or one or more combinations thereof. Embodiments of the subject matter described herein can be implemented as one or more computer programs, i.e., one or more modules of computer program instructions encoded on a tangible, non-transitory storage medium for execution by or to control the operation of a data processing apparatus. The computer storage medium may be a machine-readable storage device, a machine-readable storage substrate, a random or serial access memory device, or one or more combinations thereof. Alternatively, or in addition, the program instructions can be encoded into an artificially generated transmitted signal, such as a machine-generated electrical, optical, or electromagnetic signal generated to encode information for transmission to a suitable receiver apparatus for execution by a data processing apparatus.

[0055] The term "data processing apparatus" refers to data processing hardware and encompasses all kinds of apparatus, devices, and machines for processing data, including, by way of example, a programmable processor, a computer, or multiple processors or multiple computers. An apparatus may be or further include special-purpose logic circuitry, such as an FPGA (field-programmable gate array) or an ASIC (application-specific integrated circuit). In addition to hardware, an apparatus may also optionally include code that creates an execution environment for a computer program, such as code that constitutes processor firmware, a protocol stack, a database management system, an operating system, or one or more combinations thereof.

[0056] A computer program, which may be called or described as a program, software, software application, app, module, software module, script, or code, can be written in any form of programming language, including compiled or interpreted, declarative or procedural, and can be deployed in any form, including as a stand-alone program or as a module, component, subroutine, or other unit suitable for use in a computing environment. A program may, but need not, correspond to a file in a file system. A program can be stored in a portion of a file that holds other programs or data, for example, one or more scripts stored in a markup language document, in a single file dedicated to the program, or in multiple cooperating files, for example, files that store one or more modules, subprograms, or portions of code. A computer program can be deployed to be executed on one computer or on multiple computers located at one site or distributed across multiple sites and interconnected by a data communications network.

[0057] The processes and logic flows described herein may be performed by one or more programmable computers executing one or more computer programs to perform functions by operating on input data and generating output. The processes and logic flows may also be performed by special purpose logic circuitry, such as an FPGA or an ASIC, or a combination of special purpose logic circuitry and one or more programmed computers.

[0058] A computer suitable for executing a computer program can be based on a general-purpose or special-purpose microprocessor, or both, or any other type of central processing unit. Typically, the central processing unit receives instructions and data from a read-only memory, a random-access memory, or both. The basic elements of a computer are a central processing unit for implementing and executing instructions and one or more memory devices for storing instructions and data. The central processing unit and memory may be supplemented by, or incorporated into, special-purpose logic circuitry. Typically, a computer also includes, or is operatively coupled to receive data from, transfer data to, or both of, one or more mass storage devices for storing data, such as, for example, magnetic, magneto-optical, or optical disks. However, such devices are not required for a computer. Furthermore, a computer can be embedded in other devices, such as a mobile phone, a personal digital assistant (PDA), a mobile audio or video player, a game console, a global positioning system (GPS) receiver, or a portable storage device, such as a universal serial bus (USB) flash drive, to name a few.

[0059] Computer-readable media suitable for storing computer program instructions and data include all types of non-volatile memory, media, and memory devices, including, for example, semiconductor memory devices such as EPROM, EEPROM, and flash memory devices, magnetic disks such as internal hard disks or removable disks, magneto-optical disks, and CD-ROM and DVD-ROM disks.

[0060] In addition to the above embodiments, the following embodiments are also innovative. Embodiment 1 is a processing core configured to initiate a transition from executing in a lower power state to executing in a higher power state; a power manager configured to increase a current supplied to the processing core when the processing core transitions from a lower power state to a higher power state; The device is configured to inject a composite voltage signal into a voltage feedback line of the power supply manager to cause the power supply manager to react more quickly to the transition by increasing the current supplied to the processing core in accordance with the composite voltage signal.

[0061] Example 2 is the device of example 1, wherein the device is configured to generate a composite voltage signal to compensate for architectural voltage relaxation that limits the rate at which instructions can be executed when a processing core transitions to a higher power state.

[0062] Embodiment 3 is the device of embodiment 2, wherein the composite voltage signal has a trajectory that matches the desired voltage drop due to transitions to the high power state.

[0063] Embodiment 4 is the device of any one of embodiments 1 to 3, wherein the device is configured to generate a synthesized voltage signal to compensate for relaxation of frequency throttling that limits the clock frequency of the processing core when the processing core transitions to a higher power state.

[0064] Example 5 is the device of Example 4, wherein the device is configured to generate different composite voltage signals to compensate for frequency throttling relaxation and architectural relaxation.

[0065] Embodiment 6 is a device according to any one of embodiments 1 to 5, wherein by injecting the composite voltage signal, the power supply manager increases the current supplied to the processing core with less boost than would be required if the composite voltage signal were not used.

[0066] A seventh embodiment is the device of any one of the first to sixth embodiments, wherein injecting the synthesized voltage signal reduces the amount of clock frequency throttling in the processing core when transitioning to a higher power state.

[0067] Embodiment 8 is a device according to any one of embodiments 1 to 7, wherein by injecting the composite voltage signal, the core frequency of the processing core recovers the voltage level from the low power state faster than without using the composite voltage signal.

[0068]

[0023] Embodiment 9 is a method performed by a device having a processing core and a power manager, the method comprising: initiating a transition by a processing core from executing in a lower power state to executing in a higher power state; the device injecting a synthesized voltage signal into a voltage feedback line of the power supply manager, causing the power supply manager to react more quickly to the transition by increasing the current supplied to the processing core; increasing, by the power supply manager in accordance with the composite voltage signal, the current supplied to the processing core after the processing core transitions from the lower power state to the higher power state.

[0069] Example 10 is the method of example 9, wherein the device is configured to generate a composite voltage signal to compensate for architectural voltage relaxation that limits the rate at which instructions can be executed when the processing core transitions to a higher power state.

[0070] Example 11 is the method of Example 10, wherein the composite voltage signal has a trajectory that matches the desired voltage drop due to transitions to the high power state.

[0071] Embodiment 12 is a method according to any one of embodiments 9 to 10, wherein the device is configured to generate a synthetic voltage signal to compensate for relaxation of frequency throttling that limits the clock frequency of the processing core when the processing core transitions to a high power state.

[0072] Example 13 is the method of Example 12, in which the device is configured to generate different composite voltage signals to compensate for the frequency throttling relaxation and the architecture relaxation.

[0073] Embodiment 14 is a method according to any one of embodiments 9 to 13, wherein by injecting the composite voltage signal, the power supply manager increases the current supplied to the processing core with less boost than would be required if the composite voltage signal were not used.

[0074] In a fifteenth embodiment, the method according to any one of the ninth to fourteenth embodiments, injecting the synthesized voltage signal reduces the amount of clock frequency throttling in the processing core when transitioning to a higher power state.

[0075] Embodiment 16 is a method according to any one of embodiments 9 to 15, wherein by injecting the composite voltage signal, the core frequency of the processing core recovers the voltage level from the low power state faster than if the composite voltage signal is not used.

[0076] While the specification contains many specific implementation details, these should not be construed as limiting the scope of any invention or the scope of patentable subject matter, but rather as descriptions of features that may be unique to particular embodiments of a particular invention. Certain features described herein in the context of separate embodiments may also be implemented in combination in a single embodiment. Conversely, various features of the invention that are described in the context of a single embodiment may also be implemented in multiple embodiments separately or in any suitable subcombination. Furthermore, even if features may be described above as functioning in a particular combination and originally claimed as such, one or more features from a claimed combination may, in some cases, be deleted from the combination, and the claimed combination may be directed to subcombinations or variations of the subcombination.

[0077] Similarly, while acts are shown in a particular order in the figures, this should not be understood as requiring that such acts be performed in the particular order or sequential order shown, or that all of the acts shown be performed, to achieve desirable results. In certain situations, multitasking and parallel processing may be advantageous. Furthermore, the separation of various system modules and components in the above-described embodiments should not be understood as requiring such separation in all embodiments, and it should be understood that the described program components and systems may generally be integrated into a single software product or packaged into multiple software products.

[0078] Specific embodiments of the subject matter have been described. Other embodiments are within the scope of the following claims. For example, the actions recited in the claims can be performed in a different order and still achieve desirable results. As an example, the processes depicted in the accompanying figures do not necessarily require the particular order shown, or sequential order, to achieve desirable results. In certain implementations, multitasking and parallel processing may be advantageous.

Claims

1. A device, a processing core configured to initiate a transition from executing in a lower power state to executing in a higher power state; a power manager configured to increase a current supplied to the processing core when the processing core transitions from the lower power state to the higher power state; The device is configured to inject a composite voltage signal into a voltage feedback line of the power supply manager to cause the power supply manager to react more quickly to the transition by increasing the current supplied to the processing core in accordance with the composite voltage signal.

2. 2. The device of claim 1, wherein the device is configured to generate the composite voltage signal to compensate for architectural voltage deceleration that limits the rate at which the processing core can execute instructions when it transitions to the higher power state.

3. The device of claim 2 , wherein the composite voltage signal has a trajectory that matches an intended voltage drop due to a transition to the high power state.

4. 4. The device of claim 1, wherein the device is configured to generate the synthesized voltage signal to compensate for relaxation of frequency throttling that limits a clock frequency of the processing core when the processing core transitions to the higher power state.

5. The device of claim 4 , wherein the device is configured to generate different composite voltage signals to compensate for frequency throttling relaxation and architectural relaxation.

6. 6. The device of claim 1, wherein by injecting the composite voltage signal, the power supply manager increases the current supplied to the processing core with less boost than would be required if the composite voltage signal were not used.

7. The device of any preceding claim, wherein injecting the synthesized voltage signal reduces the amount of clock frequency throttling in the processing core when transitioning to the higher power state.

8. 8. The device of claim 1, wherein injecting the composite voltage signal causes the core frequency of the processing core to recover its voltage level from the low power state faster than if the composite voltage signal were not used.

9. 1. A method performed by a device having a processing core and a power manager, comprising: initiating a transition by a processing core from executing in a lower power state to executing in a higher power state; the device injecting a composite voltage signal into a voltage feedback line of the power supply manager, causing the power supply manager to react more quickly to the transition by increasing the current supplied to the processing core; increasing, by the power supply manager in accordance with the composite voltage signal, the current supplied to the processing core after the processing core transitions from the lower power state to the higher power state.

10. 10. The method of claim 9, wherein the device is configured to generate the composite voltage signal to compensate for architectural voltage deceleration that limits the rate at which instructions can be executed when the processing core transitions to the higher power state.

11. The method of claim 10 , wherein the composite voltage signal has a trajectory that matches an intended voltage drop due to transitioning to the high power state.

12. 11. The method of claim 9, wherein the device is configured to generate the synthesized voltage signal to compensate for relaxation of frequency throttling that limits a clock frequency of the processing core when the processing core transitions to the higher power state.

13. The method of claim 12 , wherein the device is configured to generate different composite voltage signals to compensate for frequency throttling relaxation and architectural relaxation.

14. 14. The method of claim 9, wherein by injecting the composite voltage signal, the power supply manager increases the current supplied to the processing core with less boost than would be required if the composite voltage signal were not used.

15. The method of any one of claims 9 to 14, wherein injecting the synthesized voltage signal reduces the amount of clock frequency throttling in the processing core when transitioning to the higher power state.

16. 16. The method of any one of claims 9 to 15, wherein injecting the composite voltage signal causes the core frequency of the processing core to recover its voltage level from the low power state faster than without using the composite voltage signal.

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