Network precision quantization method, system, device, electronic device and readable medium

Abstract

The present disclosure provides a quantization method, an analog-to-digital converter, an electronic device, and a computer-readable storage medium. The method includes the steps of: obtaining a reference signal including a threshold decision segment reference signal and a quantization segment reference signal, and a signal to be quantized; performing threshold decision on the signal to be quantized using the threshold decision segment reference signal to determine effective signals to be quantized for a plurality of segments; and quantizing the effective signals to be quantized for any of the effective quantized signals for the plurality of segments using the quantization segment reference signal to obtain a quantization result for the signal to be quantized. The embodiments based on the present disclosure can improve the quantization speed.

Description

[Technical Field]

[0001] The present disclosure relates to the field of electronic technology, and more particularly to a quantization method, an analog-to-digital converter, an electronic device, and a computer-readable storage medium. [Background technology]

[0002] A single-slope ADC (Analog-to-Digital Converter) converts an analog signal to a digital signal by comparing the input analog voltage signal with a single-slope signal, converting the input voltage information into time information, and then converting the time information into a digital code. Single-slope ADCs have the advantages of simple structure, high scalability, and high accuracy, and can be applied in fields such as sensors, instruments, and image recognition. Summary of the Invention [Means for solving the problem]

[0003] The present disclosure provides a quantization method, an analog-to-digital converter, an electronic device, and a computer-readable storage medium.

[0004] In a first aspect, the present disclosure provides a method for manufacturing a semiconductor device comprising: obtaining a reference signal including a threshold decision segment reference signal and a quantization segment reference signal, and a quantization waiting signal; performing thresholding on the signals to be quantized using the thresholding segment reference signals to determine effective signals to be quantized for a plurality of segments; quantizing the effective signal to be quantized of any one of the effective quantized signals of the plurality of segments using the quantization segment reference signal to obtain a quantization result of the signal to be quantized. A quantization method is provided.

[0005] In a second aspect, the present disclosure provides a method for manufacturing a method of a medical device comprising: an acquisition module for acquiring a reference signal including a threshold decision segment reference signal and a quantization segment reference signal, and a quantization waiting signal; a first judgment module for performing threshold judgment on the signal to be quantized using the threshold judgment segment reference signal to determine effective signals to be quantized of multiple segments; a quantization module for quantizing any of the effective signals to be quantized among the effective quantized signals of the plurality of segments using the quantization segment reference signal to obtain a quantization result of the signals to be quantized. An analog-to-digital converter is provided.

[0006] In a third aspect, the present disclosure provides a method for manufacturing a method of a medical device comprising: at least one processor; a memory communicatively coupled to the at least one processor; The memory stores one or more computer programs executable by the at least one processor, the one or more computer programs being executed by the at least one processor to cause the at least one processor to perform the quantization method. Provide electronic devices.

[0007] In a fourth aspect, the present disclosure provides: A computer program is stored therein, the computer program implementing the quantization method when executed by a processor / processing core. A readable storage medium is provided.

[0008] In the quantization method provided by the embodiments of the present disclosure, the reference signal includes a threshold judgment segment reference signal and a quantization segment reference signal, and the threshold judgment segment reference signal is used to perform threshold judgment on the quantization signal, and a quantization signal that is susceptible to noise among the signals to be quantized is determined as an invalid segment quantization signal. When quantizing the signals to be quantized, it is not necessary to quantize all valid signals to be quantized, but only by quantizing any of the valid segment signals to be quantized among the multiple-segment valid signals to be quantized, the quantization result of the signals to be quantized can be obtained, thereby improving the efficiency of quantization.

[0009] The contents described herein are not intended to describe the key or important features of the embodiments of the present disclosure, and are not intended to limit the scope of the present disclosure. Other features of the present disclosure will be readily understood from the following description.

[0010] The drawings are intended to provide a better understanding of the present disclosure, constitute a part of the specification, and are intended to explain the present disclosure together with the embodiments of the present disclosure, but are not intended to constitute limitations on the present disclosure. These and other features and advantages will become more apparent to those skilled in the art after detailed description of exemplary embodiments is given with reference to the drawings. [Brief explanation of the drawings]

[0011] [Figure 1] FIG. 1 is a schematic diagram of an analog-to-digital converter provided by an embodiment of the present disclosure. [Figure 2] FIG. 2 is a waveform diagram of a reference signal in an embodiment of the present disclosure. [Figure 3] FIG. 3 is a block diagram of another analog-to-digital converter provided by an embodiment of the present disclosure. [Figure 4] FIG. 4 is a circuit diagram of an analog-to-digital converter provided by an embodiment of the present disclosure. [Figure 5] FIG. 5 is a voltage diagram output by the reference signal generating module of the embodiment of the present disclosure. [Figure 6] FIG. 6 is a circuit diagram of a second determination module provided by an embodiment of the present disclosure. [Figure 7] FIG. 7 is a flowchart diagram of a quantization method provided by an embodiment of the present disclosure. [Figure 8] FIG. 8 is a waveform diagram of another reference signal provided by an embodiment of the present disclosure. [Figure 9] FIG. 9 is a waveform diagram of yet another reference signal provided by an embodiment of the present disclosure. [Figure 10] FIG. 10 is an operation timing diagram of an analog-to-digital converter provided by an embodiment of the present disclosure. [Figure 11] FIG. 11 is a waveform diagram of a reference signal and a signal to be quantized provided by an embodiment of the present disclosure. [Figure 12] FIG. 12 is another waveform diagram of a reference signal and a signal to be quantized provided by an embodiment of the present disclosure. [Figure 13] FIG. 13 is a code value curve diagram output by an analog-to-digital converter provided in an embodiment of the present disclosure. [Figure 14] FIG. 14 is a diagram showing the code value curve output by a current analog-to-digital converter. [Figure 15] FIG. 15 is a flowchart of an analog-to-digital conversion method provided by an embodiment of the present disclosure. [Figure 16] FIG. 16 is a waveform diagram of a reference signal and a signal to be quantized provided by an embodiment of the present disclosure. [Figure 17] FIG. 17 is a waveform diagram of another reference signal and a signal to be quantized provided by an embodiment of the present disclosure. [Figure 18] FIG. 18 is a block diagram of an electronic device provided by an embodiment of the present disclosure. DETAILED DESCRIPTION OF THE INVENTION

[0012] In order to allow those skilled in the art to better understand the technical solution of the present disclosure, exemplary embodiments of the present disclosure will be described below in conjunction with the drawings. Although various details of the embodiments of the present disclosure are included for ease of understanding, they should be considered as merely illustrative. Therefore, those skilled in the art should recognize that various changes and modifications can be made to the embodiments described herein without departing from the scope and spirit of the present disclosure. Similarly, for the sake of clarity and conciseness, the following description will omit descriptions of known functions and structures.

[0013] Unless contradictory, the embodiments and features of the embodiments in the present disclosure can be combined with each other.

[0014] As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0015] The terms used herein are for the purpose of describing particular embodiments only and are not intended to limit the present disclosure. Unless the context clearly dictates otherwise, the singular forms "a," "an," and "the" used herein are intended to include the plural. Additionally, the use of the terms "comprising" and / or "consisting of" herein indicates the presence of said feature, whole, step, operation, member, and / or component, but does not preclude the presence or addition of one or more other features, wholes, steps, operations, members, components, and / or groups thereof. Similar terms, such as "connected" or "coupled," are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect.

[0016] Unless otherwise specified, the meanings of all terms (including technical and scientific terms) used in the present specification are the same as those commonly understood by those skilled in the art. For example, terms defined in a common dictionary should be interpreted as having a meaning consistent with the meaning in the context of the relevant art and this disclosure, and it is understood that they should not be interpreted as having an idealized or overly formal meaning unless the present specification clearly limits them.

[0017] The monoclinic ADC uses a ramp linearly falling reference signal to quantize the signal to be quantized, compares the reference signal with the signal to be quantized during the quantization process, counts the comparison result until the comparator rolls over, stores the count result in a latch, and obtains the quantization result of the signal to be quantized.

[0018] In the related art, all signals to be quantized must be quantized, and if the reference signal has an n-bit frequency, 2n clock cycles are required to complete the quantization, resulting in low quantization efficiency.

[0019] Research has revealed that there are low signal segments in the signals to be quantized that are susceptible to noise, and the low signal segments belong to the invalid signals to be quantized, and quantizing the invalid signals to be quantized also reduces the quantization efficiency.

[0020] In view of this, an embodiment of the present disclosure provides a quantization method that can improve quantization efficiency.

[0021] 1 is a schematic diagram of an analog-to-digital converter provided by an embodiment of the present disclosure. As shown in FIG. 1, the analog-to-digital converter includes an acquisition module 10 for acquiring an input signal of the analog-to-digital converter, such as a quantization waiting signal or a reference signal.

[0022] In some embodiments, the reference signal can be generated by the reference signal generating sub-module 11, for example, a DAC signal can be the reference signal generated by the reference signal generating sub-module, and the signal to be quantized is a signal that requires analog-to-digital conversion and is generated and obtained by the corresponding signal to be quantized generating sub-module 12. In this embodiment, the specific structures of the reference signal generating sub-module 11 and the signal to be quantized generating sub-module 12 are not limited. The output ends of the reference signal generating sub-module 11 and the signal to be quantized generating sub-module 12 are electrically connected to the input end of the first judgment module 20.

[0023] In some embodiments, as shown in Figure 2, the reference signal includes a threshold decision segment reference signal and a quantization segment reference signal, and the threshold decision segment reference signal performs a threshold decision on the signal to be quantized to determine the valid signal to be quantized and the invalid signal to be quantized in the quantization signal, and the quantization segment reference signal performs a quantization process on the signal to be quantized.

[0024] In some embodiments, the reference signal further comprises a sampling segment reference signal.

[0025] As shown in FIG. 2, the reference signal includes a sampling segment reference signal, a threshold judgment segment reference signal, and a quantization segment reference signal. That is, the reference signal is divided into three segments, the voltage value of the sampling segment reference signal is a constant value (e.g., V0), the voltage value of the threshold judgment segment reference signal includes multiple voltage values ​​(e.g., V1 and V2), and the voltage value of the quantization segment reference signal is a continuously changing value.

[0026] The first decision module 20 is for performing threshold decision on the signal to be quantized using the threshold decision segment reference signal, and determining the valid signal to be quantized.

[0027] Here, the threshold judgment can determine whether the signal awaiting quantization is valid or invalid based on the voltage comparison result by comparing the voltage value of the threshold judgment segment reference signal with the voltage value of the signal awaiting quantization.

[0028] In some embodiments, the first decision module 20 includes a comparator sub-module 21 and a counter sub-module 22 .

[0029] The comparator submodule 21 is for comparing the voltage value of the threshold judgment segment reference signal with the voltage value of the signal to be quantized to obtain a first comparison result. The first input terminal INN of the comparator submodule 21 is electrically connected to the output terminal of the signal to be quantized acquisition submodule 12, and the second input terminal of the comparator submodule 21 is electrically connected to the second output terminal of the reference signal generation submodule 11.

[0030] The counter sub-module 22 is for determining the threshold judgment result according to the first comparison result, and the input end of the counter sub-module 22 is connected to the output end of the comparator sub-module 21.

[0031] The quantization module 30 includes a comparator sub-module 21 and a counter sub-module 22. The comparator sub-module 21 is further used to compare the voltage value of the signal to be quantized with the voltage value of the quantization segment reference signal to obtain a second comparison result. The counter sub-module 22 is further used to record the rollover of the comparator sub-module 21 according to the second comparison result.

[0032] In some embodiments, as shown in FIG. 2, the threshold decision segment reference signals include a sampling segment reference signal V0, a ​​first threshold decision segment reference signal V1, and a second threshold decision segment reference signal V2.

[0033] In some embodiments, the first comparison result obtained by the comparator sub-module 21 includes: the voltage value Vx of the signal awaiting quantization is less than the voltage value V1 of the first threshold decision segment reference signal; the voltage value Vx of the signal awaiting quantization is equal to the voltage value V1 of the first threshold decision segment reference signal; the voltage value Vx of the signal awaiting quantization is greater than the voltage value V1 of the first threshold decision segment reference signal; the voltage value Vx of the signal awaiting quantization is less than the voltage value V2 of the second threshold decision segment reference signal; the voltage value Vx of the signal awaiting quantization is equal to the voltage value V2 of the second threshold decision segment reference signal; and the voltage value Vx of the signal awaiting quantization is greater than the voltage value V2 of the second threshold decision segment reference signal.

[0034] When the voltage value V1 of the first threshold judgment segment reference signal is greater than the voltage value V2 of the second threshold judgment segment reference signal, the threshold judgment result determined by the counter sub-module 22 includes: the voltage value Vx of the signal awaiting quantization is greater than the voltage value V1 of the first threshold judgment segment reference signal, and the voltage value Vx of the signal awaiting quantization is less than the voltage value V1 of the first threshold judgment segment reference signal; and at the same time, the voltage value Vx of the signal awaiting quantization is greater than the voltage value V2 of the second threshold judgment segment reference signal, and the voltage value Vx of the signal awaiting quantization is less than the voltage value V2 of the second threshold judgment segment reference signal, that is, the signal awaiting quantization is divided into three section segments by the first threshold judgment segment reference signal and the second threshold judgment segment reference signal.

[0035] In the embodiment of the present disclosure, the signal awaiting quantization is a differential signal, for example, a differential signal (VIN-VIP) between the first input signal VIN and the second input signal VIP, and a signal awaiting quantization close to 0 is determined as an invalid signal awaiting quantization, that is, a signal awaiting quantization of V1≦Vx≦V2 is determined as an invalid signal awaiting quantization, where Vx is the voltage value of the signal awaiting quantization.<V1とVx> The signal awaiting quantization of V2 is determined as a valid signal awaiting quantization.

[0036] The voltage value V1 of the first threshold decision segment reference signal and the voltage value V2 of the second threshold decision segment reference signal can be adjusted to control the size of the interval between the valid and invalid quantization waiting signals. In some embodiments, the voltage value V1 of the first threshold decision segment reference signal and the voltage value V2 of the second threshold decision segment reference signal can be adjusted to control the interval between the invalid quantization waiting signal and the invalid quantization waiting signal within a range of 10%. For example, if the voltage value of the quantization waiting signal is [-1V, 1V], the invalid quantization waiting signal can be controlled within a range of [-0.1V, 0.1V], and [-1V, -0.1V] and [0.1V, 1V] are valid quantization waiting signals.

[0037] The quantization module 30 is for quantizing any effective quantized signal among the effective quantized signals of the plurality of segments using the quantization segment reference signal to obtain a quantization result of the signal to be quantized.

[0038] In some embodiments, the quantization module 30 includes a comparator sub-module 21 and a counter sub-module 22, i.e., the quantization module 30 and the first judgment module 20 share the comparator sub-module 21 and the counter sub-module 22. In some embodiments, the quantization module 30 and the first judgment module 20 use different comparator sub-modules 21 and 22. However, sharing the comparator sub-module 21 and the counter sub-module 22 between the quantization module 30 and the first judgment module 20 can reduce the cost and volume of the analog-to-digital converter.

[0039] In the threshold judgment stage, the comparator sub-module 21 is used to compare the threshold judgment segment reference signal with the signal to be quantized to obtain a first comparison result, and the counter sub-module 22 is used to calculate statistics of the first comparison result obtained by the comparator sub-module 21 to determine the effective signal to be quantized. In the quantization stage, the comparator sub-module 21 is used to compare the quantization segment reference signal with the signal to be quantized to obtain a second comparison result, and the counter sub-module 22 is used to calculate statistics of the second comparison result obtained by the comparator sub-module 21 to obtain the quantization result of the signal to be quantized.

[0040] The comparator sub-module 21 is for comparing the voltage value of the quantization segment reference signal with the voltage value of the signal awaiting quantization of any one of the segments to obtain a second comparison result, and the counter sub-module 22 is for obtaining the quantization result of the signal awaiting quantization based on the second comparison result.

[0041] In some embodiments, the comparator sub-module 21 compares the quantization segment reference signal with the valid quantization waiting signal, and when a rollover occurs in the comparator sub-module 21, the counter sub-module 22 stops counting.

[0042] In some embodiments, as shown in FIG. 1, the analog-to-digital converter further includes a common mode voltage module 40 and a reference voltage module 50 .

[0043] The common mode voltage module 40 is for generating a common mode voltage VCM for the comparator sub-module 21. The output terminal of the common mode voltage module 40 is electrically connected to the second input terminal of the comparator sub-module 21.

[0044] When the common mode voltage module 40 is electrically connected to the second input terminal of the comparator sub-module 21, the reference signal of the signal to be quantized is sampled when the common mode voltage VCM is input to the comparator sub-module 21.

[0045] The reference voltage module 50 is for generating a reference voltage VREF for the comparator sub-module 21, and the output end of the reference voltage module is electrically connected to the second input of the comparator sub-module 21.

[0046] After the threshold judgment is completed, if the highest count value of the counter sub-module 22 is "1", the reference voltage module 50 is electrically connected to the second input terminal of the comparator sub-module 21; otherwise, the reference voltage module 50 is electrically disconnected from the second input terminal of the comparator sub-module 21.

[0047] In an embodiment of the present disclosure, the reference signal acquired by the acquisition module includes a threshold judgment segment reference signal and a quantization segment reference signal, the first judgment module uses the threshold judgment segment reference signal to perform threshold judgment on the quantization signal, removes invalid band quantization signals that are susceptible to noise from the quantization signal, and determines valid waiting quantization signals of multiple segments, and the quantization module does not need to quantize all valid waiting quantization signals when quantizing the signals waiting for quantization, but only quantizes the valid waiting quantization signal of any segment among the valid waiting quantization signals of the multiple segments to obtain the quantization result of the signals waiting for quantization, thereby providing an analog-to-digital converter that can improve quantization efficiency.

[0048] The embodiments of the present disclosure further provide an analog-to-digital converter. FIG. 3 is a block diagram of the analog-to-digital converter provided by the embodiments of the present disclosure. As shown in FIG. 3, the analog-to-digital converter includes an acquisition module 10, a first judgment module 20, and a second judgment module 13. The acquisition module 10 includes a reference signal generation sub-module 11 for generating a reference signal. The reference signal includes a sampling segment reference signal, a threshold judgment segment reference signal, and a quantization segment reference signal. The sampling segment reference signal V0 is for collecting the signal to be quantized. The threshold judgment segment reference signal is for determining the voltage range V1 of the signal to be quantized, particularly the maximum voltage value of the signal to be quantized. The quantization segment reference signal V2 is for quantizing the signal to be quantized.

[0049] As shown in FIG. 3, the reference signal generation sub-module 11 includes a digital-to-analog conversion circuit 111 and at least one threshold generation circuit 112. The digital-to-analog conversion circuit 111 is used to generate a base signal. The threshold generation circuit 112 is used to generate a threshold signal. In the embodiment of the present disclosure, the threshold judgment segment reference signal is a signal obtained by superimposing the base signal and the threshold signal. Since the hopping value (voltage value) generated by the threshold signal is greater than the hopping value generated by the base signal, the hopping value of the threshold judgment segment reference signal obtained by superimposing the base signal and the threshold signal is much greater than the hopping value generated by the base signal.

[0050] In the threshold determination step, by using a threshold determination segment reference signal with a large hopping value, the voltage range of the signal to be quantized can be determined quickly, and the efficiency of the threshold determination can be improved.

[0051] As shown in FIG. 4, the digital-to-analog conversion circuit 111 includes n+1 conversion means 110, one first output resistor R1, and one second output resistor R2, where the first output terminal of each conversion means 110 is electrically connected to the first output resistor R1, and the second output terminal of each conversion means 110 is connected to the second output resistor R2, and n is an integer greater than or equal to 0, that is, the digital-to-analog conversion circuit may include at least one conversion means.

[0052] In the embodiment of the present disclosure, the n number of conversion means 110 are controlled to change the current flowing through the first output resistor R1 or the second output resistor R2, and further change the output voltage Vramp of the digital-to-analog conversion circuit 111.

number

[0053] In some embodiments, each converting means 110 includes a current source I (e.g., I0, I1...IN), a first current source switch K11 and a second current source switch K12, a first terminal of the first current source switch K11 is electrically connected to the output terminal of the current source I, a first terminal of the second current source switch K12 is electrically connected to the output terminal of the current source I, a second terminal of the first current source switch K11 is the first output terminal of the converting means 110, and a second terminal of the second current source switch K12 is the second output terminal of the converting means 110.

[0054] By controlling the on / off of the first current source switch K11 and the second current source switch K12 in each conversion means 110, the output voltage Vramp of the digital-to-analog conversion circuit 111 can be adjusted.

[0055] When the digital-analog conversion circuit 111 includes one conversion means 110, when the first current source switch K11 is on and the second current source switch K12 is open, the digital-analog conversion circuit 111 outputs one voltage value, for example, the voltage value V01, and when the first current source switch K11 is open and the second current source switch K12 is closed, the digital-analog conversion circuit 111 outputs one voltage value, for example, the voltage value V02. Assuming that the voltage value V01 is smaller than the voltage value V02, it can be determined through the voltage values ​​V01 and V02 whether the signal to be quantized is smaller than the voltage value V01, greater than the voltage value V02, or between the voltage values ​​V01 and V02.

[0056] When the digital-to-analog conversion circuit 111 includes a plurality of conversion means 110, the first current source switch K11 and the second current source switch K12 in each conversion means 110 can be controlled to adjust the output voltage value of the digital-to-analog conversion circuit 111. The number of conversion means 110 for which the first current source switch K11 is turned off and the second current source switch K12 is turned on may be adjusted depending on the output voltage value of the digital-to-analog conversion circuit 111. When all the first current source switches K11 in each conversion means 110 are turned on and all the second current source switches K12 are turned off, or when all the first current source switches K11 in each conversion means 110 are turned off and all the second current source switches K12 are turned on, the output voltage value of the digital-to-analog conversion circuit 111 is maximum. When the first current source switch K11 of one conversion means 110 in the digital-to-analog conversion circuit 111 is turned on and all the first current source switches K11 of the other conversion means 110 are turned off, the output voltage of the digital-to-analog conversion circuit 111 is minimum.

[0057] In some embodiments, the threshold generation circuit 112 includes a threshold current source I20, a first threshold switch K21, and a second threshold switch K22, where a first terminal of the first threshold switch K21 is electrically connected to the output terminal of the threshold current source I20, a first terminal of the second threshold switch K22 is electrically connected to the output terminal of the threshold current source I20, a second terminal of the first threshold switch K21 is electrically connected to the first output resistor R1, and a second terminal of the second threshold switch K22 is electrically connected to the second output resistor R2.

[0058] When the first threshold switch K21 and the second threshold switch K22 are both off, the voltage value of the threshold signal output by the threshold generation circuit 112 is 0; when the first threshold switch K21 is on and the second threshold switch K22 is off, the voltage value of the threshold signal output by the threshold generation circuit 112 is VTH; when half of the first threshold switches K21 are off and half of the second threshold switches K22 are on, the voltage value of the threshold signal output by the threshold generation circuit 112 is VTH; when all of the first threshold switches K21 are turned off and all of the second threshold switches K22 are on, the voltage value of the threshold signal output by the threshold generation circuit 112 is 2VTH.

[0059] 5 is an output voltage diagram of the reference signal generation submodule in an embodiment of the present disclosure. As shown in FIGS. 4 and 5, when the threshold switch K21 is off and both threshold switches K22 are on, the voltage output by the reference signal generation submodule 11 is Vdac=Vramp+2VTH. When half of the threshold switches K21 are on and half of the threshold switches K22 are off, or when half of the threshold switches K21 are off and half of the threshold switches K22 are on, the voltage output by the reference signal generation submodule 11 is Vdac=Vramp+VTH. When both the first threshold switch K21 and the second threshold switch K22 are off, the voltage output by the reference signal generation submodule 11 is Vdac=Vramp. When adjusting the on or off of the first current source switch K11 and the second current source switch K12 in each conversion means 110, the voltage value output by the digital-to-analog conversion circuit 111 can be fine-tuned, and the voltage value output by the reference signal generation sub-module 11 can also be fine-tuned.

[0060] It should be noted that the digital-analog conversion circuit 111 provided by the embodiments of the present disclosure may include one or more threshold generation circuits 112. When the digital-analog conversion circuit 111 includes multiple threshold generation circuits 112, the multiple threshold generation circuits 112 are electrically connected to the digital-analog conversion circuit 111 in a parallel manner.

[0061] In some embodiments, the threshold generation circuit 112 controls the output voltage threshold at a high bit position of the digital-to-analog converter, i.e., when the digital-to-analog conversion circuit is at a high bit position, the threshold generation circuit 112 outputs a threshold signal, and when the digital-to-analog conversion circuit is at a low bit position, the threshold generation circuit 112 does not output a threshold signal. In the embodiments of the present disclosure, the voltage threshold output by the threshold generation circuit 112 may be a positive voltage or a negative voltage.

[0062] 3, in some embodiments, the analog-to-digital converter further includes a signal-to-be-quantized generating sub-module 12 and a second judgment module 13, where the signal-to-be-quantized generating sub-module 12 is for generating a signal-to-be-quantized. The embodiments of the present disclosure do not limit the specific structure of the signal-to-be-quantized generating sub-module 12. The second judgment module 13 is for determining the voltage range of the signal-to-be-quantized based on the v threshold judgment segment reference signal.

[0063] In some embodiments, the quantization-ready signal generating sub-module 12 may be a differential signal, for example, a differential signal between the first input signal VIN and the second input signal VIP (VIN-VIP).

[0064] In some embodiments, as shown in FIG. 6, the second judgment module includes a first capacitor C1, a second capacitor C2, a comparator A1, a first judgment switch K31 and a second judgment switch K32, wherein the first end of the first capacitor C1 is electrically connected to the output end of the quantization waiting signal generation module 12, the second end of the first capacitor C1 is electrically connected to the first input end of the comparator A1, the first end of the second capacitor C2 is electrically connected to the output end of the reference signal generation sub-module 11, and the second end of the second capacitor C2 is electrically connected to the second input end of the comparator A1.

[0065] The first terminal of the first decision switch K31 is electrically connected to the first input terminal of the comparator A1, the second terminal of the first decision switch K31 is electrically connected to the first voltage terminal of the comparator A1, the first terminal of the second decision switch K32 is electrically connected to the first input terminal of the comparator A1, and the second terminal of the second decision switch K32 is electrically connected to the second voltage terminal of the comparator A1. The first and second voltage terminals may be voltage signal terminals that are externally connected to the comparator A1. In some embodiments, the first and second voltage terminals may externally connect positive and negative voltage signals, respectively.

[0066] In the second judgment module, the first input terminal of the comparator A1 receives the waiting-for-quantization signal Vsig, and the second input terminal receives the threshold judgment segment reference signal Vdac, and compares the waiting-for-quantization signal Vsig with the threshold judgment segment reference signal Vdac to obtain a comparison result, where the comparison result includes: the threshold judgment segment reference signal Vdac is greater than the waiting-for-quantization signal Vsig, the threshold judgment segment reference signal Vdac is equal to the waiting-for-quantization signal Vsig, or the threshold judgment segment reference signal Vdac is less than the waiting-for-quantization signal Vsig.

[0067] For example, if the voltage of the threshold signal generated by the threshold generating circuit 112 is VTH, the first reference voltage Vdac1 is Vramp+VTH. If the voltage Vsig of the signal awaiting quantization is lower than the first reference voltage Vdac1, the output voltage of the threshold generating circuit 112 is adjusted to 0 and the second reference voltage Vdac2 is adjusted to Vramp, i.e., the voltage of the threshold determination segment reference signal jumps from Vramp+VTH to Vramp. At this time, if the voltage Vsig of the signal awaiting quantization is lower than the second reference voltage Vdac2, the voltage range of the voltage Vsig of the signal awaiting quantization can be determined to be between Vramp and Vramp+VTH. If the voltage Vsig of the signal awaiting quantization is higher than the first reference voltage Vdac1, the output voltage of the threshold generating circuit 112 is adjusted to 2VTH and the third reference voltage Vdac3 is adjusted to Vramp+2VTH, i.e., the voltage of the threshold determination segment reference signal jumps from Vramp+VTH to Vramp+2VTH. At this time, if the voltage Vsig of the signal awaiting quantization is smaller than the third reference signal Vdac3, it can be determined that the voltage range of the voltage Vsig of the signal awaiting quantization is between Vramp+VTH and Vramp+2VTH, thereby quickly and accurately determining the range of the voltage Vsig of the signal awaiting quantization. During the quantization stage, the maximum voltage value of the quantized segment reference signal can be accurately increased. Without the threshold signal of the threshold generating circuit 112, the hopping range of the base signal is at least one order of magnitude smaller than that of the threshold signal, so it takes a long time to determine the voltage range of the voltage Vsig of the signal awaiting quantization using only the base signal of the digital-to-analog conversion circuit.

[0068] In some embodiments, the analog-to-digital converter further includes a determining module for determining an increasing range value of the quantization segment reference signal based on the comparison result. For example, if the first threshold decision segment reference signal is smaller than the waiting-for-quantization signal and the second threshold decision segment reference signal is larger than the waiting-for-quantization signal, it can be determined that the waiting-for-quantization signal is between the first threshold decision segment reference signal and the second threshold decision segment reference signal, and the difference between the first threshold decision segment reference signal and the second threshold decision segment reference signal can be determined as the increasing range of the quantization segment reference signal.

[0069] In this analog-to-digital converter, the reference signal generation sub-module includes a digital-to-analog conversion circuit and a threshold generation circuit, and the threshold judgment segment reference signal is a superposition of the base signal generated by the digital-to-analog conversion circuit and the threshold signal generated by the threshold generation circuit. Since the threshold signal has a larger voltage hopping range than the base signal, the threshold judgment segment reference signal, which is the superposition of the base signal and the threshold signal, can generate a larger voltage hopping range. Therefore, the threshold judgment segment reference signal can be used to quickly and accurately determine the voltage range of the signal to be quantized, thereby shortening the threshold judgment time and thereby improving the quantization efficiency of the analog-to-digital converter.

[0070] The embodiments of the present disclosure also provide a quantization method that can improve quantization efficiency. Figure 7 is a flowchart of the quantization method provided by the embodiments of the present disclosure. As shown in Figure 7, the quantization method includes the following steps:

[0071] Step S301: obtain a signal to be quantized and a reference signal, the reference signal including a threshold judgment segment reference signal and a quantization segment reference signal, and the signal to be quantized and the reference signal are both analog signals.

[0072] Step S302: Perform threshold judgment on the quantized signal using the threshold judgment segment reference signal to determine valid signals to be quantized for multiple segments.

[0073] In step S303, the quantization segment reference signal is used to quantize any one of the segment effective signals awaiting quantization among the effective quantized signals of the plurality of segments, thereby obtaining a quantization result of the signals awaiting quantization.

[0074] In the quantization method provided by the embodiments of the present disclosure, the reference signal includes a threshold judgment segment reference signal and a quantization segment, and the threshold judgment segment reference signal is used to perform threshold judgment on the signals to be quantized, thereby eliminating invalid band quantized signals that are susceptible to noise from the signals to be quantized, and determining effective signals to be quantized of multiple segments. When quantizing the signals to be quantized, there is no need to quantize all effective signals to be quantized. Simply quantizing the effective signal to be quantized of any one of the effective signals to be quantized of the multiple segments can obtain the quantization result of the signals to be quantized, thereby improving the efficiency of quantization.

[0075] In some embodiments, the reference signal includes one or more segments of threshold decision segment reference signals, each segment having a different voltage value of the threshold decision segment reference signal.

[0076] As shown in Figure 2, the reference signal includes two threshold judgment segment reference signals, where the voltage value of the first threshold judgment segment reference signal is V1 and the voltage value of the second threshold judgment segment reference signal is V2, where V1 ≠ V2.

[0077] In some embodiments, the reference signal includes a one-segment threshold decision segment reference signal that can determine the forward direction of the quantization-awaiting signal or the negative direction of the quantization-awaiting signal. For example, the one-segment threshold decision segment reference signal is used to determine the forward direction of the quantization-awaiting signal, and if the voltage value of the quantization-awaiting signal is equal to or less than the voltage value of the threshold decision segment reference signal, the quantization-awaiting signal is an invalid quantization-awaiting signal; otherwise, the quantization-awaiting signal is a valid quantization-awaiting signal. For example, the one-segment threshold decision segment reference signal is used to determine the negative direction of the quantization-awaiting signal, and if the voltage value of the quantization-awaiting signal is equal to or greater than the voltage value of the threshold decision segment reference signal, the quantization-awaiting signal is an invalid quantization-awaiting signal; otherwise, the quantization-awaiting signal is a valid quantization-awaiting signal.

[0078] In some embodiments, the reference signal includes a plurality of threshold decision segment reference signals, such as, for example, in Figure 8, the reference signal includes four threshold decision segment reference signals, where the first threshold decision segment reference signal has a voltage value of V1, the second threshold decision segment reference signal has a voltage value of V2, the third threshold decision segment reference signal has a voltage value of V3, and the fourth threshold decision segment reference signal has a voltage value of V4, where V1 ≠ V2 ≠ V3 ≠ V4.

[0079] The voltage value V2 of the second threshold decision segment reference signal and the voltage value V4 of the fourth threshold decision segment reference signal are used to perform threshold decisions for the forward and negative directions of the awaiting quantization signal, respectively. If the voltage value of the awaiting quantization signal is greater than the voltage value V2 of the second threshold decision segment reference signal, the awaiting quantization signal is a valid awaiting quantization signal. If the voltage value of the awaiting quantization signal is less than the voltage value V2 of the second threshold decision segment reference signal and greater than the voltage value V4 of the fourth threshold decision segment reference signal, the awaiting quantization signal is an invalid awaiting quantization signal. If the voltage value of the awaiting quantization signal is less than the voltage value V4 of the fourth threshold decision segment reference signal, the awaiting quantization signal is a valid awaiting quantization signal.

[0080] If it is determined that the voltage value of the signal to be quantized is greater than the voltage value V2 of the second threshold judgment segment reference signal, the voltage value of the quantization segment reference signal is increased by referring to the voltage value V1 of the first threshold judgment segment reference signal, so that the quantization segment reference signal crosses the signal to be quantized. In this embodiment, the voltage value of the quantization segment reference signal can be more accurately determined by using multiple threshold judgment methods, and the voltage value of the quantization segment reference signal can be determined within an appropriate range without needing to adjust the voltage value of the quantization segment reference signal multiple times, thereby achieving more efficient quantization efficiency of the signal to be quantized.

[0081] Although the embodiments of the present disclosure only list two types of reference signals, the present disclosure is not limited thereto. The reference signal may include only one threshold judgment segment reference signal or multiple threshold judgment segment reference signals. When the reference signal includes multiple threshold judgment segment reference signals, the voltage values ​​of the threshold judgment segment reference signals for each segment are different.

[0082] In some embodiments, as shown in FIG. 2, the reference signal further includes a sampled segment reference signal, in which the analog-to-digital converter is for collecting a signal to be quantized, and does not perform threshold determination and quantization steps.

[0083] The threshold decision segment reference signal includes a first threshold decision segment reference signal and a second threshold decision segment reference signal, and a first voltage difference between the voltage value V1 of the first threshold decision segment reference signal and the voltage value V0 of the sampling segment reference signal is equal to a second voltage difference between the voltage value V2 of the second threshold decision segment reference signal and the voltage value V0 of the sampling segment reference signal. In other words, in the disclosed embodiment, the voltage value V1 of the first threshold decision segment reference signal and the voltage value V2 of the second threshold decision segment reference signal are symmetrical with respect to the voltage value V0 of the sampling segment reference signal. In the disclosed embodiment, the voltage value V1 of the first threshold decision segment reference signal and the voltage value V2 of the second threshold decision segment reference signal may be asymmetrical, but the voltage value V1 of the first threshold decision segment reference signal and the voltage value V2 of the second threshold decision segment reference signal are located on either side of the voltage value V0 of the sampling segment reference signal. For example, the voltage value V1 of the first threshold decision segment reference signal may be equal to the voltage value V0 of the sampling segment reference signal, or the voltage value V2 of the second threshold decision segment reference signal may be equal to the voltage value V0 of the sampling segment reference signal, or the voltage value V1 of the first threshold decision segment reference signal and the voltage value V2 of the second threshold decision segment reference signal may be different values.

[0084] In some embodiments, step S302 performs thresholding on the signals to be quantized using the thresholding segment reference signals to determine effective signals to be quantized for a plurality of segments, and includes the following steps: The method includes the steps of: when the reference signal jumps from the sampling segment reference signal to a first threshold judgment segment reference signal, performing threshold judgment on the signal awaiting quantization using the first threshold judgment segment reference signal to obtain a first threshold judgment result; when the reference signal jumps from the first threshold judgment segment reference signal to a second threshold judgment segment reference signal, performing threshold judgment on the signal awaiting quantization using the second threshold judgment segment reference signal to obtain a second threshold judgment result; and segmenting the signal awaiting quantization based on the first threshold judgment result and the second threshold judgment result to determine effective signals awaiting quantization of multiple segments.

[0085] In the embodiment of the present disclosure, the threshold judgment result includes a first threshold judgment result and a second threshold judgment result, where the first threshold judgment result is a comparison result between the voltage value of the first threshold judgment segment reference signal and the voltage value of the signal awaiting quantization, and the second threshold judgment result is a comparison result between the voltage value of the second threshold judgment segment reference signal and the voltage value of the signal awaiting quantization. Based on the first threshold judgment result and the second threshold judgment result, the signal awaiting quantization may be divided into multiple segments of effective signals awaiting quantization.

[0086] In some embodiments, when the voltage value of the first threshold judgment segment reference signal is equal to or greater than the voltage value of the second threshold judgment segment reference signal, the signal to be quantized is segmented according to the first threshold judgment result and the second threshold judgment result, and effective signals to be quantized of a plurality of segments are determined, which includes: If the voltage value of the quantization waiting signal is greater than the voltage value of the first threshold judgment segment reference signal, the quantization waiting signal is a valid quantization waiting signal; if the voltage value of the quantization waiting signal is less than or equal to the voltage value of the first threshold judgment segment reference signal and the voltage value of the quantization waiting signal is greater than or equal to the voltage value of the second threshold judgment segment reference signal, the quantization waiting signal is an invalid quantization waiting signal; and if the voltage value of the quantization waiting signal is less than the voltage value of the second threshold judgment segment reference signal, the quantization waiting signal is a valid quantization waiting signal.

[0087] For example, the voltage value Vx of the signal awaiting quantization is greater than the voltage value V1 of the first threshold judgment segment reference signal, and the voltage value Vx of the signal awaiting quantization is less than the voltage value V1 of the first threshold judgment segment reference signal; at the same time, the voltage value Vx of the signal awaiting quantization is greater than the voltage value V2 of the second threshold judgment segment reference signal, and the voltage value Vx of the signal awaiting quantization is less than the voltage value V2 of the second threshold judgment segment reference signal; that is, the signal awaiting quantization is divided into three section segments through the first threshold judgment segment reference signal and the second threshold judgment segment reference signal.

[0088] When the signal to be quantized is a differential signal, the signal to be quantized that is close to 0 is determined as an invalid signal to be quantized, that is, the signal to be quantized that satisfies V1≦Vx≦V2 is determined as an invalid signal to be quantized.<V1とVx> The signal awaiting quantization of V2 is determined as a valid signal awaiting quantization.

[0089] In some embodiments, step S303 uses the quantization segment reference signal to quantize any valid signal to be quantized among the valid quantized signals of the plurality of segments to obtain a quantization result of the signal to be quantized, and includes the following steps: The method includes the steps of comparing the quantized segment reference signal with any of the segment valid quantized signals to obtain a plurality of second comparison results, and obtaining a quantization result of the signal to be quantized based on the plurality of second comparison results.

[0090] In the embodiment of the present disclosure, when the quantization segment reference signal is compared with any of the signals to be quantized, a second comparison result is obtained, and the comparison is performed once per clock cycle, i.e., multiple times for each quantization, so that multiple second comparison results can be obtained for each quantization, and the quantization result can be obtained by counting these second comparison results.

[0091] In the embodiment of the present disclosure, it is only necessary to quantize any valid signals to be quantized, and it is not necessary to quantize all signals to be quantized, so the number of comparisons is reduced, and the quantization time requires only 2n-1 clocks, which improves the quantization speed compared to the current 2n clocks.

[0092] To better understand the analog-to-digital converter and quantization method provided by the embodiments of the present disclosure, the following takes as an example a case where the reference signal includes two threshold decision segment reference signals.

[0093] 9, in the embodiment of the present disclosure, the voltage value of the sampling segment reference signal is VA+VTH, the voltage value of the first threshold judgment segment reference signal is VA+2*VTH, and the voltage value of the second threshold judgment segment reference signal is VA, where VA=127*LSB and VTH=k*LSB, where LSB represents the quantization precision, and the k value can be set by a register.

[0094] The signal to be quantized is a differential signal (VIN-VIP) between the first input signal VIN and the second input signal VIP, and the embodiment of the present disclosure quantizes the differential value of the input differential signal, with a quantization precision of 8 bits, which can be set arbitrarily according to needs.

[0095] 1, in the embodiment of the present disclosure, the first input terminal INN of the comparator submodule 21 accesses the signal to be quantized, and the second input terminal INP of the comparator submodule 21 accesses the reference signal, which can also access the common-mode voltage signal or the reference voltage signal. When the output of the comparator submodule 21 is at a high level, the counter submodule 22 counts, and when the output of the comparator submodule 21 is at a low level, the counter submodule 22 does not count.

[0096] Figure 10 is an operation timing diagram of the analog-to-digital converter. In Figure 10, DAC_CODE is the input code value (each a corresponding decimal value) that controls the reference signal. In the sampling stage, DAC_CODE = (127 + k), in the threshold judgment stage, DAC_CODE becomes 127 from (127 + 2 k), and in the fine quantization stage, DAC_CODE decreases linearly from 127 to 0.

[0097] CNT_RSTN is a counter reset signal, which resets the comparator submodule to zero at the sampling stage.

[0098] CNT_CLK0 is the clock signal of the threshold judgment stage, there are only two high pulses in each quantization period, the rising edge is the trigger edge, the first rising edge corresponds to when DAC_CODE jumps from (127+2k) to 127, and determines which interval segment the quantization waiting signal is in.

[0099] CNT_CLK1 is the clock signal after the start of fine quantization, and there are 127 high pulses in each quantization period.

[0100] The LATCH signal is a signal that stores the code value Q<7:0> in the counter in a latch, and obtains the latched code value DOUT<7:0>.

[0101] As shown in Figures 1, 9 and 10, the quantization process of the analog-to-digital converter includes the following steps:

[0102] Step S61: In the sampling segment reference signal step, the first input signal VIN and the sampling segment reference signal are input to the first input terminal INN and the second input terminal INP of the comparator sub-module, respectively.

[0103] Step S62: The second input signal VIP is input to the first input terminal of the comparator sub-module, and at this time, the voltage change amount at the first input terminal of the comparator sub-module is the absolute value of (VIN-VIP).

[0104] Step S63: When the reference voltage jumps from the voltage value (VA + VTH) of the sampling segment reference signal to the voltage value (VA + 2*VTH) of the first threshold judgment segment reference signal, the first threshold judgment is performed. That is, the difference value of the quantization waiting signal (VIN - VIP) is compared with the magnitude of -VTH. If (VIN - VIP) < -VTH, the output of the comparator sub-module rolls over from high level to low level, the first rising edge of the CNT_CLK0 signal is not counted, and the counter sub-module outputs the first count digital value Q<7> = 0 and the second count digital value Q_TMP<7> = 0. If (VIN - VIP) > -VTH, the output of the comparator sub-module is at a high level, the first rising edge of the CNT_CLK0 signal counts one number, and the comparator sub-module outputs the first count digital value Q<7> = 0 and the second count digital value Q_TMP<7> = 1. Here, Q<7> is the maximum value in Q<7:0>.

[0105] Step S64: When the output voltage of the reference signal jumps from the voltage value (VA + 2*VTH) of the first threshold judgment segment reference signal to the voltage value VA of the second threshold judgment segment reference signal, the second threshold judgment is performed. That is, the difference value of (VIN - VIP) is compared with the magnitude of VTH. If (VIN - VIP) < VTH, the output of the comparator sub-module rolls over from high level to low level, the second rising edge of the CNT_CLK0 signal is not counted, and the output of the counter sub-module remains unchanged, that is, the first count digital value Q<7> = 0 and the second count digital value Q_TMP<7> = 1. If (VIN - VIP) > VTH, the output of the comparator sub-module is still at a high level, the second rising edge of the CNT_CLK0 signal continues to count one number, and the counter sub-module outputs the first count digital value Q<7> = 1 and the second count digital value Q_TMP<7> = 0.

[0106] Step S65: Segment the quantization waiting signal based on the above threshold judgment result.

[0107] When VIN - VIP < -VTH, the first count digital value Q<7> = 0, the second count digital value Q_TMP<7> = 0, and the quantization waiting signal is a valid quantization waiting signal.

[0108] When -VTH <= VIN - VIP <= VTH, the first counter digital value Q<7> = 0, the second counter digital value Q_TMP<7> = 1, and the quantization waiting signal is an invalid quantization waiting signal.

[0109] When VIN - VIP >= VTH, the first counter digital value Q<7> = 1, the second counter digital value Q_TMP<7> = 0, and the quantization waiting signal is a valid quantization waiting signal.

[0110] When the first count digital value Q<7> = 0, the reference voltage module is electrically connected to the second input terminal INP of the comparator sub - module. At this time, the value of the second input terminal INP is VREF, that is, VREF = VCM + VTH + VA. When the first count digital value Q<7> = 1, the reference voltage module and the second input terminal INP of the comparator sub - module are disconnected, and the value of the second input terminal INP is maintained as it is.

[0111] It is not difficult to understand that according to the threshold judgment result, the quantization waiting signal is divided into three segments, and the middle segment is an invalid quantization waiting signal close to 0.

[0112] Step S66: Quantize the valid quantization waiting signal of one segment based on the threshold judgment result.

[0113] In step S66, the threshold determination result is the first count digital value Q <7> =0, and when the differential signal (VIN-VIP)>0, the voltage of the quantization segment reference signal decreases linearly from VA to 0, and quantization is performed according to the waveform shown in Figure 11. The waveforms of the first input terminal INN and the first input terminal INP of the comparator submodule, the first input terminal INP of the comparator submodule, decrease from VCM+VTH+VA to VCM+VTH. The threshold judgment result is the first count digital value Q <7> When V = 1 and (VIN - VIP) > 0, the voltage of the quantization segment reference signal decreases linearly from VA to 0, performing quantization according to the waveform shown in Figure 12. The first input terminal INP of the comparator submodule decreases from VCM - VTH to VCM - VTH - VA. Each fine quantization requires only 27 - 1 = 127 clock cycles, which is shorter than the quantization time of a conventional 8-bit monoclinic ADC (the conventional quantization time is 28 - 1 clock cycles). The quantization segment reference signal of the reference signal shown in Figure 11 has a signal value rising process at the start of quantization compared to the voltage value of the second threshold judgment segment reference signal. That is, in the reference signal of Figure 11, at the junction of the "threshold judgment" and "quantization" stages, the reference signal rises from VCM - VTH to VCM + VTH + VA, causing the ramp signal of the quantization reference signal and the quantization wait signal to intersect. It can be understood that the elevation value of the quantized segment reference signal can be determined according to an empirical value or in combination with the voltage value of the first threshold decision segment reference signal.

[0114] Step S67: In the counter submodule, all counter code values ​​Q<7:0> are stored in a latch (not shown) when the LATCH signal is in a high pulse, to obtain a quantized code value DOUT<7:0>.

[0115] 13 is a diagram illustrating the output code value curve of an analog-to-digital converter according to an embodiment of the present disclosure. Here, the horizontal axis represents the difference value of the signal to be quantized, i.e., (VIN-VIP), and the vertical axis represents the 8-bit code value of the quantized output. As can be seen from the diagram, for the invalid signal to be quantized segment (VIN-VIP)=[-VTH,VTH], the output code value is 8'h7f, i.e., no quantization is performed. When (VIN-VIP)>VTH, the output code value is within (8'h7f,8'hff), and when (VIN-VIP)<-VTH, the output code value is within [0,8'h7f].

[0116] 14 is a diagram showing the code value curve output by a current analog-to-digital converter. As can be seen from FIG. 14, the invalid signal segment awaiting quantization [-VTH, VTH] is also quantized. Quantizing the invalid signal segment awaiting quantization reduces the efficiency of quantization. On the other hand, in the embodiment of the present disclosure, only the valid signal segments awaiting quantization are quantized, thereby improving the quantization efficiency. Furthermore, only one segment of the valid signal segments awaiting quantization can be selected and quantized, thereby further improving the quantization efficiency.

[0117] The quantization method provided by the embodiments of the present disclosure can generate a threshold judgment segment reference signal with a large hopping value in the threshold judgment step, so that the voltage range of the signal to be quantized can be quickly determined.

[0118] 15 is a flowchart of a quantization method provided by an embodiment of the present disclosure. As shown in FIG. 15, the quantization method includes: The method includes a step S601 of obtaining a reference signal, which includes a threshold judgment segment reference signal, and the threshold judgment segment reference signal is a signal obtained by superposing a base signal and a threshold signal.

[0119] In some embodiments, the base signal may be provided by a digital-to-analog conversion circuit provided by an embodiment of the present disclosure, and the threshold signal may be provided by a threshold generation circuit provided by an embodiment of the present disclosure.

[0120] Step S602: Determine the voltage range of the signal to be quantized according to the threshold judgment segment reference signal.

[0121] The threshold decision segment reference signal is compared with the signal to be quantized. If the voltage value of the threshold decision segment reference signal is higher than the voltage value of the signal to be quantized, the voltage value of the threshold decision segment reference signal is decreased before comparison. If the voltage value of the threshold decision segment reference signal is lower than the voltage value of the signal to be quantized, the voltage value of the threshold decision segment reference signal is increased before comparison. Through multiple comparisons, the voltage range of the signal to be quantized can be determined, which can provide basis for determining the voltage value of the subsequent quantization segment reference signal.

[0122] In some embodiments, the voltage values ​​of the threshold signal include a plurality of voltage thresholds, and the plurality of voltage thresholds are arranged in an arithmetic sequence, with the voltage difference values ​​between two adjacent voltage thresholds being equal.

[0123] Here, the voltage value of the threshold signal includes multiple voltage thresholds, and the threshold judgment segment reference signal generated by superposing the threshold signal and the base signal includes multiple voltage values. As shown in Figure 2, the voltage value of the threshold signal includes two voltage thresholds, namely V1 and V2, and the corresponding threshold judgment segment reference signal includes Vramp+2 VTH and Vramp.

[0124] In some embodiments, the threshold signal control bit and the input control bit of the digital-to-analog conversion circuit are controlled to adjust the voltage threshold output by the reference signal generation sub-module. In some embodiments, the threshold signal is generated at a high bit position. For example, when the potential of the digital-to-analog conversion circuit is at a high bit position, the threshold generation circuit outputs the threshold signal.

[0125] In some embodiments, the reference signal further includes a quantization segment reference signal that quantizes the signal to be quantized, the quantization segment reference signal decreasing linearly from a first voltage value to a second voltage value, the first voltage value being greater than the signal to be quantized and the second voltage value being less than the signal to be quantized.

[0126] In some embodiments, step S602 determines a voltage range of the signal awaiting quantization based on the threshold decision segment reference signal, and includes the steps of: comparing the signal awaiting quantization with the threshold decision segment reference signal, and determining a range of the signal awaiting quantization based on the comparison result, where the comparison result includes: the threshold decision segment reference signal is greater than the signal awaiting quantization, the threshold decision segment reference signal is equal to the signal awaiting quantization, or the threshold decision segment reference signal is less than the signal awaiting quantization.

[0127] After comparing the signal to be quantized with the threshold decision segment reference signal, the range of the signal to be quantized can be determined based on the comparison result. For example, if the first threshold decision segment reference signal is smaller than the signal to be quantized and the second threshold decision segment reference signal is larger than the signal to be quantized, it can be determined that the signal to be quantized is between the first threshold decision segment reference signal and the second threshold decision segment reference signal.

[0128] In some embodiments, after determining the voltage range of the signal to be quantized based on the threshold decision segment reference signal, the method further includes determining to increase the range of the quantization segment reference signal if the signal to be quantized is equal to or greater than the threshold decision segment reference signal.

[0129] 16 is a waveform diagram of a reference signal and a signal waiting to be quantized provided by an embodiment of the present disclosure. As shown in FIG. 16, INN is a signal at the first input terminal input to comparator A1, and INP is a signal at the second input terminal input to comparator A1. The signal waiting to be quantized is a differential signal INN=VIN-VIP. In the threshold determination step, the signal waiting to be quantized is compared with the threshold determination segment reference voltage Vramp+VTH and the threshold determination reference voltage Vramp-VTH. After the voltage value of the signal waiting to be quantized INN is determined to be greater than the threshold determination reference voltage Vramp+VTH, the first voltage value of the quantization segment reference signal is set as the threshold determination reference voltage Vramp+VTH+VA. Vramp+VTH+VA is greater than the differential signal INN, allowing the quantization segment reference signal and the signal waiting to be quantized to cross each other.

[0130] 17 is a waveform diagram of another reference signal and a signal waiting to be quantized provided by an embodiment of the present disclosure. As shown in FIG. 17, INN is a signal input to the first input terminal of the comparator A1, and INP is a signal input to the second input terminal of the comparator A1. The signal waiting to be quantized is a difference signal INN=VIN-VIP. In the threshold determination step, the signal waiting to be quantized is compared with the threshold determination reference voltage Vramp+VTH and the threshold determination reference voltage Vramp-VTH. After the voltage value of the signal waiting to be quantized INN is determined to be less than the threshold determination reference voltage Vramp-VTH, the first voltage value of the quantization segment reference signal is set to be equal to or greater than the threshold determination reference voltage Vramp-VTH, so that the quantization segment reference signal and the signal waiting to be quantized intersect.

[0131] In the analog-to-digital conversion method provided by the embodiments of the present disclosure, the reference signal generation sub-module includes a digital-to-analog conversion circuit and a threshold generation circuit, and the threshold judgment segment reference signal is a superposition of the base signal generated by the digital-to-analog conversion circuit and the threshold signal generated by the threshold generation circuit, where the threshold signal has a larger voltage hopping range than the base signal, and the threshold judgment segment reference signal, which is the superposition of the base signal and the threshold signal, can generate a larger voltage hopping range. Therefore, the threshold judgment segment reference signal can be used to quickly and accurately determine the voltage range of the signal to be quantized, thereby shortening the threshold judgment time and thereby improving the quantization efficiency of the analog-to-digital converter.

[0132] The quantization method and analog-to-digital converter provided by the embodiments of the present disclosure can be applied to various fields, such as various sensors, instruments, and image and voice recognition, and can increase the quantization speed while also combining the advantages of high accuracy and small area of ​​an ADC.

[0133] It is understood that the above-mentioned method embodiments and analog-to-digital converters mentioned in this disclosure can be combined with each other to form combined embodiments, provided that the principles and logic are not violated. Due to space limitations, this disclosure will not provide a detailed explanation. Those skilled in the art will understand that the specific execution order of each step in the above-mentioned method of a specific embodiment should be determined by its function and possible inherent logic.

[0134] FIG. 18 is a block diagram of an electronic device provided by an embodiment of the present disclosure.

[0135] Referring to FIG. 18, an embodiment of the present disclosure provides an electronic device including at least one processor 1101, at least one memory 1102, and one or more I / O interfaces 1103 connected between the processor 1101 and the memory 502, wherein the memory 1102 stores one or more computer programs executable by the at least one processor 1101, and the one or more computer programs are executed by the at least one processor 1101 to cause the at least one processor 1101 to perform the above-mentioned quantization method.

[0136] An embodiment of the present disclosure further provides a computer-readable storage medium having a computer program stored thereon, the computer program implementing the above quantization method when executed by a processor / processing core. The computer-readable storage medium may be a volatile or non-volatile computer-readable storage medium.

[0137] An embodiment of the present disclosure further provides a computer program product including computer-readable code or a non-volatile computer-readable storage medium having computer-readable code thereon, the computer-readable code, when executed by a processor in an electronic device, causing the processor in the electronic device to perform the above-described quantization method.

[0138] Those skilled in the art will understand that all or some of the steps of the methods, systems, and devices disclosed above may be implemented as software, firmware, hardware, or a suitable combination thereof. In hardware embodiments, the division between the functional modules / means mentioned in the above description does not necessarily correspond to the division of physical components; for example, one physical component may have multiple functions, or one function or step may be performed jointly by several components. Some or all of the physical components may be implemented as software executed by a processor, such as a central processing unit, digital signal processor, or microprocessor, or as hardware, or as an integrated circuit such as a dedicated integrated circuit. Such software may be located on a computer-readable medium, which may include a computer storage medium (or non-transitory medium) and a communication medium (or transitory medium).

[0139] As those skilled in the art will appreciate, the term computer storage media includes volatile and nonvolatile, removable and non-removable media implemented in any method or technology for storage of information (e.g., computer-readable instructions, data structures, program modules, or other data). Computer storage media includes, but is not limited to, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM), static random access memory (SRAM), flash memory or other memory technology, portable compressed disk read-only memory (CD-ROM), digital versatile disk (DVD) or other optical disk storage, magnetic cassettes, magnetic tape, magnetic disk storage or other magnetic storage devices, or any other medium used to store the desired information and accessible by a computer. In addition, those skilled in the art will appreciate that communication media typically include computer-readable instructions, data structures, program modules, or other data in a modulated data signal such as a carrier wave or other transmission mechanism, and can include any information delivery media.

[0140] The computer-readable program instructions described herein can be downloaded to each computing / processing device from a computer-readable storage medium, or can be downloaded to an external computer or external storage device via a network, such as the Internet, a local area network, a wide area network, and / or a wireless network. The network may include copper transmission cables, fiber optic transmissions, wireless transmissions, routers, firewalls, switches, gateway computers, and / or edge servers. A network adapter card or network interface in each computing / processing device receives the computer-readable program instructions from the network and forwards the computer-readable program instructions for storage in a computer-readable storage medium stored in each computing / processing device.

[0141] Computer program instructions for carrying out the operations of the present disclosure may be assembly instructions, instruction set architecture (ISA) instructions, machine instructions, machine-related instructions, microcode, firmware instructions, state-setting data, or source or object code written in any combination of one or more programming languages, including, for example, object-oriented programming languages ​​such as Smalltalk, C++, and the like, and conventional procedural programming languages ​​such as "C" or similar programming languages. The computer-readable program instructions may be executed entirely on the user computer, partially on the user computer, as a separate software package, partially on the user computer and partially on a remote computer, or entirely on a remote computer or server. In situations involving remote computers, the remote computer may be connected to the user computer via any type of network, including a local area network (LAN) or a wide area network (WAN), or may be connected to an external computer (e.g., connected via the Internet through an Internet Service Provider). In some embodiments, state information of computer-readable program instructions, such as programmable logic circuits, field programmable gate arrays (FPGAs), or programmable logic arrays (PLAs), can be used to personalize electronic circuits that execute computer-readable program instructions to implement aspects of the present disclosure.

[0142] The computer program product described herein may be tangibly embodied in hardware, software, or a combination thereof. In an alternative embodiment, the computer program product is tangibly embodied as a computer storage medium. In another alternative embodiment, the computer program product is tangibly embodied as a software product, such as a software development kit (SDK).

[0143] Aspects of the present disclosure have been described herein based on flowchart illustrations and / or block diagrams of methods, apparatuses (systems), and computer program products according to embodiments of the present disclosure. It will be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer-readable program instructions.

[0144] These computer-readable program instructions can be provided to a processor of a general-purpose computer, special-purpose computer, or other programmable data processing apparatus to produce an apparatus that, when executed by the processor of the computer or other programmable data processing apparatus, implements the functions / acts specified in one or more blocks in the flowchart illustrations and / or block diagrams. These computer-readable program instructions can be stored on a computer-readable storage medium, and the instructions cause a computer, programmable data processing apparatus, and / or other device to operate in a particular manner. Thus, a computer-readable medium having instructions stored thereon includes an article of manufacture containing instructions for implementing the functions / acts specified in one or more blocks in the flowchart illustrations and / or block diagrams.

[0145] The computer-readable program instructions can be loaded into a computer, other programmable data processing apparatus, or other device and caused to execute a sequence of operational steps on the computer, other programmable data processing apparatus, or other device to complete a computer-implemented process, thereby executing the instructions on the computer, other programmable data processing apparatus, or other device to implement the functions / acts defined in one or more blocks of the flowchart diagrams and / or block diagrams.

[0146] The flowcharts and block diagrams in the drawings illustrate possible architectures, functions, and operations based on systems, methods, and computer program products according to several exemplary embodiments of the present disclosure. In this regard, each block in the flowcharts or block diagrams may represent a module, program segment, or part of instructions. The module, program segment, or part of instructions includes one or more executable instructions for implementing a given logical function. In some alternatives, the functions depicted in the blocks may occur in a different order than depicted in the drawings. For example, two consecutive blocks may actually be executed essentially in parallel, or they may be executed in the reverse order depending on the functionality involved. Note that each block in the block diagrams and / or flowcharts, and combinations of blocks in the block diagrams and / or flowcharts, may be implemented in a dedicated hardware-based system that performs a given function or operation, or in a combination of dedicated hardware and computer instructions. Although exemplary embodiments are disclosed herein and specific terms are employed, these should be used and interpreted in a general, illustrative sense only, and not for limiting purposes. It will be apparent to those skilled in the art that in some instances, unless expressly indicated otherwise, features, characteristics, and / or elements described in combination with a particular embodiment may be used alone, or features, characteristics, and / or elements described in combination with other embodiments may be used in combination. Accordingly, those skilled in the art will recognize that various changes in form and detail may be made without departing from the scope of the present disclosure as defined by the appended claims.

Claims

1. obtaining a reference signal including a threshold decision segment reference signal and a quantization segment reference signal, and a quantization waiting signal; performing thresholding on the signals to be quantized using the thresholding segment reference signals to determine effective signals to be quantized for a plurality of segments; quantizing the effective signal to be quantized of any one of the effective quantized signals of the plurality of segments using the quantization segment reference signal to obtain a quantization result of the signal to be quantized. Quantization method characterized by:

2. The reference signal includes one or more segments of the threshold decision segment reference signal, each segment having a different voltage value of the threshold decision segment reference signal.

2. The method of claim 1 .

3. the reference signal further comprises a sampling segment reference signal; the threshold decision segment reference signals include a first threshold decision segment reference signal and the second threshold decision segment reference signal; A first voltage difference value between the voltage value of the first threshold decision segment reference signal and the voltage value of the sampling segment reference signal is equal to a second voltage difference value between the voltage value of the second threshold decision segment reference signal and the voltage value of the sampling segment reference signal.

3. The method of claim 2.

4. The step of performing threshold judgment on the signals to be quantized using the threshold judgment segment reference signals to determine effective signals to be quantized for a plurality of segments includes: When the reference signal jumps from the sampling segment reference signal to the first threshold judgment segment reference signal, performing threshold judgment on the signal to be quantized using the first threshold judgment segment reference signal to obtain a first threshold judgment result; When the reference voltage jumps from the first threshold judgment segment reference signal to the second threshold judgment segment reference signal, performing threshold judgment on the signal to be quantized using the second threshold judgment segment reference signal to obtain a second threshold judgment result; segmenting the signal to be quantized based on the first threshold judgment result and the second threshold judgment result, and determining effective signals to be quantized for the plurality of segments.

4. The method according to claim 3.

5. a voltage value of the first threshold decision segment reference signal is equal to or greater than a voltage value of the second threshold decision segment reference signal; The step of segmenting the signal to be quantized based on the first threshold judgment result and the second threshold judgment result, and determining effective signals to be quantized of the plurality of segments, includes: When the voltage value of the signal awaiting quantization is greater than the voltage value of the first threshold decision segment reference signal, the signal awaiting quantization is set as the valid signal awaiting quantization; When the voltage value of the waiting-for-quantization signal is equal to or less than the voltage value of the first threshold decision segment reference signal and the voltage value of the waiting-for-quantization signal is equal to or greater than the voltage value of the second threshold decision segment reference signal, the waiting-for-quantization signal is set as an invalid waiting-for-quantization signal. If the voltage value of the signal awaiting quantization is smaller than the voltage value of the second threshold decision segment reference signal, the signal awaiting quantization is set as the valid signal awaiting quantization.

5. The method of claim 4.

6. The step of quantizing the effective signal to be quantized of any one of the effective quantized signals of the plurality of segments using the quantization segment reference signal to obtain a quantization result of the signal to be quantized, comparing a quantization segment reference signal with the valid signal to be quantized of any segment to obtain a plurality of second comparison results; and obtaining a quantization result of the signal to be quantized based on the plurality of second comparison results.

5. The method of claim 4.

7. the threshold judgment segment reference signal is a signal obtained by superposing a base signal and a threshold signal; A voltage range of the signal to be quantized is determined based on the threshold decision segment reference signal.

3. The method according to claim 1 or 2.

8. The voltage value of the threshold signal includes a plurality of voltage thresholds, the plurality of voltage thresholds are arranged in an arithmetic manner, and a voltage difference value between two adjacent voltage thresholds is equal.

8. The method of claim 7.

9. The quantization segment reference signal is used to quantize the signal to be quantized, and the quantization segment reference signal decreases linearly from a first voltage value to a second voltage value, the first voltage value being greater than the signal to be quantized, and the second voltage value being less than the signal to be quantized.

8. The method of claim 7.

10. determining a voltage range of the signal to be quantized based on the threshold decision segment reference signal; comparing the signal to be quantized with the threshold decision segment reference signal, and determining the range of the signal to be quantized based on the comparison result; After the step of determining the voltage range of the signal to be quantized based on the threshold decision segment reference signal, If the to-be-quantized signal is equal to or greater than the threshold decision segment reference signal, determining to widen the range of the quantized segment reference signal is further included.

10. The method of claim 9.

11. an acquisition module for acquiring a reference signal including a threshold decision segment reference signal and a quantization segment reference signal, and a quantization waiting signal; a first judgment module for performing threshold judgment on the signal to be quantized using the threshold judgment segment reference signal to determine effective signals to be quantized of multiple segments; a quantization module for quantizing any of the effective signals to be quantized among the effective quantized signals of the plurality of segments using the quantization segment reference signal to obtain a quantization result of the signals to be quantized.

1. An analog-to-digital converter comprising:

12. The first determination module: a comparator sub-module, which compares the voltage value of the threshold judgment segment reference signal with the voltage value of the signal to be quantized to obtain a first comparison result, and whose first input terminal is electrically connected with the first output terminal of the acquisition module and whose second input terminal is electrically connected with the second output terminal of the acquisition module; a counter sub-module, the counter sub-module being used to determine a threshold judgment result based on the first comparison result, the input terminal of which is connected to the output terminal of the comparator sub-module; 12. An analog-to-digital converter according to claim 11.

13. The comparator sub-module is further used for comparing the voltage value of the quantization segment reference signal with the voltage value of the valid signal to be quantized of any segment to obtain a second comparison result; The counter sub-module is further used for obtaining a quantization result of the signal to be quantized according to the second comparison result.

13. An analog-to-digital converter according to claim 12.

14. a common-mode voltage module, used to generate an initial common-mode voltage of the comparator sub-module, and having an output terminal electrically connected to the second input terminal of the comparator sub-module; a reference voltage module for generating a reference voltage for the comparator sub-module, the output terminal of which is electrically connected to the second input terminal of the comparator sub-module; 13. An analog-to-digital converter according to claim 12.

15. The acquisition module: a reference signal generation sub-module for generating the reference signal; The reference signal generation sub-module: a digital-to-analog conversion circuit for generating a base signal; at least one threshold generating circuit for generating a threshold signal; The threshold judgment segment reference signal is a signal obtained by superposing the base signal and the threshold signal.

12. An analog-to-digital converter according to claim 11.

16. The digital-to-analog conversion circuit includes n conversion means, a first output resistor, and a second output resistor, wherein the first output terminal of each conversion means is electrically connected to the first output resistor, and the second output terminal of each conversion means is electrically connected to the second output resistor, and n is an integer equal to or greater than 1.

16. An analog-to-digital converter according to claim 15.

17. The converting means includes a current source, a first current source switch, and a second current source switch, a first terminal of the first current source switch is electrically connected to an output terminal of the current source, a first terminal of the second current source switch is electrically connected to an output terminal of the current source, a second terminal of the first current source switch is a first output terminal of the converting means, and a second terminal of the second current source switch is a second output terminal of the converting means.

17. An analog-to-digital converter according to claim 16.

18. The threshold generation circuit includes a threshold current source, a first threshold switch, and a second threshold switch, a first terminal of the first threshold switch electrically connected to an output terminal of the threshold current source, a first terminal of the second threshold switch electrically connected to an output terminal of the threshold current source, a second terminal of the first threshold switch electrically connected to the first output resistor, and a second terminal of the second threshold switch electrically connected to the second output resistor.

17. An analog-to-digital converter according to claim 16.

19. The acquisition module: further comprising a quantization-awaiting signal generating submodule for generating the quantization-awaiting signal; The analog-to-digital converter a second determining module for determining a voltage range of the signal to be quantized based on the reference signal; 15. The analog-to-digital converter according to claim 11, wherein the analog-to-digital converter is a digital signal processing circuit.

20. The second judgment module is for comparing the reference signal with the signal to be quantized to obtain a comparison result; The analog-to-digital converter a determining module for determining whether to increase the range value of the quantized segment reference signal based on the comparison result, 20. An analog-to-digital converter according to claim 19.

21. the second judgment module includes a first capacitor, a second capacitor, a comparator, a first judgment switch and a second judgment switch, a first end of the first capacitor is electrically connected to the output end of the quantization waiting signal generation sub-module, a second end of the first capacitor is electrically connected to the first input end of the comparator, a first end of the second capacitor is electrically connected to the output end of the reference signal generation sub-module, and a second end of the second capacitor is electrically connected to the second input end of the comparator; a first terminal of the first decision switch electrically connected to a first input terminal of the comparator, and a second terminal of the first decision switch electrically connected to a first voltage terminal of the comparator; A first terminal of the second decision switch is electrically connected to a first input terminal of the comparator, and a second terminal of the second decision switch is electrically connected to a second voltage terminal of the comparator.

20. An analog-to-digital converter according to claim 19.

22. at least one processor; a memory communicatively coupled to the at least one processor; The memory stores one or more computer programs executable by the at least one processor, and the one or more computer programs, when executed by the at least one processor, cause the at least one processor to perform the quantization method according to any one of claims 1 to 10. An electronic device characterized by:

23. A computer program is stored The computer program, when executed by a processor, implements the quantization method according to any one of claims 1 to 10. A computer-readable storage medium comprising:

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