Circuit board and semiconductor package including same

Abstract

A circuit board according to an embodiment includes a first insulating layer, a second insulating layer disposed on the first insulating layer, a third insulating layer disposed on the second insulating layer, a fourth insulating layer embedded in the third insulating layer, and a fifth insulating layer disposed on the third insulating layer, wherein the first insulating layer, the second insulating layer, the third insulating layer, and the fourth insulating layer are made of different materials, the second insulating layer and the fifth insulating layer are made of the same material, and the vertical thickness between the top surface of the fourth insulating layer and the top surface of the third insulating layer is smaller than the vertical thickness of the second insulating layer.

Description

[Technical Field]

[0001] The embodiments relate to a circuit board, and more particularly to a circuit board with improved mechanical reliability and electrical reliability, and a semiconductor package including the same. [Background technology]

[0002] As the performance of electrical and electronic products continues to improve, technologies for arranging more semiconductor elements on a semiconductor package circuit board with a limited size are being proposed and researched. However, because a typical semiconductor package is designed to mount only one semiconductor element, there is a limit to how much performance can be achieved.

[0003] Recently, semiconductor packages have been developed that use multiple substrates to arrange multiple semiconductor devices. These semiconductor packages have a structure in which multiple semiconductor devices are connected to each other horizontally and / or vertically on a circuit board. This allows for efficient use of the mounting area of ​​the semiconductor devices and allows for high-speed signal transmission via short signal transmission paths between the semiconductor devices.

[0004] Due to these advantages, the above-mentioned semiconductor package is widely used in mobile devices and the like.

[0005] In addition, semiconductor packages applied to products that provide the Internet of Things (IOT), autonomous vehicles, and high-performance servers are becoming more highly integrated, and the number of semiconductor elements and / or the size of each semiconductor element are increasing, or the functional parts of the semiconductor element are being divided, expanding the concept to semiconductor chiplets.

[0006] This makes intercommunication between semiconductor devices and / or semiconductor chiplets important, and thus there is a trend to place an interposer between a semiconductor package circuit board and a semiconductor device.

[0007] The interposer functions as a redistribution layer that gradually increases the width of a circuit pattern from the semiconductor device toward the semiconductor package in order to facilitate intercommunication between semiconductor devices and / or semiconductor chiplets or to interconnect the semiconductor device and a semiconductor package circuit board, thereby facilitating transmission of electrical signals between the semiconductor device and a semiconductor package circuit board having a circuit pattern that is relatively larger than the circuit pattern of the semiconductor device.

[0008] The interposer may have an area equal to or larger than the entire area of ​​the semiconductor devices and / or semiconductor chiplets to mount the semiconductor devices and / or semiconductor chiplets as a whole, or may be disposed only in a portion for interconnecting the semiconductor devices and / or semiconductor chiplets. That is, the area of ​​the interposer may or may not increase as the number of semiconductor devices and / or semiconductor chiplets increases. However, as the number of semiconductor devices and / or semiconductor chiplets increases, the area of ​​the circuit board of the semiconductor package tends to increase. As a result, the larger the area of ​​the semiconductor package, the greater the warpage of the semiconductor package.

[0009] Meanwhile, a package circuit board and / or an interposer applied to a semiconductor package includes a connecting member connected to a semiconductor device and / or a semiconductor chiplet. The connecting member functions to horizontally connect a plurality of semiconductor devices and / or semiconductor chiplets. Accordingly, the connecting member may be embedded in the package circuit board and / or the interposer. In this case, the connecting member may be either an inorganic bridge or an organic bridge.

[0010] The inorganic and / or organic material constituting the connecting member may include an insulating material different from that of the insulating layer provided on the package circuit board and / or interposer. Therefore, the package circuit board and / or interposer and the connecting member may have different thermal expansion coefficients. Therefore, when thermal stress is applied to the semiconductor package, the stress may be concentrated on the connecting member embedded in the package circuit board and / or interposer. This may result in cracks occurring in the semiconductor package in the region where the connecting member is embedded. Summary of the Invention [Problem to be solved by the invention]

[0011] The embodiments provide a circuit board with a new structure and a semiconductor package including the same.

[0012] Furthermore, the embodiments provide a circuit board with improved warpage characteristics and a semiconductor package including the same.

[0013] Furthermore, the embodiments provide a circuit board having improved electrical and mechanical reliability with respect to the connecting members, and a semiconductor package including the same.

[0014] In the proposed embodiments, the technical problems to be solved are not limited to the technical problems mentioned above, and other technical problems not mentioned will be clearly understood by a person having ordinary skill in the technical field to which the proposed embodiments pertain from the following description. [Means for solving the problem]

[0015] A circuit board according to an embodiment includes a first insulating layer, a second insulating layer disposed on the first insulating layer, a third insulating layer disposed on the second insulating layer, a fourth insulating layer embedded in the third insulating layer, and a fifth insulating layer disposed on the third insulating layer, wherein the first insulating layer, the second insulating layer, the third insulating layer, and the fourth insulating layer are made of different materials, the second insulating layer and the fifth insulating layer are made of the same material, and the vertical thickness between the top surface of the fourth insulating layer and the top surface of the third insulating layer is smaller than the vertical thickness of the second insulating layer.

[0016] Furthermore, the vertical thickness between the lower surface of the fourth insulating layer and the lower surface of the third insulating layer is smaller than the vertical thickness of the second insulating layer.

[0017] The second insulating layer includes a first resin layer and a first reinforcing member provided within the first resin layer.

[0018] The fourth insulating layer also includes a second resin layer and a second reinforcing member provided within the second resin layer, and the number of layers or thickness of the first reinforcing member is different from the number of layers or thickness of the second reinforcing member.

[0019] The first and second reinforcing members include glass fibers or reinforcing fibers, which are distinguished from fillers.

[0020] The number of layers of the first reinforcing member is smaller than the number of layers of the second reinforcing member.

[0021] Additionally, the thickness of a single layer of the first reinforcing member is smaller than the thickness of a single layer of the second reinforcing member.

[0022] Additionally, the third insulating layer does not include a reinforcing member.

[0023] The semiconductor package also includes a first electrode portion that penetrates at least a portion of the second insulating layer, a second electrode portion that penetrates at least a portion of the third insulating layer, and a third electrode portion that penetrates the fourth insulating layer.

[0024] The first electrode portion includes a first pad portion and a first through portion, and the first through portion has a slope whose width gradually decreases from the lower surface of the second insulating layer toward the upper surface of the second insulating layer.

[0025] Further, the second electrode portion includes a second pad portion and a second through portion, and the second through portion has a slope such that its width gradually decreases from the lower surface of the third insulating layer toward the lower surface of the fourth insulating layer, and the slope of the first through portion is different from the slope of the second through portion.

[0026] The third electrode portion includes a third pad portion and a third through portion, and the third through portion includes a first slope adjacent to the upper surface of the fourth insulating layer and gradually decreasing in width toward the lower surface of the fourth insulating layer, and a second slope adjacent to the lower surface of the fourth insulating layer and gradually decreasing in width toward the upper surface of the fourth insulating layer.

[0027] Furthermore, the vertical thickness of the first through portion is greater than the vertical thickness of the second through portion and less than the vertical thickness of the third through portion, the vertical thickness of the second through portion is less than the vertical thickness of each of the first and third through portions, and the vertical thickness of the third through portion is greater than the vertical thickness of each of the first and second through portions.

[0028] Furthermore, each of the first through portion and the third through portion has a recess that overlaps horizontally with the reinforcing member, and the second through portion does not have a recess that overlaps horizontally with the reinforcing member.

[0029] Furthermore, the number of recesses or the vertical thickness of a single recess provided in the first through-hole is smaller than the number of recesses or the vertical thickness of a single recess provided in the third through-hole.

[0030] The fourth insulating layer also has a through hole penetrating the upper and lower surfaces of the fourth insulating layer, and includes a first dummy electrode arranged on the upper surface of the fourth insulating layer adjacent to the through hole, and a second dummy electrode arranged on the lower surface of the fourth insulating layer adjacent to the through hole.

[0031] At least one of the side surface of the first dummy electrode and the side surface of the second dummy electrode is disposed on the same plane as the side wall of the through hole in the fourth insulating layer.

[0032] Furthermore, a side surface of the first dummy electrode, a side surface of the second dummy electrode, and a side wall of the through hole in the fourth insulating layer are arranged on the same plane.

[0033] Furthermore, the side surfaces of the first dummy electrode and the second dummy electrode are offset from each other in the vertical direction.

[0034] The through-hole has an upper width and a lower width that are different from each other.

[0035] The semiconductor package also includes a connecting member disposed within the through hole.

[0036] The connecting member is one of a semiconductor active element, a semiconductor passive element, an inorganic bridge, and an organic bridge.

[0037] The upper surface of the first dummy electrode has a step with the upper surface of the terminal of the connecting member.

[0038] Furthermore, the upper surface of the terminal of the connecting member is positioned higher than the upper surface of the first dummy electrode, and the vertical distance of the step is 8 μm or less. [Effects of the Invention]

[0039] A semiconductor package according to an embodiment may include a first insulating layer, a second insulating layer disposed on the first insulating layer, a third insulating layer disposed on the second insulating layer, a fourth insulating layer embedded in the third insulating layer, and a fifth insulating layer disposed on the third insulating layer, wherein the first insulating layer, the second insulating layer, the third insulating layer, and the fourth insulating layer may be made of different materials, the second insulating layer and the fifth insulating layer may be made of the same material, and a vertical thickness between an upper surface of the fourth insulating layer and an upper surface of the third insulating layer may be smaller than a vertical thickness of the second insulating layer. Thus, the embodiment may use the third insulating layer to reduce the thickness of the semiconductor package while preventing the semiconductor package from warping in a specific direction.

[0040] Specifically, the third insulating layer may have a relatively low Young's modulus, thereby suppressing warpage of the semiconductor package. Furthermore, the third insulating layer may absorb impacts applied to the semiconductor package, preventing the semiconductor package from warping significantly in a specific direction. This may solve the problem of reduced operational characteristics due to significant warpage in a specific direction of the semiconductor package, and may also solve the problem of damage to the connecting members disposed within the third insulating layer due to the impact. Furthermore, the third insulating layer may be used to dispose electrodes connected to the connecting members, thereby improving alignment between the electrodes and the connecting members.

[0041] The fourth insulating layer may include a through hole, and the connecting member may be disposed within the through hole. A first dummy electrode may be disposed on an upper surface of the fourth insulating layer, and a second dummy electrode may be disposed on a lower surface of the fourth insulating layer. At least one side surface of the first dummy electrode and the second dummy electrode may be flush with a sidewall of the through hole. The first and second dummy electrodes may be electrodes used to form the through hole using a laser process. In some embodiments, the first and second dummy electrodes may make the upper and lower widths of the through hole substantially identical, thereby reducing the area of ​​a dead region that would otherwise be increased by the difference between the upper and lower widths. This allows the semiconductor package to be thinner.

[0042] In addition, in the embodiment, the shape of the through hole may be changed by positioning the first dummy electrode and the second dummy electrode so as to be offset in the vertical direction, thereby enabling the shape of the through hole to be freely changed according to the shape of the connecting member, thereby improving design freedom.

[0043] In addition, in the embodiment, there may be a step between the upper surface of the terminal of the connecting member and the upper surface of the first dummy electrode, and the step is controlled to be maintained at a certain level or less, thereby improving the degree of connection alignment between the electrode part and the terminal, and further minimizing voids that occur in a process of filling the through hole with an insulating material. [Brief explanation of the drawings]

[0044] [Figure 1a] 1 is a cross-sectional view showing a semiconductor package according to a first embodiment. [Figure 1b] FIG. 10 is a cross-sectional view showing a semiconductor package according to a second embodiment. [Figure 1c] FIG. 10 is a cross-sectional view showing a semiconductor package according to a third embodiment. [Figure 1d] FIG. 10 is a cross-sectional view showing a semiconductor package according to a fourth embodiment. [Figure 1e] FIG. 10 is a cross-sectional view showing a semiconductor package according to a fifth embodiment. [Figure 1f] FIG. 10 is a cross-sectional view showing a semiconductor package according to a sixth embodiment. [Figure 1g] FIG. 13 is a cross-sectional view showing a semiconductor package according to a seventh embodiment. [Figure 2] FIG. 1 is a cross-sectional view showing a circuit board according to a first embodiment. [Figure 3] FIG. 3 is a cross-sectional view showing the first electrode portion of FIG. 2. [Figure 4] FIG. 3 is a cross-sectional view showing the second electrode portion of FIG. 2. [Figure 5] FIG. 3 is a cross-sectional view showing the third electrode portion of FIG. 2. [Figure 6] FIG. 4 is a plan view showing a dummy electrode of the third electrode section in the embodiment. [Figure 7] FIG. 3 is a cross-sectional view showing a dummy electrode and a through hole according to the first embodiment. [Figure 8] FIG. 10 is a cross-sectional view showing a dummy electrode and a through hole according to a second embodiment. [Figure 9] FIG. 10 is a cross-sectional view showing a dummy electrode and a through hole according to a third embodiment. [Figure 10] FIG. 4 is a cross-sectional view showing the positions of the dummy electrodes and the terminals of the connecting member according to the first embodiment. [Figure 11] FIG. 4 is a cross-sectional view showing the positions of the dummy electrodes and the terminals of the connecting member according to the first embodiment. [Figure 12] FIG. 10 is a cross-sectional view showing a circuit board according to a second embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0045] Hereinafter, the embodiments disclosed herein will be described in detail with reference to the accompanying drawings. Regardless of the drawing numbers, identical or similar components will be assigned the same reference numerals, and redundant descriptions thereof will be omitted. The suffixes "module" and "unit" used in the following description are used or mixed together solely for the convenience of drafting the specification, and do not have any distinct meanings or roles. Furthermore, in describing the embodiments disclosed herein, if a detailed description of related publicly known technology is deemed to obscure the gist of the embodiments disclosed herein, such a detailed description will be omitted. Furthermore, the accompanying drawings are merely provided to facilitate understanding of the embodiments disclosed herein, and the technical concept disclosed herein should not be limited by the accompanying drawings. It should be understood that the accompanying drawings include all modifications, equivalents, and alternatives within the concept and technical scope of the present invention.

[0046] Terms including ordinal numbers such as first, second, etc. may be used to describe various components, but the components are not limited by the terms. The terms are used only to distinguish one component from another.

[0047] When a component is referred to as being "coupled" or "connected" to another component, it should be understood that it may be directly coupled or connected to the other component, but that there may be other components in between. Conversely, when a component is referred to as being "directly coupled" or "directly connected" to another component, it should be understood that there are no other components in between.

[0048] The singular expression includes the plural expression unless the context clearly indicates otherwise.

[0049] In this application, the use of terms such as "comprises" or "having" is intended to specify the presence of features, numbers, steps, operations, components, parts, or combinations thereof described herein, and should be understood as not precluding the possible presence or addition of one or more other features, numbers, steps, operations, components, parts, or combinations thereof.

[0050] DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

[0051] -Electronic Devices-

[0052] Before describing the embodiments, an electronic device to which the semiconductor package of the embodiments can be applied will be briefly described. The electronic device includes a main board (not shown). The main board may be physically and / or electrically connected to various components. For example, the main board may be connected to the semiconductor package of the embodiments. Various semiconductor elements may be mounted in the semiconductor package.

[0053] The semiconductor device may include active devices and / or passive devices. The active device may be a semiconductor chip in the form of an integrated circuit (IC) in which hundreds to millions of devices are integrated into a single chip. The semiconductor device may be a logic chip, a memory chip, or the like. The logic chip may be a central processor (CPU), a graphics processor (GPU), or the like. For example, the logic chip may be an application processor (AP) chip including at least one of a central processor (CPU), a graphics processor (GPU), a digital signal processor, a cryptographic processor, a microprocessor, and a microcontroller, or may be an analog-to-digital converter, an application-specific IC (ASIC), or the like, or a chipset including a specific combination of the above.

[0054] The memory chips may be stacked memories such as HBM, and may include volatile memory (e.g., DRAM), non-volatile memory (e.g., ROM), flash memory, and the like.

[0055] Meanwhile, the product group to which the semiconductor package of the embodiment is applied may be any one of CSP (Chip Scale Package), FC-CSP (Flip Chip-Chip Scale Package), FC-BGA (Flip Chip Ball Grid Array), POP (Package On Package), and SIP (System In Package), but is not limited thereto.

[0056] The electronic device may be a smartphone, a personal digital assistant, a digital video camera, a digital still camera, a vehicle, a high-performance server, a network system, a computer, a monitor, a tablet, a laptop, a netbook, a television, a video game, a smart watch, an automobile, etc. However, it is not limited to these, and it may also be any other electronic device that processes data.

[0057] Hereinafter, a semiconductor package including a circuit board according to an embodiment will be described. The semiconductor package according to the embodiment may have various package structures including the circuit board described below.

[0058] In one embodiment, the circuit board may be a first circuit board described below.

[0059] In other embodiments, the circuit board may be a second circuit board, as described below.

[0060] Figure 1a is a cross-sectional view showing a semiconductor package according to a first embodiment, Figure 1b is a cross-sectional view showing a semiconductor package according to a second embodiment, Figure 1c is a cross-sectional view showing a semiconductor package according to a third embodiment, Figure 1d is a cross-sectional view showing a semiconductor package according to a fourth embodiment, Figure 1e is a cross-sectional view showing a semiconductor package according to a fifth embodiment, Figure 1f is a cross-sectional view showing a semiconductor package according to a sixth embodiment, and Figure 1g is a cross-sectional view showing a semiconductor package according to a seventh embodiment.

[0061] Referring to FIG. 1 a, the semiconductor package of the first embodiment may include a first circuit board 1100 , a second circuit board 1200 , and a semiconductor device 1300 .

[0062] The first circuit board 1100 may refer to a package circuit board.

[0063] For example, the first circuit board 1100 may provide a space to which at least one external circuit board is coupled. The external circuit board may refer to a second circuit board 1200 coupled on the first circuit board 1100. The external circuit board may also refer to a main board included in an electronic device coupled to a lower portion of the first circuit board 1100.

[0064] Although not shown in the drawings, the first circuit board 1100 may provide a space in which at least one semiconductor device is mounted.

[0065] The first circuit board 1100 may include at least one insulating layer and an electrode portion disposed on the at least one insulating layer.

[0066] A second circuit board 1200 may be disposed on the first circuit board 1100 .

[0067] The second circuit board 1200 may be an interposer. For example, the second circuit board 1200 may provide a space in which at least one semiconductor device is mounted. The second circuit board 1200 may be connected to the at least one semiconductor device 1300. For example, the second circuit board 1200 may provide a space in which a first semiconductor device 1310 and a second semiconductor device 1320 are mounted. The second circuit board 1200 may electrically connect the first semiconductor device 1310 and the second semiconductor device 1320, and may also electrically connect the first and second semiconductor devices 1310 and 1320 to the first circuit board 1100. That is, the second circuit board 1200 may function as a horizontal connection between a plurality of semiconductor devices and a vertical connection between the semiconductor devices and a package circuit board.

[0068] 1a illustrates two semiconductor elements 1310 and 1320 disposed on the second circuit board 1200, but is not limited thereto. For example, one semiconductor element may be disposed on the second circuit board 1200, or alternatively, three or more semiconductor elements may be disposed on the second circuit board 1200.

[0069] A second circuit board 1200 may be disposed between the at least one semiconductor device 1300 and the first circuit board 1100 .

[0070] In one embodiment, the second circuit board 1200 may be an active interposer that functions as a semiconductor device. When the second circuit board 1200 functions as a semiconductor device, the semiconductor package of the embodiment may have a vertically stacked structure on the first circuit board 1100 and may have the functions of multiple logic chips. Having the functions of a logic chip may mean having the functions of both active and passive devices. Unlike passive devices, active devices do not need to have linear current-voltage characteristics. An active interposer may have the functions of an active device. Furthermore, the active interposer may perform the functions of a logic chip while also transmitting signals between the first circuit board 1100 and a second logic chip disposed thereon.

[0071] According to another embodiment, the second circuit board 1200 may be a passive interposer. For example, the second circuit board 1200 may function as a signal relay between the semiconductor device 1300 and the first circuit board 1100 and may have passive element functions such as a resistor, capacitor, or inductor. For example, the number of terminals on the semiconductor device 1300 is gradually increasing due to factors such as 5G, the Internet of Things (IoT), improved image quality, and increased communication speed. That is, the number of terminals provided on the semiconductor device 1300 is increasing, and as a result, the width of the terminals and the spacing between the terminals are decreasing. In this case, the first circuit board 1100 may be connected to a main board of an electronic device. Therefore, in order for the electrodes provided on the first circuit board 1100 to have the width and spacing required for connection to the semiconductor device 1300 and the main board, respectively, the thickness of the first circuit board 1100 increases or the layer structure of the first circuit board 1100 becomes complex. Therefore, in the first embodiment, a second circuit board 1200 may be disposed between the first circuit board 1100 and the semiconductor device 1300. The second circuit board 1200 may include electrodes having fine widths and intervals corresponding to the terminals of the semiconductor device 1300.

[0072] The semiconductor device 1300 may be a logic chip, a memory chip, or the like. The logic chip may be a central processor (CPU), a graphics processor (GPU), or the like. For example, the logic chip may be an AP including at least one of a central processor (CPU), a graphics processor (GPU), a digital signal processor, a cryptographic processor, a microprocessor, or a microcontroller, or may be an analog-to-digital converter, an application-specific integrated circuit (ASIC), or the like, or a chipset including a specific combination of the above. The memory chip may be a stacked memory such as HBM. The memory chip may also include memory chips such as volatile memory (e.g., DRAM), non-volatile memory (e.g., ROM), and flash memory.

[0073] On the other hand, the semiconductor package of the first embodiment can include a connecting portion.

[0074] For example, the semiconductor package may include a first connection portion 1410 disposed between the first circuit board 1100 and the second circuit board 1200. The first connection portion 1410 may electrically connect the first circuit board 1100 and the second circuit board 1200 while coupling them to each other.

[0075] For example, the semiconductor package may include a second connection part 1420 disposed between the second circuit board 1200 and the semiconductor device 1300. The second connection part 1420 may electrically connect the semiconductor device 1300 to the second circuit board 1200 while coupling the semiconductor device 1300 to the second circuit board 1200.

[0076] The semiconductor package may include a third connection portion 1430 disposed on the lower surface of the first circuit board 1100. The third connection portion 1430 may couple the first circuit board 1100 to a main board and electrically connect them.

[0077] In this case, the first connecting unit 1410, the second connecting unit 1420, and the third connecting unit 1430 may electrically connect the multiple components using at least one bonding method selected from wire bonding, solder bonding, and direct metal-to-metal bonding. That is, since the first connecting unit 1410, the second connecting unit 1420, and the third connecting unit 1430 have the function of electrically connecting the multiple components, when direct metal-to-metal bonding is used, the semiconductor package may be understood as the electrically connected part, rather than the solder or wire.

[0078] The wire bonding method may refer to electrically connecting multiple components using a conductive wire such as gold (Au). The solder bonding method may refer to electrically connecting multiple components using a material including at least one of Sn, Ag, and Cu. The inter-metal direct bonding method may refer to directly bonding multiple components through recrystallization by applying heat and pressure between multiple components without using a material such as solder, wire, or conductive adhesive. The inter-metal direct bonding method may refer to a bonding method using the second connecting part 1420. In this case, the second connecting part 1420 may refer to a metal layer formed between multiple components through the recrystallization.

[0079] Specifically, the first connecting portion 1410, the second connecting portion 1420, and the third connecting portion 1430 may be bonded to each other by a thermal compression bonding method. The thermal compression bonding method may refer to a method of directly bonding the first connecting portion 1410, the second connecting portion 1420, and the third connecting portion 1430 by applying heat and pressure to the first connecting portion 1410, the second connecting portion 1420, and the third connecting portion 1430.

[0080] In this case, in at least one of the first circuit board 1100 and the second circuit board 1200, electrodes on which the first connection portion 1410, the second connection portion 1420, and the third connection portion 1430 are disposed may have protrusions that protrude outward away from the insulating layer of the circuit board. The protrusions may protrude outward from the first circuit board 1100 or the second circuit board 1200.

[0081] The protrusions may be referred to as bumps, posts, or pillars. Preferably, the protrusions may refer to electrodes of the second circuit board 1200 on which second connection parts 1420 for coupling with the semiconductor device 1300 are disposed. That is, as the pitch of the terminals of the semiconductor device 1300 becomes finer, short circuits may occur between the second connection parts 1420, which are respectively connected to the terminals of the semiconductor device 1300 by a conductive adhesive such as solder. Therefore, in this embodiment, thermal compression bonding may be performed to reduce the volume of the second connection parts 1420. As a result, in this embodiment, the electrode of the second circuit board 1200 on which the second connection portion 1420 is disposed may include a protrusion in order to ensure the degree of matching, the diffusion force, and the diffusion prevention force that prevents the intermetallic compound (IMC) formed between the conductive adhesive such as solder and the protrusion from diffusing into the interposer and / or the circuit board.

[0082] Meanwhile, referring to FIG. 1B, the semiconductor package of the second embodiment may differ from the semiconductor package of the first embodiment in that a connecting member 1210 is disposed on the second circuit board 1200. The connecting member may be referred to as a bridge circuit board. For example, the connecting member 1210 may include a redistribution layer. The connecting member 1210 may serve to electrically connect a plurality of semiconductor devices horizontally to each other. Exemplarily, since a semiconductor device generally requires a large area, the connecting member 1210 may include a redistribution layer. Since the semiconductor package and the semiconductor device have a large difference in circuit pattern width, etc., a buffering function for the circuit pattern is required for electrical connection. The buffering function may mean having an intermediate size between the width, etc., of the circuit pattern of the semiconductor package and the width, etc., of the circuit pattern of the semiconductor device, and the redistribution layer may function as a buffer.

[0083] In one embodiment, the connecting member 1210 may be an inorganic bridge. Exemplarily, the inorganic bridge may be a silicon bridge. That is, the connecting member 1210 may include a silicon circuit substrate and a redistribution layer disposed on the silicon circuit substrate.

[0084] In another embodiment, the connecting member 1210 may be an organic bridge. For example, the connecting member 1210 may include an organic material. For example, the connecting member 1210 may include an organic circuit board including an organic material instead of the silicon circuit board.

[0085] The connecting member 1210 may be, but is not limited to, embedded in the second circuit board 1200. For example, the connecting member 1210 may be disposed on the second circuit board 1200 to have a protruding structure.

[0086] In addition, the second circuit board 1200 may include a cavity, and the connecting member 1210 may be disposed within the cavity of the second circuit board 1200 .

[0087] The connecting member 1210 may horizontally connect a plurality of semiconductor devices disposed on the second circuit board 1200 .

[0088] 1c, the semiconductor package of the third embodiment may include a second circuit board 1200 and a semiconductor device 1300. In this case, the semiconductor package of the third embodiment may have a structure in which the first circuit board 1100 is omitted compared to the semiconductor package of the second embodiment.

[0089] That is, the second circuit board 1200 of the third embodiment can function as both an interposer and a package circuit board.

[0090] The first connection part 1410 disposed on the lower surface of the second circuit board 1200 can couple the second circuit board 1200 to a main board of an electronic device.

[0091] Referring to FIG. 1 d, the semiconductor package of the fourth embodiment may include a first circuit board 1100 and a semiconductor device 1300 .

[0092] In this case, the semiconductor package of the fourth embodiment may have a structure in which the second circuit board 1200 is omitted compared to the semiconductor package of the second embodiment.

[0093] That is, the first circuit board 1100 of the fourth embodiment can function as a package circuit board and also as a connection between the semiconductor device 1300 and a main board. To this end, the first circuit board 1100 can include a connecting member 1110 for connecting between the plurality of semiconductor devices. The connecting member 1110 can be an inorganic bridge or an organic bridge for connecting between the plurality of semiconductor devices.

[0094] Referring to FIG. 1e, the semiconductor package of the fifth embodiment further includes a third semiconductor element 1330 compared to the semiconductor package of the fourth embodiment.

[0095] For this purpose, a fourth connection portion 1440 may be disposed on the lower surface of the first circuit board 1100.

[0096] A third semiconductor element 1330 may be disposed in the fourth connection portion 1400. That is, the semiconductor package of the fifth embodiment may have a structure in which semiconductor elements are mounted on both the upper and lower sides.

[0097] In this case, the third semiconductor device 1330 may have a structure in which it is disposed on the lower surface of the second circuit board 1220 in the semiconductor package of FIG. 1c.

[0098] 1f, the semiconductor package of the sixth embodiment may include a first circuit board 1100. A first semiconductor device 1310 may be disposed on the first circuit board 1100. To this end, a first connection part 1410 may be disposed between the first circuit board 1100 and the first semiconductor device 1310.

[0099] The first circuit board 1100 may also include a conductive coupling part 1450. The conductive coupling part 1450 may further protrude from the first circuit board 1100 toward the second semiconductor device 1320. The conductive coupling part 1450 may be referred to as a bump or alternatively as a post. The conductive coupling part 1450 may be disposed to have a protruding structure on an electrode disposed on the top side of the first circuit board 1100.

[0100] A second semiconductor device 1320 may be disposed on the conductive coupling part 1450. In this case, the second semiconductor device 1320 may be connected to the first circuit board 1100 via the conductive coupling part 1450. In addition, a second connection part 1420 may be disposed on the first semiconductor device 1310 and the second semiconductor device 1320.

[0101] Thus, the second semiconductor device 1320 may be electrically connected to the first semiconductor device 1310 through the second connection portion 1420 .

[0102] That is, the second semiconductor device 1320 may be connected to the first circuit board 1100 through the conductive coupling portion 1450 and also connected to the first semiconductor device 1310 through the second connection portion 1420 .

[0103] At this time, the second semiconductor device 1320 may receive a power signal and / or power through the conductive coupling part 1450. In addition, the second semiconductor device 1320 may transmit and receive a communication signal to and from the first semiconductor device 1310 through the second connection part 1420.

[0104] The semiconductor package of the sixth embodiment supplies a power signal and / or power to the second semiconductor element 1320 through the conductive coupling part 1450, thereby providing sufficient power for driving the second semiconductor element 1320 and smoothly controlling the power supply operation.

[0105] As a result, the embodiment may improve the driving characteristics of the second semiconductor device 1320. That is, the embodiment may solve the problem of insufficient power provided to the second semiconductor device 1320. Furthermore, the embodiment may provide at least one of a power signal, power, and a communication signal of the second semiconductor device 1320 via different paths via the conductive coupling part 1450 and the second connection part 1420. As a result, the embodiment may solve the problem of loss of the communication signal due to the power signal. For example, the embodiment may minimize mutual interference between the power signal and the communication signal.

[0106] Meanwhile, in the sixth embodiment, the second semiconductor device 1320 may be disposed on the first circuit board 1100 in a package-on-package (POP) structure in which a plurality of package circuit boards are stacked. For example, the second semiconductor device 1320 may be a memory package including a memory chip. The memory package may be coupled to the conductive coupling part 1450. In this case, the memory package may not be connected to the first semiconductor device 1310.

[0107] Meanwhile, the semiconductor package according to the sixth embodiment may include a molding member 1460. The molding member 1460 may be disposed between the first circuit board 1100 and the second semiconductor element 1320. For example, the molding member 1460 may mold the first connecting portion 1410, the second connecting portion 1420, the first semiconductor element 1310, and the conductive coupling portion 1450.

[0108] Referring to FIG. 1g, the semiconductor package of the seventh embodiment may include a first circuit board 1100, a first connecting portion 1410, a semiconductor element 1300, and a third connecting portion 1430.

[0109] The semiconductor package of the seventh embodiment may differ from the semiconductor package of the fourth embodiment in that the connecting member 1110 is omitted and the first circuit board 1100 includes a plurality of board layers.

[0110] The first circuit board 1100 may include multiple substrate layers, such as a first circuit board layer 1100A corresponding to a package substrate and a second circuit board layer 1100B corresponding to a connecting member.

[0111] In other words, the semiconductor package of the seventh embodiment may include a first circuit board layer 1100A and a second circuit board layer 1100B in which the first circuit board 1100 (package substrate) and the second circuit board 1200 (interposer) disclosed in FIG. 1A are integrally formed. The material of the insulating layer of the second circuit board layer 1100B may be different from the material of the insulating layer of the first circuit board layer 1100A. For example, the material of the insulating layer of the second circuit board layer 1100B may include a photo-curable material. For example, the second circuit board layer 1100B may be a photo-imageable dielectric (PID). Furthermore, the second circuit board layer 1100B may include a photo-curable material, thereby enabling fine electrodes. Therefore, in the seventh embodiment, the second circuit board layer 1100B may be formed by sequentially stacking insulating layers of a photo-curable material on the first circuit board layer 1100A and forming fine electrodes on the insulating layers of the photo-curable material. Thus, the second circuit board layer 1100B may have a function of a redistribution layer including miniaturized electrodes and a function of horizontally connecting a plurality of semiconductor elements 1310 and 1320.

[0112] Prior to describing the circuit board of the embodiments, the circuit board described below may refer to any one of the circuit boards included in the semiconductor package. For example, the circuit board described below may refer to any one of the first circuit board 1100 and the second circuit board 1200 included in the semiconductor packages of the first to seventh embodiments.

[0113] 2 is a cross-sectional view showing a circuit board according to the first embodiment, FIG. 3 is a cross-sectional view showing a first electrode portion of FIG. 2, FIG. 4 is a cross-sectional view showing a second electrode portion of FIG. 2, FIG. 5 is a cross-sectional view showing a third electrode portion of FIG. 2, FIG. 6 is a plan view showing a dummy electrode of the third electrode portion according to the embodiment, FIG. 7 is a cross-sectional view showing a dummy electrode and a through hole according to the first embodiment, FIG. 8 is a cross-sectional view showing a dummy electrode and a through hole according to the second embodiment, FIG. 9 is a cross-sectional view showing a dummy electrode and a through hole according to the third embodiment, FIG. 10 is a cross-sectional view showing the positions of the dummy electrode and the terminal of the connecting member according to the first embodiment, FIG. 11 is a cross-sectional view showing the positions of the dummy electrode and the terminal of the connecting member according to the second embodiment, and FIG. 12 is a cross-sectional view showing a circuit board according to the second embodiment.

[0114] The semiconductor package according to the embodiment will be specifically described below with reference to FIGS.

[0115] Referring to FIG. 2, a semiconductor package may include a circuit board and a connecting member 200 embedded in the circuit board.

[0116] In one embodiment, the connecting member 200 may perform a function of horizontally connecting a plurality of semiconductor elements arranged on the circuit board. For example, the connecting member 200 may include a high-density electrode pattern to connect the plurality of semiconductor elements. For this purpose, in one embodiment, the connecting member 200 may be an inorganic bridge. The inorganic bridge may include a silicon bridge. In another embodiment, the connecting member 200 may be an organic bridge. The organic bridge may include at least one organic insulating layer and an electrode pattern arranged on the organic insulating layer.

[0117] In another embodiment, the connecting member 200 may refer to a semiconductor device. For example, in another embodiment, the connecting member 200 may refer to a semiconductor device embedded in the circuit board. The connecting member 200 may include active and / or passive devices. The active device may refer to a semiconductor device in the form of an integrated circuit (IC) in which hundreds to millions of devices are integrated into a single chip. For example, the semiconductor device may be an application processor (AP) device including at least one of a central processor (CPU), a graphics processor (GPU), a digital signal processor, a cryptographic processor, a microprocessor, or a microcontroller, or may be an analog-to-digital converter, an application-specific IC (ASIC), or a chipset including a specific combination of the above. The connecting member 200 may also be an integrated passive device (IPD). The connecting member 200 may also be a multilayer ceramic capacitor (MLCC) or a silicon-based capacitor.

[0118] The connecting member 200 may be embedded in a circuit board and electrically connected to an electrode portion included in the circuit board. For example, the connecting member 200 may include a terminal, which may be electrically connected to an electrode portion of the circuit board. The terminal may refer to an electrode pattern provided on an organic bridge and / or an inorganic bridge, or may refer to an electrode pattern provided on a semiconductor device.

[0119] The circuit board may provide a space for receiving and embedding the connecting member 200. The circuit board may provide a space in which at least one semiconductor element is mounted.

[0120] The circuit board may include an insulating layer and an electrode portion. The insulating layer may be provided in multiple layers. The electrode portion may be provided in each of the multiple insulating layers. For example, the electrode portion may be provided so as to penetrate at least a partial region of the multiple insulating layers.

[0121] The insulating layer may include a first insulating layer 111.

[0122] The first insulating layer 111 may refer to the insulating layer disposed at the bottom of the insulating layers provided on the circuit board. The first insulating layer 111 may serve to protect the circuit board. Therefore, the first insulating layer 111 may be referred to as a resist layer or a protective layer.

[0123] The first insulating layer 111 may be a solder resist layer including an organic polymer material. For example, the first insulating layer 111 may include an epoxy acrylate resin. In particular, the first insulating layer 111 may include a resin, a hardener, a photoinitiator, a pigment, a solvent, a filler, an additive, an acrylic monomer, etc. However, embodiments are not limited thereto, and the first insulating layer 111 may be any one of a photo solder resist layer, a coverlay, and a polymer material.

[0124] For example, when a semiconductor element and / or an external circuit board is bonded to the electrode portion of the embodiment using a conductive adhesive material such as solder, the solder and the first insulating layer 111 do not have good wettability with each other, which can solve the problem of electrical reliability caused by contact between adjacent solders.

[0125] The first insulating layer 111 may not include a reinforcing member. The reinforcing member may be a reinforced fiber or a glass fiber.

[0126] The reinforcing member may be distinguished from the filler. For example, the reinforcing member may refer to a glass fiber material extending horizontally within the insulating layer, and may have a different meaning from inorganic fillers spaced apart from the reinforcing member. That is, the reinforcing member may have a different length or width from the filler in the horizontal direction. Exemplarily, the glass fiber may extend to have a width equal to or greater than the width of the insulating layer. Here, having a width equal to or greater than the width of the insulating layer may mean that the glass fiber may be arranged in a horizontally bent shape. The filler may be distinguished from the reinforcing member and may, for example, refer to an inorganic filler.

[0127] The first insulating layer 111 may have a vertical thickness in the range of 6 μm to 20 μm. Preferably, the first insulating layer 111 may have a vertical thickness of 8 μm to 18 μm. The first insulating layer 111 may have a vertical thickness of 10 μm to 16 μm. The vertical thickness of the first insulating layer 111 may refer to the vertical distance from the lower surface of the electrode unit closest to the first insulating layer 111 to the lower surface of the first insulating layer 111. For example, the vertical thickness of the first insulating layer 111 may refer to the vertical distance from the lower surface of the first electrode unit 120 in contact with the first insulating layer 111 to the lower surface of the first insulating layer 111.

[0128] If the vertical thickness of the first insulating layer 111 exceeds 20 μm, the thickness of the semiconductor package increases, making it difficult to make it thinner, or stress applied to the second insulating layer 112, the third insulating layer 113, and the fourth insulating layer 114 may increase. Also, if the thickness of the first insulating layer 111 is less than 6 μm, it may be difficult to stably protect the circuit board and / or the electrode part, which may result in reduced electrical or physical reliability.

[0129] The circuit board may include a second insulating layer 112 disposed on the first insulating layer 111 .

[0130] The second insulating layer 112 may include an insulating material different from that of the first insulating layer 111. The second insulating layer 112 may have rigidity. For example, the second insulating layer 112 may include a reinforcing member. The second insulating layer 112 may include reinforced fiber and / or glass fiber. Exemplarily, the second insulating layer 112 may be, but is not limited to, a prepreg including a reinforcing member.

[0131] The second insulating layer 112 may be formed as at least one layer on the first insulating layer 111. When the second insulating layer 112 is formed as a plurality of layers, the interfaces between the plurality of layers of the second insulating layer 112 may not be distinct. In this case, the interfaces between the plurality of layers of the second insulating layer 112 may be defined by a first electrode portion 120 penetrating the second insulating layer 112. For example, the first electrode portion 120 may include a pad portion 121 and a through portion 122. The pad portion 121 and the through portion 122 may have different horizontal widths and / or different vertical slopes. When the second insulating layer 112 is formed as a plurality of layers made of the same insulating material, the interfaces between the layers may be defined based on the difference in width or slope between the pad portion 121 and the through portion 122 of the first electrode portion 120.

[0132] The vertical thickness of the single layer of the second insulating layer 112 may be in the range of 15 μm to 35 μm. The vertical thickness of the single layer of the second insulating layer 112 may be in the range of 17 μm to 33 μm. The vertical thickness of the single layer of the second insulating layer 112 may be in the range of 20 μm to 30 μm. If the vertical thickness of the single layer of the second insulating layer 112 is less than 15 μm, the reinforcing fibers of the second insulating layer 112 may be exposed from the second insulating layer 112, and the exposed reinforcing fibers may come into contact with the electrodes, resulting in problems with electrical reliability. If the vertical thickness of the single layer of the second insulating layer 112 is less than 15 μm, the rigidity of the semiconductor package may be reduced, resulting in problems with the semiconductor package being significantly warped in a specific direction. If the vertical thickness of the single layer of the second insulating layer 112 is more than 35 μm, the thickness of the semiconductor package may increase, making it difficult to thin the package, or increasing stress applied to adjacent insulating layers.

[0133] Preferably, the vertical thickness of the single layer of the second insulating layer 112 may be greater than the vertical thickness of the first insulating layer 111. Thus, the second insulating layer 112 can prevent stress from being applied to the underside of the first insulating layer 111, thereby improving the overall mechanical reliability of the semiconductor package.

[0134] 2, the second insulating layer 112 is shown to be formed of two layers, but is not limited thereto. The second insulating layer 112 may be formed of one layer or three or more layers.

[0135] The circuit board may include a third insulating layer 113 disposed on the second insulating layer 112. The third insulating layer 113 may include a different insulating material than the first insulating layer 111 and the second insulating layer 112.

[0136] The third insulating layer 113 may not include a reinforcing member. For example, the third insulating layer 113 may not include glass fiber and / or reinforcing fiber. The third insulating layer 113 may include an organic material without a reinforcing member, which allows slimming of the circuit board, excellent processability, and miniaturization of the electrode portion. Exemplarily, the third insulating layer 113 may be Ajinomoto Build-up Film (ABF), a product sold by Ajinomoto Co., Inc. However, embodiments are not limited thereto, and the third insulating layer 113 may include resin coated copper (RCC) or photo-imagable dielectric resin (PID) without a reinforcing member.

[0137] The third insulating layer 113 can prevent the semiconductor package from warping significantly in a specific direction. For example, the Young's modulus of the third insulating layer 113 can be smaller than that of the second insulating layer 112, thereby preventing the semiconductor package from warping. The Young's modulus of the second insulating layer 112 can be 32 GPa / RT, and the Young's modulus of the third insulating layer 113 can be 5.0 GPa / RT.

[0138] The third insulating layer 113 may be provided in a plurality of layers. For example, the third insulating layer 113 may be provided in a plurality of layers sandwiching a fourth insulating layer 114. In this case, the fourth insulating layer 114 is provided between the plurality of layers of the third insulating layer 113, and therefore, the interfaces between the plurality of layers of the third insulating layer 113 may be separated by the fourth insulating layer 114.

[0139] The third insulating layer 113 may include a first region arranged below the fourth insulating layer 114, a second region arranged above the fourth insulating layer 114, and a third region arranged within the through hole TH of the fourth insulating layer 114.

[0140] The vertical thickness of each of the first and second regions of the third insulating layer 113 may be smaller than the vertical thickness of a single layer of the second insulating layer 112 and larger than the vertical thickness of the first insulating layer 111. For example, the vertical thickness from the top surface of the third insulating layer 113 to the top surface of the fourth insulating layer 114 may be smaller than the vertical thickness of a single layer of the second insulating layer 112. For example, the vertical thickness from the bottom surface of the third insulating layer 113 to the bottom surface of the fourth insulating layer 114 may be smaller than the vertical thickness of a single layer of the second insulating layer 112. That is, in embodiments, the thickness of the third insulating layer 113 may be controlled within the range described below, thereby achieving optimal reliability of the semiconductor package.

[0141] For example, the vertical thickness of the third insulating layer 113 can be in the range of 10 μm to 30 μm. Preferably, the vertical thickness of the third insulating layer 113 can be in the range of 12 μm to 28 μm. More preferably, the vertical thickness of the third insulating layer 113 can be in the range of 15 μm to 25 μm.

[0142] If the vertical thickness of the third insulating layer 113 is less than 10 μm, the warpage prevention effect of the semiconductor package provided by the third insulating layer 113 may be insufficient. For example, the third insulating layer 113 may be provided between the fourth insulating layer 114 and the second insulating layer 112 and may function to absorb impacts applied to the semiconductor package and prevent the semiconductor package from warping significantly in a specific direction. The third insulating layer 113 may also be provided to cover the connecting member 200, thereby preventing the connecting member 200 from being subjected to impacts. If the vertical thickness of the third insulating layer 113 is less than 10 μm, the impact absorption effect may be insufficient, which may result in a deterioration in operational characteristics due to a significant warpage of the semiconductor package in a specific direction or may result in cracks occurring in the connecting member 200. If the vertical thickness of the third insulating layer 113 is more than 30 μm, the thickness of the semiconductor package may increase, making it difficult to thin the semiconductor package, or increasing stress applied to other insulating layers adjacent to the third insulating layer 113.

[0143] The circuit board may include a fourth insulating layer 114 embedded in the third insulating layer 113. For example, the third insulating layer 113 may be provided on the top and bottom of the fourth insulating layer 114, respectively, so that the fourth insulating layer 114 may have a structure embedded in the third insulating layer 113.

[0144] The fourth insulating layer 114 may include an insulating material different from that of the first insulating layer 111, the second insulating layer 112, and the third insulating layer 113. Here, including a different insulating material may mean that the type of insulating material provided therein is different, or the insulating material has different widths and / or thicknesses.

[0145] The fourth insulating layer 114 may include a reinforcing member. For example, the fourth insulating layer 114 may include a reinforcing fiber or a glass fiber. In this case, the reinforcing member of the fourth insulating layer 114 may be the same type of reinforcing fiber or glass fiber as the reinforcing member of the second insulating layer 112.

[0146] However, the number of layers and / or thickness of the reinforcing members provided in the fourth insulating layer 114 may be different from the number of layers and / or thickness of the reinforcing members provided in the second insulating layer 112.

[0147] Preferably, the number of reinforcing member layers provided on the fourth insulating layer 114 may be greater than the number of reinforcing member layers provided on the second insulating layer 112. For example, the reinforcing member provided on the second insulating layer 112 may have a stacked structure of one or two layers. The reinforcing member provided on the fourth insulating layer 114 may have a stacked structure of three to five layers. The vertical thickness of the reinforcing member provided on the fourth insulating layer 114 may be greater than the vertical thickness of the reinforcing member provided on the second insulating layer 112. This is because the fourth insulating layer 114 is an insulating layer disposed at the center of the stacked structure of multiple insulating layers of the semiconductor package, and thus can function as the skeleton of the semiconductor package. The fourth insulating layer 114 must have a certain level of rigidity to increase the overall rigidity of the semiconductor package. As a result, processes for laminating insulating layers and forming electrodes above and below the fourth insulating layer 114 can be stably performed during the manufacturing process of the semiconductor package.

[0148] The fourth insulating layer 114 may be greater than the vertical thickness of a single layer of each of the first insulating layer 111, the second insulating layer 112, and the third insulating layer 113.

[0149] For example, the vertical thickness of the fourth insulating layer 114 may be in the range of 50 μm to 110 μm. Preferably, the vertical thickness of the fourth insulating layer 114 may be in the range of 60 μm to 100 μm. More preferably, the vertical thickness of the fourth insulating layer 114 may be in the range of 70 μm to 90 μm. If the vertical thickness of the fourth insulating layer 114 is less than 50 μm, the fourth insulating layer 114 may not be able to adequately function as a skeleton, which may reduce the rigidity of the semiconductor package and cause problems in the manufacturing process. For example, if the fourth insulating layer 114 does not adequately function as a skeleton, the semiconductor package may warp, which may cause problems such as electrodes on the upper and lower parts of the fourth insulating layer 114 not being formed at the correct positions. Furthermore, if the vertical thickness of the fourth insulating layer 114 exceeds 110 μm, the thickness of the semiconductor package increases, making it difficult to make it thinner.

[0150] Meanwhile, the fourth insulating layer 114 may include a through hole TH. The through hole TH can be regarded as a receiving portion in which the connecting member 200 is received. The horizontal width of the through hole TH may be greater than the horizontal width of the connecting member 200. For example, an inner wall of the through hole TH of the fourth insulating layer 114 may be spaced apart from a side surface of the connecting member 200 by a predetermined distance. Thus, the fourth insulating layer 114 may not be in contact with the connecting member 200. The connecting member 200 may be disposed in the through hole TH of the fourth insulating layer 114, and the third insulating layer 113 may be provided surrounding the connecting member 200.

[0151] The circuit board may include a fifth insulating layer 115 disposed on the third insulating layer 113. The fifth insulating layer 115 may include the same insulating material as the second insulating layer 112. For example, the second insulating layer 112 and the fifth insulating layer 115 may be layers including the same insulating material and may be disposed above and below the third insulating layer 113, respectively. Features of the fifth insulating layer 115 may correspond to the features of the second insulating layer 112, and therefore detailed description thereof will be omitted.

[0152] The circuit board may include a sixth insulating layer 116 disposed on a fifth insulating layer 115. The sixth insulating layer 116 may include the same insulating material as the first insulating layer 111. Characteristics of the sixth insulating layer 116 may correspond to the characteristics of the first insulating layer 111, and therefore, detailed description thereof will be omitted.

[0153] As described above, the insulating layer of the circuit board of the embodiment may be formed of multiple layers containing different insulating materials. That is, the fourth insulating layer 114 may be formed in the center of the circuit board, the third insulating layer 113, the second insulating layer 112, and the first insulating layer 111 may be sequentially disposed below the fourth insulating layer 114, and the third insulating layer 113, the fifth insulating layer 113, and the sixth insulating layer 116 may be sequentially disposed above the fourth insulating layer 114. That is, the circuit board may be formed symmetrically above and below the fourth insulating layer 114 with the same insulating material. Based on this, the embodiment may prevent the circuit board from warping due to the stacked structure of insulating layers having the vertically symmetrical structure.

[0154] Meanwhile, the circuit board includes electrode portions that may be provided penetrating at least a portion of each of the second insulating layer 112, the third insulating layer 113, the fourth insulating layer 114, and the fifth insulating layer 115.

[0155] For example, the electrode portion may include a first electrode portion 120 that penetrates at least a portion of the second insulating layer 112, a second electrode portion 130 that penetrates at least a portion of the third insulating layer 113, a third electrode portion 140 that penetrates at least a portion of the fourth insulating layer 114, and a fourth electrode portion 160 that penetrates at least a portion of the fifth insulating layer 115.

[0156] Each of the first electrode unit 120, the second electrode unit 130, the third electrode unit 140, and the fourth electrode unit 160 may include a pad unit and a through-hole. The pad unit may refer to an electrode that transmits a signal horizontally in each insulating layer or is connected to the through-hole. The through-hole may penetrate at least a portion of each insulating layer and vertically connect multiple pad units arranged on different layers. The through-hole may be referred to as a via electrode.

[0157] Specifically, referring to FIG. 3, the first electrode portion 120 may include a first pad portion 121 and a first through portion 122 .

[0158] The first pad portion 121 of the first electrode portion 120 may be provided on a lower surface of the second insulating layer 112. At least a portion of the lower surface of the first pad portion 121 of the first electrode portion 120 may be covered by the first insulating layer 111. The first insulating layer 111 may have at least one opening, and at least a portion of the first pad portion 121 of the first insulating layer 111 may vertically overlap the opening.

[0159] The first electrode portion 120 may include a first through portion 122 that penetrates at least a portion of the second insulating layer 112 and is connected to the first pad portion 121 .

[0160] The first through-hole 122 of the first electrode unit 120 may have a slope. For example, the first through-hole 122 of the first electrode unit 120 may have a slope such that its width gradually decreases from the lower surface of the second insulating layer 112 toward the upper surface of the second insulating layer 112. For example, an interior angle between the side surface of the first through-hole 122 and the lower surface of the first through-hole 122 may be an acute angle. A vertical cross section of the first through-hole 122 of the first electrode unit 120 may have a trapezoidal shape. The upper surface of the first through-hole 122 of the first electrode unit 120 may have a smaller horizontal width than the lower surface of the first through-hole 122.

[0161] An outer wall 112S of the first through portion 122 of the first electrode portion 120 may include an uneven portion. Preferably, the outer wall 112S of the first through portion 122 of the first electrode portion 120 may be in contact with the second insulating layer 112. The second insulating layer 112 may include a resin layer 112a and reinforcing fibers 112b.

[0162] The outer wall 112S of the first through portion 122 may include a portion in contact with the resin layer 112a and a portion in contact with the reinforcing fibers 112b. The portion of the first through portion 122 in contact with the reinforcing fibers 112b may have at least a portion of the reinforcing fibers 112b embedded therein.

[0163] Therefore, the outer wall 112S of the first through portion 122 may include a recess 122CP in which the reinforcing fibers 112b of the second insulating layer 112 are arranged while horizontally overlapping the reinforcing fibers 112b of the second insulating layer 112. The recess 122CP formed in the outer wall 112S of the first through portion 122 may refer to the portion of the second insulating layer 112 where the reinforcing fibers 112b are arranged.

[0164] The vertical length of the recess 122CP formed in the outer wall 112S of the first through portion 122 may correspond to the thickness of the reinforcing fibers 112b formed in the second insulating layer 112. The outer wall 112S of the first through portion 122 may have a plurality of recesses spaced apart in the vertical direction. The number of the recesses 122CP may correspond to the number of layers of the reinforcing fibers 112b formed in the second insulating layer 112. For example, the second insulating layer 112 may have one or two layers of reinforcing fibers 112b, and the outer wall 112S of the first through portion 122 of the first electrode unit 120 may have one or two recesses 122CP. The slope of the outer wall 112S of the first through portion 122 may vary in the portion corresponding to the recess 122CP. Although not shown in the drawings, the second insulating layer 112 may include a filler in addition to the reinforcing fibers 112b. Therefore, the outer wall 112S of the first through-hole 122 of the first electrode portion 120 may further include recesses and / or protrusions corresponding to the filler, in addition to recesses 122CP corresponding to the reinforcing fibers 112b.

[0165] Meanwhile, referring to FIG. 4, the second electrode part 130 may include a second pad part 131 and a second through part 132 .

[0166] The second pad portion 131 of the second electrode portion 130 may be provided on a lower surface of the third insulating layer 113. At least a portion of the lower surface of the second pad portion 131 of the second electrode portion 130 may be covered with the second insulating layer 112.

[0167] The second electrode portion 130 may include a second through-portion 123 that penetrates at least a portion of the third insulating layer 113 and is connected to the second pad portion 122 .

[0168] The second through-hole 132 of the second electrode unit 130 may have a slope. For example, the second through-hole 132 of the second electrode unit 130 may have a slope such that its width gradually decreases from the lower surface of the third insulating layer 113 toward the upper surface of the third insulating layer 113. For example, an interior angle between the side surface of the second through-hole 132 and the lower surface of the second through-hole 132 may be an acute angle. A vertical cross section of the second through-hole 132 of the second electrode unit 130 may have a trapezoidal shape. The upper surface of the second through-hole 132 of the second electrode unit 130 may have a smaller horizontal width than the lower surface of the second through-hole 132.

[0169] The second through-hole 132 of the second electrode portion 130 may be inclined in the same direction as the first through-hole 122 of the first electrode portion 120 .

[0170] However, the inclination of the second through portion 132 of the second electrode portion 130 may be different from the inclination of the first through portion 122 of the first electrode portion 120 .

[0171] Specifically, the second through portion 132 of the second electrode portion 130 may be provided in the third insulating layer 113, which does not include the reinforcing fiber. Thus, when a through hole is formed through the third insulating layer 113, there may be little difference between the upper surface width and the lower surface width of the through hole.

[0172] Therefore, the inclination of the second through-hole 132 of the second electrode unit 130 may be greater than the inclination of the first through-hole 122 of the first electrode unit 120. For example, the inclination of the side of the second through-hole 132 with respect to the lower surface of the second through-hole 132 of the second electrode unit 130 may be greater than the inclination of the side of the first insulating layer 111 with respect to the lower surface of the first through-hole 122 of the first electrode unit 120. Also, the horizontal width of the second through-hole 132 of the second electrode unit 130 may be smaller than the horizontal width of the first through-hole 122 of the first electrode unit 120. In this case, the second electrode unit 130 may include an electrode connected to the connecting member 200 embedded in the fourth insulating layer 114. The connecting member 200 may include a fine terminal. Therefore, in an embodiment, an electrode connected to the terminal of the connecting member 200 may be provided in the third insulating layer 113. As a result, the embodiment allows the second electrode unit 130 connected to the connecting member 200 to be miniaturized and accurately positioned in a region corresponding to the terminal of the connecting member 200. Furthermore, the embodiment allows the signal transmitted from the connecting member 200 to be smoothly transmitted through the second electrode unit 130, thereby minimizing signal transmission loss and thereby improving electrical characteristics.

[0173] Meanwhile, the second through-hole 132 of the second electrode unit 130 may not have a recess corresponding to the first through-hole 122 of the first electrode unit 120. For example, the second through-hole 132 of the second electrode unit 130 may not overlap with reinforcing fibers overlapping in the horizontal direction. However, the third insulating layer 113 may include a filler, and the outer surface of the second through-hole 132 may include a recess and / or a protrusion that contacts the filler.

[0174] 5, the fourth insulating layer 114 may include a third electrode portion 140. The third electrode portion 140 may include a third pad portion 141 and a third through portion 142.

[0175] The third pad portion 141 of the third electrode portion 140 may be provided on the upper and lower surfaces of the fourth insulating layer 114. The third through portion 142 of the third electrode portion 140 may be connected to the third pad portion 141 of the third insulating layer 113 and may penetrate the fourth insulating layer 114.

[0176] The third through-hole 142 of the third electrode portion 140 may include a plurality of slopes.

[0177] The third through-hole portion 142 of the third electrode unit 140 may be adjacent to the upper surface of the fourth insulating layer 114 and may include a first slope 142S1 whose width gradually decreases toward the lower surface of the fourth insulating layer 114. The third through-hole portion 142 of the third electrode unit 140 may be adjacent to the lower surface of the fourth insulating layer 114 and may include a second slope 142S2 whose width gradually decreases toward the upper surface of the fourth insulating layer 114. The first slope 142S1 and the second slope 142S2 may be different from each other. For example, the first slope portion 142S1 and the second slope portion 142S2 may be inclined in different directions from each other.

[0178] In the embodiment, the third through-hole 142 of the third electrode unit 140 may include a plurality of slopes. Thus, in the embodiment, the third through-hole 142 of the third electrode unit 140 may have a relatively large thickness and easily penetrate the fourth insulating layer 114 having a relatively large amount of reinforcing fibers. Thus, in the embodiment, the third through-hole 142 of the third electrode unit 140 may solve the problem of the third through-hole 142 not penetrating the fourth insulating layer 114, thereby improving electrical reliability.

[0179] Meanwhile, the fourth insulating layer 114 may include a resin layer 114a and reinforcing fibers 114b. The third through-hole 142 of the third electrode portion 140 may include a recess 142CP that horizontally overlaps with the reinforcing fibers 114b of the fourth insulating layer 114.

[0180] In this case, the recess 122CP formed in the first through-hole 122 of the first electrode portion 120 may be different from the recess 142CP formed in the third through-hole 142 of the third electrode portion 140.

[0181] For example, the vertical length and / or number of the recesses 142CP provided in the third through-hole 142 of the third electrode portion 140 may be different from the vertical length and / or number of the recesses 142CP provided in the first through-hole 122 of the first electrode portion 120.

[0182] Specifically, the vertical length in the vertical direction of the recesses 142CP provided in the third through portion 142 of the third electrode portion 140 may be larger than the vertical length in the vertical direction of the recesses 122CP provided in the first through portion 122 of the first electrode portion 120. Furthermore, the number of recesses 142CP provided in the third through portion 142 of the third electrode portion 140 may be larger than the number of recesses 122CP provided in the first through portion 122 of the first electrode portion 120.

[0183] Meanwhile, the fourth electrode unit 160 may include a fourth pad unit 161 and a fourth through-hole 162. The fourth pad unit 161 and the fourth through-hole 162 of the fourth electrode unit 160 may have a structure corresponding to the first pad unit 121 and the second through-hole 122 of the first electrode unit 120. For example, the fourth pad unit 161 and the fourth through-hole 162 of the fourth electrode unit 160 may have a symmetrical structure to the first pad unit 121 and the second through-hole 122 of the first electrode unit 120.

[0184] The circuit board may also include a protruding electrode portion 170. The protruding electrode portion 170 may include a protruding portion 171 protruding onto the sixth insulating layer 116 and a penetrating portion 172 penetrating at least a portion of the sixth insulating layer 116.

[0185] The protruding electrode portion 170 may be a post bump that is connected to a semiconductor device.

[0186] That is, as the width and pitch of the terminals of semiconductor devices coupled to a circuit board become finer, when the semiconductor devices are mounted using a conductive adhesive such as solder, the conductive adhesive may diffuse, resulting in multiple pieces of conductive adhesive being connected to each other. To address this issue, in some embodiments, thermal compression bonding may be performed to reduce the volume of the conductive adhesive. However, if the protruding electrode portion 170 is not provided on the circuit board, it may be difficult to reduce the volume of the conductive adhesive. This may be because the height of the electrodes on which the conductive adhesive is disposed is lower than the top surface of the sixth insulating layer 116, and therefore the volume of the conductive adhesive increases by the difference between the height of the electrodes and the height of the insulating layer.

[0187] Therefore, the embodiment may include a protruding electrode portion 170 having a protruding structure to ensure a degree of alignment with the terminal of the semiconductor element and a diffusion prevention force to prevent the intermetallic compound (IMC) formed between the conductive adhesive and the electrode portion from diffusing into the circuit board.

[0188] Meanwhile, the circuit board may include a dummy electrode 150. The dummy electrode 150 may include a first dummy electrode 151 provided on an upper surface of the fourth insulating layer 114 and a second dummy electrode 152 provided on a lower surface of the fourth insulating layer 114.

[0189] 6, the dummy electrode 150 may be provided to surround the periphery of a through hole TH formed in the fourth insulating layer 114. For example, a first dummy electrode 151 of the dummy electrode 150 may be provided to surround the periphery of an upper region of the through hole TH, and a second dummy electrode 152 of the dummy electrode 150 may be provided to surround the periphery of a lower region of the through hole TH.

[0190] Each of the first dummy electrode 151 and the second dummy electrode 152 of the dummy electrode 150 may have a ring shape. Each of the first dummy electrode 151 and the second dummy electrode 152 of the dummy electrode 150 may have a closed loop shape. Each of the first dummy electrode 151 and the second dummy electrode 152 of the dummy electrode 150 may have a shape corresponding to the planar shape of the through hole TH.

[0191] The dummy electrode 150 may have a first width W1. The first width W1 of the dummy electrode 150 may be in the range of 80 μm to 120 μm. Preferably, the first width W1 of the dummy electrode 150 may be in the range of 85 μm to 115 μm. More preferably, the first width W1 of the dummy electrode 150 may be in the range of 90 μm to 110 μm. If the first width W1 of the dummy electrode 150 is less than 80 μm, a portion of the fourth insulating layer 114 may be damaged during the process of forming the through hole TH. In addition, to prevent damage to the portion of the fourth insulating layer 114, the position of the laser must be adjusted during the process of forming the through hole TH, and as a result, the inner wall of the through hole TH may have an inclination that is significantly different from 90 degrees. In addition, if the first width W1 of the dummy electrode 150 exceeds 120 μm, the dummy area in the fourth insulating layer 114 increases, which may make it difficult to thin the semiconductor package.

[0192] On the other hand, the width of the through hole TH may be larger than the width of the connecting member 200. Preferably, the area of ​​the through hole TH may be larger than the area of ​​the connecting member 200.

[0193] For example, the horizontal distance W2 between the side wall of the through hole TH and the side surface of the connecting member 200 can be in the range of 75 μm to 120 μm. Preferably, the horizontal distance W2 between the side wall of the through hole TH and the side surface of the connecting member 200 can be in the range of 75 μm to 120 μm. More preferably, the horizontal distance W2 between the side wall of the through hole TH and the side surface of the connecting member 200 can be in the range of 75 μm to 120 μm.

[0194] If the horizontal distance W2 between the sidewall of the through hole TH and the side surface of the connecting member 200 is less than 75 μm, a process error in the process of embedding the connecting member 200 may cause the connecting member 200 to come into contact with the sidewall of the through hole TH, which may result in damage to the connecting member 200. Also, if the horizontal distance W2 between the sidewall of the through hole TH and the side surface of the connecting member 200 exceeds 120 μm, a dummy area increases by the horizontal distance, which may make it difficult to thin the semiconductor package.

[0195] 7, the sidewall 114S of the through hole TH may be perpendicular to the upper or lower surface of the fourth insulating layer 114. This may depend on the positions of the first dummy electrode 151 and the second dummy electrode 152 provided on the fourth insulating layer 114.

[0196] The first dummy electrode 151 may include a side surface 151S surrounding the periphery of the through hole TH, and the second dummy electrode 152 may include a side surface 152S surrounding the periphery of the through hole TH.

[0197] A side surface 114S of the first dummy electrode 151 may be located on the same plane as a side wall 114S of the through hole TH. Also, the side surface 152S of the second dummy electrode 152 may be located on the same plane as a side wall 114S of the through hole TH. Also, the side surface 151S of the first dummy electrode 151 may be located on the same plane as the side surface 152S of the second dummy electrode 152.

[0198] In other words, the respective side surfaces of the first dummy electrode 151 and the second dummy electrode 152 may be positioned vertically in the same plane, and thus the inner wall 114S of the through hole TH formed in the fourth insulating layer 114 may be positioned in the same plane as the respective side surfaces of the first dummy electrode 151 and the second dummy electrode 152. Thus, in the embodiment, the upper width and the lower width of the through hole TH may be substantially the same. Therefore, in the embodiment, an increase in a dead zone caused by the difference between the upper width and the lower width of the through hole TH may be minimized, thereby enabling a thinner semiconductor package.

[0199] On the other hand, in the embodiment, the side wall 114S of the through hole TH can have a certain inclination depending on the shape of the connecting member 200 and the application design.

[0200] 8, for example, a side surface 151S of the first dummy electrode 151 may be vertically offset from a side surface 152S of the second dummy electrode 152. The side surface 151S of the first dummy electrode 151 may be positioned closer to the connecting member 200 than the side surface 152S of the second dummy electrode 152. Thus, a sidewall 114S of the through hole TH may have a slope in which the width gradually decreases from the lower surface to the upper surface of the fourth insulating layer 114.

[0201] 9, for example, a side surface 151S of the first dummy electrode 151 may be vertically offset from a side surface 152S of the second dummy electrode 152. The side surface 151S of the first dummy electrode 151 may be spaced farther from the connecting member 200 than the side surface 152S of the second dummy electrode 152. Thus, a sidewall 114S of the through hole TH may have a slope in which the width gradually increases from the lower surface to the upper surface of the fourth insulating layer 114.

[0202] Meanwhile, as shown in the previous drawings, the top surface of the first dummy electrode 151 may be flush with the top surface of the terminal 210 of the connecting member 200. However, it may be difficult to precisely match the thickness of the connecting member 200 with the thickness of the fourth insulating layer 114, and it may also be difficult to precisely match the thickness of the terminal 210 with the thickness of the first dummy electrode 151.

[0203] Therefore, in this embodiment, the upper surface of the terminal 210 of the connecting member 200 and the upper surface of the first dummy electrode 151 may have a step.

[0204] Referring to FIG. 10, an upper surface of the terminal 210 of the connecting member 200 may be positioned higher than an upper surface of the first dummy electrode 151 by a first height H1. In this case, the first height H1 may be smaller than a vertical thickness of the first dummy electrode 151. Preferably, the first height H1 may be 8 μm or less. More preferably, the first height H1 may be 5 μm or less. Also, referring to FIG. 11, an upper surface of the terminal 210 of the connecting member 200 may be positioned lower than an upper surface of the first dummy electrode 151 by the first height H1. In this case, the first height H1 may be smaller than a vertical thickness of the first dummy electrode 151. Preferably, the first height H1 may be 8 μm or less.

[0205] That is, if the step between the upper surface of the terminal 210 of the connecting member 200 and the upper surface of the first dummy electrode 151 is greater than 8 μm, it may be difficult for the first electrode connected to the terminal 210 of the connecting member 200 in the third electrode portion 140 and the second electrode horizontally overlapping the first electrode to have a uniform height, which may reduce the mechanical and physical reliability of the semiconductor package.

[0206] However, in the embodiment, if the upper surface of the terminal 210 of the connecting member 200 is positioned lower than the upper surface of the first dummy electrode 151, voids may occur during the process of filling the through hole TH of the fourth insulating layer 114 in the third insulating layer 113. Therefore, the upper surface of the terminal 210 of the connecting member 200 is positioned higher than the upper surface of the first dummy electrode 151 to minimize the occurrence of the voids.

[0207] Meanwhile, referring to FIG. 12, the circuit board of the second embodiment may have a different structure of the electrode portion compared to the circuit board of FIG.

[0208] For example, the circuit board can include a first insulating layer 111, a second insulating layer 112, a third insulating layer 113, a fourth insulating layer 114, a fifth insulating layer 115, and a sixth insulating layer .

[0209] The circuit board may also include a connection member 200 embedded in a through hole TH formed in the fourth insulating layer 114 .

[0210] The circuit board may also include a first electrode unit 120 including a first pad unit 121 and a first through-hole 122. The circuit board may also include a second electrode unit 130 including a second pad unit 131 and a second through-hole 132. The circuit board may also include a third electrode unit 140 including a third pad unit 141 and a third through-hole 142. The circuit board may also include a fourth electrode unit 160 including a fourth pad unit 161 and a fourth through-hole 162. The circuit board may also include a dummy electrode unit 150 including a first dummy electrode 151 and a second dummy electrode 152.

[0211] In this case, among the electrode portions of the second embodiment, the electrode portions provided on the second insulating layer 112 and the fifth insulating layer 115 containing the same insulating material may be different from the electrode portions of the first embodiment.

[0212] For example, the circuit board may include a first electrode unit 120 and a fourth electrode unit 160 that are provided on the outermost layer of the plurality of electrodes. In this case, the first pad unit 121 of the first electrode unit 120 of the first embodiment may have a structure that protrudes below the lower surface of the second insulating layer 112. In addition, the fourth pad unit 161 of the fourth electrode unit 160 of the first embodiment may have a structure that protrudes above the upper surface of the fifth insulating layer 115.

[0213] In contrast to this, the first pad portion 121 of the first electrode portion 120 in the second embodiment may have a structure embedded in the second insulating layer 112. Also, the fourth pad portion 161 of the fourth electrode portion 160 in the second embodiment may have a structure embedded in the fifth insulating layer 115.

[0214] Here, the fact that the first pad portion has an embedded structure may mean that at least a portion of the side surface of the first pad portion 121 is covered with the second insulating layer 112. In addition, the fact that the first pad portion has an embedded structure may mean that the upper surface of the first pad portion 121 is located higher than the lower surface of the second insulating layer 112.

[0215] In addition, the fact that the fourth pad portion has a buried structure may mean that at least a portion of the side surface of the fourth pad portion 141 is covered with the fifth insulating layer 115. In addition, the fact that the fourth pad portion has a buried structure may mean that the bottom surface of the fourth pad portion 151 is located lower than the top surface of the fifth insulating layer 115.

[0216] In this embodiment, the pad portion provided on the outermost layer of the circuit board has a structure in which the pad portion is embedded in the insulating layer, thereby preventing the pad portion from collapsing or peeling, and thereby enabling the pad portion to be further miniaturized.Furthermore, in the embodiment, the pad portion is embedded in the insulating layer, thereby enabling the thickness of the circuit board to be reduced by the depth of the embedding, and thereby enabling the semiconductor package to be made thinner.

[0217] In addition, the through holes formed in the respective electrodes of the embodiment may be offset from each other rather than being aligned on the same vertical line, thereby improving design flexibility in forming the through holes.

[0218] Meanwhile, in FIG. 12, the lower surface of the first pad portion 121 is shown to be flush with the lower surface of the second insulating layer 112, but this is not limiting.

[0219] For example, in another embodiment, the lower surface of the first pad portion 121 may be positioned lower than the lower surface of the second insulating layer 112. Also, in another embodiment, the upper surface of the fourth pad portion 161 may be positioned higher than the upper surface of the fifth insulating layer 115. In this case, a conductive adhesive member may be disposed on the lower surface of the first pad portion 121 and / or the upper surface of the fourth pad portion 161, and in this case, the first pad portion 121 and the fourth pad portion 161 may function as the protruding electrodes in the first embodiment. This may improve alignment with the conductive adhesive member and prevent the conductive adhesive member from spreading.

[0220] In yet another embodiment, the lower surface of the first pad portion 121 may be positioned higher than the lower surface of the second insulating layer 112. In yet another embodiment, the upper surface of the fourth pad portion 161 may be positioned lower than the upper surface of the fifth insulating layer 115. In this embodiment, the volume of the conductive adhesive material disposed in the first pad portion 121 and / or the fourth pad portion 161 is further increased compared to the previous embodiment, thereby preventing the conductive adhesive material from spreading and further improving the bonding strength with the semiconductor device.

[0221] A semiconductor package according to an embodiment may include a first insulating layer, a second insulating layer disposed on the first insulating layer, a third insulating layer disposed on the second insulating layer, a fourth insulating layer embedded in the third insulating layer, and a fifth insulating layer disposed on the third insulating layer, wherein the first insulating layer, the second insulating layer, the third insulating layer, and the fourth insulating layer may be made of different materials, the second insulating layer and the fifth insulating layer may be made of the same material, and a vertical thickness between an upper surface of the fourth insulating layer and an upper surface of the third insulating layer may be smaller than a vertical thickness of the second insulating layer. Thus, the embodiment may use the third insulating layer to reduce the thickness of the semiconductor package while preventing the semiconductor package from warping in a specific direction.

[0222] Specifically, the third insulating layer may have a relatively low Young's modulus, thereby suppressing warpage of the semiconductor package. Furthermore, the third insulating layer may absorb impacts applied to the semiconductor package, preventing the semiconductor package from warping significantly in a specific direction. This may solve the problem of reduced operational characteristics due to significant warpage in a specific direction of the semiconductor package, and may also solve the problem of damage to the connecting members disposed within the third insulating layer due to the impact. Furthermore, the third insulating layer may be used to dispose electrodes connected to the connecting members, thereby improving alignment between the electrodes and the connecting members.

[0223] The fourth insulating layer may include a through hole, and the connecting member may be disposed within the through hole. A first dummy electrode may be disposed on an upper surface of the fourth insulating layer, and a second dummy electrode may be disposed on a lower surface of the fourth insulating layer. At least one side surface of the first dummy electrode and the second dummy electrode may be flush with a sidewall of the through hole. The first and second dummy electrodes may be electrodes used to form the through hole using a laser process. In some embodiments, the first and second dummy electrodes may make the upper and lower widths of the through hole substantially identical, thereby reducing the area of ​​a dead region that would otherwise be increased by the difference between the upper and lower widths. This allows the semiconductor package to be thinner.

[0224] In addition, in the embodiment, the shape of the through hole may be changed by positioning the first dummy electrode and the second dummy electrode so as to be offset in the vertical direction, thereby enabling the shape of the through hole to be freely changed according to the shape of the connecting member, thereby improving design freedom.

[0225] In addition, in the embodiment, there may be a step between the upper surface of the terminal of the connecting member and the upper surface of the first dummy electrode, and the step is controlled to be maintained at a certain level or less, thereby improving the degree of connection alignment between the electrode part and the terminal, and further minimizing voids that occur in a process of filling the through hole with an insulating material.

[0226] Meanwhile, when a semiconductor package having the above-described inventive features is used in IT devices or home appliances such as smartphones, server computers, and TVs, it can stably perform functions such as signal transmission or power supply. For example, when a circuit board having the features of the present invention functions as a semiconductor package, it can safely protect a semiconductor chip from external moisture and contaminants, and can solve problems such as leakage current, electrical shorts between terminals, and electrical open circuits in terminals supplying power to the semiconductor chip. Furthermore, when it functions as a signal transmission device, it can solve noise problems. As a result, a circuit board having the above-described inventive features can maintain stable functionality in IT devices and home appliances, and the entire product and the circuit board to which the present invention is applied can achieve functional integration or technical interrelationship with each other.

[0227] When a circuit board having the above-described features of the present invention is used in a transportation device such as a vehicle, it can solve the problem of distortion of signals transmitted to the transportation device, safely protect the semiconductor chip that controls the transportation device from the outside, and solve the problems of leakage current, electrical short circuits between terminals, and electrical open circuits of terminals supplying power to the semiconductor chip, thereby further improving the stability of the transportation device. Therefore, the transportation device and the circuit board to which the present invention is applied can be functionally integrated or technically linked with each other.

[0228] The features, structures, effects, etc. described in the above embodiments are included in at least one embodiment and are not necessarily limited to only one embodiment. Furthermore, the features, structures, effects, etc. exemplified in each embodiment can be combined or modified in other embodiments by a person skilled in the art to which the embodiment belongs. Therefore, content related to such combinations and modifications should be interpreted as being included in the scope of the embodiments.

[0229] The above description focuses on the embodiments, but these are merely illustrative and do not limit the embodiments. Those skilled in the art will understand that various modifications and applications not exemplified above are possible within the scope of the essential characteristics of the embodiments. For example, each component specifically illustrated in the embodiments can be modified and implemented. Differences related to such modifications and applications should be construed as being included within the scope of the embodiments defined in the appended claims.

Claims

1. a first insulating layer; a second insulating layer disposed on the first insulating layer; a third insulating layer disposed on the second insulating layer; a fourth insulating layer embedded within the third insulating layer; a fifth insulating layer disposed on the third insulating layer; the first insulating layer, the second insulating layer, the third insulating layer, and the fourth insulating layer are formed of different materials; the second insulating layer and the fifth insulating layer are formed of the same material; The circuit board of claim 1 , wherein a vertical thickness between the top surface of the fourth insulating layer and the top surface of the third insulating layer is less than a vertical thickness of the second insulating layer.

2. The circuit board of claim 1 , wherein a vertical thickness between the lower surface of the fourth insulating layer and the lower surface of the third insulating layer is smaller than a vertical thickness of the second insulating layer.

3. The circuit board according to claim 1 , wherein the second insulating layer includes a first resin layer and a first reinforcing member provided within the first resin layer.

4. the fourth insulating layer includes a second resin layer and a second reinforcing member provided in the second resin layer, The circuit board according to claim 3 , wherein the number of layers or thickness of the first reinforcing member is different from the number of layers or thickness of the second reinforcing member.

5. The circuit board according to claim 4 , wherein the first and second reinforcing members include glass fibers or reinforcing fibers distinct from fillers.

6. The circuit board according to claim 5 , wherein the number of layers of the first reinforcing member is smaller than the number of layers of the second reinforcing member.

7. The circuit board of claim 5 , wherein the thickness of a single layer of the first strength member is less than the thickness of a single layer of the second strength member.

8. The circuit board of claim 5 , wherein the third insulating layer does not include a strength member.

9. a first electrode portion penetrating at least a partial region of the second insulating layer; a second electrode portion penetrating at least a portion of the third insulating layer; The circuit board according to claim 8 , further comprising: a third electrode portion penetrating the fourth insulating layer.

10. the first electrode portion includes a first pad portion and a first through portion; The circuit board according to claim 9 , wherein the first through portion has a slope such that the width gradually decreases from the lower surface of the second insulating layer toward the upper surface of the second insulating layer.

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