Post-etch plasma treatment to reduce sidewall contaminants and roughness

Abstract

A method for forming a feature in a stack having a silicon-containing layer below a mask is provided, the feature being etched into the stack, and a post-etch plasma treatment is provided to reduce surface roughness on the sidewalls of the feature.

Description

[Technical Field]

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS This application claims the benefit of priority to U.S. Patent Application No. 63 / 411,331, filed September 29, 2022, which is incorporated herein by reference for all purposes. [Background technology]

[0002] When forming semiconductor devices, etching layers may be performed to form memory holes or lines or other semiconductor features. Some semiconductor devices may be formed, for example, by etching a single stack of silicon dioxide, also known as silicon oxide (SiO2), to form a capacitor in a dynamic access random memory (DRAM). Other semiconductor devices may be formed by etching a stack of alternating bilayers of silicon dioxide (oxide) and silicon nitride (nitride) (ONON) or an alternating bilayer of silicon dioxide and polysilicon (OPOP). Other stacks of alternating layers may be etched. In some stacks of alternating layers, one of the layers may be silicon oxide. Some alternating layers may be alternating triple layers. Such stacks may be used for memory applications and three-dimensional "NOT AND" gates (3D NAND). These stacks tend to require relatively high aspect ratio (HAR) etching of the dielectric. For high aspect ratio etches, examples of desirable etch characteristics include high etch selectivity to the mask (such as an amorphous carbon mask), low sidewall etching with a straight profile, and a high etch rate at the etch front. Some high aspect ratio etches result in tapered features where the top is much wider than the bottom. Such features can increase device failure or limit device density, device performance, and device depth.

[0003] In some etching processes for OPOP stacks using amorphous carbon masks, a metal-containing passivation agent is used during the etching process. The metal-containing passivation agent may be provided during the etching process so that passivation and etching occur simultaneously, or there may be alternating steps of passivation and etching.

[0004] The background art description provided herein is intended to provide a general overview of the present disclosure. Information described in this background art section, as well as aspects of the description that may not otherwise be considered prior art at the time of filing, are not admitted, expressly or impliedly, as prior art against the present disclosure. Summary of the Invention

[0005] To achieve the above, and in accordance with the objects of the present disclosure, a method is provided for etching a feature in a stack including a silicon oxide layer below a mask. A substrate support for supporting the stack in an etching chamber is cooled to a temperature below 0° C. An etching gas including a halogen-containing component and a phosphorus-containing component is supplied. A plasma is generated from the etching gas. A bias is applied to accelerate ions from the plasma into the stack. The feature is selectively etched in the stack relative to the mask.

[0006] In another aspect, an apparatus is provided for processing an upper stack of substrates comprising at least one of a silicon oxide layer and a silicon nitride layer below a mask. An etching chamber is provided. A substrate support supports the substrate within the etching chamber. A temperature controller controls the temperature of the substrate support. An electrode provides RF power within the etching chamber. An RF power source provides RF power to the electrode. A gas source provides an etching gas within the etching chamber, the gas source including a halogen-containing component source and an HF gas source.

[0007] These and other features of the present disclosure are described in more detail below in conjunction with the detailed description and the following figures. [Brief explanation of the drawings]

[0008] The present disclosure is presented by way of illustration and not by way of limitation.In the figures of the accompanying drawings, like reference numerals refer to like elements.

[0009] [Figure 1] FIG. 1 shows a flow chart illustrating a method for etching recessed features in a stack containing dielectric materials according to various embodiments.

[0010] [Figure 2A] FIG. 2A shows a stack processed according to some embodiments. [Figure 2B] FIG. 2B shows a stack processed according to some embodiments. [Figure 2C] FIG. 2C shows a stack processed according to some embodiments. [Figure 2D] FIG. 2D shows a stack processed according to some embodiments. [Figure 2E] FIG. 2E shows a stack processed according to some embodiments.

[0011] [Figure 3] FIG. 3 illustrates a reaction chamber that can be used to practice the techniques described herein according to certain embodiments.

[0012] [Figure 4] FIG. 4 illustrates a computer system for implementing a controller used in an embodiment of the present invention.

[0013] In the drawings, like reference numerals may be used to designate like structural elements, and it should be understood that the depictions in the figures are schematic and not to scale. DETAILED DESCRIPTION OF THE INVENTION

[0014] The present disclosure will now be described in detail with reference to several preferred embodiments thereof, as illustrated in the accompanying drawings. In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present disclosure. However, it will be apparent to those skilled in the art that the present disclosure may be practiced without some or all of these specific details. In other instances, well-known process steps and / or structures have not been described in detail in order to avoid unnecessarily obscuring the present disclosure.

[0015] The fabrication of certain semiconductor devices involves etching features in a stack of materials using a plasma-based etching process. In various embodiments herein, the stack of materials includes alternating / repeating layers of dielectric materials. Often, at least one of the layers in the stack is or includes a silicon-containing layer. The silicon-containing layer may contain silicon nitride, silicon oxide, silicon carbide, silicon oxynitride, silicon oxycarbide, polysilicon, or silicon germanium. In one example, the stack includes alternating layers of silicon oxide and polysilicon. In some embodiments, the stack includes alternating silicon oxide and silicon nitride films, or a single silicon oxide layer, or a single silicon layer.

[0016] Features etched into silicon-containing materials may be cylinders, trenches, or other concave features. The aspect ratio of such features is defined as the lateral critical dimension divided by the depth. As the aspect ratio of such features continues to increase, several problems arise, including (1) feature twist, (2) feature non-circularity, (3) aspect-ratio-dependent etch rates, (4) curved etch profiles, (5) poor mask selectivity, and (6) low etch rates. Twist refers to irregular deviations between the intended feature bottom location and the actual final feature bottom location (e.g., the final feature location corresponds to the position of the feature bottom after the feature is etched). For example, in some cases, cylindrical features are intended to be etched in a regular array. If some or all of the features irregularly deviate from this array at their bottoms, they are considered to have twist.

[0017] A non-circular feature refers to a deviation of the bottom hole shape from a circular hole shape. This problem is relevant when etching circular features, such as cylinders, where it is desired that the bottom of the recessed feature be circular. When the bottom hole shape deviates from a circular shape, it is often formed into a shape that more closely resembles an ellipse, triangle, or irregular polygon. In many cases, these non-circular shapes are undesirable.

[0018] Aspect ratio dependent etch rate refers to the problem that the etch rate slows as the aspect ratio of a feature increases. In other words, the further a feature is etched into the dielectric material, the slower the etching process becomes. This problem is problematic because it can lead to low throughput and a corresponding increase in processing costs.

[0019] A curved etch profile refers to the tendency of a feature to etch laterally within a dielectric layer such that the final profile curves outward excessively somewhere along the depth of the feature. In other words, the actual maximum critical dimension of the feature may exceed the desired maximum critical dimension of the feature, potentially compromising the integrity of the resulting structure or limiting the electrical performance of the final device.

[0020] Poor mask selectivity is a problem when an etching process removes too much mask, leaving no mask at the end of the process, or when the amount of mask that remains is insufficient to adequately transfer the pattern from the mask to one or more dielectric films. Poor mask selectivity often results in poor feature profile near the top of recessed features.

[0021] A low etch rate refers to an etch rate that is slower than desired for a particular application. A low etch rate is problematic because it increases etching times, reduces throughput, and increases processing costs.

[0022] Unfortunately, techniques that ameliorate some of these problems often exacerbate others. As a result, these problems are balanced against one another when designing etch operations. For example, conventional commercial dielectric etch processes often result in substantial bowing. Low-temperature etch processes have recently been developed to address the bowing problems associated with conventional commercial dielectric etch processes. Such low-temperature processes may be performed while the substrate support is cooled to a temperature below about 25° C. Advantageously, low-temperature processes result in relatively high etch rates and relatively reduced bowing. However, these low-temperature processes substantially exacerbate problems related to twisting and non-circular features. Until now, such trade-offs have been difficult to avoid.

[0023] Dry development of high-aspect-ratio contacts requires strict control of the sidewall taper angle. Various methods have been attempted to limit the lateral critical dimension (CD) difference between the top and bottom of etched structures. The recent development of 3D NAND memory, which has thicker structures with an increased number of ONON or OPOP bilayers, has particularly increased the demand for strict control of top and bottom shapes. A large profile (the difference between the top and bottom CDs) poses risks to subsequent device fabrication steps, impacting device performance. Current technology, reactive ion etching of high-aspect-ratio structures, relies on sidewall deposition to protect against lateral CD erosion. Maintaining the delicate balance between etching and sidewall deposition is particularly challenging for high-aspect-ratio features. As a result, dry development of high-aspect-ratio structures is limited to thinner structures, and highly complex development is required to enable etching of thick stacks.

[0024] As etched features become deeper and etching times become longer, the surface roughness of the sidewalls increases due to defects such as notches, mouse bites, and scalloping in the interfacial layer. This increase in surface roughness affects downstream processes, such as deposition, and negatively impacts device fabrication. Although passivation during etching can reduce surface roughness, the resulting surface roughness is still too high.

[0025] The embodiments described herein provide deeper, high-aspect ratio features etched into stacks with reduced sidewall roughness and contaminants. For ease of understanding, FIG. 1 is a high-level flowchart that may be used in some embodiments. A stack having a silicon-containing layer and mask above a substrate is received in a process chamber (step 104). FIG. 2A is a schematic cross-sectional view of a stack 200 used in the embodiments. In some embodiments, the stack comprises a substrate 208 beneath a plurality of bilayers 212, which are disposed below a carbon-containing patterned mask 216. One or more layers may be disposed between the substrate 208 and the plurality of bilayers 212 or between the plurality of bilayers 212 and the carbon-containing patterned mask 216. The carbon-containing patterned mask 216 may be amorphous carbon. In some embodiments, the patterned mask pattern provides mask features 220 for high-aspect ratio contacts. In some embodiments, the mask features are formed before the substrate is placed in the etch chamber. In other embodiments, the mask features 220 are formed while the substrate is in the etch chamber. In some embodiments, the plurality of bilayers 212 are bilayers of a layer of silicon oxide 224 and a layer of silicon nitride 228. In some embodiments, the stack may include a repeating sequence of three or more layers.

[0026] A passivation layer is deposited on the sidewalls of the feature, and the feature is etched into the stack 200 through the carbon-containing mask 216 (step 108). In some embodiments, the etching step includes supplying an etching gas and forming a plasma from the etching gas, where the plasma etches the feature into the stack 200. In some embodiments, the etching gas includes a halogen-containing etchant, an inert bombardment gas, and a passivation agent. In some embodiments, the halogen-containing etchant is a fluorine-containing gas. In some embodiments, the bombardment gas includes at least one of He, Ne, Ar, Kr, Xe, and N2. In some embodiments, the substrate support is maintained at a temperature in a range of about −80° C. to 150° C. In some embodiments, the chamber pressure is maintained at a pressure of about 5 to 400 milliTorr (mT). In some embodiments, the etching gas is converted into a plasma. In some embodiments, pulsed RF power is supplied at different frequencies and power ranges. For example, during the first stage, RF power may be provided at 400 kilohertz (kHz) with a power in the range of 0 to 1500 watts (W) and at 60 megahertz (MHz) with a power in the range of 0 to 1000 W. Different powers may be provided at each frequency component. The patterned mask layer protects the underlying stack material where the patterned mask layer is present. This ensures that etched features are formed in the patterned openings in the mask layer where recessed features are desired. To etch the etch front of high aspect ratio features, in some embodiments, a bias power greater than 10 kW is provided. In some embodiments, a substrate support for supporting the stack in the etching chamber during feature etching is cooled to a temperature below 0° C. In some embodiments, the substrate support is cooled to a temperature below −10° C.

[0027] 2B is a cross-sectional view of stack 200 after contact 232 has been etched. The contact is a high aspect ratio contact. Preferably, a high aspect ratio contact has a height to CD width ratio of greater than 40:1. More preferably, the contact has an aspect ratio of etch depth to feature CD width of greater than 100:1.

[0028] FIG. 2C shows an enlarged portion of FIG. 2B, illustrating the sidewalls of the bilayer of silicon oxide 224 and silicon nitride 228 layers beneath the carbon-containing mask 216, as noted above. The sidewalls 240 are neither vertical nor smooth. For example, the sidewalls 240 have a mouse-bite or fan-shaped roughness. The roughness may be defined as the roughness from the silicon oxide 224 layer to the silicon nitride 228 layer measured using an electron microscope. In some embodiments, the sidewall roughness is in the range of 5 nm to 10 nm. In some embodiments, a passivation layer 244 is formed over the sidewalls 240. In some embodiments, the passivation layer 244 includes a metal component.

[0029] An optional wet clean may be applied to remove the passivation layer (step 112). FIG. 2D shows an enlarged section after the optional wet clean has been applied. The passivation layer 244 (shown in FIG. 2C) has been removed. In some embodiments, metal-containing contaminants 248 remain after the optional wet clean process. In some embodiments, the metal-containing contaminants 248 may be embedded 1 to 2 nm into the sidewalls. Because the contaminants are electrically conductive, the contaminants may cause defects in the resulting semiconductor device.

[0030] Next, a post-etch plasma treatment is provided to reduce sidewall roughness (step 116). A treatment gas is supplied. The treatment gas may include bombardment gases to provide concentrations of mask protection components, which may act as passivators, and halogens, which may act as etchants. The bombardment ions have sufficient energy to reduce sidewall roughness and remove embedded contaminants, but not enough energy to vertically etch the etch front. Reducing sidewall roughness and removing contaminants improves the reliability and reduces defects in the resulting semiconductor device. In an example, the pre-treatment process may provide 0-5% hydrofluorocarbon, 75-100% neutral gas, and 0-20% NF3, where the gas percentages are measured by volume. Pulsed RF power is supplied at 60 MHz with 1-3 kW of power and 400 kHz with 0-15 kW of power, with a duty cycle of 20-60%. The post-etch plasma treatment is supplied for a duration of 1-200 seconds. Generally, in some embodiments, the etchant is less than 20% of the total process gas volume, the passivation agent is less than 5% of the total process gas volume, and the bombardment gas is greater than 75% of the total process gas volume measured by volume. In some embodiments, other low frequency bias RF may be provided instead of 400 kHz. Other high frequency excitation RF may be provided instead of 60 MHz. In some embodiments, the bias power is less than 15 kW.

[0031] Figure 2E shows a close-up view after post-etch plasma treatment. The roughness of the sidewalls 240 has been reduced. Additionally, the metal-containing contaminants 248 shown in Figure 2D have been removed. In some embodiments, the sidewall roughness is less than 2 nm.

[0032] In some embodiments, an optional wet clean is provided (step 120) after the post-etch plasma treatment (step 116). In some embodiments, an optional wet clean is not performed before the post-etch plasma treatment (step 112), but an optional wet clean is provided after the post-etch plasma treatment (step 120). In some embodiments, an optional wet clean is provided both before the post-etch plasma treatment (step 112) and after the post-etch plasma treatment (step 120). In some embodiments, an optional wet clean is not provided before the post-etch plasma treatment (step 112) or after the post-etch plasma treatment (step 120).

[0033] By providing a post-etch plasma treatment, sidewall smoothness and sidewall contaminant reduction do not need to be considered during the etch process. Consequently, the etch recipe can be tailored to other potential characteristics, such as etch selectivity, aspect ratio, twist prevention, CD uniformity, etch rate, and circularity. Some etch processes create metal-containing sidewall passivation or use metal-doped masks that create metal contaminants. While wet cleaning removes most of the metal contaminants, a post-etch plasma treatment not only reduces sidewall roughness but also more completely removes the metal contaminants.

[0034] Because the post-etch plasma treatment is intended to remove contaminants and roughness on the sidewalls, rather than to etch at the etch front, the ion energy during the post-etch plasma treatment is lower than the ion energy during the etch. As a result, the bias power and voltage during the post-etch plasma treatment are lower than the bias power and voltage during the etch. A passivation layer is deposited on the sidewalls during the etch. No passivation layer is deposited during the post-etch plasma treatment. However, in some embodiments, the post-etch plasma treatment may deposit a mask protection deposit. As a result, the process gas may contain no passivation agent or a passivation agent at a concentration lower than that of the etch gas to provide mask protection. If a metal-containing passivation agent or another non-hydrocarbon passivation agent is used for the etch, in some embodiments, the process gas does not contain such a non-hydrocarbon passivation agent. In some embodiments, the process gas does not contain a hydrocarbon passivation agent or has a lower concentration of hydrocarbon passivation agent than the etch gas. The post-etch plasma treatment relies on ion bombardment of the sidewalls to reduce roughness and remove contaminants, rather than combining halogens with ion bombardment to vertically etch the etch front. Therefore, the process gas is halogen-free or has a lower concentration of halogen than the etch gas. In some embodiments, the process gas has a low concentration of halogen, such as fluorine, to prevent clogging of features or capping of the mask. In some embodiments, the etchant is at least one of sulfur hexafluoride (SF6) and nitrogen trifluoride (NF3). In some embodiments, the bias and power, halogen concentration, and mask protection can be adjusted during the post-etch plasma treatment to minimize surface roughness without increasing the impact on bowing or pillar profile. In some embodiments, the post-etch plasma treatment is performed in the same chamber as the etch.In some embodiments, the post-etch plasma treatment is performed in a different chamber than the etching. Controlling the ratio of the inert bombardment gas to the etchant gas allows for sufficient etchant gas to prevent clogging or capping of the mask, but not enough etchant gas to significantly etch the mask and / or cause sidewall damage. Etching the feature provides an etching gas including a bombardment gas and an etchant, with a bombardment gas to etchant ratio, where the bombardment gas to etchant ratio of the process gas is greater than the bombardment gas to etchant ratio of the etching gas. The process gas has a passivation agent to bombardment gas ratio. The etching gas has a passivation agent to bombardment gas ratio. In some embodiments, the process gas has a passivation agent to bombardment gas ratio that is less than the passivation agent to bombardment gas ratio of the etching gas.

[0035] In some embodiments, there is more surface roughness near the top of the etch feature and little surface roughness near the bottom of the feature. As a result, in some embodiments, the post-treatment ions only need enough energy and bias to reduce the surface roughness closer to the top of the etch feature. In some embodiments, the post-treatment ions do not have enough energy to affect the bottom of the etch feature. Control of ion energy allows ions with sufficient energy to reduce the surface roughness near the top of the etch feature, and ions with low energy to prevent damage to the sidewalls of the etch feature lower within the etch feature, thereby preventing bowing, and ions with low energy to also prevent mask sputtering. In some embodiments, RF pulses are used to provide the controlled bias power.

[0036] In some embodiments, controlling the mask thickness during post-etch plasma processing is another parameter that can be used to control the depth of surface roughness reduction. The thinner the mask and the lower the aspect ratio, the deeper into the etch feature the surface roughness can be reduced. The thicker the mask and the higher the aspect ratio, the shallower the depth to which the surface roughness is reduced. The aspect ratio of the mask can be controlled by the concentration of the etchant gas and the resulting etching species. The higher the concentration of the etchant gas, the larger the aspect ratio of the mask feature and the deeper into the etch feature the surface roughness can be reduced.

[0037] In some embodiments, controlling the length of time of the post-etch plasma treatment can be used to control how much the surface roughness is reduced. The longer the duration of the post-etch plasma treatment, the more the surface roughness will be reduced. However, if the duration is too long, there is a high possibility of sidewall damage.

[0038] In some embodiments, the post-etch plasma treatment is separate from the etch process, allowing the surface roughness to be tuned or even completely eliminated without affecting the results of the etch process. As a result, no additional tradeoffs are required during the etch process. In some embodiments, the post-etch plasma treatment can be scaled to higher aspect ratios to meet the needs of future devices.

[0039] Device: The various hardware and method embodiments described above can be used in conjunction with lithographic patterning tools or processes, for example, for the fabrication or manufacturing of semiconductor devices, displays, LEDs, photovoltaic panels, etc. Typically, although not necessarily, such tools / processes will be used or performed together in a common fabrication facility.

[0040] Lithographic patterning of films typically includes some or all of the following steps: (1) applying a photoresist onto a workpiece, e.g., a substrate having a silicon-containing film formed thereon, using a spin-on or spray-on tool; (2) curing the photoresist using a hotplate or furnace or other suitable curing tool; (3) exposing the photoresist to visible, ultraviolet (UV), or X-ray light using a tool such as a wafer stepper; (4) developing the resist to selectively remove and thereby pattern the resist using a tool such as a wet bench or spray developer; (5) transferring the resist pattern to the underlying film or workpiece by using a dry or plasma-assisted etching tool; and (6) removing the resist using a tool such as an RF or microwave plasma resist stripper, each of which can be accomplished with multiple available tools. In some embodiments, an ashing hard mask layer (e.g., an amorphous carbon layer) and another suitable hard mask (e.g., an antireflective layer) may be deposited before applying the photoresist.

[0041] In this application, the terms “semiconductor wafer,” “wafer,” “substrate,” “wafer substrate,” and “partially fabricated integrated circuit” are used interchangeably. Those skilled in the art will understand that the term “partially fabricated integrated circuit” can refer to a silicon wafer during any of the many stages upon which an integrated circuit is fabricated. Wafers or substrates used in the semiconductor device industry typically have diameters of 200 mm, 300 mm, or 450 mm. The above detailed description assumes that the embodiments are implemented on wafers; however, the embodiments are not so limited. Workpieces may be of various shapes, sizes, and materials. In addition to semiconductor wafers, other workpieces that may utilize embodiments of the present disclosure include various articles such as printed circuit boards, magnetic recording media, magnetic recording sensors, mirrors, optical elements, micromechanical devices, and the like.

[0042] Unless otherwise defined for a particular parameter, the terms "about" and "approximately" as used herein are intended to mean ±10% relative to the associated value.

[0043] 3 is a schematic diagram of a plasma processing chamber 300 for plasma processing a substrate, in an embodiment. In one or more embodiments, the plasma processing chamber 300 includes a gas distribution plate 306 that provides a gas inlet and an electrostatic chuck (ESC) 316 within a plasma processing chamber 304, surrounded by a chamber wall 350. Within the plasma processing chamber 304, the substrate 208 is positioned on top of the ESC 316. The ESC 316 may receive a bias from an ESC power supply 348. A gas source 310 is connected to the plasma processing chamber 304 through the gas distribution plate 306. An ESC temperature controller 351 is connected to the ESC 316 and provides temperature control of the ESC 316. A radio frequency (RF) power supply 330 supplies RF power to the ESC 316 and an upper electrode. In this embodiment, the upper electrode is the gas distribution plate 306. In a preferred embodiment, 400 kilohertz (kHz), 13.56 megahertz (MHz), 1 MHz, 2 MHz, 60 MHz, and / or optionally, 27 MHz power sources comprise the RF power source 330 and the ESC power source 348. A controller 335 is controllably connected to the RF power source 330, the ESC power source 348, the exhaust pump 320, and the gas source 310. A high-flow liner 360 is a liner within the plasma processing chamber 304 that confines gas from the gas source and has slots 362. The slots 362 maintain a controlled flow of gas passing from the gas source 310 to the exhaust pump 320. An example of such a plasma processing chamber is the Flex® Etch System manufactured by Lam Research, Inc. of Fremont, California. The process chamber can be a CCP (capacitively coupled plasma) reactor or an ICP (inductively coupled plasma) reactor.

[0044] FIG. 4 is a high-level block diagram illustrating a computer system 400 for implementing a controller 535 used in embodiments of the present invention. Computer systems may take many physical forms, ranging from integrated circuits, printed circuit boards, and small handheld devices to massive supercomputers. The computer system 400 may include one or more processors 402 and may further include an electronic display device 404 (for displaying graphics, text, and other data), main memory 406 (e.g., random access memory (RAM)), storage device 408 (e.g., a hard disk drive), removable storage device 410 (e.g., an optical disk drive), user interface device 412 (e.g., a keyboard, touch screen, keypad, mouse, or other pointing device, etc.), and / or a communication interface 414 (e.g., a wireless network interface). The communication interface 414 allows software and / or data to be transferred between the computer system 400 and external devices via a link. The system may also include a communication infrastructure 416 (e.g., a communication bus, crossover bar, or network) to which the aforementioned devices / modules may be connected.

[0045] Information transferred via communications interface 414 may be in the form of signals, such as electronic, electromagnetic, optical, or other signals receivable by communications interface 414 via a communications link that transmits the signals, and may be implemented using wire or cable, fiber optics, telephone lines, cellular phone links, radio frequency links, and / or other communications channels. It is contemplated that such communications interfaces may enable one or more processors 402 to receive information from a network or output information to a network in the course of performing the method steps described above. Furthermore, method embodiments may be performed solely by the processor, or may be performed over a network, such as the Internet, in conjunction with a remote processor that shares some of the processing.

[0046] The term "non-transitory computer-readable medium" is generally used to refer to media such as storage devices, including main memory, secondary memory, removable storage, and hard disks, flash memory, disk drive memory, CD-ROMs, and other forms of persistent memory, and is not to be construed as covering transient subject matter, such as transmitted waves or signals. Examples of computer code include machine code, such as produced by a compiler, and files containing high-level code that are executed by a computer using an interpreter. Computer-readable media may also be computer code embodied in a transmitted wave and transmitted by a computer data signal representing a sequence of instructions executable by a processor.

[0047] It should be understood that the configurations and / or approaches described herein are exemplary in nature and are susceptible to numerous variations, and therefore, these specific embodiments or examples are not to be construed in a limiting sense. A particular routine or method described herein may represent one or more of any number of processing strategies. As such, various illustrated operations may be performed in the order illustrated, in other orders, in parallel, or in some cases omitted. Similarly, the order of processes described above may be changed. Certain references are incorporated herein by reference. It is understood that any disclaimers or disclaimers made in such references do not necessarily apply to the embodiments described herein. Similarly, any features described in such references as required may be omitted in embodiments herein. The subject matter of the present disclosure includes all novel and non-obvious combinations and subcombinations of the various processes, systems, configurations, and other features, functions, acts, and / or properties disclosed herein, and any and all equivalents thereof.

[0048] Conclusion: While the present disclosure has been described in terms of several preferred embodiments, there are alterations, modifications, permutations, and various substitute equivalents that fall within the scope of the present disclosure. It should also be noted that there are many alternative ways of implementing the methods and apparatuses of the present disclosure. Therefore, it is intended that the following appended claims be construed to include all such alterations, modifications, permutations, and various substitute equivalents as fall within the true spirit and scope of the present disclosure. As used herein, the phrase "A, B, or C" should be construed to mean logic ("A or B or C") using a non-exclusive logical "OR," and not to mean "only one of A or B or C." Each step within a process may be optional and not required. Different embodiments may omit one or more steps or provide steps in a different order. Furthermore, various embodiments may provide different steps simultaneously rather than sequentially.

Claims

1. 1. A method of forming a feature in a stack having a silicon-containing layer below a mask, the method comprising: Etching a feature in the stack; providing a post-etch plasma treatment to reduce surface roughness of the sidewalls of the feature; A method comprising:

2. 10. The method of claim 1, The method further comprising providing a wet cleaning of a passivation layer formed in the feature by etching the feature.

3. 3. The method of claim 2, providing the wet cleaning before providing the post-etch plasma treatment; providing the wet cleaning to leave contaminants in the features; The method wherein the contaminants are removed by providing the post-etch plasma treatment.

4. 4. The method of claim 3, The method, wherein the contaminant is a metal-containing contaminant.

5. 3. The method of claim 2, The method, wherein providing the wet clean is after providing the post-etch plasma treatment.

6. 10. The method of claim 1, providing the post-etch plasma treatment to provide a bias power and etching the feature to provide a bias power; The method, wherein the bias power supplied by the post-etch plasma treatment is less than the bias power supplied by etching the feature.

7. 10. The method of claim 1, Providing the post-etch plasma treatment includes providing a process gas including a bombardment gas and an etchant, the process gas having a bombardment gas to etchant ratio; Etching the feature includes providing an etching gas comprising a bombardment gas and an etchant, the etching gas having a bombardment gas to etchant ratio; The method wherein the bombardment gas to etchant ratio of the process gas is greater than the bombardment gas to etchant ratio of the etching gas.

8. 10. The method of claim 1, providing the post-etch plasma treatment, wherein a process gas including a bombardment gas and a passivation agent is provided with a ratio of passivation agent to bombardment gas; Etching the feature includes providing an etching gas comprising a bombardment gas and a passivation agent, the etching gas having a ratio of passivation agent to bombardment gas; The method wherein the ratio of the passivation agent to bombardment gas in the process gas is less than the ratio of the passivation agent to bombardment gas in the etching gas.

9. 8. The method of claim 7, The bombardment gases are He, Ne, Ar, Kr, Xe, and N 2 The method includes at least one of the following:

10. 10. The method of claim 1, Etching the feature deposits metallic contaminants in the feature; The method wherein providing said post-etch plasma treatment removes metallic contaminants.

11. 10. The method of claim 1, The method, wherein the mask is a carbon-containing mask.

12. 10. The method of claim 1, The method wherein the mask is amorphous carbon.

13. 10. The method of claim 1, The method, wherein the mask is a carbon-containing mask and the stack includes a plurality of alternating silicon oxide or silicon nitride layers.

14. 10. The method of claim 1, the mask is a carbon-containing mask; The method, wherein the stack comprises a plurality of alternating silicon oxide and polysilicon layers.

15. 10. The method of claim 1, The method wherein the features have a height to width ratio greater than 40:

1.

16. 10. The method of claim 1, the mask is a carbon-containing mask; The method wherein the stack comprises at least one layer of silicon oxide.

17. 10. The method of claim 1, providing the post-etch plasma treatment by providing a process gas containing a passivation agent; The method, wherein the passivation agent is less than or equal to 5% of the total volume of the process gas.

18. 10. The method of claim 1, Providing the post-etch plasma treatment includes providing a process gas including an etchant; The method, wherein the etchant is 20% or less of the total volume of the process gas.

19. 10. The method of claim 1, providing the post-etch plasma treatment, providing a treatment gas including a bombardment gas; The method wherein the impact gas is at least 75% of the total volume of the treatment gas.

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