Method for forming trench-fill void-free DRAM devices

Abstract

Disclosed herein is an approach for forming a dynamic DRAM device without trench fill voids. The method includes providing a plurality of trenches in a substrate, the plurality of trenches defining a plurality of device structures, and depositing a plurality of layers over the device structures. The layers may include a first layer over the device structures, a second layer over the first layer, and a third layer over the second layer. The method may further include forming a plurality of contact trenches through the plurality of layers to expose one or more of the plurality of device structures, and directing ions into sidewalls of the trenches at a non-zero angle, where the ions collide with the third layer without colliding with the second layer. The method may further include forming a fill material within the trenches after directing the ions into the sidewalls of the trenches.

Description

[Technical Field]

[0001] FIELD OF THE DISCLOSURE

[0001] This disclosure relates to semiconductor structures, and more particularly to methods for forming dynamic random access memory (DRAM) devices without trench fill voids. [Background technology]

[0002]

[0002] Currently, the density of dynamic random access memories (DRAMs) is continuously increasing. Therefore, it is necessary to scale the bit line contact (BLC) used in the cell transistor for high density DRAM devices. This part affects the electrical resistance of the cell transistor, which in turn affects the cell performance such as write recovery time and refresh time. Typically, the BLC plug is filled in the trench and acts as an electrode plate for the capacitor. + The most common method is to fill the trench with doped polysilicon. However, seams and voids often remain inside the trench after the polysilicon filling process, which increases resistance, reduces reliability, and impacts DRAM scaling. Some prior art techniques use a series of deposition and etching steps to address this issue. However, this increases device damage, raises particle concerns, and makes it difficult to continue scaling smaller features.

[0003]

[0003] The present disclosure is provided with respect to these and other shortcomings of the current art. Summary of the Invention

[0004] This Summary is provided to introduce in a simplified form selected concepts that are detailed below in the Detailed Description. This Summary is not intended to identify key features or essential features of the claimed subject matter, nor is it intended as an aid in determining the scope of the claimed subject matter.

[0005] In one aspect, a method includes providing a plurality of trenches in a substrate, the plurality of trenches defining a plurality of device structures, and depositing a plurality of layers over the plurality of device structures. The plurality of layers may include a first layer over the plurality of device structures, a second layer over the first layer, and a third layer over the second layer. The method may further include forming a plurality of contact trenches through the plurality of layers to expose one or more of the plurality of device structures; directing ions into sidewalls of the plurality of contact trenches at a non-zero angle with respect to a normal extending from a top surface of the plurality of layers, the ions colliding with the third layer without colliding with the second layer; and forming a fill material within the plurality of contact trenches after directing the ions into the sidewalls of the plurality of contact trenches.

[0006] In another aspect, a method for forming a DRAM device may include forming a source trench isolation (STI) material over a plurality of trenches in a substrate, the plurality of trenches defining a plurality of device structures. The method may further include depositing a plurality of layers over the plurality of device structures, the plurality of layers including a first layer over the STI material, a second layer over the first layer, and a third layer over the second layer, the second layer and the third layer being different materials. The method may further include forming a plurality of contact trenches through the plurality of layers to expose one or more of the plurality of device structures; directing ions into sidewalls of the plurality of contact trenches at a non-zero angle with respect to a normal extending from a top surface of the plurality of layers, the ions colliding with the third layer without colliding with the second layer; and forming a fill material within the plurality of contact trenches after directing the ions into the sidewalls of the plurality of contact trenches.

[0007] In yet another aspect, a method for forming bit line contacts for a DRAM device may include providing a plurality of trenches in a substrate, the plurality of trenches defining a plurality of device structures; and depositing a plurality of layers over the plurality of device structures, the plurality of layers including a first layer over the plurality of device structures, a second layer over the first layer, and a third layer over the second layer, the second layer and the third layer being different materials. The method may further include forming a plurality of contact trenches through the plurality of layers to expose one or more of the plurality of device structures; forming a passivation layer along sidewalls of the plurality of trenches by directing ions into sidewalls of the plurality of trenches at a non-zero angle with respect to a normal extending from a top surface of the plurality of layers, the ions impinging on the third layer without impinging on the second layer; and forming a filler material within the plurality of contact trenches after directing ions into the sidewalls of the plurality of contact trenches. [Brief explanation of the drawings]

[0008]

[0008] The accompanying drawings illustrate exemplary approaches of the present disclosure, including practical applications of the principles of the present disclosure, as follows:

[0009] [Figure 1]

[0009] FIG. 1 is a cross-sectional view of a device including multiple layers over multiple trenches and over multiple device structures according to an embodiment of the present disclosure. [Figure 2]

[0010] 1 is a cross-sectional side view of a device after formation of multiple contact trenches according to an embodiment of the present disclosure. [Figure 3]

[0011] FIG. 1 is a cross-sectional side view of a device during angled ion implantation according to an embodiment of the present disclosure. [Figure 4]

[0012] 1A-1C are cross-sectional side views of a device during trench filling formation according to an embodiment of the present disclosure. [Figure 5]1A-1C are cross-sectional side views of a device during trench filling formation according to an embodiment of the present disclosure. [Figure 6]

[0013] 1 is a schematic diagram of a processing apparatus according to an embodiment of the present disclosure.

[0010]

[0014] The drawings are not necessarily to scale. The drawings are merely representational and are not intended to represent specific parameters of the present disclosure. The drawings are intended to illustrate exemplary embodiments of the present disclosure and therefore are not to be considered limiting in scope. In the drawings, like numbering represents like elements.

[0011]

[0015] Additionally, certain elements in the drawings may be omitted or not drawn to scale for clarity of illustration. The cross-sectional views may be in "slice" format or in the form of "close-up" cross-sections, which for clarity of illustration omit certain background lines that would be visible in a "true" cross-section. Additionally, some reference numbers may be omitted in some of the drawings for clarity. DETAILED DESCRIPTION OF THE INVENTION

[0012]

[0016] The methods and devices according to the present disclosure will now be described in more detail with reference to the accompanying drawings, which illustrate various embodiments. The methods may be embodied in many different forms and are not to be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the methods to those skilled in the art.

[0013]

[0017] To address the deficiencies of the prior art as discussed above, embodiments of the present disclosure advantageously use angled ion implantation to modify desired portions of the trench surface of a DRAM plug and stabilize the growth rate of the subsequently formed trench fill, thereby avoiding voids or gaps within the trench fill, resulting in reduced resistance and improved reliability and DRAM scaling.

[0014]

[0018] 1 is a cross-sectional side view of a portion of a semiconductor device (hereinafter "device") 100, such as a DRAM device, according to one or more embodiments. As shown, the device 100 may include a base or substrate 102 that includes a plurality of trenches 104 and a plurality of device structures 106. Without limitation, the plurality of device structures 106 may correspond to a plurality of source trench isolation (STI) structures. An STI fill 108 may be formed over the device structures 106 and within the trenches 104. The STI fill 108 may be planarized to a top surface 109 of the device structures 106.

[0015]

[0019] As further shown, multiple layers 110 may be formed over the STI fills 108 and over the device structures 106. In some embodiments, a first layer 111 may be formed over the STI fills 108, a second layer 112 may be formed over the first layer 111, a third layer 113 may be formed over the second layer 112, and a fourth layer 114 may be formed over the third layer 113. The third layer 113 and the second layer 112 may be different materials, and the first layer 111 and the fourth layer 114 may be the same material. In this non-limiting example, the first layer 111 is an oxide material, the second layer 112 is a silicon nitride layer, the third layer 113 is a polysilicon layer, and the fourth layer 114 is an oxide material. It should be understood that there may be fewer or more layers in the multiple layers 110. Additionally, it should be understood that the materials of each of the plurality of layers 110 may vary in alternative embodiments.

[0016]

[0020] 2 , a plurality of contact trenches 118 may then be formed (e.g., etched) through the plurality of layers 110 to expose one or more of the device structures 106. In some embodiments, the etching process may recess one or more of the device structures 106 and the top surface 109 of the STI fill material 108. Each of the plurality of contact trenches 118 is defined by a first sidewall 121 and a second sidewall 122 that extend between a trench bottom 123 and a top surface 124 of the plurality of layers 110. Within each of the plurality of contact trenches 118 are exposed portions of the first layer 111, the second layer 112, the third layer 113, and the fourth layer 114.

[0017]

[0021] 3 , a portion of the first and second sidewalls 121, 122 of each of the plurality of contact trenches 118 may then be passivated by ions 132 directed / delivered into the plurality of contact trenches 118 at a non-zero angle “θ” with respect to a normal 134 extending from an upper surface 124 of the plurality of layers 110. In other words, a passivation layer 130 may be formed on the plurality of layers 110, including portions along the tops of the first and second sidewalls 121, 122 of each of the plurality of contact trenches 118. In an exemplary embodiment, the ions 132 may impinge on the third layer 113 and the fourth layer 114 without impinging on the second layer 112 or the first layer 111. As a result, the passivation layer 130 may be formed on the third and fourth layers 113, 114 without being formed on the first or second layers 111, 112. In some embodiments, the passivation layer 130 may be formed along the second layer 112 and the first layer 111, as well as the third layer 113 and the fourth layer 114, but not along the trench bottom 123. In some embodiments, the passivation layer 130 may be formed partially along the second layer 112 within the plurality of contact trenches 118.

[0018]

[0022] In various embodiments, the ions 132 may be oxygen and / or nitrogen ions delivered at an angle of approximately 25-65 degrees. It will be appreciated that in other embodiments, the implant angle may vary, for example, within + / - 10 degrees. The ions may be implanted into the plurality of contact trenches 118 at an angle selected to prevent the ions from impinging on the second layer 112, the first layer 111, and the trench bottom 123.

[0019]

[0023] It should be understood that the degree to which the physical and / or chemical composition of the first and second sidewalls 121, 122 of each of the plurality of contact trenches 118 is modified can be determined by one or more variables, including, but not limited to, the species of ions selected, the material properties of the surface to be modified, the rotational orientation of the device 100, the temperature at which the ions are implanted, the concentration and / or dose of the ions implanted, and the amount of energy at which the ions are implanted into the surface to be modified. Additionally, the device 100 can be rotated during or between successive implantations to impinge on each of the first and second sidewalls 121, 122 of the device 100. For example, the device 100 can be rotated 45°, 90°, 180°, etc. between implantation processes. Embodiments herein are not limited to this situation.

[0020]

[0024] As shown in FIG. 4 , a fill material 142 may then be formed within the plurality of contact trenches 118 following the formation of the passivation layer 130. Specifically, polysilicon may be epitaxially grown within each of the plurality of contact trenches 118, including over each of the first layer 111, the second layer 112, the third layer 113, and the fourth layer 114. As shown, the fill material 142 may be in direct contact with one or more of the device structures 106. Generally, the Si growth rate is higher on the Si surface than on the SiN surface, resulting in intermediate pinch-off by the poly, which creates gaps or voids within the poly fill material. However, in the present disclosure, surface modification from the ions 132 along the top of the plurality of contact trenches 118 (e.g., along the third and fourth layers 113, 114) reduces or slows the growth rate of the fill material 142 along the third layer 113. As a result, the filler material 142 typically grows at the same or similar rate along both the second and third layers 112, 113 of the layers 110. As shown in Figure 5, after the filler material 142 has filled the entire plurality of contact trenches 118 (and then planarized), there are no voids or seams within the filler material 142.

[0021]

[0025] 6 is a schematic diagram of a processing apparatus 200 useful for carrying out the processes described herein. One example of a beamline ion implantation processing apparatus is the Varian VIISTA® Trident, commercially available from the applicant. The processing apparatus 200 may include an ion source 201 for generating ions. For example, the ion source 201 may provide ion implantation, such as the implantation of ions 132 shown in FIG. 3. The ion source 201 may also provide ion etching, such as the etching used to form the plurality of contact trenches 118.

[0022]

[0026] The processing apparatus 200 may also include a series of beamline components. Examples of beamline components may include an extraction electrode 203, a magnetic mass analyzer 211, multiple lenses 213, and a beam collimator 217. The processing apparatus 200 may also include a platen 219 for supporting a substrate 202 to be processed. The substrate 20 may be the same as the substrate 102 described above. The substrate 202 may be moved (e.g., translated, rotated, tilted, etc.) in one or more dimensions by a component sometimes referred to as a "plate" (not shown). It is also contemplated that the processing apparatus 200 may be configured to perform a heated implantation process to improve control of the implantation characteristics, such as ion trajectories and implantation energies, utilized to dope the substrate.

[0023]

[0027] During operation, ions of a desired species, e.g., dopant ions, are generated and extracted from the ion source 201. The extracted ions 235 then travel in a beam-like manner along the beamline components and may be implanted into the substrate 202. Similar to a series of optical lenses steering a beam of light, the beamline components steer the extracted ions 235 along the ion beam. In this manner, the extracted ions 235 are steered by the beamline components and directed toward the substrate 202. It is envisioned that the apparatus 200 may provide improved mass selection to reduce the likelihood of implanting undesired ions (impurities) into the substrate 202 while implanting desired ions.

[0024]

[0028] In some embodiments, the processing device 200 can be controlled by a processor-based system controller, such as the controller 230. For example, the controller 230 can be configured to control beamline components and processing parameters associated with a beamline ion implantation process. The controller 230 can include a programmable central processing unit (CPU) 232 operable with a memory 234 and mass storage devices, such as power supplies, clocks, cache, and input / output (I / O) circuitry, an input control unit, and a display unit (not shown), coupled to various components of the processing device 200 to facilitate control of substrate processing. The controller 230 also includes hardware for monitoring substrate processing through sensors within the processing device 200, including sensors that monitor the position of the substrate and sensors configured to receive feedback from and control heating devices coupled to the processing device 200. Other sensors measuring system parameters, such as substrate temperature, can also provide information to the controller 230.

[0025]

[0029] To facilitate control of the processing device 200 described above, the CPU 232 may be any form of general-purpose computer processor that can be used in an industrial environment, such as a programmable logic controller (PLC) for controlling the various chambers and sub-processors. The memory 234 is coupled to the CPU 232 and may be non-transitory and comprise one or more of readily available memory, such as random access memory (RAM), read-only memory (ROM), a floppy disk drive, a hard disk, or any other form of local or remote digital storage. Support circuits 236 may be coupled to the CPU 232 to support the processor in a conventional manner. Injection and other processes are typically stored in the memory 234, typically as software routines. The software routines may be stored and / or executed by a second CPU (not shown) located remotely from the hardware controlled by the CPU 232.

[0026]

[0030] Memory 234 is in the form of a computer-readable storage medium containing instructions that, when executed by CPU 232, facilitate operation of device 200. The instructions in memory 234 are in the form of a program product, such as a program, that implements the methods of the present disclosure. The program code may be in any one of several different programming languages. In one example, the present disclosure may be implemented as a program product stored on a computer-readable storage medium for use with a computer system. One or more programs in the program product define functions of embodiments (including the methods described herein). Exemplary computer-readable storage media include, but are not limited to, (i) non-writable storage media in which information is permanently stored (e.g., a read-only memory device internal to a computer, such as a CD-ROM disk readable by a CD-ROM drive, flash memory, a ROM chip, or any type of solid-state nonvolatile semiconductor memory), and (ii) writable storage media in which changeable information is stored (e.g., a floppy disk inside a diskette drive or hard disk drive, or any type of solid-state random-access semiconductor memory). Such computer-readable storage media, when carrying computer-readable instructions that direct the functions of the methods described herein, are embodiments of the present disclosure.

[0027]

[0031] It should be understood that the various layers, structures, and regions shown in the accompanying drawings are schematic representations. For ease of explanation, one or more layers, structures, and regions of the type commonly used to form semiconductor devices or structures may not be explicitly shown in the given drawings. This does not mean that any layer, structure, and / or region not explicitly shown is omitted from the actual semiconductor structure.

[0028]

[0032] In various embodiments, a design tool can be provided, which can be configured to generate a dataset used to pattern a semiconductor layer of device 100, as described herein, for example. For example, the dataset can generate a photomask used during a lithography process to pattern a layer for a structure described herein. Such a design tool can include a collection of one or more modules and can be comprised of hardware, software, or a combination thereof. Thus, for example, a tool can be a collection of one or more software modules, hardware modules, software / hardware modules, or any combination or permutation thereof. As another example, a tool can be a computing device or other apparatus that executes software or is implemented in hardware.

[0029]

[0033] As used herein, modules may be implemented using any form of hardware, software, or a combination thereof. For example, one or more processors, controllers, ASICs, PLAs, logic components, software routines, or other mechanisms may be implemented to constitute a module. In implementation, the various modules described herein may be implemented as separate modules, or the described functions and features may be shared, partially or entirely, among one or more. In other words, as will be apparent to one of ordinary skill in the art upon reading this detailed description, the various features and functionality described herein may be implemented in any application and in various combinations and permutations in one or more separate or shared modules. While various features or elements of functionality may be individually described or claimed as separate modules, one of ordinary skill in the art will understand that these features and functionality may be shared among one or more shared software and hardware elements.

[0030]

[0034] For convenience and clarity, terms such as "top," "bottom," "upper," "lower," "vertical," "horizontal," "lateral," and "longitudinal" will be understood to describe the relative placement and orientation of components and their constituent parts in the drawings. The terminology includes the words specifically mentioned, derivatives thereof, and words of similar import.

[0031]

[0035] As used herein, elements or operations referred to in the singular should be understood to include the plural unless the exclusion of the plural elements or operations is expressly stated. Furthermore, references to "one embodiment" of the present disclosure are not intended to be limiting. Additional embodiments may also include the recited features.

[0032]

[0036] Additionally, the terms "substantial" or "substantially," as well as "approximately" or "generally," can be used interchangeably in some embodiments and can be described using any relative measure accepted by those of ordinary skill in the art. For example, these terms serve as a comparison to a reference parameter and indicate a tolerance that can provide the intended function. Without limitation, deviation from the reference parameter can be, for example, less than 1%, less than 3%, less than 5%, less than 10%, less than 15%, less than 20%, etc.

[0033]

[0037] Furthermore, when an element, such as a layer, region, or substrate, is referred to as being formed, deposited, or disposed on or above another element, those skilled in the art will understand that the element may be directly on the other element, or intervening elements may be present. In contrast, when an element is referred to as being "directly on" or "directly above" another element, there are no intervening elements present.

[0034]

[0038] As used herein, "deposit" and / or "deposited" may include any now known or later developed technique suitable for the material being deposited, including, for example, but not limited to, chemical vapor deposition (CVD), low-pressure CVD (LPCVD), and plasma-enhanced CVD (PECVD). Additional techniques may include semi-atmospheric CVD (SACVD) and high-density plasma CVD (HDPCVD), rapid thermal CVD (RTCVD), ultra-high vacuum CVD (UHVCVD), limited reaction processing CVD (LRPCVD), metal-organic CVD (MOCVD), and sputtering deposition. Additional techniques may include ion beam deposition, electron beam deposition, laser-assisted deposition, thermal oxidation, thermal nitridation, spin-on processes, physical vapor deposition (PVD), atomic layer deposition (ALD), chemical oxidation, molecular beam epitaxy (MBE), plating, and evaporation.

[0035]

[0039] While specific embodiments of the present disclosure have been described herein, the present disclosure is not limited thereto, as the present specification is to be interpreted as broadly as the art will permit. Therefore, the above description should not be construed as limiting. Rather, the above description is merely an exemplification of specific embodiments. Those skilled in the art will envision other modifications within the scope and spirit of the claims.

Claims

1. providing a plurality of trenches in a substrate, the plurality of trenches defining a plurality of device structures; depositing a plurality of layers over the plurality of device structures, the plurality of layers including a first layer over the plurality of device structures, a second layer over the first layer, and a third layer over the second layer; forming a plurality of contact trenches through the plurality of layers to expose one or more of the plurality of device structures; directing ions into sidewalls of the plurality of contact trenches at a non-zero angle relative to a normal extending from top surfaces of the plurality of layers, wherein the ions impinge on the third layer without impinging on the second layer; forming a fill material within the plurality of contact trenches after directing the ions into the sidewalls of the plurality of contact trenches; A method comprising:

2. forming the filler material over the top surfaces of the plurality of layers; planarizing the filler; and The method of claim 1 further comprising:

3. 10. The method of claim 1, further comprising forming a fourth layer on the third layer of the plurality of layers, the fourth layer and the first layer being the same material.

4. 4. The method of claim 3, further comprising directing ions into the sidewalls of the plurality of contact trenches to form a passivation layer along the sidewalls of the plurality of contact trenches, the passivation layer being formed on the fourth layer and the third layer without being formed on the second layer or the first layer, and the passivation layer retarding growth of the fill material along the third layer.

5. 4. The method of claim 3, wherein the first layer is an oxide material, the second layer is a silicon nitride layer, the third layer is a polysilicon layer, and the fourth layer is the oxide material.

6. The method of claim 1 , wherein the filler material is formed directly on the one or more of the plurality of device structures.

7. 2. The method of claim 1, wherein forming the fill material within the plurality of contact trenches comprises epitaxially growing polysilicon within the plurality of contact trenches.

8. 1. A method of forming a DRAM device, comprising: forming a source trench isolation (STI) material over a plurality of trenches in a substrate, the plurality of trenches defining a plurality of device structures; depositing a plurality of layers over the plurality of device structures, the plurality of layers including a first layer over the STI material, a second layer over the first layer, and a third layer over the second layer, the second layer and the third layer being different materials; forming a plurality of contact trenches through the plurality of layers to expose one or more of the plurality of device structures; directing ions into sidewalls of the plurality of contact trenches at a non-zero angle relative to a normal extending from top surfaces of the plurality of layers, wherein the ions impinge on the third layer without impinging on the second layer; forming a fill material within the plurality of contact trenches after directing the ions into the sidewalls of the plurality of contact trenches; A method comprising:

9. forming the filler material on the top surfaces of the plurality of layers; planarizing the filler material to the top surfaces of the plurality of layers; The method of claim 8 further comprising:

10. 9. The method of claim 8, further comprising forming a fourth layer on the third layer of the plurality of layers, the fourth layer and the first layer being the same material.

11. 11. The method of claim 10, wherein directing ions into the sidewalls of the plurality of contact trenches results in a passivation layer formed along the sidewalls of the plurality of trenches, the passivation layer being formed on the fourth layer and the third layer without being formed on the second or third layers, and the passivation layer retarding growth of the fill material along the third layer.

12. 11. The method of claim 10, wherein the first layer is an oxide material, the second layer is a silicon nitride layer, the third layer is a polysilicon layer, and the fourth layer is the oxide material.

13. The method of claim 8 , wherein the filler material is formed directly on the one or more of the plurality of device structures.

14. 9. The method of claim 8, wherein forming the fill material within the plurality of contact trenches comprises epitaxially growing polysilicon within the plurality of contact trenches.

15. 1. A method of forming a bit line contact for a DRAM device, comprising: providing a plurality of trenches in a substrate, the plurality of trenches defining a plurality of device structures; depositing a plurality of layers over the plurality of device structures, the plurality of layers including a first layer over the plurality of device structures, a second layer over the first layer, and a third layer over the second layer, the second layer and the third layer being different materials; forming a plurality of contact trenches through the plurality of layers to expose one or more of the plurality of device structures; forming a passivation layer along the sidewalls of the plurality of contact trenches by directing ions into the sidewalls of the plurality of contact trenches at a non-zero angle relative to a normal extending from top surfaces of the plurality of layers, wherein the ions impinge on the third layer without impinging on the second layer; forming a fill material within the plurality of contact trenches after directing the ions into the sidewalls of the plurality of contact trenches; A method comprising:

16. 16. The method of claim 15, further comprising forming a fourth layer on the third layer of the plurality of layers, wherein the fourth layer and the first layer are the same material.

17. 17. The method of claim 16, wherein the passivation layer is formed only on the fourth layer and the third layer, the passivation layer retarding growth of the fill material along the third layer.

18. 17. The method of claim 16, wherein the first layer is an oxide material, the second layer is a silicon nitride layer, the third layer is a polysilicon layer, and the fourth layer is the oxide material.

19. The method of claim 15 , wherein the filler material is formed directly on the one or more of the plurality of device structures.

20. 16. The method of claim 15, wherein forming the fill material within the plurality of contact trenches comprises epitaxially growing polysilicon within the plurality of contact trenches, and wherein delaying epitaxial growth of the polysilicon along the third layer relative to growth along the second layer prevents formation of voids within the fill material after the fill material reaches the top surfaces of the plurality of layers.

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