Memory storage format to support machine learning acceleration

Abstract

A processor-implemented method for a memory storage format for accelerating machine learning (ML) on a computing device is described. The method includes receiving an image in a first layer storage format of a neural network. The method also includes assigning addresses to image pixels of each of three channels of the first layer storage format for accessing the image pixels in the blocked ML storage acceleration format. The method further includes storing the image pixels in the blocked ML storage acceleration format according to the assigned addresses of the image pixels. The method also includes accelerating inference video processing of the image according to the assigned addresses for the image pixels corresponding to the blocked ML storage acceleration format.

Description

[Technical Field]

[0001] (CROSS-REFERENCE TO RELATED APPLICATIONS) This application claims priority to U.S. Patent Application Publication No. 17 / 946,753, filed September 16, 2022, entitled "MEMORY STORAGE FORMAT FOR SUPPORTING MACHINE LEARNING ACCELERATION," the disclosure of which is expressly incorporated herein by reference in its entirety.

[0002] Certain aspects of the present disclosure relate generally to artificial neural networks, and more particularly to memory storage formats to support machine learning (ML) acceleration. [Background technology]

[0003] An artificial neural network, which may include a group of interconnected artificial neurons, may be a computing device or may represent a method implemented by a computing device. Artificial neural networks may have a structure and / or function comparable to biological neural networks. However, artificial neural networks may provide a useful computational technique for certain applications where traditional computational techniques are cumbersome, cumbersome, impractical, or insufficient. Because artificial neural networks can infer function from observations, such networks may be useful in applications where the complexity of the task and / or data makes function design cumbersome using traditional techniques.

[0004] In computing, hardware acceleration is the use of computer hardware to perform some functions more efficiently than is possible in software running on a more general-purpose central processing unit (CPU). Hardware that performs acceleration is sometimes called a hardware accelerator. Machine learning accelerators can improve the performance of artificial neural networks. In practice, the first layer of many computer vision machine learning (ML) networks is potentially limited to three channels (e.g., red, green, and blue (RGB)). Unfortunately, provision for processing the first layer of these computer vision ML networks results in a large allocation of tightly coupled memory (TCM) due to the limited channel depth of this first layer caused by inefficient allocation of memory. A memory storage format to support machine learning (ML) acceleration in computer vision networks is desired. Summary of the Invention

[0005] A processor-implemented method for a memory storage format for accelerating machine learning (ML) on a computing device is described. The method includes receiving an image in a first layer storage format of a neural network. The method also includes assigning addresses to image pixels of each of three channels of the first layer storage format for accessing the image pixels in the blocked ML storage acceleration format. The method further includes storing the image pixels in the blocked ML storage acceleration format according to the assigned addresses of the image pixels. The method also includes accelerating inference video processing of the image according to the assigned addresses for the image pixels corresponding to the blocked ML storage acceleration format.

[0006] A non-transitory computer-readable medium having recorded thereon program code for a memory storage format for accelerating machine learning (ML) on a computing device is described. The program code is executed by a processor of the computing device. The non-transitory computer-readable medium includes program code for receiving an image in a first layer storage format of a neural network. The non-transitory computer-readable medium also includes program code for assigning addresses to image pixels of each of three channels of the first layer storage format to access the image pixels in the blocked ML storage acceleration format. The non-transitory computer-readable medium further includes program code for storing the image pixels in the blocked ML storage acceleration format according to the assigned addresses of the image pixels. The non-transitory computer-readable medium also includes program code for accelerating inferential video processing of the image according to the assigned addresses for the image pixels corresponding to the blocked ML storage acceleration format.

[0007] A system for machine learning (ML) acceleration architecture is described. The system includes a neural signal processor (NSP) for assigning addresses to image pixels of each of three channels of a storage format of a first layer of a neural network to access the image in a blocked ML storage accelerated format. The NSP is further for storing the image pixels in the blocked ML storage accelerated format according to the assigned addresses. The system also includes an ML accelerator for accelerating inference video processing of the image according to the assigned addresses for the image pixels of the image corresponding to the blocked ML storage accelerated format.

[0008] The foregoing has outlined rather broadly the features and technical advantages of the present disclosure in order that the detailed description that follows may be better understood. Additional features and advantages of the present disclosure are described below. Those skilled in the art will appreciate that this disclosure may readily be utilized as a basis for modifying or designing other structures for carrying out the same purposes of the present disclosure. Those skilled in the art will also realize that such equivalent constructions do not depart from the teachings of the present disclosure as set forth in the appended claims. The novel features believed characteristic of the present disclosure, both as to its organization and method of operation, together with further objects and advantages, will be better understood from the following description when considered in connection with the accompanying figures. It is to be expressly understood, however, that each of the figures is provided for the purpose of illustration and description only and is not intended to define the scope of the present disclosure.

[0009] The features, nature, and advantages of the present disclosure will become more apparent from the detailed description set forth below when taken in conjunction with the drawings in which like reference characters identify correspondingly throughout. [Brief explanation of the drawings]

[0010] [Figure 1] 1 illustrates an exemplary implementation of designing a neural network using a system-on-chip (SoC) that includes a general-purpose processor, according to certain aspects of the present disclosure. [Figure 2A] FIG. 1 illustrates a neural network according to an aspect of the present disclosure. [Figure 2B] FIG. 1 illustrates a neural network according to an aspect of the present disclosure. [Figure 2C] FIG. 1 illustrates a neural network according to an aspect of the present disclosure. [Figure 2D] FIG. 1 illustrates a neural network according to an aspect of the present disclosure. [Figure 3] FIG. 1 is a block diagram illustrating an inference video pre-processing engine configured to output data in a machine learning (ML) storage acceleration format, according to aspects of the present disclosure. [Figure 4]FIG. 4 is a block diagram further illustrating the machine learning (ML) storage acceleration format block of FIG. 3 according to an aspect of the present disclosure. [Figure 5A] FIG. 1 is a block diagram illustrating image partitioning into a machine learning (ML) storage accelerated format, according to aspects of the present disclosure. [Figure 5B] FIG. 1 is a block diagram illustrating image partitioning into a machine learning (ML) storage accelerated format, according to aspects of the present disclosure. [Figure 6A] 1 illustrates various machine learning (ML) storage acceleration formats according to aspects of the present disclosure. [Figure 6B] 1 illustrates various machine learning (ML) storage acceleration formats according to aspects of the present disclosure. [Figure 6C] 1 illustrates various machine learning (ML) storage acceleration formats according to aspects of the present disclosure. [Figure 7] FIG. 1 is a block diagram illustrating a stride 2 machine learning (ML) acceleration format, according to an aspect of the present disclosure. [Figure 8] 1 is a table including a formula for a data packing format to support a machine learning (ML) storage acceleration format, according to an aspect of the present disclosure. [Figure 9A] FIG. 1 illustrates a memory addressing sequence for a machine learning (ML) memory acceleration format, according to an aspect of the present disclosure. [Figure 9B] FIG. 1 illustrates a memory addressing sequence for a machine learning (ML) memory acceleration format, according to an aspect of the present disclosure. [Figure 10] FIG. 1 is a flow diagram illustrating a method for memory storage formatting for accelerating machine learning (ML) on a computing device, according to an aspect of the present disclosure. DETAILED DESCRIPTION OF THE INVENTION

[0011] The detailed description, set forth below with reference to the accompanying drawings, illustrates various configurations and does not represent the only configurations in which the described concepts may be practiced. The detailed description includes specific details intended to provide a thorough understanding of various concepts. Nevertheless, it will be apparent to those skilled in the art that these concepts may be practiced without these specific details. In some instances, well-known structures and components are shown in block diagram form to avoid obscuring such concepts.

[0012] Based on the teachings, those skilled in the art will understand that the scope of the present disclosure is intended to encompass any aspect of the present disclosure, whether implemented independently of or in combination with any other aspect of the present disclosure. For example, an apparatus may be implemented or a method may be practiced using any number of the described aspects. In addition, the scope of the present disclosure is intended to encompass such apparatuses or methods practiced using other structures, functions, or structures and functions in addition to or other than the various aspects of the present disclosure described. It will be understood that any aspect of the present disclosure that is disclosed may be embodied by one or more elements of a claim.

[0013] While particular aspects are described, many variations and permutations of these aspects fall within the scope of the present disclosure. While some benefits and advantages of the preferred aspects are described, the scope of the present disclosure is not limited to particular benefits, applications, or objectives. Rather, aspects of the present disclosure are intended to be broadly applicable to different technologies, system configurations, networks, and protocols, some of which are illustrated by way of example in the figures and the following description of the preferred aspects. The Detailed Description and drawings are merely illustrative of the present disclosure, rather than limiting, the scope of which is defined by the appended claims and their equivalents.

[0014] In computing, hardware acceleration is the use of computer hardware to perform some functions more efficiently than is possible in software running on a more general-purpose central processing unit (CPU). The hardware that performs the acceleration is sometimes called a hardware accelerator. Machine learning accelerators can improve the performance of artificial neural networks.

[0015] Generally, hardware (HW) accelerators are designed for specific corresponding input configurations. As a result, differently configured inputs are unlikely to benefit from the accelerator. Because the input blocks (or what IDF calls "croutons") to many layers contain many channels, some CNN accelerators are designed for input blocks with tens of channels. However, the first layer of a CNN often has inputs with only a small number of channels (e.g., three or four). As a result, the input block to the HW accelerator is padded with zeros based on the first layer input, significantly reducing the processing efficiency of the first layer using the HW accelerator.

[0016] In practice, the first layer of many computer vision machine learning (ML) networks has an input consisting of three channels (e.g., red, green, and blue (RGB)). For example, a tensor may represent the first layer of a computer vision ML network according to the standard NCHW (e.g., batch_size(N), channel(C), height(H), weight(W)) format or the NHWC (e.g., batch_size(N), height(H), weight(W), channel(C)) format, which is fully packed and does not waste any space. In contrast, layers of a computer vision ML network beyond the first layer typically have a larger number of channels (e.g., 32 or more channels).

[0017] ML hardware accelerators expect different data formats. In particular, input tensors encountered in computer vision networks have three channels in the first layer and a significant number of channels (e.g., 32 or more) in subsequent layers. Typically, these ML accelerators are architected to process tensors with multiples of 32 channels. Nevertheless, for tensors with fewer than 32 channels (e.g., a first layer with three channels), the three-channel tensor can be padded with random data to convert it to the expected 32-channel tensor. Because vision networks typically have many layers beyond the first layer, padding the three-channel tensor with random data to convert it to the expected 32-channel tensor is a reasonable tradeoff.

[0018] Unfortunately, storing this type of padded tensor occupies many times the space (e.g., 32 is roughly 10 times larger than 3). As a result, preparation for first-layer processing results in a large allocation of tightly coupled memory (TCM) space due to the wasted channel depth associated with the first layer of a computer vision neural network. This larger allocation of TCM space can result in a 10x expansion of TCM space. Furthermore, high-definition (HD) images provided by computer vision neural networks can be large (e.g., full HD 1920x1080 pixels), which can cause a spill to remote / off-chip / external memory. In particular, if this space expansion is statically allocated and it is the largest user of TCM space, the network weights may be forced into dynamic random access memory (DRAM). Additionally, in the case of video processing, several streams and multiple frames from each stream may be in flight at any one time. As a result, DRAM memory allocation can become problematic if a 10x expansion is performed for each frame of an HD image. Furthermore, if the first layer provisioning is implemented on the host, interconnect traffic (eg, peripheral component interconnect express (PCIe) traffic) can increase by a factor of ten.

[0019] A machine learning (ML) memory acceleration format is desired that reduces wasted allocation of TCM space and DRAM, as well as wasted bandwidth for moving padding and wasted PCIe bandwidth. In particular, a memory storage format is desired to support ML acceleration in computer vision networks. A proposed solution is the packed dense depth data dump (D4) format.

[0020] Some aspects of the present disclosure are directed to an ML memory acceleration format, sometimes referred to as the packed D4 format. This packed D4 format allows for less wasted space for processing the first layer of a computer vision neural network. This packed D4 format is 8 * 64 * It receives 4 input blocks and divides them into 8 * 8 * It can be directly processed by the ML hardware accelerator without the need to convert it to a standard layout by rearranging it into 32 input blocks. In some aspects of the present disclosure, the ML memory acceleration format is, for example, 8 spatial patches (e.g., 8x8 * It supports up to four input channels by packing 32 input blocks (32 input blocks) into one storage block. In these aspects of the disclosure, the video preprocessing unit that prepares raw images for processing by the ML vision-based network provides direct output in an ML storage-accelerated format.

[0021] In some aspects of the present disclosure, the ML memory acceleration format is compatible with cases where the initial layer is a stride-2 convolution using a quarter-order approach. Furthermore, the ML memory acceleration format is also compatible with cases where the initial layer uses either 16-bit floating point (FP16) or quantized 8-bit integer (INT8) precision. The ML memory acceleration format also supports both spatial and channel-major formats of the matrix unit. Furthermore, the ML memory acceleration format may utilize matrix instructions that enable sub-block (e.g., 4-input channel) granularity.

[0022] 1 illustrates an example implementation of a system-on-chip (SoC) 100 that may include a central processing unit (CPU) 102 or a multi-core CPU, such as an artificial intelligence (AI) accelerator, according to certain aspects of the present disclosure. Variables (e.g., neural signals and synaptic weights), system parameters associated with a computational device (e.g., a neural network with weights), delays, frequency bin information, and task information may be stored in memory blocks associated with a neural processing unit (NPU) 130, a memory block associated with the CPU 102, a memory block associated with a graphics processing unit (GPU) 104, a memory block associated with a digital signal processor (DSP) 106, or memory block 118, or may be distributed across multiple blocks. Instructions executed in the CPU 102 may be loaded from a program memory associated with the CPU 102 or from memory block 118.

[0023] One aspect of the present disclosure is directed to an ML memory acceleration format for machine learning accelerators (MLAs) 132 (e.g., artificial intelligence inference accelerators (AIIAs)) of the NPU 130, which may be referred to as a packed dense depth data dump (D4) format. This packed D4 format allows for less wasted space for processing the first layer of a computer vision neural network. This packed D4 format can be processed directly by the MLA 132 without the need to convert it to a standard layout. In some aspects of the present disclosure, the ML memory acceleration format of the MLA 132 supports up to four input channels, for example, by packing eight spatial patches (e.g., 8x8) into one memory storage block.

[0024] SoC 100 may also include a connectivity block 110, which may include fifth generation (5G) new radio (NR) connectivity, fourth generation long-term evolution (4G LTE) connectivity, unlicensed Wi-Fi connectivity, USB connectivity, Bluetooth connectivity, etc., as well as additional processing blocks tailored to specific functions, such as a multimedia processor 112, which may detect and recognize gestures. In one implementation, the NPU is implemented in a CPU, DSP, and / or GPU. SoC 100 may also include a sensor processor 114 for providing sensor image data, image signal processors (ISPs) 116, and / or a navigation module 120, which may include a global positioning system.

[0025] Deep learning architectures may perform object recognition tasks by learning to represent inputs at successively higher levels of abstraction within each layer, thereby building useful feature representations of the input data. In this way, deep learning addresses a major bottleneck of traditional machine learning. Prior to the advent of deep learning, machine learning approaches to object recognition problems may have relied heavily on human-designed features, possibly in combination with shallow classifiers. A shallow classifier may, for example, be a two-class linear classifier that can compare a weighted sum of feature vector components to a threshold to predict which class an input belongs to. Human-designed features may be templates or kernels adapted to a specific problem domain by an engineer with domain expertise. In contrast, deep learning architectures may learn, but through training, to represent features similar to those a human engineer could design. Furthermore, deep networks may learn to represent and recognize new types of features that humans may not have considered.

[0026] Deep learning architectures may learn a hierarchy of features. When presented with visual data, for example, a first layer may learn to recognize relatively simple features, such as edges, in the input stream. In another example, when presented with auditory data, the first layer may learn to recognize spectral power at specific frequencies. A second layer, taking the output of the first layer as input, may learn to recognize combinations of features, such as simple shapes in the case of visual data, or combinations of sounds in the case of auditory data. For example, higher layers may learn to represent complex shapes in visual data or words in auditory data. Even higher layers may learn to recognize common visual objects or spoken phrases.

[0027] Deep learning architectures can perform particularly well when applied to problems that have a natural hierarchical structure. For example, classification of electric vehicles can benefit from first learning to recognize wheels, windshields, and other features. These features may be combined in different ways in higher layers to recognize cars, trucks, and airplanes.

[0028] Neural networks may be designed with various connectivity patterns. In feedforward networks, each neuron in a given layer communicates with neurons in a higher layer, and information is passed from lower layers to higher layers. As described above, hierarchical representations may be constructed within successive layers of a feedforward network. Neural networks may also have recurrent or feedback (also called top-down) connections. In recurrent connections, the output from a neuron in a given layer may be transmitted to another neuron in the same layer. Recurrent architectures may be useful in recognizing patterns across two or more of the input data chunks delivered to the neural network in sequence. Connections from neurons in a given layer to neurons in a lower layer are called feedback (or top-down) connections. Networks with many feedback connections may be useful when recognizing high-level concepts can help distinguish certain low-level features of the input.

[0029] The connections between layers of a neural network may be fully connected or locally connected. FIG. 2A shows an example of a fully connected neural network 202. In a fully connected neural network 202, a neuron in a first layer may transmit its output to every neuron in a second layer, resulting in each neuron in the second layer receiving input from every neuron in the first layer. FIG. 2B shows an example of a locally connected neural network 204. In a locally connected neural network 204, a neuron in a first layer may be connected to a limited number of neurons in the second layer. More generally, the locally connected layers of a locally connected neural network 204 may be configured such that each neuron in a layer has the same or similar connectivity pattern but may have different values ​​(e.g., 210, 212, 214, and 216). Because higher layer neurons in a given region may receive inputs that, through training, are tuned to the properties of a constrained subset of all inputs to the network, the connectivity patterns of local connections may give rise to spatially distinct receptive fields within the higher layers.

[0030] An example of a locally connected neural network is a convolutional neural network. Figure 2C shows an example of a convolutional neural network 206. The convolutional neural network 206 may be configured such that the connection strengths associated with the inputs for each neuron in the second layer are shared (e.g., 208). Convolutional neural networks may be suitable for problems in which the spatial location of the inputs is meaningful.

[0031] One type of convolutional neural network is the deep convolutional network (DCN). Figure 2D shows a detailed example of a DCN 200 designed to recognize visual features from images 226 input from an image capture device 230, such as an in-car camera. The DCN 200 in this example may be trained to identify traffic signs and numbers printed on traffic signs. Of course, the DCN 200 may also be trained for other tasks, such as identifying lane markings or traffic signals.

[0032] The DCN 200 may be trained using supervised learning. During training, the DCN 200 may be presented with an image, such as a speed limit sign image 226, and then a forward pass may be computed to generate the output 222. The DCN 200 may include a feature extraction section and a classification section. Upon receiving the image 226, the convolutional layer 232 may apply a convolutional kernel (not shown) to the image 226 to generate the first set of feature maps 218. As an example, the convolutional kernel for the convolutional layer 232 may be a 5×5 kernel that generates 28×28 feature maps. In this example, four different convolutional kernels were applied to the image 226 in the convolutional layer 232, so four different feature maps are generated in the first set of feature maps 218. A convolutional kernel may also be referred to as a filter or a convolutional filter.

[0033] The first set of feature maps 218 may be subsampled by a max pooling layer (not shown) to generate a second set of feature maps 220. The max pooling layer reduces the size of the first set of feature maps 218. That is, the size of the second set of feature maps 220, such as 14×14, is smaller than the size of the first set of feature maps 218, such as 28×28. The reduced size provides similar information to subsequent layers while reducing memory consumption. The second set of feature maps 220 may be further convolved through one or more subsequent convolutional layers (not shown) to generate one or more subsequent sets of feature maps (not shown).

[0034] 2D , the second set of feature maps 220 are convolved to generate a first feature vector 224. Furthermore, the first feature vector 224 is further convolved to generate a second feature vector 228. Each feature in the second feature vector 228 may include a number corresponding to a possible feature of the image 226, such as "sign," "60," and "100." A softmax function (not shown) may convert the numbers in the second feature vector 228 into probabilities. Thus, the output 222 of the DCN 200 is the probability that the image 226 contains one or more features.

[0035] In this example, the probabilities in output 222 for "sign" and "60" are higher than the probabilities of other of the outputs 222, such as "30," "40," "50," "70," "80," "90," and "100." Prior to training, the outputs 222 generated by DCN 200 may be inaccurate. Therefore, an error may be calculated between the outputs 222 and a target output. The target output is the ground truth of image 226 (e.g., "sign" and "60"). The weights of DCN 200 may then be adjusted to more closely align the outputs 222 of DCN 200 with the target output.

[0036] FIG. 3 is a block diagram illustrating an inference video pre-processing engine configured to output data in a machine learning (ML) storage-accelerated format, according to an embodiment of the present disclosure. The inference video pre-processing (VPP) engine 300 includes a data unpacker 330 that unpacks video data from a bus read block 320 in response to a command 310. The bus read block 320 may read video data from a video subsystem (VideoSS) network-on-chip (NoC) 302. In this configuration, the video data is provided to transformation / multidimensional scaling / cropping logic 340. The transformation / multidimensional scaling / cropping logic 340 may perform pre-processing / post-processing on the decoded image or video stream. The transformation / multidimensional scaling / cropping logic 340 outputs red (R) pixels 342, green (G) pixels 344, blue (B) pixels 346, and RGB channels 348.

[0037] The inference VPP engine 300 may process the first layer of a computer vision ML network. In practice, the first layer of many computer vision ML networks is limited to three channels (e.g., red, green, and blue (RGB)). In practice, tensors may represent the first layer of a computer vision ML network according to the standard NCHW (e.g., batch_size(N), channel(C), height(H), weight(W)) format or the NHWC (e.g., batch_size(N), height(H), weight(W), channel(C)) format, which is fully packed and does not waste any space. In contrast, layers of a computer vision ML network beyond the first layer typically have a larger number of channels (e.g., 32 or more channels). Unfortunately, ML hardware accelerators expect a different data format. In these aspects of the present disclosure, the R pixels 342, G pixels 344, and B pixels 346 are processed by the ML memory acceleration format block 400, which outputs pixel data in the ML memory acceleration format to the bus write block 350, which writes the formatted data to the VideoSS NoC 302.

[0038]

[0033] Figure 4 is a block diagram further illustrating the machine learning (ML) memory acceleration format block 400 of Figure 3, in accordance with an embodiment of the present disclosure. As shown in Figure 4, the ML memory acceleration format block 400 includes a pixel input interface 410 for receiving, for example, R pixels 342, G pixels 344, and B pixels 346 from the transform / multidimensional scaling / cropping logic 340 of Figure 3. In operation, each RGB channel from the R pixels 342, G pixels 344, and B pixels 346 transmits four pixels per clock (PPC). The ML memory acceleration format block 400 also includes a pixel input demultiplexer (DeMux) and line buffer 420 coupled to the pixel input interface 410. In this configuration, pixel input DeMux and line buffer 420 demultiplexes two by two (2×2) RGB pixels, which are sorted and simultaneously stored in transaction buffers 432, 434, 436, and 438 of a first transaction buffer bank 430. In stride 2 mode, the first two lines are stored in line buffer 420. For the next two lines, incoming pixels and pixels from line buffer 420 are transferred to transaction buffers such as transaction buffers 442, 444, 446, and 448 of a second transaction buffer bank 440.

[0039] In some aspects of the present disclosure, each of the transaction buffers (e.g., 432, 434, 436, 438, 442, 444, 446, and 448) is 8 bits wide and can hold a full 256 (256) byte transaction. In operation, the transaction selector 450 selects a transaction for writing from one of the transaction buffers (e.g., 432, 434, 436, 438, 442, 444, 446, and 448). For example, the transaction selector 450 selects a transaction based on the availability of transaction data in one of the transaction buffers (e.g., buffer full) when the transaction is selected for writing. In response to the transaction selector 450, the transaction output multiplexer (Mux) 460 transfers the transaction data from the selected transaction buffer (e.g., 432, 434, 436, 438, 442, 444, 446, and 448) to the write interface 470. Additionally, a transaction (Txn) address generator 480 generates an address for the write transaction, which is substituted by an output multiplexer 490 at the NoC address interface 492 and at the output of the write interface 470 at the NoC data interface 472 .

[0040] Some aspects of the first transaction buffer bank 430 and the second transaction buffer bank 440 operate in ping-pong mode. For example, the first transaction buffer bank 430 is filling with incoming pixels while the second transaction buffer bank 440 is draining to the write interface 470. Similarly, the first transaction buffer bank 430 is filling with incoming pixels while the second transaction buffer bank 440 is draining to the write interface 470. Each of the line buffers 420 can hold 4096 pixels (e.g., a full image line width) before filling the first transaction buffer bank 430 and / or the second transaction buffer bank 440. In stride 2 mode, two lines per RGB channel (e.g., six lines total) for R pixels 342, G pixels 344, and B pixels 346 are stored in the line buffers 420.

[0041] In the case of spatial major stride 2 mode, the first two lines are stored in line buffer 420. For the next two lines, incoming pixels (e.g., R pixel 342, G pixel 344, and B pixel 346) as well as pixels from line buffer 420 are stored in transaction buffers (e.g., 432, 434, 436, 438, 442, 444, 446, and 448). This sequence of operations is repeated every four lines. In these aspects of the disclosure, ML memory acceleration format block 400 converts the first layer of neural network data into the ML memory acceleration format, for example, as shown in Figures 5A and 5B.

[0042] 5A and 5B are block diagrams illustrating image partitioning into a machine learning (ML) memory acceleration format according to an embodiment of the present disclosure. As shown in FIG. 5A, an image 500 having an image height 510 and an image width 520 is partitioned into stripes 550 (550-0, 550-1, 550-2, ..., 550-17). In this example, the image 500 is partitioned into stripes having a fixed size, which varies according to the memory access stride size (e.g., for stride 1 and for stride 2). For example, a stripe size of 64x8 is used for stride 1, and a stripe size of 128x16 is used for stride 2. In this example, the stripe order is in a raster scan format (e.g., left to right and top to bottom).

[0043] FIG. 5B shows that one of the stripes 550, having a stripe height 552 and a stripe width 570, is divided into blocks 560 (560-0, 560-1, 560-2, ..., 560-7). In this example, the stripe height 552 has a stripe size of 64x8 for stride 1, such that the stripe height 552 is 8 pixels and the stripe width 570 is 64 pixels. Block order is from left to right. In these aspects of the disclosure, the stripe 550 is divided into blocks 560 having a block size of 8x8 for stride 1. Alternatively, for stride 2, the block size is 16x16. Based on the block size of 8x8 for stride 1, the stripe 550 has eight blocks (e.g., block 0 560-0, block 1 560-1, block 2 560-2, ..., block 7 560-7).

[0044] In practice, machine learning hardware accelerators (e.g., MLA 132) and neural signal processors (NSPs) can be configured to operate according to a blocked memory storage format. As shown in FIG. 5B, block 560 may have a depth of four, corresponding to the first layer of many computer vision neural networks, which are generally limited to three channels (e.g., red, green, and blue (RGB)). This machine learning (ML) storage acceleration format reduces wasted space for processing the first layer of a computer vision neural network. In particular, this ML storage acceleration format can be directly processed by hardware accelerators and NSPs without the need to convert to a standard layout. In some embodiments of the present disclosure, the ML storage acceleration format supports up to four input channels, for example, by packing eight spatial patches (e.g., 8×8) into one storage block (e.g., block 0 560-0, block 1 560-1, block 2 560-2, ..., block 7 560-7). In these aspects of the present disclosure, the video preprocessing unit that prepares the stripes 550 for processing by the vision-based neural network directly provides output in an ML memory-accelerated format, for example, as shown in Figures 6A-6C.

[0045] 6A-6C illustrate various machine learning (ML) memory acceleration formats according to embodiments of the present disclosure. As shown in FIGS. 6A-6C, the ML memory acceleration format is described as supporting two ML memory acceleration formats that can vary according to the memory stride and desired precision according to embodiments of the present disclosure. For example, for 8-bit integer (INT8) precision, each stripe represents data with a spatial size of 64 (e.g., 8×8) and a channel depth of 32 (=2K bytes), as shown in FIG. 5B. For 16-bit floating-point (FP16) precision, each stripe represents data with a spatial size of 32 (e.g., 8×4) and a channel depth of 32 (=2K bytes). In these examples, each block contains pixels for each channel (e.g., RGB channels) in the image. Based on the spatial / channel major memory acceleration format, pixel addresses are laid out on the spatial axis or the channel axis.

[0046] FIG. 6A is a block diagram illustrating a stripe 600 in a first storage acceleration format according to an embodiment of the present disclosure. FIG. 6A illustrates a spatial major storage acceleration formation according to an embodiment of the present disclosure. In this example, a red channel 612, a green channel 614, and a blue channel 616 are shown for a first block 610 (block 0) of the stripe 600. In this example, the stripe 600 includes additional memory blocks (e.g., block 0 610, block 1 620, block 2 630, ..., block 7 640). In accordance with the spatial major storage acceleration format, the pixels of the first block 610 are arranged in contiguous 2x2 spatial patches (e.g., for 8-bit integers (INT8)) along the red channel 612, green channel 614, and blue channel 616 of the first block 610. These 2x2 spatial patches then step through 32 channels of the stripe 600, and then through the remaining rows and columns, as shown in FIG. 6B.

[0047] FIG. 6B is a diagram further illustrating a stripe 600 in a spatial major memory acceleration format, according to an embodiment of the present disclosure. In this example, red channel 622, green channel 624, and blue channel 626 are shown for the next block 620 (block 1) of stripe 600. Additionally, red channel 632, green channel 634, and blue channel 636 are shown for the final block 640 (block 7) of stripe 600 among the memory blocks (e.g., block 0 610, block 1 620, ..., block 7 640). In accordance with the spatial major memory acceleration format, the pixels of the next block 620 and the final block 640 continue arranging pixels in successive 2x2 spatial patches along the red, green, and blue channels of the next block 620 and the final block 640. These 2x2 spatial patches then proceed for the remaining rows and columns. In some embodiments of the present disclosure, pixels are laid out in 2x2 spatial regions and then in channel regions for the remaining blocks. In this example, each of the two pixel rows in stripe 600 covers 512 bytes and can be written to memory in two consecutive write transactions.

[0048] FIG. 6C is a diagram of a second storage acceleration format according to an embodiment of the present disclosure. FIG. 6C illustrates a channel major storage acceleration format 650 according to an embodiment of the present disclosure. In this example, the 32 channels of memory blocks (e.g., block 0610, block 1620, ..., block 7640) for each "pixel" are contiguous in memory, then proceeding row-by-row and then column-by-column. The spatial major storage acceleration format and the channel major storage acceleration format enable accelerated pixel processing by a matrix unit configured to process N input channels per cycle (e.g., N≦32), where N may be equal to four (N=4). In these examples, each of the memory blocks (e.g., block 0610, block 1620, ..., block 7640) contains pixels for each channel (e.g., RGB channels) in the image. Based on the spatial / channel major storage acceleration format, pixel addresses are laid out in the spatial axis or the channel axis. In some embodiments of the present disclosure, pixels are laid out in the channel domain and then in the spatial domain for the remaining memory blocks. In this example, each row in stripe 600 covers 256 bytes and can be written to memory in one write transaction.

[0049] FIG. 7 is a block diagram illustrating a stride 2 machine learning (ML) acceleration format 700 according to an embodiment of the present disclosure. In the stride 2 ML memory acceleration format 700, the pixels in each 2×2 microblock 710 of a block 720 (e.g., 16×16) are divided into four pixel planes 730 (e.g., (8×8)×4). In this example, the four pixel planes 730 include a first pixel plane 732, a second pixel plane 734, a third pixel plane 736, and a fourth pixel plane 738. The pixel planes 730 are written to separate sections in memory. In this example, the memory addresses of the 2×2 microblocks 710 (e.g., @, C+@, 2C+@, 3C+@) correspond to the channel (C) numbers of the strides shown in FIGS. 6A-6C .

[0050]

number

[0051] FIG. 8 shows a table including formulas for data packing formats to support machine learning (ML) memory acceleration formats according to embodiments of the present disclosure. In this example, table 800 provides formulas for calculating data packing formats for the spatial major ML acceleration format and the channel major memory acceleration format shown in FIGS. 6A-6C. The formulas are provided for 8-bit integer (INT8) precision and 16-bit floating-point (FP16) precision for stride 1 and stride 2. Note that the channel major ML memory acceleration format may not be supported for stride 2 with FP16 precision. The formulas provided in table 800 for calculating data packing formats may provide memory address sequencing, for example, as shown in FIGS. 9A and 9B.

[0052] 9A and 9B are diagrams illustrating memory addressing sequences for a machine learning (ML) storage acceleration format according to an embodiment of the present disclosure. FIG. 9A illustrates writing an image 900 in the ML storage acceleration format according to an embodiment of the present disclosure. In this example, data packing according to the ML storage acceleration format writes image data for the image 900 into stripes (e.g., 904, 910, 920, 930, 940, 945) in a raster scan order 902 (e.g., left to right and top to bottom). Additionally, data packing within each of the stripes (e.g., 904, 910, 920, 930, 940, 945) is in a top to bottom order. This process may be implemented by the write interface 470 of the ML storage acceleration format block 400 of FIG. 4. In some embodiments of the present disclosure, the write interface 470 supports both planar and channel interleaved formats.

[0053] FIG. 9B illustrates writing an image 950 in a machine learning (ML) storage acceleration format according to aspects of the present disclosure. In this example, data packing according to the ML storage acceleration format writes image data for image 950 into stripes (e.g., 954, 960, 970, 980, 990, 995), where the number of stripes is directly proportional to the width of image 950. In some aspects of the present disclosure, the ML storage acceleration format generates write transactions for two rows within a stripe (e.g., 954, 960, 970, 980, 990, 995) according to pattern 952, and then proceeds to the next stripe (e.g., 954, 960, 970, 980, 990, 995). This process may also be performed by the write interface 470 of the ML storage acceleration format block 400 of FIG. 4. In some aspects of the present disclosure, the number of simultaneously open memory pages is directly proportional to the width of image 950 and the ML storage acceleration format.

[0054] FIG. 10 is a flow diagram illustrating a method for a memory storage format for accelerating machine learning (ML) on a computing device according to an embodiment of the present disclosure. Method 1000 begins at block 1002, where an image is received in a first layer storage format of a neural network. In practice, the first layer of many computer vision machine learning (ML) networks is limited to three channels (e.g., red, green, and blue (RGB)). For example, a tensor may represent the first layer of a computer vision ML network according to the standard NCHW (e.g., batch_size(N), channel(C), height(H), weight(W)) format or the NHWC (e.g., batch_size(N), height(H), weight(W), channel(C)) format, which is fully packed and does not waste any space. In contrast, layers of a computer vision ML network beyond the first layer typically have a larger number of channels (e.g., 32 or more channels).

[0055] In block 1004, to access image pixels in the blocked ML storage acceleration format, addresses are assigned to image pixels in each of the three channels of the first-tier storage format. For example, as shown in FIG. 5A, image 500 is divided into stripes 550 (550-0, 550-1, 550-2, ..., 550-17) having a fixed size, which varies according to the memory access stride size (e.g., "variable stride size" for stride 1 and stride 2). In FIG. 5B, stripe 550 is divided into blocks 560 (560-0, 560-1, 560-2, ..., 560-7), and stripe height 552 has a size of 64x8 for stride 1, such that stripe height 552 is 8 pixels and stripe width 570 is 64 pixels. As shown in FIGS. 6A-6C, each block of stripe 600 includes pixels of each channel (e.g., RGB channels) in the image. Based on the spatial / channel major memory acceleration format, pixel addresses are laid out on the spatial axis or the channel axis. As shown in Figure 4, a transaction (Txn) address generator 480 generates an address for a write transaction, which is substituted by an output multiplexer 490 at the NoC address interface 492 and at the output of the NoC data interface 472 at the write interface 470.

[0056] In block 1006, the image pixels are stored in a blocked ML storage acceleration format according to the assigned addresses of the image pixels. For example, as shown in FIG. 9A, data packing according to the ML storage acceleration format writes image data of image 900 into stripes (e.g., 904, 910, 920, 930, 940, 945) in raster scan order 902 (e.g., left to right and top to bottom). In addition, data packing within each of the stripes (e.g., 904, 910, 920, 930, 940, 945) is in top to bottom order. As shown in FIG. 9B, the ML storage acceleration format generates write transactions for two rows within a stripe (e.g., 954, 960, 970, 980, 990, 995) according to pattern 952, and then proceeds to the next stripe (e.g., 954, 960, 970, 980, 990, 995).

[0057] At block 1008, accelerated inference video processing of the image is performed according to the assigned addresses for the image pixels of the image corresponding to the blocked ML storage acceleration format. For example, as shown in FIG. 1, the NPU 130 includes a machine learning accelerator (MLA) 132. As shown in FIGS. 3 and 4, the ML storage acceleration format block 400 includes a pixel input interface 410 for receiving, for example, the R pixels 342, the G pixels 344, and the B pixels 346 from the transform / multidimensional scaling / cropping logic 340 of the inference VPP engine 300 of FIG. 3. In some aspects of the present disclosure, the ML storage acceleration format block 400 is configured to output data in a machine learning (ML) storage acceleration format to enable accelerated inference video processing.

[0058] The method 1000 may include dividing the image into stripes according to an image width and an image height. The method 1000 may also include dividing each of the stripes into memory blocks having a memory block size according to a stride size. The method 1000 may further include calculating assigned addresses for laying out the image pixels in the memory blocks, each of which is assigned image pixels for each channel in the image. The method 1000 may also include arranging the image pixels in the memory blocks according to a spatial axis or a channel axis of the memory blocks.

[0059] Method 1000 may also include storing image pixels in memory blocks in the spatial domain and then storing the image pixels in the channel domain. Method 1000 may further include storing a first group of image pixels in a first one of the memory blocks in a first channel of the first memory block. Method 1000 may also include storing a next group of image pixels in the first one of the memory blocks in a second channel of the first memory block. Method 1000 may also include storing a subsequent group of image pixels in the first one of the memory blocks in a third channel of the first memory block. Method 1000 may also include repeating the storing for each of the memory blocks and for each successive group of image pixels, for example, as shown in FIG. 6B .

[0060] Method 1000 may include storing image pixels in the memory blocks in channel regions of the memory blocks and then storing image pixels in spatial regions of the memory blocks. For example, method 1000 may include storing a first image pixel in a first one of the memory blocks in a first channel of the first memory block. Method 1000 may also include storing a next image pixel in a first one of the memory blocks for a second channel of the first memory block. Method 1000 may also further include storing a subsequent image pixel in the first one of the memory blocks in a third channel of the first memory block. Method 1000 may also include repeating the storing of the selected image pixel, the next image pixel, and the subsequent image pixel for each memory block of the memory blocks and for each successive selected, next, and subsequent image pixel, as shown in FIG. 6C , for example.

[0061] In some aspects, method 1000 may be performed by SoC 100 (FIG. 1). That is, each of the elements of method 1000 may be performed by, for example, but not limited to, SoC 100 or one or more processors (e.g., CPU 102 and / or NPU 130) and / or other components included therein.

[0062] Example implementations are described in the following numbered clauses. 1. A processor-implemented method for a memory storage format for accelerating machine learning (ML) on a computing device, comprising: receiving an image in a neural network first layer storage format; assigning addresses to image pixels of each of three channels of the first layer storage format for accessing the image pixels in the blocked ML storage acceleration format; storing the image pixels in a blocked ML storage accelerated format according to the assigned addresses of the image pixels; and accelerating inferential video processing of the image according to assigned addresses for image pixels of the image corresponding to a blocked ML storage acceleration format. 2. Address assignment Dividing the image into a plurality of stripes according to an image width and an image height; Dividing each of the stripes into memory blocks having a memory block size according to a stride size; 10. The method of claim 1, further comprising: calculating assigned addresses for laying out image pixels in memory blocks, wherein each of the image pixels for each channel in the image is assigned to a memory block. 3. The method of clause 1 or 2, wherein storing the image includes arranging the image pixels in the memory block according to a spatial or channel axis of the memory block. 4. Storing image pixels in a memory block in the spatial domain; and then 4. The method of clause 3, further comprising storing the image pixels in the channel region. 5. storing a first group of image pixels in a first one of the memory blocks in a first channel of the first memory block; storing a next group of image pixels in a first one of the memory blocks into a second channel of the first memory block; storing a subsequent group of image pixels in a first one of the memory blocks in a third channel of the first memory block; 5. The method of clause 4, further comprising repeating the storing for each memory block of the memory blocks and for each successive group of image pixels. 6. storing image pixels in a memory block in a channel region of the memory block; and 4. The method of claim 3, further comprising storing the image pixels in a spatial domain in a memory block. 7. storing selected image pixels in a first one of the memory blocks in a first channel of the first memory block; storing a next image pixel in a first one of the memory blocks for a second channel of the first memory block; storing subsequent image pixels in a first one of the memory blocks in a third channel of the first memory block; 7. The method of claim 6, further comprising: for each memory block of the memory blocks, and for each successive selected, next, and subsequent one of the image pixels, repeating the storing of the selected image pixel, the storing of the next image pixel, and the storing of the subsequent image pixel. 8. The method of any of clauses 1 to 7, wherein accelerating the inference video processing includes simultaneously processing each of the three channels of the first layer storage format in a blocked ML storage acceleration format through a matrix unit of a neural signal processor (NSP) of the computing device. 9. The method of any of clauses 1-8, wherein the precision of the first layer storage format of the neural network includes 16-bit floating point (FP16) or quantized 8-bit integer (INT8). 10. A non-transitory computer-readable medium having recorded thereon program code for a memory storage format for accelerating machine learning (ML) on a computing device, the program code being executed by a processor; program code for receiving an image in a neural network first layer storage format; program code for assigning addresses to image pixels in each of the three channels of the first layer storage format for accessing the image pixels in the blocked ML storage acceleration format; program code for storing the image pixels in a blocked ML storage accelerated format according to the assigned addresses of the image pixels; and program code for accelerating inferential video processing of an image according to assigned addresses for image pixels of the image corresponding to a blocked ML storage acceleration format. 11. The program code for address allocation is program code for dividing the image into a plurality of stripes according to an image width and an image height; program code for dividing each of the stripes into memory blocks having a memory block size according to the stride size; and program code for calculating assigned addresses to layout image pixels within memory blocks, wherein each image pixel for each channel in the image is assigned to a memory block. 12. The non-transitory computer-readable medium of clause 9 or 10, wherein the program code for storing an image comprises program code for arranging image pixels in the memory block according to a spatial axis or a channel axis of the memory block. 13. program code for storing image pixels in a memory block in the spatial domain; and 13. The non-transitory computer-readable medium of clause 12, further comprising: program code for storing image pixels in the channel region. 14. program code for storing a first group of image pixels in a first one of the memory blocks in a first channel of the first memory block; program code for storing a next group of image pixels in a first one of the memory blocks into a second channel of the first memory block; program code for storing a subsequent group of image pixels in a first one of the memory blocks into a third channel of the first memory block; and program code for repeating the program code for storing for each memory block of the memory blocks and for each successive group of image pixels. 15. program code for storing image pixels in the memory block in a channel region of the memory block; and and program code for storing image pixels in spatial regions of memory blocks. 16. program code for storing selected image pixels in a first one of the memory blocks in a first channel of the first memory block; program code for storing a next image pixel in a first one of the memory blocks for a second channel of the first memory block; program code for storing subsequent image pixels in a first one of the memory blocks in a third channel of the first memory block; and program code for, for each memory block of the memory blocks, and for each successive selected, next, and subsequent ones of the image pixels, repeating: program code for storing the selected image pixel, program code for storing the next image pixel, and program code for storing the subsequent image pixel. 17. A non-transitory computer-readable medium according to any of clauses 10-16, wherein the program code for accelerating inference video processing includes program code for simultaneously processing each of three channels of a first layer storage format in a blocked ML storage acceleration format through a matrix unit of a neural signal processor (NSP) of a computing device. 18. The non-transitory computer-readable medium of any of clauses 10-17, wherein the precision of the first layer storage format of the neural network includes 16-bit floating point (FP16) or quantized 8-bit integer (INT8). 19. A system for machine learning (ML) acceleration architecture, the system comprising: a neural signal processor (NSP) for assigning addresses to image pixels of each of three channels of a storage format of a first layer of a neural network to access the image pixels in the blocked ML storage accelerated format, and for storing the image pixels in the blocked ML storage accelerated format according to the assigned addresses of the image pixels; an ML accelerator for accelerating inference video processing of an image according to assigned addresses for image pixels of the image corresponding to a blocked ML storage acceleration format. 20. The system of clause 19, wherein the NSP is further for storing the image pixels in the memory block in the spatial domain and then storing the image pixels in the channel domain. 21. The system of clause 19, wherein the NSP is further for storing image pixels in the memory block in a channel region of the memory block and then storing image pixels in a spatial region of the memory block. 22. The system described in any of clauses 19 to 21, wherein the NSP comprises a matrix unit for simultaneously processing each of the three channels of the first layer storage format in a blocked ML storage acceleration format to accelerate inference video processing of images by the ML accelerator. 23. The system of any of clauses 19-22, wherein the precision of the first layer storage format of the neural network includes 16-bit floating point (FP16) or quantized 8-bit integer (INT8).

[0063] The system for accelerating machine learning includes a means for storing images in a blocked ML storage acceleration format according to assigned addresses. In one embodiment, the storage means may be a storage acceleration format block 400 configured to perform the described functions. In another configuration, the aforementioned means may be any module or any device configured to perform the functions recited by the aforementioned means.

[0064] The various operations of the methods described above may be performed by any suitable means capable of performing the corresponding functions. The means may include various hardware and / or software components and / or modules, including, but not limited to, circuits, application specific integrated circuits (ASICs), or processors. Generally, where there are operations illustrated in figures, those operations may have corresponding counterpart means-plus-function components that are similarly numbered.

[0065] When used, the term "determining" encompasses a wide variety of actions. For example, "determining / determining" may include calculating, computing, processing, deriving, investigating, looking up (e.g., looking up in a table, database, or another data structure), ascertaining, etc. Additionally, "determining" may include receiving (e.g., receiving information), accessing (e.g., accessing data in a memory), etc. Furthermore, "determining" may include resolving, selecting, choosing, establishing, etc.

[0066] When used, a phrase referring to "at least one of" a list of items refers to any combination of those items, including single members. As an example, "at least one of a, b, or c" is intended to encompass a, b, c, ab, ac, bc, and abc.

[0067] The various example logic blocks, modules, and circuits described in connection with this disclosure may be implemented or performed using a general-purpose processor, a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA) or other programmable logic device (PLD), discrete gate or transistor logic, discrete hardware components, or any combination thereof designed to perform the functions described herein. A general-purpose processor may be a microprocessor, but alternatively, the processor may be any commercially available processor, controller, microcontroller, or state machine. A processor may also be implemented as a combination of computing devices, e.g., a combination of a DSP and a microprocessor, multiple microprocessors, one or more microprocessors in conjunction with a DSP core, or any other such configuration.

[0068] The steps of a method or algorithm described in connection with the present disclosure may be embodied directly in hardware, in a software module executed by a processor, or in a combination of the two. A software module may reside in any form of storage medium known in the art. Some examples of storage media that may be used include random access memory (RAM), read-only memory (ROM), flash memory, erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), registers, hard disks, removable disks, CD-ROMs, etc. A software module may comprise a single instruction, or multiple instructions, and may be distributed across several different code segments, among different programs, and across multiple storage media. A storage medium may be coupled to a processor such that the processor can read information from, and write information to, the storage medium. Alternatively, the storage medium may be integral to the processor.

[0069] The disclosed methods include one or more steps or actions for achieving the described method. The steps and / or actions of those methods may be interchanged with one another without departing from the scope of the claims. In other words, unless a specific order of steps or actions is specified, the order of specific steps and / or actions and / or the use of those steps and / or actions may be modified without departing from the scope of the claims.

[0070] The described functions may be implemented in hardware, software, firmware, or any combination thereof. When implemented in hardware, an exemplary hardware configuration may comprise a processing system within a device. The processing system may be implemented using a bus architecture. The bus may include any number of interconnected buses and bridges, depending on the particular application of the processing system and overall design constraints. The bus may link various circuits together, including processors, machine-readable media, and bus interfaces. The bus interface may be used to, among other things, connect a network adapter to the processing system via the bus. The network adapter may be used to implement signal processing functions. In certain aspects, a user interface (e.g., a keypad, a display, a mouse, a joystick, etc.) may also be connected to the bus. The bus may also link various other circuits, such as timing sources, peripherals, voltage regulators, power management circuits, etc., which are well known in the art and therefore will not be described further.

[0071] The processor may be responsible for managing the bus and general processing, including executing software stored on a machine-readable medium. The processor may be implemented using one or more general-purpose and / or special-purpose processors. Examples include microprocessors, microcontrollers, DSP processors, and other circuitry capable of executing software. Software shall be broadly construed to mean instructions, data, or any combination thereof, whether referred to as software, firmware, middleware, microcode, hardware description language, or otherwise. The machine-readable medium may include, by way of example, random access memory (RAM), flash memory, read-only memory (ROM), programmable read-only memory (PROM), erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), registers, a magnetic disk, an optical disk, a hard drive, or any other suitable storage medium, or any combination thereof. The machine-readable medium may be embodied in a computer program product. The computer program product may comprise packaging materials.

[0072] In a hardware implementation, the machine-readable medium may be part of a processing system separate from the processor. However, as one skilled in the art will readily appreciate, the machine-readable medium, or any portion thereof, may be external to the processing system. By way of example, the machine-readable medium may include a transmission line, a carrier wave modulated by data, and / or a computer product separate from the device, all of which may be accessed by the processor through a bus interface. Alternatively, or in addition, the machine-readable medium, or any portion thereof, may be integrated into the processor, such as is the case with cache and / or general-purpose register files. While various components discussed may be described as having particular locations, such as local components, these components may also be configured in various ways, such as certain components configured as part of a distributed computing system.

[0073] The processing system may be configured as a general-purpose processing system having one or more microprocessors providing processor functionality and external memory providing at least a portion of the machine-readable medium, all linked to other support circuitry through an external bus architecture. Alternatively, the processing system may include one or more neuromorphic processors for implementing the described neuron model and model of the neural system. As another alternative, the processing system may be implemented using an application-specific integrated circuit (ASIC) having the processor, bus interface, user interface, support circuitry, and at least a portion of the machine-readable medium integrated into a single chip, or using one or more field programmable gate arrays (FPGAs), programmable logic devices (PLDs), controllers, state machines, gate logic, discrete hardware components, or any other suitable circuitry or combination of circuitry capable of performing the various functions described throughout this disclosure. Those skilled in the art will recognize how to best implement the described functionality of the processing system depending on the particular application and the overall design constraints imposed on the entire system.

[0074] The machine-readable medium may comprise several software modules. The software modules include instructions that, when executed by a processor, cause the processing system to perform various functions. The software modules may include a transmitting module and a receiving module. Each software module may reside in a single storage device or may be distributed across multiple storage devices. As an example, a software module may be loaded into RAM from a hard drive when a trigger event occurs. During execution of a software module, the processor may load some of the instructions into a cache to increase access speed. One or more cache lines may then be loaded into a general-purpose register file for execution by the processor. When referring hereinafter to functionality of a software module, it will be understood that such functionality is implemented by the processor upon executing instructions from that software module. Furthermore, it will be understood that aspects of the present disclosure result in improved functionality of a processor, computer, machine, or other system implementing such aspects.

[0075] If implemented in software, the functions may be stored on or transmitted over as one or more instructions or code on a computer-readable medium. Computer-readable media includes both computer storage media and communication media, including any medium that facilitates transfer of a computer program from one place to another. Storage media may be any available medium that can be accessed by a computer. By way of example, and not limitation, such computer-readable media may include RAM, ROM, EEPROM, CD-ROM, or other optical disk storage, magnetic disk storage, or other magnetic storage devices, or any other medium that can be used to carry or store desired program code in the form of data structures or instructions and that can be accessed by a computer. Additionally, any connection is properly termed a computer-readable medium. For example, if software is transmitted from a website, server, or other remote source using coaxial cable, fiber optic cable, twisted pair, digital subscriber line (DSL), or wireless technologies such as infrared (IR), radio, and microwave, the coaxial cable, fiber optic cable, twisted pair, DSL, or wireless technologies such as infrared, radio, and microwave are included in the definition of medium. As used herein, disk and disc include compact disc (CD), laser disc, optical disc, digital versatile disc (DVD), floppy disk, and Blu-ray disc, where disks typically reproduce data magnetically and discs reproduce data optically using lasers. Thus, in some aspects a computer-readable recording medium may comprise a non-transitory computer-readable recording medium (e.g., tangible medium). In addition, in other aspects, a computer-readable medium may include a transitory computer-readable medium (e.g., a signal).Combinations of the above should also be included within the scope of computer-readable media.

[0076] Accordingly, certain aspects may comprise a computer program product for performing the presented operations. For example, such a computer program product may comprise a computer-readable medium having instructions stored (and / or encoded) thereon, the instructions being executable by one or more processors to perform the operations described herein. In certain aspects, the computer program product may include packaging materials.

[0077] Furthermore, it should be understood that modules and / or other suitable means for implementing the methods and techniques described herein may be downloaded and / or otherwise obtained by a user terminal and / or base station, where applicable. For example, such devices may be coupled to a server to facilitate the transfer of means for implementing the methods described herein. Alternatively, the various methods described herein may be provided via storage means such that the user terminal and / or base station may obtain the various methods upon coupling or providing storage means (e.g., a physical storage medium such as RAM, ROM, a compact disc (CD), or a floppy disk) to the device. Moreover, any other suitable technique for providing the methods and techniques described herein to a device may be utilized.

[0078] It is to be understood that the claims are not limited to the precise configuration and components illustrated above. Various modifications, changes and variations may be made in the arrangement, operation and details of the methods and apparatus described above without departing from the scope of the claims.

Claims

1. 1. A processor-implemented method for a memory storage format for accelerating machine learning (ML) on a computing device, comprising: receiving an image in a neural network first layer storage format; assigning addresses to image pixels in each of three channels of the first layer storage format for accessing the image pixels in a blocked ML storage acceleration format; storing the image pixels in the blocked ML storage acceleration format according to the assigned addresses of the image pixels; accelerating inferential video processing of the image according to the assigned addresses for the image pixels of the image corresponding to the blocked ML storage acceleration format; 2. A processor implementation method comprising:

2. the step of assigning an address comprises: Dividing the image into a plurality of stripes according to an image width and an image height; dividing each of the stripes into memory blocks having memory block sizes according to a variable stride size; calculating the assigned addresses for laying out the image pixels within the memory block; wherein each of the image pixels for each channel in the image is assigned to a memory block. The method of claim 1.

3. 2. The method of claim 1, wherein storing the image comprises arranging image pixels in the memory blocks according to a spatial or channel axis of the memory blocks.

4. storing the image pixels in the memory block in the spatial domain; storing the image pixels in a channel region; The method of claim 3 further comprising:

5. storing a first group of the image pixels in a first one of the memory blocks in a first channel of the first memory block; storing a next group of the image pixels in the first one of the memory blocks in a second channel of the first memory block; storing a subsequent group of the image pixels in the first one of the memory blocks in a third channel of the first memory block; repeating the storing step for each memory block of said memory blocks and for each successive group of said image pixels; The method of claim 4 further comprising:

6. storing the image pixels in the memory block in a channel region of the memory block; storing the image pixels in a spatial domain in the memory block; The method of claim 3 further comprising:

7. storing selected image pixels in a first one of said memory blocks in a first channel of said first memory block; storing a next image pixel in the first one of the memory blocks for a second channel of the first memory block; storing subsequent image pixels in the first one of the memory blocks in a third channel of the first memory block; repeating the steps of storing the selected image pixel, storing the next image pixel, and storing the subsequent image pixel for each memory block of the memory blocks, and for each successive selected, next, and subsequent one of the image pixels; The method of claim 6 further comprising:

8. 2. The method of claim 1, wherein accelerating inference video processing includes simultaneously processing each of the three channels of the first layer storage format in the blocked ML storage acceleration format through a matrix unit of a neural signal processor (NSP) of the computing device.

9. 2. The method of claim 1, wherein the precision of the first layer storage format of the neural network comprises 16-bit floating point (FP16) or quantized 8-bit integer (INT8).

10. 1. A non-transitory computer-readable medium having recorded thereon program code for a memory storage format for accelerating machine learning (ML) on a computing device, the program code being executed by a processor; program code for receiving an image in a neural network first layer storage format; program code for assigning addresses to image pixels in each of three channels of the first layer storage format for accessing the image pixels in a blocked ML storage acceleration format; program code for storing the image pixels in the blocked ML storage accelerated format according to the assigned addresses of the image pixels; program code for accelerating inferential video processing of the image according to the assigned addresses for the image pixels of the image corresponding to the blocked ML storage acceleration format; 1. A non-transitory computer-readable medium comprising:

11. the program code for assigning addresses comprises: program code for dividing the image into a plurality of stripes according to an image width and an image height; program code for dividing each of the stripes into memory blocks having memory block sizes according to a variable stride size; program code for calculating the assigned addresses for laying out the image pixels within the memory block; 11. The non-transitory computer-readable medium of claim 10, wherein each of the image pixels for each channel in the image is assigned to the memory block.

12. 11. The non-transitory computer-readable medium of claim 10, wherein the program code for storing the image pixels comprises program code for arranging the image pixels in the memory blocks according to a spatial axis or a channel axis of the memory blocks.

13. program code for storing the image pixels in the memory blocks in the spatial domain; program code for storing the image pixels in a channel region; 13. The non-transitory computer-readable medium of claim 12, further comprising:

14. program code for storing a first group of the image pixels in a first one of the memory blocks in a first channel of the first memory block; program code for storing a next group of the image pixels in the first one of the memory blocks in a second channel of the first memory block; program code for storing a subsequent group of the image pixels in the first one of the memory blocks in a third channel of the first memory block; program code for repeating the program code for storing for each memory block of the memory blocks and for each successive group of the image pixels; 14. The non-transitory computer-readable medium of claim 13, further comprising:

15. program code for storing the image pixels in the memory block in a channel region of the memory block; and and program code for storing the image pixels in a spatial domain of the memory block.

16. program code for storing selected image pixels in a first one of the memory blocks in a first channel of the first memory block; program code for storing a next image pixel in the first one of the memory blocks for a second channel of the first memory block; program code for storing subsequent image pixels in the first one of the memory blocks in a third channel of the first memory block; and program code for repeating, for each memory block of the memory blocks and for each successive selected, next, and subsequent one of the image pixels, the program code for the storing of the selected image pixel, the program code for the storing of the next image pixel, and the program code for the storing of the subsequent image pixel.

17. 11. The non-transitory computer-readable medium of claim 10, wherein the program code for accelerating inference video processing comprises program code for simultaneously processing each of the three channels of the first layer storage format in the blocked ML storage acceleration format through a matrix unit of a neural signal processor (NSP) of the computing device.

18. 11. The non-transitory computer-readable medium of claim 10, wherein the precision of the first layer storage format of the neural network comprises 16-bit floating point (FP16) or quantized 8-bit integer (INT8).

19. 1. A system for a machine learning (ML) acceleration architecture, the system comprising: a neural signal processor (NSP) for assigning addresses to image pixels of each of three channels of a storage format of a first layer of a neural network in order to access the image pixels in a blocked ML storage accelerated format, and for storing the image pixels in the blocked ML storage accelerated format according to the assigned addresses of the image pixels; an ML accelerator for accelerating inferential video processing of the image according to the assigned addresses for the image pixels of the image corresponding to the blocked ML storage acceleration format.

20. 20. The system of claim 19, wherein the NSP is further for storing the image pixels in the memory blocks in a spatial domain and then storing the image pixels in a channel domain.

21. 20. The system of claim 19, wherein the NSP is further for storing the image pixels in the memory block in a channel region of the memory block and then storing the image pixels in a spatial region of the memory block.

22. The NSP, 20. The system of claim 19, further comprising a matrix unit for simultaneously processing each of the three channels of the first layer storage format in the blocked ML storage acceleration format to accelerate inferential video processing of the image by the ML accelerator.

23. 20. The system of claim 19, wherein the precision of the first layer storage format of the neural network comprises 16-bit floating point (FP16) or quantized 8-bit integer (INT8).

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