High-density via-pitch interconnects for increased wiring density

Abstract

Improved integrated circuit interconnect packages, methods, and multilayer integrated circuit stack structures enable increased routing density per layer while maintaining signal strength performance. Differential signal via pairs of vertical interconnect vias provide differential signaling. The vias of the differential signal via pair are closely spaced together with each via offset from the central axis of the associated LGA contact, minimizing the space between the differential signal vias while maintaining signal strength performance and providing an increased number of available routing signal channels. (Figure 5B)

Description

[Background technology]

[0001] The present disclosure relates to integrated circuit packaging designs, and more particularly to high speed differential signal integrated circuit interconnect packages and structures that connect chips / dies and land grid array (LGA) or hybrid land grid array (HLGA) socket connectors.

[0002] High data rate and bandwidth integrated circuit interconnect applications typically require differential signal via pairs for high-speed differential signaling. For example, integrated circuit interconnect packages connecting chips / dies and land grid array (LGA) or hybrid land grid array (HLGA) socket connectors require reliable and efficient signal strength performance with high-speed differential signaling. Summary of the Invention

[0003]

[0003] Embodiments of the present disclosure are directed to improved integrated circuit interconnect packages, methods, and multilayer integrated circuit stacked interconnect structures configured to enable increased routing density per layer while maintaining signal strength performance. A non-limiting example multilayer integrated circuit structure includes a substrate core and multiple build-up layers above and below the substrate core. Multiple vertical interconnect vias extend through the substrate core. A differential signal via pair of the vertical interconnect vias provides differential signaling. The differential signal vias of a via pair are spaced apart with each via offset from a central axis of an associated LGA contact, minimizing the space between the pair of vertical interconnect vias while maintaining signal strength performance and increasing the routing signal channel. [Brief explanation of the drawings]

[0004] [Figure 1]1 illustrates an integrated circuit (IC) interconnect package according to one or more disclosed embodiments that provides connection between a semiconductor chip / die and a land grid array (LGA) or hybrid land grid array (HLGA) socket connector.

[0005] [Figure 2] 2 is a cross-sectional view illustrating an example multi-layer interconnect substrate structure of the IC interconnect package of FIG. 1 according to disclosed embodiments.

[0006] [Figure 3] 1 is a flowchart illustrating the operation of one or more exemplary disclosed embodiments.

[0007] [Figure 4] 4A and 4B are plan views of a conventional interconnect substrate structure having a signal via pair of vertical interconnect vias of a conventional configuration for comparison with the configuration of a differential signal via pair of vertical interconnect vias configured according to the disclosed embodiments in FIGS. 5A and 5B, respectively.

[0008] [Figure 5] 5A and 5B are diagrams of the interconnect substrate structure of the IC interconnect package of FIGS. 1 and 2, respectively, showing differential signal via pairs of vertical interconnect vias configured with high density via pitch according to disclosed embodiments. DETAILED DESCRIPTION OF THE INVENTION

[0009] The description of various embodiments of the present invention is presented for illustrative purposes and is not intended to be exhaustive or limited to the disclosed embodiments. Many modifications and variations will be apparent to those skilled in the art without departing from the scope of the described embodiments. The terminology used herein has been selected to best explain the principles of the embodiments, practical applications, or technical improvements over commercially available technologies, or to enable others skilled in the art to understand the embodiments disclosed herein.

[0010] Reference will be made below to the embodiments presented in this disclosure. However, the scope of the disclosure is not limited to the specific embodiments described. Instead, any combination of the following features and elements, whether associated with a different embodiment or not, is contemplated for implementing and practicing the contemplated embodiments. Furthermore, while the embodiments disclosed herein may achieve advantages over other possible solutions or over the prior art, whether or not a particular advantage is achieved by a given embodiment does not limit the scope of the disclosure. Accordingly, the following aspects, features, embodiments, and advantages are exemplary only and should not be considered elements or limitations of the appended claims unless expressly recited in the claims. Similarly, references to "the present invention" should not be construed as a generalization of any of the inventive subject matter disclosed herein, nor should they be considered elements or limitations of the appended claims unless expressly recited in the claims.

[0011] According to the disclosed embodiment, the IC interconnect package 100 has an improved arrangement of differential signal vias in via pairs. The differential signal via pair includes two differential signal vertical interconnect vias. The vias in the differential signal via pair are spaced apart, with each via in the via pair being offset from the central axis of the associated LGA contact to which the via is electrically connected. The via arrangement in the differential signal via pair provides a reduced pitch or space between the differential signal vertical interconnect vias over previous configurations. The reduced via pitch creates additional available wiring channels while maintaining electrical signal strength performance. The IC interconnect package 100 enables increased routing density per layer, minimizing the number of layers required in the build-up layer stack while maintaining signal strength performance for high-speed differential signal pairs.

[0012] Referring now to FIG. 1 , an IC interconnect package 100 according to a disclosed embodiment is shown. As shown, the IC interconnect package 100 is connected between a chip / die 102 and a land grid array (LGA) or hybrid land grid array (HLGA) socket connector 104. The chip / die 102 may include a variety of complex high-speed integrated circuits, e.g., requiring numerous high-speed differential signal connections, electrically connected to the IC interconnect package 100 by solder balls or coined pre-solder sites. The chip / die 102 may include, e.g., an application specific integrated circuit (ASIC), a field programmable gate array (FPGA), a central processing unit or processor, etc. The LGA or HLGA socket connector 104 includes a high-density array of conductive contact members connected to the IC interconnect package 100 by the solder balls.

[0013] The IC interconnect package 100 may be used in a variety of computing systems, such as servers, desktop computers, mobile devices, networking devices, and the like.

[0014] FIG. 2 is a cross-sectional view of an example of the IC interconnect package 100 illustrating an example IC interconnect substrate structure 200 according to disclosed embodiments. The IC interconnect structure 200 is a multi-layer laminate structure 200 including an intermediate substrate core 202. The intermediate substrate core 202 includes a front circuit (FC) layer FC1 and a bottom circuit (BC) layer BC1. The IC interconnect structure 200 has a front circuit (FC) buildup stack 204 and a corresponding bottom circuit (BC) buildup stack 206. The substrate core 202 can be fabricated from a fiber-reinforced organic or resin material. The FC buildup stack 204 and the BC buildup stack 206 include multiple corresponding dielectric reference and signal layers fabricated on each side of the substrate core 202. The dielectric layers forming the FC buildup stack 204 and the BC buildup stack 206 include, for example, an organic resin material and / or Ajinomoto buildup film (ABF). The FC buildup stack 204 and the BC buildup stack 206 are constructed layer-by-layer on top of each other on the top and bottom of the substrate core 202 by conventional fabrication processes. As shown, the FC buildup stack 204 includes four layers 208, namely, FC2, FC3, FC4, and a top layer (Pwr). The BC buildup stack 206 includes four corresponding buildup layers 210, namely, BC2, BC3, BC4, and a bottom layer (Pwr). The top layer (Pwr) of the FC buildup stack 204 and the bottom layer of the BC buildup stack 206 provide connections to the chip / die 102 and the LGA or HLGA socket connector 104, respectively. That is, the chip / die 102 (not shown) is connected to the top layer, while the socket connector 104 (not shown) is connected to the bottom layer.

[0015] The features and advantages of one or more of the disclosed embodiments of the IC interconnect package 100 can be advantageously implemented in a variety of known IC interconnect packaging techniques and fabrication processes. It should be understood that the IC interconnect substrate structure 200 provides an illustrative example only. The multi-layer stack structure 200 of the IC interconnect package 100 can be implemented using a variety of techniques and including a variety of numbers of build-up layers and layers forming the substrate core 202.

[0016] As shown, each buildup layer 208, i.e., FC2, FC3, FC4, and top layer, and buildup layer 210, i.e., BC2, BC3, BC4, and bottom layer, comprise corresponding layers formed in sequence above and below the substrate core 202. As shown, the even-numbered buildup layers 208, i.e., FC2 and FC4, and layers 210, i.e., BC2 and BC4, are signal lines (Sig) providing internal signal interconnections typical of chip circuit interconnections. The odd-numbered buildup layers 208, i.e., FC3, and layers 210, i.e., BC3, are reference layers associated with conductive reference power planes (Pwr), e.g., copper sheets, that provide signal path shielding and isolation in IC package design. The signal line 209, i.e., FC2, in the buildup layer 208 shown in FIG. 2 represents a high-density internal signal interconnection.

[0017] The IC interconnect structure 200 includes a plurality of vertical interconnect vias 212 extending through a substrate core 202, such as resin filled plated (RFP) vias 212 as shown in FIG. 2. A pattern of holes in the substrate core 202 defines the locations of the RFP vias 212. It should be understood that the IC interconnect substrate structure 200 and the interconnect vias 212 are not limited to RFP vias 212. The substrate structure 200 and the interconnect vias 212 can be implemented with a variety of other via technologies. For example, other plated through hole (PTH) vias can implement the interconnect vias 212.

[0018] The IC interconnect structure 200 comprises an RFP via 212 and a plurality of smaller microvias 214 configured to interconnect stacked buildup layers 208, 210, such as buildup signal layers 208, i.e., FC2 and FC4, and signal layers 210, i.e., BC2, BC4, as required by the IC package design. As shown, for example, the plurality of microvias 214 are arranged as stacked microvias 216 and jogged microvias 218. The RFP vias 212 and microvias 214 are formed in the IC interconnect substrate structure 200 by known fabrication techniques, including, optionally, mechanical and / or laser drilling and filling with, for example, a resin / conductive electrolytic copper filling.

[0019] For example, in IC interconnect substrate structure 200, the core may range in thickness between 200 μm and 1500 μm, the diameter of the interconnect RFP vias 212 may range between 120 μm and 500 μm in diameter, while the stack buildup layer microvias 214 may range between 40 μm and 70 μm in diameter. Due to the relative thickness of the core 202, larger diameter RFP vias 212 are used that extend through the core 202, making reliable creation and resin / conductive filling of the vias more difficult than microvias 214 between the thin buildup layers stacked on the core.

[0020] The isolation regions, indicated by reference lines 220 in FIG. 2, are defined areas that are free of metal and filled with dielectric material. The isolation regions 220 are formed in the core layers FC1 and BC1. The isolation regions 220 may extend further above and below the RFP vias 212 into the build-up layers 208 and 210. The isolation regions 220 are used in conjunction with the RFP vias 212 to eliminate the adverse effects of capacitance between the RFP and the core and the build-up layers 208, 210 above and below the RFP vias. The isolation regions 220 between the RFP vias 212 and the core and build-up layers or planes limit the available wiring channels.

[0021] The isolation regions 220 in the buildup and core layers FC1 and BC1 limit the routing density in the buildup signal layers 208 and 210 because the isolation regions do not provide an adequate return path for the signal references. The loss of routing density due to the isolation regions 220 can increase the number of layers required. The addition of signal layers and associated reference layers in organic buildup technologies significantly increases cost.

[0022] As shown, IC interconnect structure 200 includes top-layer controlled collapse chip connection pads 222, also referred to as flip-chip or C4 contact pads 222, electrically and mechanically connected to corresponding electrical solder balls or coined pre-solder sites 224 that connect to die / chip 102. IC interconnect structure 200 includes bottom-layer conductive LGA contacts 226 that are electrically and mechanically connected to corresponding LGA connections (not shown) of LGA / HLGA socket connector 104.

[0023] The IC interconnect package 100 and IC interconnect structure 200 effectively and efficiently enable high-speed buses using differential signaling for high data rate and bandwidth applications. According to the disclosed embodiments, as shown in Figures 5A and 5B, differential signal pairs 402 of differential signal vias 212 are closely spaced together with each via offset from the central axis C of the associated LGA contact 226, minimizing the space between pairs of vertical interconnect vias, maintaining signal strength performance, and providing an increased available routing signal channel.

[0024] According to the disclosed embodiments, via placement with minimized spacing between differential signal vias 212 of via pair 402 increases routing signal channels in buildup layers 208, 210. IC interconnect package 100 and IC interconnect structure 200 provide a package design for differential signaling that achieves required signal strength performance and provides isolation areas in core layers FC1, BC1 and reference layers above and below signal RFP vias 212, while maximizing available routing density and resulting in reduced package costs. FIG. 3 illustrates exemplary operations of a method 300 for implementing one or more disclosed embodiments of IC interconnect package 100 and IC interconnect structure 200. Method 300 begins at block 302 by providing a substrate core 202, where core 202 includes layers FC1 and BC1. At block 304, method 300 forms a plurality of vertical interconnect vias 212 extending through the substrate core 202, with selected pairs of vertical interconnect vias 212 for differential signaling. As shown in block 306, the vias 212 of the selected differential signal via pairs are selectively spaced together, with each via of the via pair positioned offset from a central axis of the associated LGA contact to which the via is electrically connected, to minimize the space between the vertical interconnect via pairs. An example configuration and arrangement of interconnect vias and differential signal via pairs of the disclosed embodiments is shown in Figures 5A and 5B. At block 308, method 300 forms a plurality of build-up layers disposed above and below the substrate core, the build-up layers including a plurality of corresponding dielectric reference and signal layers. For example, in block 308, as shown in FIG. 2, build-up layers 208, i.e., FC2, FC3, FC4, and the top layer, and build-up layers 210, i.e., BC2, BC3, BC4, and the bottom layer, are created on each side of the intermediate substrate core 202 above and below core layers FC1 and BC1.

[0025] 4A and 4B provide respective plan views showing conventional or standard configurations and arrangements of differential signal via pairs for comparison with corresponding views of the illustrated IC interconnect package 100 and substrate structure 200 according to the disclosed embodiments shown in FIGS. 5A and 5B.

[0026] Figures 4A and 5A provide top views showing core layer FC1 for the bottom LGA layer, which provides connection to the associated LGA / HLGA socket connector 104 shown in Figure 1. Figures 4B and 5B provide top views showing one of the build-up signal layers 208, i.e., FC2 and FC4, superimposed on a respective core layer 202, i.e., FC1, and build-up reference layer 208, i.e., FC3, also shown for the LGA layer. In Figures 3, 4A, 4B, 5A, and 5B, the same reference numerals are used for components similar to those used in Figure 2.

[0027] As shown in Figures 4A and 4B, the differential signal vias 212 of the differential signal via pair 402 have a standard or full via pitch FP, with the RFP vias being positioned above or aligned with the central axes of their associated LGA contacts. The standard full RFP via pitch FP has large spaces between the differential signal RFP vias, potentially reducing the remaining available routing channel and increasing the number of required layers. Referring also to Figures 5A and 5B, the reduced RFP via pitch P of the differential signal pair 402 of the IC interconnect package 100 and IC interconnect structure 200 provides a significantly increased available routing channel while maintaining required signal strength performance.

[0028] As shown in FIG. 4B , the illustrated signal lines 408 and 410 with conventional placement of differential signal RFP vias cannot be routed, resulting in a loss of available wiring channel space and potentially requiring additional wiring layers. The illustrated conventional signal lines 408, 410 extend over isolation regions in the build-up reference layer 208, i.e., FC3, and core layer FC1. The conventional placement of the RFP vias 212 of the via pair 402 causes signal strength performance issues as a result of loss of the reference return path in the build-up reference layer 208, i.e., FC3, and core layer 202, i.e., FC1. The required signal strength performance is maintained with the reduced RFP via pitch P of the differential signal pair 402 of the disclosed embodiments as shown in FIGS. 5A and 5B .

[0029] As a result of the conventional placement of differential signal RFP vias, signal lines 408, 410 cannot be routed in build-up signal layers 208, i.e., FC2 and FC4, in Figure 4B with the conventional configuration, so there is a relatively large non-routable area 420 between the RFP vias containing signal lines 408, 410. The high density via pitch P of the disclosed embodiments of IC interconnect package 100 and IC interconnect structure 200 makes the signal lines 408, 410 shown in Figures 5A and 5B possible.

[0030] 5A and 5B, the illustrated configuration and placement of RFP vias 212 in differential signal via pairs 402 in IC interconnect package 100 and corresponding IC interconnect substrate structure 200 enables features and advantages according to disclosed embodiments. IC interconnect package 100 and IC interconnect structure 200 provide improved placement of interconnect RFP vias 212 that creates additional available wiring channels while maintaining required signal strength performance.

[0031] 5A and 5B illustrate an example improved arrangement of differential signal vias in a via pair 402, such as RFP via 212 (one shown in FIG. 2), configured in accordance with disclosed embodiments. The differential signal via pair 402 includes two differential signal vertical interconnect RFP vias 212 with a reduced pitch or space between the RFP vias 212, indicated by line P, which provides the electrical signal strength performance required for high-speed differential signaling. The RFP vias 212 of the differential signal via pair 402 are closely spaced together, with each of the RFP vias 212 positioned offset from the central axis C of the associated LGA contact 404. The arrangement of the differential signal via pair 402 reduces the space between the RFP vias of the differential signal via pair 402 over previous configurations, such as the full-pitch FP shown in FIGS. 4A and 4B, providing a high-density RFP via pitch P. The high density via pitch P of the differential signal RFP vias 212 is used to create additional available routing channels and minimize the space between the differential signal interconnect vias 212 of the via pairs 402 while maintaining electrical signal strength performance.

[0032] The dense via pitch P of the differential signal vertical interconnect vias 212 is larger than the required minimum manufactured via pitch between differential signal RFP vias based on the manufacturing capabilities for a particular fabrication technology. In IC interconnect package 100, electrical performance in terms of signal strength requires a larger than minimum manufactured pitch for RFP vias 212. The RFP via pitch P of the densely packed differential signal RFP vias 212 of via pair 402 is larger than the minimum manufactured pitch and can be significantly smaller than the standard pitch FP.

[0033] An RFP via pitch P is provided within a defined range that allows for minimized spacing with effective and reliable signal strength performance. The RFP via pitch P value is selected within a range based on a particular one of various IC interconnect packaging technologies and fabrication processes that implement the IC interconnect substrate structure 200. For example, in an IC interconnect substrate structure 200 having a core 202 that is 1200 μm thick and interconnect RFP vias 212 that have a diameter of 200 μm, the selected RFP via pitch P value may be 500 μm, where a conventional or standard full RFP via pitch may be approximately 1000 μm. It should be understood that this example is merely a conceptual, non-limiting example of the RFP via pitch P, and that implementations of the IC interconnect package 100 and the IC interconnect substrate structure 200 are not limited by this example.

[0034] In Figure 5A, isolation regions 406 are shown in core layer FC1 above the corresponding LGA layer. The isolation regions 406 formed in core layers FC1 and BC1 and in the respective build-up layers surround via pairs 402 of differential signal vertical interconnect RFP vias 212. The isolation regions 406 appear as a roughly figure-8 shaped void area around the via pairs 402 in Figure 5A.

[0035] The isolation regions 406 provided above and below the RFP via 212 in the core layers FC1, BC1 and respective build-up layers substantially reduce or eliminate the adverse effects of capacitive coupling between the differential signal pair 402 of the RFP via 212 and the build-up signal layers 208, i.e., FC2, FC4, and the build-up signal layers 210, i.e., BC2, BC4, in the planes above and below the interconnect RFP via.

[0036] As shown in FIG. 5B , the high-density RFP via pitch P placement creates additional available routing channels, enabling additional pairs of signal lines 408, 410, respectively, shown on the build-up signal layers 208, i.e., FC2 and FC4. The pairs of signal lines 408, 410 on the build-up signal layers 208, i.e., FC2 and FC4, are spaced from the isolation region 406 formed in the build-up reference layer, enabling an effective reference return path. The increased available routing channel areas 412 and 414 shown on the build-up signal layers 208, i.e., FC2 and FC4, include the additional pairs of signal lines 408, 410, respectively. The high-density RFP via pitch P placement effectively increases the available routing density and avoids any signal strength issues.

[0037] By comparing the high-density RFP via pitch P arrangement of Figures 5A and 5B with the conventional via arrangement shown in Figures 4A and 4B, it can be seen that the full via pitch FP spacing between differential signal vias is significantly larger than the high-density RFP via pitch P arrangement of the disclosed embodiments. As a result, in the conventional via arrangement configuration, there is a relatively large area 420 in the build-up signal layers 208, i.e., FC2 and FC4, in Figure 4B, that is non-routable, i.e., where signal lines cannot be routed. The non-routed area 420 includes the corresponding area of ​​the signal lines 408, 410 shown in Figures 5A and 5B, which is made possible by the high-density RFP via pitch P arrangement according to the disclosed embodiments.

[0038] The IC substrate structure 200 and IC interconnect package 100 provide an improved differential signaling configuration for high data rate and bandwidth applications. The package design and fabrication of the IC interconnect package 100 and IC interconnect substrate structure 200 allows for differential signaling at the required signal strength due to the reduced RFP via pitch P and isolation regions 406 surrounding the RFP vias 212, while allowing for improved routing density and resulting reduced package costs.

[0039] For example, IC interconnect package 100 and IC interconnect structure 200 can have a reduced RFP via pitch P, such as half of a typical full pitch (FP) (as shown in FIGS. 4A and 4B ), and provide effective and reliable signal strength performance. Simulation results for frequency and time domain analyses comparing previous full-pitch FP designs and the reduced half-RFP via pitch P of the disclosed embodiments show very little, if any, degradation between the RFP half-pitch and previous full-pitch designs. IC interconnect package 100 and substrate structure 200 with an RFP via pitch P arrangement of RFP via pairs 402 can be commonly utilized without concerns about signal strength performance, resulting in additional available wiring channel space.

[0040] While the forgoing is directed to embodiments of the present invention, other and further embodiments of the invention may be devised without departing from the basic scope thereof, the scope of which is determined by the claims that follow.

Claims

1. Substrate core; a plurality of build-up layers disposed above and below the substrate core; a plurality of vertical interconnect vias extending through the substrate core; a differential signal via pair of vertical interconnect vias that provides differential signaling; and the vias of the differential signal via pair being spaced together with each via positioned offset from a central axis of an associated land grid array (LGA) contact to which the via is electrically connected, minimizing the space between the vias of the differential signal via pair; 1. An integrated circuit (IC) interconnect package comprising:

2. A top contact layer for electrical and mechanical connection to the associated chip / die The IC interconnect package of claim 1 further comprising:

3. A bottom contact layer for electrically and mechanically connecting to a selected associated one of a land grid array (LGA) socket connector and a hybrid land grid array (HLGA) socket connector, wherein the bottom contact layer has the LGA contacts. The IC interconnect package of claim 1 further comprising:

4. a metal-free isolation region surrounding the vias of the differential signal via pair formed in a core layer surrounding the differential signal via pair; The IC interconnect package of claim 1 further comprising:

5. 2. The IC interconnect package of claim 1, wherein the vias of the differential signal via pair have a selected via pitch P that increases available wiring density, the selected via pitch P being greater than a minimum manufacturing pitch.

6. 2. The IC interconnect package of claim 1, wherein the substrate core is a dielectric layer containing a pattern of the vias of the differential signal via pairs having the selected via pitch P.

7. 2. The IC interconnect package of claim 1, wherein the plurality of buildup layers disposed above and below the substrate core include corresponding layers in a front circuit (FC) buildup stack above the substrate core and a bottom circuit (BC) buildup stack below the substrate core.

8. 8. The IC interconnect package of claim 7, wherein the corresponding layers in a front circuit (FC) buildup stack above the substrate core and a bottom circuit (BC) buildup stack below the substrate core include at least one signal layer providing internal signal interconnections and an associated reference layer providing signal path shielding and isolation.

9. The IC interconnect package of claim 1 , wherein the vertical interconnect via comprises a resin filled plated (RFP) via.

10. The IC interconnect package of claim 1 , wherein the vertical interconnect via comprises a plated through hole (PTH) via.

11. Substrate core; a plurality of build-up layers disposed above and below the substrate core; a plurality of vertical interconnect vias extending through the substrate core; a differential signal via pair of vertical interconnect vias that provides differential signaling; and the vias of the differential signal via pair being spaced together with each via positioned offset from a central axis of an associated LGA contact to which the via is electrically connected, minimizing the space between the vias of the differential signal via pair; A substrate structure for an integrated circuit (IC) interconnect package comprising:

12. a metal-free isolation region surrounding the vias of the differential signal via pair formed in a core layer surrounding the differential signal via pair; The substrate structure of claim 11 further comprising:

13. a top contact layer for electrical and mechanical connection to the associated chip / die; and A bottom contact layer for electrically and mechanically connecting to a selected associated one of a land grid array (LGA) socket connector and a hybrid land grid array (HLGA) socket connector. The substrate structure of claim 11 further comprising:

14. 12. The substrate structure of claim 11, wherein the vias of the differential signal via pair have a selected via pitch P that increases available wiring density, the selected via pitch P being greater than a minimum manufacturing pitch.

15. 15. The substrate structure of claim 14, wherein the vertical interconnect via is a resin filled plating (RFP) via.

16. providing a substrate core; forming a plurality of vertical interconnect vias extending through the substrate core; forming a plurality of build-up layers disposed above and below the substrate core; providing a differential signal via pair of the vertical interconnect vias for differential signaling; and spaced apart the vias of the differential signal via pair with each via of the via pair positioned offset from a central axis of an associated LGA contact to which the via is electrically connected, minimizing the space between the vias of the differential signal via pair.

1. A method for implementing an integrated circuit (IC) interconnect package, comprising:

17. 17. The method of claim 16, wherein arranging the vias of the differential signal via pair together comprises providing a selected via pitch P for the vias, the selected via pitch P being greater than a minimum manufacturing pitch.

18. forming a metal-free isolation region in the core layer surrounding the differential signal via pair; 17. The method of claim 16, further comprising:

19. 17. The method of claim 16, wherein forming the plurality of build-up layers disposed above and below the substrate core includes providing corresponding layers in a front circuit (FC) build-up stack above the substrate core and a bottom circuit (BC) build-up stack below the substrate core, the corresponding layers including reference layers and signal layers.

20. Providing a top contact layer for electrical and mechanical connection to the associated chip / die; and Providing a bottom contact layer for electrical and mechanical connection to a selected associated one of a land grid array (LGA) socket connector and a hybrid land grid array (HLGA) socket connector.

17. The method of claim 16, further comprising:

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