High-resolution time-based junction temperature estimation and calibration

Abstract

A measurement method for estimating a junction temperature of a power semiconductor module (1), comprising: duplicating a pulse current; and applying a first replicated pulse current to a control electrode (G) of a power transistor (TR) of the power semiconductor module (1) and a capacitor (C emu ) and a series resistor (R emu ) and injecting a second replica pulse current into an emulator circuit (EMU) including a comparison signal (V CMP ) to generate a voltage signal (V ge ) and the voltage signal (V emu ) and the comparison signal (V CMP ) as a function of the voltage signal (V ge ) of the emulator circuit (EMU) emu ) and the measured duration (Δt) is used to calculate the junction temperature (T J and converting the signal into an estimate of

Description

[Technical Field]

[0001] The present disclosure relates to the field of power semiconductor monitoring and related calibration methods applicable during the operational life of such components. Priority is claimed to European Patent Application No. 23305441.0, filed March 29, 2023, the contents of which are incorporated herein by reference. [Background technology]

[0002] It is known to monitor the temperature of power semiconductor devices / modules, such as multi-chip power modules, for protection, condition, and health monitoring, since temperature is one of the main causes of failure. Power semiconductor datasheets provide the maximum junction temperature at which they can operate without thermal runaway and consequent catastrophic failure. Therefore, monitoring the junction temperature, or at least the maximum junction temperature measurement, is very important to ensure the safe operation of the device.

[0003] The free surface area of ​​the die is generally very small. Fixing a sensor to the die is difficult, and in some cases even impossible. The number of external connections is large, and the acquisition system is complex. It is very difficult to do this under laboratory conditions. In practice, industrial and operating conditions make the use of separate PN junction sensors impractical. Additionally, sensors must be integrated inside the power module packaging, which means that their presence must be planned from the beginning during module conception and that they cannot be retrofitted to existing power modules.

[0004] Many temperature-sensitive electrical parameter (TSEP)-based methods and on-chip sensors are known for online junction temperature estimation on power semiconductors. This allows direct access to the junction temperature without the need for an external sensor. Typically, transistor TSEP measurements are performed using an analog-to-digital converter (ADC). Because the resolution and sampling rate of the ADC are directly related to the quality of the temperature estimation, using an ADC can be a constraint for low-cost systems. The transistor TSEP can be measured as time. More specifically, the transistor TSEP can be measured as the duration relative to a detection threshold. Time measurements can be problematic due to their low temperature-to-time sensitivity. The simplest method is to monitor the passage of temperature above a critical safety-related temperature value. This can be done using an analog comparator that compares the TSEP value to a threshold value. Such a technique is described in EP 3855145. In this way, an ADC is not required, but it does constrain the measurement to one specific temperature value. The specific temperature value is adjusted to correspond to the over-temperature of a specific power transistor. However, such an approach presents the following limitations: Only one temperature is monitored. The predetermined temperature threshold is generally selected according to the data sheet provided by the manufacturer. While it is possible to monitor multiple temperature values, this directly impacts the complexity of the circuitry and calibration. Multiple temperatures can actually be monitored by duplicating the monitoring circuitry, thus doubling the number of emulator components and doubling the calibration effort. Over-Temperature-Detection (OTD) circuit hardware must be unique for each monitored device. The TSEP characteristics are device-specific and calibration must be performed for each OTD circuit. This limits the functionality of the OTD to one specific transistor. The OTD circuitry is non-modifiable and cannot be adjusted during operation. Deviations of the TSEP during the device's mission profile, which may change the operation of the OTD, for example by modifying the measured temperature values, cannot be ruled out. If the TSEP of a power transistor is time, the time-to-temperature sensitivity is low, which results in low precision / accuracy and / or the need for expensive signal conditioning circuitry. Summary of the Invention [Problem to be solved by the invention]

[0005] The present disclosure improves this situation. [Means for solving the problem]

[0006] A measurement method for estimating a junction temperature of a power semiconductor module, comprising: a. replicating a pulse current into two replica pulse currents; b. a first replica pulse current to a control electrode of a power transistor of the power semiconductor module; and A second replica pulse current into an emulator circuit containing a resistor in series with a capacitor Simultaneous injection of c. comparing the voltage signal of the power transistor with the voltage signal of the emulator circuit to generate a comparison signal; d. measuring the duration of the voltage signal of the power transistor as a function of the comparison signal to reach the same value as the voltage signal of the emulator circuit; e. converting said measured duration into an estimate of junction temperature; A method is proposed, including:

[0007] In another aspect, there is provided a power semiconductor module, comprising: at least one power transistor; a source of current pulses supplied via a control electrode of the power transistor; a current copier configured to replicate the current provided by the current pulse source; an emulator circuit including a resistor in series with a capacitor; a comparator configured to compare the voltage signal of the power transistor with the voltage signal of the emulator circuit to generate a comparison signal; A power semiconductor module is proposed, comprising:

[0008] In another aspect, proposed is computer software comprising instructions for implementing the methods defined herein when the computer software is executed by a processor. In another aspect, proposed is a computer-readable non-transitory storage medium having registered thereon software for implementing the methods defined herein when the software is executed by a processor.

[0009] The following features can optionally be implemented separately or in combination with other features.

[0010] The resistor of the emulator circuit is adjustable and the value of the resistor is set to select a temperature estimation range amplitude.

[0011] The capacitor of the emulator circuit is adjustable and the value of the capacitor is set to select a temperature estimation range position.

[0012] The method comprises the following calibration steps: if the generated comparison signal corresponds to a situation in which the voltage signal of the power transistor is less than the voltage signal of the emulator circuit for a portion of the duration of a pulse injection that is greater than a predetermined maximum value; increasing the value of the capacitor in the emulator circuit; and if the generated comparison signal corresponds to a situation in which the voltage signal of the power transistor is greater than the voltage signal of the emulator circuit for a portion of the duration of a pulse injection that is less than a predetermined maximum value; Reducing the value of the capacitor of the emulator circuit further includes.

[0013] The module is a controller programmed to adjust the resistor and / or the capacitor further includes.

[0014] Other features, details and advantages are shown in the following detailed description and drawings.

Brief Description of Drawings

[0015] [Figure 1] It is a schematic diagram of a module according to some embodiments.

[0016] [Figure 2] It is an illustration of the measured output voltage and the corresponding comparison signal during the current pulse.

[0017] [Figure 3] It is an illustration of the measured output voltage and the corresponding comparison signal during the current pulse.

[0018] [Figure 4] It is an illustration of the linear relationship of the signal duration as a function of the temperature estimated from the comparison like FIGS. 2 and 3.

[0019] [[ID=*]] [Figure 5] Similar to FIGS. 2 or 3 in the situation of Cg > Cemu.

[0020] [Figure 6] Similar to FIGS. 2 or 3 in the situation of Cg < Cemu.

[0021] [Figure 7] It is an illustration of the temperature vs. time resolution as a function of the emulator capacitance.

[0022] [Figure 8] FIG. 1 is a schematic diagram of a controller arrangement for adjusting the emulator circuit.

[0023] [Figure 9] 1 is a flowchart of an algorithm that may be implemented in an embodiment.

[0024] [Figure 10] 1 is a flowchart of an algorithm that may be implemented in an embodiment.

[0025] [Figure 11] 1 is a flowchart of an algorithm that may be implemented in an embodiment.

[0026] [Figure 12] 1 is a diagram illustrating the dynamic adaptation of the emulator circuit.

[0027] [Figure 13] 1 is a flowchart of an algorithm that may be implemented in an embodiment.

[0028] [Figure 14] 1 is a flowchart of an algorithm that may be implemented in an embodiment.

[0029] [Figure 15] FIG. 1 is a schematic diagram of an embodiment of a dynamic adaptation of an emulator circuit. DETAILED DESCRIPTION OF THE INVENTION

[0030] In this document, the term "power" is used in its general sense in the technical field of energy conversion (power electronics). Additionally, the solutions described below are intended to be used during the operational life of a power semiconductor module under "normal" conditions, which means that they are not limited to laboratory or test bench situations under ideal and controlled conditions, such as a post-manufacturing quality control phase.

[0031] Here, reference is made to FIG. 1, which shows a power semiconductor module 1. The power semiconductor module 1 includes: at least one power transistor TR; a current pulse source CPS supplied via a control electrode G of the power transistor TR; a current copier CC arranged to replicate the current provided by the current pulse source; Capacitor C emu and a resistor R in series emu an emulator circuit EMU including: Here, the voltage signal V of the power transistor TR ge and the voltage signal V of the emulator circuit EMU emu and compare the comparison signal V CMP and a comparator COMP arranged to generate Includes:

[0032] 1, the module 1 further includes a time detector CHR, which detects the comparison signal V CMP Structurally, the time detector CHR can be a specific module in itself or a sub-module functionally integrated into the comparator COMP.

[0033] Next, an example of a measurement method for estimating the junction temperature of a power semiconductor module as shown in FIG. 1 will be described.

[0034] In the first operation, the pulse current is duplicated into two identical pulse currents. In the example of Fig. 1, the pulse current from the current pulse source CPS is duplicated by a current copier CC, e.g., a "current mirror circuit." The purpose is to inject the same current pulse into the transistor TR and the emulator circuit EMU simultaneously.

[0035] In the second operation, the first replica pulse current and the second replica pulse current are simultaneously injected into the control electrode of the power transistor TR and the emulator circuit EMU, respectively. In the example of Fig. 1, the control electrode is the gate G of the transistor TR. In this way, the internal gate resistance of the transistor (present in the transistor structure) is used as TSEP.

[0036] In the third operation, the resulting voltage V ge and voltage V emu In the example of Figure 1, the comparator COMP compares the gate-emitter voltage V of the transistor TR with the ge and the output voltage V of the emulator circuit EMU emu A comparison is made with.

[0037] The resulting voltage V ge and voltage V emu can be described by equations (1) and (2), respectively.

[0038]

number

[0039]

number

[0040] where I is the current, t is the time, and R g (T j ) is the gate resistor.

[0041] Gate resistor R g is linearly dependent on temperature and can be described by equation (3).

[0042]

number

[0043] In this example, the comparison is binary: if the transistor voltage is greater than or equal to the emulator circuit voltage (V ge ≧V emu ), output signal V CMP is equal to "1", otherwise (V ge <V emu ), is equal to "0". Therefore, the duration of the situation where the transistor voltage is equal to or greater than the emulator circuit voltage (V CMP =1) can be measured using equations (1) and (2) according to equation (4).

[0044]

number

[0045] Here, the difference is analyzed as a binary value ("1" or "0"), since the value of the difference itself is not relevant; only the duration of the sign of the difference. In various embodiments, the comparison of the two voltages can be done differently, for example, analogically.

[0046] The time-temperature relationship is independent of the value of the current injection. Thus, the method is robust to imperfections in the current pulse source CPS and allows good accuracy and low drift even when low-cost current injection circuits are used. The temperature can be measured without an additional ADC, and the junction temperature T j This significantly reduces the cost of the measurement. Alternatively, a time-to-digital converter (TDC) can be used, or even the time-to-digital conversion can be implemented in an FPGA, ultimately in the same FPGA that generates the control signals for the switches and other functions of Module 1.

[0047] V ge and V emu The comparison is illustrated in Figures 2, 3 and 4. Figure 2 corresponds to an implementation under a first temperature T1, and Figure 3 corresponds to an implementation under a second temperature T2.

[0048] In a fourth operation, the measured duration Δt is converted to a junction temperature T by a linear relationship of duration Δt as a function of temperature T. As shown in FIG. 4, the relationship n can be estimated from multiple measurements at

[0049] The conversion can be implemented using a time-to-digital converter (TDC), including TDCs known per se. Some TDCs offer a resolution better than 1 ns. For example, a component with the commercial reference "TDC7401-ZAX" has a resolution of 55 ps. The temperature resolution can be expressed as a function of the TDC resolution using equation (5):

[0050]

number

[0051] The temperature versus time resolution can easily be less than 1°C / ns, meaning that a TDC with a resolution of 55 ps allows for a temperature resolution of less than 0.055°C. To see the high resolution that can be achieved by such methods, one needs to compare this with the art-known current injection of 100 mA and resistance to a temperature resolution of 0.013 Ω / °C; in such a case, the temperature resolution is on the order of 0.5°C using a known 14-bit ADC and ±5V rails.

[0052] The temperature resolution, and subsequent accuracy and precision, can be much lower than state-of-the-art methods.

[0053] In the proposed example, the output signal value of the comparator COMP can be either 0 or 1. emu and C emu Depending on the value of C, two cases can be considered. The two cases are shown in Figures 5 and 6, respectively. In the first case (Figure 5), C g and R g are Cemu and R emu The output signal V of the comparator COMP is higher than CMP is equal to "1" and the signal length (duration) is the temperature T j In the second case (Figure 6), C g and R g are C emu and R emu The output signal V of the comparator COMP is lower than CMP is equal to "0", and the signal length (duration) is the temperature T j is proportional to.

[0054] In this example, the emulator circuit EMU is adjustable, i.e., the resistors R emu The value of the capacitor C emu In various embodiments, only the resistors are adjustable, or only the capacitors are adjustable. In other embodiments, the emulator circuit EMU is not adjustable.

[0055] Therefore, the capacitor value C emu If is configurable, R emu Regardless of the value of C emu It is possible to estimate the temperature by simply setting R emu <R g (See Figure 5) and R emu >R g (See Figure 6) emu <C g and C emu >C g Therefore, for example, T j After the estimation circuit is connected to the transistor TR, C emu Only the calibration process can be performed.

[0056] R emu For a given value of : If no signal ("0") is detected at the output of the comparator COMP, C emu must be increased, If only a positive signal ("1") is detected at the output of the comparator COMP, C emu must be reduced.

[0057] Therefore, the capacitor value C emu If is configurable, then C emu C g It is possible to improve the temperature versus time resolution by setting the temperature close to . According to equation (5), C emu The closer the temperature vs. time resolution, the better. This is shown in Figure 7, i.e., C emu -C g The temperature versus time resolution as a function of C is plotted. emu C g The closer it is to , the higher the resolution.

[0058] (during the operating life of module 1) capacitance C emu Reducing the capacitance can be achieved by using laser-trimmable chip capacitors constructed as multilayer plate capacitors. Laser vaporization of the top layer reduces the area of ​​the top electrode, thereby reducing the capacitance. Depending on the industrial situation, the resistor trimming process can be replaced by a capacitor trimming process when more convenient.

[0059] [calibration] Adjustable resistance R emu and an adjustable capacitor C emu In some embodiments with an emulator circuit EMU having a further operation of calibration can be implemented. In such cases, the module 1 can further include a controller CONT.

[0060] As an example, the adjustable capacitors and resistors can be digital potentiometers controlled by a controller such as an FPGA. As just one example, a component with the trade name "NCD2400MTR" can be used, providing a range of 200 pF with 512 discrete 355 fF steps. If this range is not sufficient to cover the full range of different device capacitances, the range can be extended by adding several larger capacitances in parallel with one "NCD2400MTR," controlled by the FPGA, as shown in Figure 8.

[0061] As a second example, an n-bit R-2R resistor ladder network controlled by an FPGA can be used, resulting in 2n resistor stages that can be adjusted directly by the FPGA. As a third example, a digital potentiometer such as the AD5258, which has 64 resistor stages, can be used.

[0062] Those skilled in the art will select an emulator circuit EMU that includes a controller CONT adapted to the transistor to be driven and the operating conditions to adapt the capacitance range. By using adjustable capacitors and resistors, the TSEP of the transistor can be automatically calibrated using various algorithms. This makes it possible to change the transistor (only) and keep the temperature measurement operational. In addition, calibration procedures can be performed periodically during the operating life of the transistor (not just in laboratory conditions on a test bench) to balance any TSEP parameter variations.

[0063] Figures 9, 10 and 11 are three examples of calibration algorithms that can be used.

[0064] In the example of Figure 9, the transistor is exposed to two different temperatures T1 and T2. emu and resistor R emuare initially set to their lower values ​​to obtain different output voltages between the transistor and the emulator circuit. When this calibration algorithm is combined with the comparator COMP described above, this situation is resolved by V CMP = 1. The assembly is set to a first fixed temperature T1, and the time detection is set to a time t1. The transistor and the emulator circuit are set to the same output voltage (V CMP =0), resistance R emu Then, the time detection is set to another time t2 until the transistor and the emulator circuit obtain different output voltages (V CMP = 1), capacitance C emu Gradually increase V until the same output voltage is obtained from the transistor and the emulator circuit. CMP =0), perform a time scan.

[0065] The example of Fig. 9 allows to reduce the calibration effort since module 1 only needs to be exposed to two different temperatures T1, T2, and a regular (cheap) FPGA is sufficient to do so.

[0066] In the example in Figure 10, the capacitor C emu Only the value of is modified. The time detection is gradually increased to set the time detection corresponding to the first temperature T1. Then, the capacitor C is closed to fix the detector resolution. emu Finally, the temperature is fixed at a second temperature T2, and V is gradually increased until different output voltages are obtained between the transistor and the emulator circuit. CMP =1), gradually increasing the time detection.

[0067] The example in Figure 10 uses a fixed (non-adjustable) resistor R emu This allows you to use

[0068] The example in Figure 11 shows the resistance of the transistor R g is the resistance R of the emulator circuit emu If it is greater than (R g >Remu , see Figure 5) and the transistor resistance R g is the resistance R of the emulator circuit emu If it is smaller than (R g <R emu , see Figure 6) and are adapted to the two situations mentioned above. First, the capacitance C emu Fix V to an intermediate value (for example, the middle of a known range) and fix the temperature to the first known temperature T1. Gradually increase the time detection. The output voltages between the transistor and the emulator circuit are different and are now equal (V CMP changes from 1 to 0), it means that R g >R emu This means that the output voltages between the transistor and the emulator circuit are equal, and they are now different (V CMP changes from 0 to 1), it means that R g <R emu This means that it is the case of FIG. 6. Then, to set the time sensitivity, the first case (R g >R emu ) has capacitance C emu In the second case (R g <R emu ) has capacitance C emu Then, the temperature is fixed at a second known temperature T2 and the time detection is increased as in the first case (R g >R emu ) until you get the same output voltage between the transistor and the emulator circuit (V CMP =0), or in the second case (R g <R emu ) until you get a different output voltage between the transistor and the emulator circuit (V CMP =1), and gradually increase it.

[0069] In the example of Figure 11, the transistor resistance R g Resistance R of the emulator circuit to emu The value of is not so important, R emu may be a fixed resistance value rather than an adjustable value.

[0070] One way to expose a transistor to a known temperature (T1 or T2) is to consider the ambient (heat sink) temperature when the transistor has been in an off state for a few minutes. Another way to expose a transistor to a known temperature is to consider the base plate temperature when the transistor has been in an off state for a few seconds. Temperature exposure can be done ex-situ (i.e., outside the module) using a heat plate and / or in situ by considering the temperature at two different moments.

[0071] [Time-based T j Estimated dynamic resolution] As explained above, the adjustable resistor R emu and an adjustable capacitor C emu The emulator circuit EMU having allows for calibrating the emulator circuit EMU as a function of transistors, for example, only once after the manufacturing / assembly process, periodically during the operational life of the module (e.g., during maintenance operations), or even during "normal" operation of the module. In the following, we focus on solutions that are specifically adapted to be implemented dynamically during the operational life of the module in order to dynamically adapt the resolution of the temperature estimation as the temperature changes due to the embedded controller.

[0072] The temperature range that can be estimated is the resistance R of the emulator circuit EMU. emu The amplitude (sensitivity) of the temperature that can be estimated from the time t is related to the conductance C of the emulator circuit EMU. emu In other words, in contrast to prior art solutions where a critical compromise must be made between large amplitude and high resolution, the solution we propose here allows for automatic and dynamic optimization of range and resolution for each transistor and each life state (changing characteristic) of each transistor.

[0073] As an example, one calibration goal could be to cover the temperature range included between 125°C and 200°C (i.e., for protection). Alternatively, the goal could be to cover the range between -40°C and 200°C (i.e., for counting temperature cycles). The sensitivity can be optimized for a particular temperature range. Junction temperature T J The performance of the estimator circuit can be optimized for best accuracy in each temperature range.

[0074] Junction temperature T J Since is estimated, the following behavior can be implemented: f. The corresponding temperature estimation range is corrected, and the junction temperature T J The resistor R of the emulator circuit EMU is adjusted so that the estimated value of approaches the center of the corrected temperature estimation range. emu Modify the value of g1. Junction temperature T J is sufficiently centered in the center of the temperature estimation range corrected according to a predefined criterion, the capacitor C of the emulator circuit EMU is emu Modify the value of g2. Junction temperature T J The capacitor C of the emulator circuit EMU is turned on so that the sensitivity is reduced (and the range is expanded) if the estimated value of is not sufficiently centered in the center of the temperature estimation range corrected according to a predefined criterion. emu Modify the value of

[0075] The above operation is illustrated in Figure 12. In the first scenario (left part of Figure 12), the junction temperature T J is T J1 It is estimated that the value T J1 is well concentrated in the measured range (curve "A"). Then the time vs. temperature sensitivity increases, and the value T J1 is concentrated in the measured range (curve "B"). The time vs. temperature sensitivity increases again, with values ​​of T J1 is again kept centered within the measurement range (curve “C”). In the second scenario (right part of Figure 12), the junction temperature TJ changes (in the example, increases), and T J2 It is estimated that the junction temperature T J =T J2 is no longer within the measurement range (curve "C"). The time vs. temperature sensitivity (capacitor C in the emulator circuit) emu (by modifying the value of the temperature T J2 is within the measurement range but is not concentrated (curve "D"). The temperature range is emu By correcting the value of the curve "E"), the estimated temperature T J2 The sensitivity is adjusted by the capacitor C emu By modifying the value of the curve (F), the curve (F) increases.

[0076] In the example of Figure 12, the temperature range is maximized to know the approximate temperature range of the transistor. Once the temperature range is known, the controller applies an algorithm to adjust R to focus on the temperature. emu Set the value of C to optimize the resolution. emu As the transistor temperature changes, the algorithm adjusts R to focus the measurement on the new temperature. emu and C emu Readjust.

[0077] In summary, C emu C g By moving it closer to , the time sensitivity can be increased. This allows for precision measurement over a wide temperature range and overcomes the trade-off range / sensitivity by using different algorithms. Dynamic repetition is achieved by using the emulator circuit (R emu and C emu ) is implemented to set the range / sensitivity trade-off. In other words, using a few iterations, both a high measurement range and high sensitivity can be reached.

[0078] By way of example only, Figures 13 and 14 show implementations of the dynamic estimation / calibration algorithm, the example of Figure 13 being general, and the example of Figure 14 being more detailed to consider the two cases discussed above with respect to Figures 5, 6, and 11.

[0079] In various embodiments, an adjustable R emu and C emu The dynamic estimation of temperature by using the parameters also fixes the duration t close to "0" (R g This can be done by using equation (1) to obtain (T). This method is shown in Figure 15 and emu is constant and R emu will result in different output voltages between the transistor and the emulator circuit (V CMP =1), which allows a regulator, such as a proportional-integral regulator ("PI" in Figure 15), to be used to regulate the temperature and gate resistance R g Without measuring the duration of the output signal of the comparator COMP, it is possible to determine the value R g and the temperature TJ can be estimated. [Industrial Applicability]

[0080] For the purposes of the preceding discussion, the internal gate resistor R g The aim of this study is to measure the junction temperature of a power transistor with high resolution, low circuit cost, low calibration effort, and high circuit generality using an emulator circuit. Optionally, calibration can be performed. Two equal currents are simultaneously injected through the control electrode (generally the gate) of the transistor and an equivalent RC circuit called an "emulator circuit." In embodiments where one wishes to do more than just measurement / estimation for a particular transistor, an adjustable emulator circuit (resistance R emu and / or capacitance C emu are the transistor R g and C g A further calibration step can be implemented by using a voltage V geand voltage V emu is compared with an analog comparator. The duration of the comparator's output signal (but not the amplitude itself) is linearly proportional to the transistor temperature. This makes it possible to measure the transistor's junction temperature without an ADC. In addition, by using adjustable resistors and capacitors controlled by a controller, e.g., an FPGA, it is possible to perform in-situ calibration for different component characteristics and repeat the calibration during the module's operational life to compensate for deviations.

[0081] Without being limiting, modules according to the above can be used for example as power modules and inverters in the automotive and powertrain technology sector, factory automation, air conditioning systems, HVDC and renewable energies.

[0082] The present disclosure is not limited to the methods, modules, components, and computer software described herein, which are merely examples, and the present invention encompasses all alternatives that one skilled in the art would contemplate upon reading this text. [Explanation of symbols]

[0083] 1 module CPS Current Pulse Source CC Current Copier TR transistor EMU emulator circuit COMP comparator CHR Time Detector CONT Controller

Claims

1. A measurement method for estimating the junction temperature of a power semiconductor module (1), a. Duplicating a pulsed current into two duplicated pulsed currents, b. A first replicated pulse current to the control electrode (G) of the power transistor (TR) of the power semiconductor module (1), and Capacitor (C) ｅｍｕ ) and a series resistor (R ｅｍｕ ) a second replicated pulse current to the emulator circuit (EMU) Injecting them simultaneously, c. A voltage signal (V) that crosses the control electrode (G) of the power transistor (TR). ｇｅ ) and the voltage signal (V) that crosses the emulator circuit (EMU) ｅｍｕ ) is compared with the comparison signal (V ＣＭＰ ) to generate, d. The comparison signal (V ＣＭＰ The voltage signal (V) of the power transistor (TR) as a function of ) ｇｅ ) the voltage signal (V) of the emulator circuit (EMU) ｅｍｕ ) Measure the duration (Δt) until it reaches the same value, e. Converting the measured duration (Δt) into an estimated value of the joint temperature (T Ｊ ) Methods that include...

2. The resistor (R) of the emulator circuit (EMU) ｅｍｕ ) is adjustable, and the resistor (R ｅｍｕ The method according to claim 1, wherein the aforementioned value of is set so that a temperature estimation range position is selected.

3. The capacitor (C) of the emulator circuit (EMU) ｅｍｕ ) is adjustable, and the capacitor (C ｅｍｕ The method according to claim 1 or 2, wherein the value of is set so that a temperature estimation range amplitude is selected.

4. The generated comparison signal (V ＣＭＰ ) during a portion of the duration of the pulse injection, the voltage signal (V) crosses the control electrode (G) of the power transistor (TR). ｇｅ ) crosses the emulator circuit (EMU) and the voltage signal (V ｅｍｕ When indicating that it is smaller than ), The capacitor (C) of the emulator circuit (EMU) ｅｍｕ Increasing the aforementioned value of ) and The generated comparison signal (V ＣＭＰ ) the voltage signal (V) crosses the control electrode (G) of the power transistor (TR) during a portion of the duration of the pulse injection. ｇｅ ) crosses the emulator circuit (EMU) and the voltage signal (V ｅｍｕ When indicating that it is greater than, The capacitor (C) of the emulator circuit (EMU) ｅｍｕ Decreasing the aforementioned value of ) The method according to claim 3, further comprising:

5. At least one power transistor (TR), A current pulse source (CPS) supplied via the control electrode (G) of the power transistor (TR), A current copy (CC) arranged to replicate the current supplied by the current pulse source, Capacitor (C) ｅｍｕ ) and a series resistor (R ｅｍｕ An emulator circuit (EMU) including, A voltage signal (V) crossing the control electrode (G) of the power transistor (TR) ｇｅ ) and the voltage signal (V) that crosses the emulator circuit (EMU) ｅｍｕ ) is compared with the comparison signal (V ＣＭＰ A comparator (COMP) organized to generate ) The aforementioned comparison signal (V ＣＭＰ A time detector (CHR) is configured to measure the duration (Δt) until the voltage signal (V ge) of the power transistor (TR) reaches the same value as the voltage signal (V emu) of the emulator circuit (EMU), as a function of ) A power semiconductor module (1) including the above.

6. The aforementioned resistor (R ｅｍｕ ) and / or the capacitor (C ｅｍｕ A controller (CONT) configured to adjust ) The power semiconductor module (1) according to claim 5, further comprising:

7. Computer software comprising instructions causing a processor to perform the method according to claim 1.

8. A computer-readable non-temporary recording medium having computer software recorded on it that causes a processor to perform the method described in claim 1.

Images