Metadata registers for memory devices

Abstract

The present disclosure provides systems, methods, and devices for memory systems that support metadata. In a first aspect, a method for processing data and metadata in a memory device includes receiving data from a host over at least one data connection into a first plurality of registers, receiving metadata from the host over at least one non-data connection into a second plurality of registers, and storing the data in a first portion of a memory array and storing the metadata in a second portion of the memory array. Other aspects and features are also claimed and described.

Description

[Technical Field]

[0001] (CROSS-REFERENCE TO RELATED APPLICATIONS) This application claims the benefit of U.S. Patent Application No. 18 / 047,493, filed October 18, 2022, entitled "METADATA REGISTERS FOR A MEMORY DEVICE," which is expressly incorporated herein by reference in its entirety.

[0002] Aspects of the present disclosure relate generally to computer information systems, and more particularly to memory systems that store data. Some features may enable and provide improved memory capabilities for storing metadata, such as error correction codes (ECCs), for data stored in the memory.

[0003] introduction A computing device (e.g., a laptop, a mobile phone, etc.) may include one or several processors that perform various computing functions, such as telephony, wireless data access, and camera / video functions. Memory is an important component of a computing device. The processor may be coupled to the memory to perform the above-mentioned computing functions. For example, the processor may fetch instructions from the memory, such as to perform the computing functions and / or to store temporary data in the memory to process these computing functions. Summary of the Invention

[0004] The following summarizes some aspects of the present disclosure in order to provide a basic understanding of the discussed technology. This summary is not an extensive overview of all of the contemplated features of the present disclosure, and is not intended to identify key or critical elements of all aspects of the present disclosure or to delineate the scope of any or all aspects of the present disclosure. Its sole purpose is to present some concepts of one or more aspects of the present disclosure in summary form as a prelude to the more detailed description presented later.

[0005] An apparatus according to at least one embodiment includes a memory configured to communicate with a host. The memory includes a memory array configured to store data. The memory is configured to provide data stored in the memory array to the host when performing a computing function. In some aspects, registers of the memory device can be configured to separately store data and metadata in different sets of registers. The metadata registers can temporarily store information during transmission between the host device and the memory device for retrieval from the memory array of the memory device in response to a read command or for storage in the memory array of the memory device in response to a write command.

[0006] In one aspect of the present disclosure, a memory device includes a memory array having a first portion and a second portion, and a memory input / output (I / O) module. The memory I / O module may be coupled to the memory array, configured to communicate with a host via a channel including a plurality of connections, including at least one data connection and at least one non-data connection, and consisting of at least one first register and at least one second register. The memory I / O module may be configured to perform operations including receiving data from the host via the at least one data connection into the at least one first register, receiving metadata from the host via the at least one non-data connection into the at least one second register, storing the data in the first portion of the memory array, and storing the metadata in the second portion of the memory array. The memory I / O module may also be configured to perform operations including retrieving data from a first portion of the memory array into at least one first register, retrieving metadata from a second portion of the memory array into at least one second register, transmitting data from the at least one first register to a host over at least one data connection, and transmitting metadata from the at least one second register to the host over at least one non-data connection.

[0007] In an additional aspect of the present disclosure, an apparatus, such as a wireless device, includes at least one processor and a memory coupled to the at least one processor. The at least one processor is configured to communicate with the memory through a memory controller coupled to a channel coupling the processor to the memory. The processor may be a processor, a controller, or other logic circuit within a host.

[0008] In an additional aspect of the present disclosure, a non-transitory computer-readable medium stores instructions that, when executed by a processor, cause the processor to perform the operations described herein with respect to aspects of the present disclosure.

[0009] In this disclosure, the term error correcting code (ECC or ECCs) may refer to an error detecting code, an error correcting code, or an error detecting and correcting code. An ECC is not limited to a particular type of coding. In some examples, an ECC may include a Hamming code and / or a parity code.

[0010] The memory in this disclosure may be embedded within the processor on a semiconductor die or may be part of a different semiconductor die. The memory may be of various types. For example, the memory may be static random access memory (SRAM), dynamic random access memory (DRAM), magnetic random access memory (MRAM), NAND flash, or NOR flash, etc.

[0011] Methods and apparatus are presented in this disclosure as a non-limiting example of a Low-Power Double Data Rate (LPDDR) Synchronous Dynamic Random Access Memory (SDRAM). For example, an LPDDR memory that operates in accordance with the LPDDR specification promulgated by the Joint Electronic Device Engineering Council (JEDEC). One such LPDDR specification may be LPDDR5. Another such LPDDR specification may be LPDDR6.

[0012] Other aspects, features, and implementations will become apparent to those skilled in the art upon reviewing the following description of certain exemplary aspects in conjunction with the accompanying figures. While features may be discussed in conjunction with certain aspects and figures below, various aspects may include one or more of the advantageous features discussed herein. In other words, although one or more aspects may be discussed as having certain advantageous features, one or more of such features may also be used in accordance with various aspects. Similarly, although exemplary aspects may be discussed below as device, system, or method aspects, the exemplary aspects may be implemented in various devices, systems, and methods.

[0013] The method may be embodied in a computer-readable medium as computer program code including instructions that cause a processor to perform the steps of the method. In some embodiments, the processor may be part of a mobile device including a first network adapter configured to transmit data, such as images or video, in a recording or as streaming data over a first network connection of a plurality of network connections. The processor may be coupled to the first network adapter and to a memory that stores data supporting processing and communication operations performed by the processor. The network adapter may support communication over a wireless communication network, such as a 5G NR communication network. The processor may cause transmission of the data stored in the memory over the wireless communication network.

[0014] The foregoing has outlined rather broadly the features and technical advantages of examples according to the present disclosure in order that the following Detailed Description may be better understood. Additional features and advantages are described below. The concepts and specific examples disclosed may be readily utilized as a basis for modifying or designing other structures for carrying out the same purposes of the present disclosure. Such equivalent constructions do not depart from the scope of the appended claims. The properties of the concepts disclosed herein, both their organization and method of operation, together with associated advantages, will be better understood from the following description when considered in conjunction with the accompanying figures. Each of the figures is provided for purposes of illustration and description, and not as a definition of the limits of the claims.

[0015] While aspects and implementations are described herein by way of example for several examples, those skilled in the art will recognize that additional implementations and use cases may occur in many different configurations and scenarios. The innovations described herein can be implemented across many different platform types, devices, systems, shapes, sizes, and packaging configurations. For example, aspects and / or applications may be performed by integrated chip implementations and other non-modular component-based devices (e.g., end-user devices, vehicles, communication devices, computing devices, industrial equipment, retail / purchasing devices, medical devices, artificial intelligence (AI)-enabled devices, etc.). Some examples may or may not be specifically targeted to a use case or application, but may result in applicability of a wide range of combinations of the described innovations. Implementations may range from chip-level or modular components to non-modular, non-chip-level implementations, and even to aggregated, distributed, or original equipment manufacturer (OEM) devices or systems incorporating one or more aspects of the described innovations. In some practical settings, devices incorporating the described aspects and features may also necessarily include additional components and features for implementation and practice of the claimed and described aspects. For example, transmitting and receiving wireless signals necessarily includes several components for analog and digital purposes (e.g., hardware components including antennas, radio frequency (RF) chains, power amplifiers, modulators, buffers, processor(s), interleavers, summers / analog summers, etc.). It is contemplated that the innovations described herein may be practiced in a wide variety of devices, chip-level components, systems, distributed configurations, end-user devices, etc., of various sizes, shapes, and configurations.

[0016] A further understanding of the nature and advantages of the present disclosure can be realized by referring to the following drawings. In the accompanying drawings, similar components or features may have the same reference label. Furthermore, various components of the same type may be distinguished by following the reference label with a dash and a second label that distinguishes between the similar components. When only a first reference label is used in this specification, the description is applicable to any one of the similar components having the same first reference label, regardless of the second reference label. [Brief explanation of the drawings]

[0017] [Figure 1] 1 illustrates a block diagram of an exemplary computing system incorporating a host, a memory, and a channel coupling the host and the memory, in accordance with one or more aspects of the present disclosure. [Figure 2A] 1 illustrates a block diagram of an exemplary computing system incorporating a host, a memory, and a channel coupling the host and the memory, with another implementation of the channel, in accordance with one or more aspects of the present disclosure. [Figure 2B] 1 illustrates a block diagram of an exemplary computing system incorporating a host, a memory, and a channel coupling the host and the memory, with link error correcting code (ECC) protection of the channel, in accordance with one or more aspects of the present disclosure. [Figure 2C] 1 illustrates a block diagram of an exemplary computing system incorporating a host, a memory, and a channel coupling the host and the memory, with another implementation of the channel, in accordance with one or more aspects of the present disclosure. [Figure 3A] 1 depicts a flowchart illustrating an exemplary method of a memory implementing a write command using a metadata register, in accordance with one or more aspects of the present disclosure. [Figure 3B] 1 depicts a flowchart illustrating an example method of a memory implementing a read command using a metadata register, in accordance with one or more aspects of the present disclosure. [Figure 4A]FIG. 1 shows a block diagram illustrating an example configuration of a metadata register, in accordance with one or more aspects of the present disclosure. [Figure 4B] FIG. 1 shows a block diagram illustrating an example configuration of a metadata register, in accordance with one or more aspects of the present disclosure. [Figure 5A] 1 illustrates a timing diagram illustrating a write operation transferring metadata over a non-data connection in accordance with one or more aspects of the present disclosure. [Figure 5B] 1 illustrates a timing diagram illustrating a write operation transferring metadata over a non-data connection in accordance with one or more aspects of the present disclosure. [Figure 6A] 10 illustrates a timing diagram illustrating a read operation transferring metadata over a non-data connection in accordance with one or more aspects of the present disclosure. [Figure 6B] 10 illustrates a timing diagram illustrating a read operation transferring metadata over a non-data connection in accordance with one or more aspects of the present disclosure. [Figure 7] 1 shows a block diagram illustrating the configuration of a memory array in a memory device that stores metadata, in accordance with one or more aspects of the present disclosure. [Figure 8] 1 shows a block diagram illustrating another configuration of a memory array in a memory device for storing metadata, in accordance with one or more aspects of the present disclosure. [Figure 9] 1 shows a block diagram illustrating storage of data and metadata in a memory array in accordance with one or more aspects of the present disclosure.

[0018] Like reference numbers and designations in the various drawings indicate like elements. DETAILED DESCRIPTION OF THE INVENTION

[0019] The detailed description set forth below, with reference to the accompanying figures, is intended as an illustration of various configurations and is not intended to limit the scope of the present disclosure. Rather, the detailed description includes specific details intended to provide a thorough understanding of the inventive subject matter. Those skilled in the art will appreciate that these specific details are not required in every instance and that, in some instances, well-known structures and components are shown in block diagram form for clarity of explanation.

[0020] The present disclosure provides systems, apparatuses, methods, and computer-readable media for supporting data processing, including techniques for supporting communication of data between a host and a memory device. The host may transmit data and associated metadata to be stored in a memory array of the memory device. The memory device may include registers for receiving and storing data and metadata to be written to the memory array. The metadata registers of the memory device may be organized to associate metadata with data without using two separate addresses for the data and metadata. Examples of metadata stored with data include error correction codes (ECCs) to protect the data from errors and / or signatures to protect the data from tampering. However, metadata may be used for purposes beyond protecting data.

[0021] Particular implementations of the subject matter described in this disclosure may be implemented to achieve one or more of the following potential advantages or benefits: In some aspects, the present disclosure provides techniques for storing metadata along with data in a manner that is compatible with current memory array architectures by coordinating the storage of data and metadata within pages of a memory array. Furthermore, in some aspects, metadata may be transmitted between a host and a memory device without a dedicated connection in a channel between the host and the memory device that carries the metadata.

[0022] As the demand for computing devices to perform more functions at increasing speeds increases, so too do errors associated with data stored in memory. Errors can increase as more data is stored in memory and transferred between blocks. One example of protecting against such errors is the use of error-correcting codes (ECCs) associated with data. Schemes that improve error detection / correction when accessing memory without placing undue strain on the host or memory would be advantageous for improving system performance. ECC can be added during transmission over a channel, such as with link ECC. ECC can also be added for storage within the memory array, such as with system ECC. In some examples, end-to-end system ECC can be implemented within the host by adding high-density on-chip SRAM to store in-line ECC parity bits for certain data to increase overall data reliability. However, such high-density on-chip SRAM can be prohibitively expensive in terms of overall system cost, and high-density SRAM is susceptible to soft errors associated with SRAM cells.

[0023] In the present disclosure, system ECC data or other metadata is generated internally to the host and transferred between the host and the memory device via a non-data channel (e.g., RDQS_t for write operations and DM for read operations). The ECC bits may be stored in the memory array (e.g., DRAM cell array) along with the corresponding data, such that ECC protection provides a unified and consistent method to reduce overall system cost by enabling the elimination of on-chip SRAM and achieve better performance without requiring separate memory link ECC. Thus, the present disclosure provides a simplified and efficient ECC scheme that implements system ECC by sharing certain resources with non-data connections. In this manner, overall system cost may be reduced and performance may be improved.

[0024] 1 shows an apparatus 100 incorporating a host 110, a memory 150, and a channel 190 coupling the host 110 and the memory 150. The apparatus 100 may be, for example, a computing system (e.g., a server, a data center, a desktop computer), a mobile computing device (e.g., a laptop, a cell phone, a vehicle, etc.), an Internet of Things device, a virtual reality (VR) system, an augmented reality (AR) system, an automotive system (e.g., a driver assistance system, an autonomous driving system), an image capture device (e.g., a standalone digital camera or digital video camcorder, a wireless communication device handset with a camera such as a mobile phone, cellular phone, or satellite radiotelephone, a personal digital assistant (PDA), a panel or tablet, a gaming device, a computing device such as a webcam, a video surveillance camera, or other device with digital imaging or video capabilities), and / or a device in a multimedia system (e.g., a television, a disc player, a streaming device).

[0025] Host 110 may include at least one processor, such as a central processing unit (CPU), a graphics processing unit (GPU), a digital signal processor (DSP), a multimedia engine, and / or a neural processing unit (NPU). Host 110 may be configured to be coupled to and communicate with memory 150 (e.g., memories 150-1 through 150-4) via channel 190 (e.g., channels 190-1 through 190-4) when performing a computing function, such as one of data processing, data communication, graphics display, camera, AR or VR rendering, image processing, neural processing, etc. For example, memory 150-1 through 150-4 may store instructions or data for the host to perform a computing function.

[0026] Host 110 may include memory controller 130, which may include controller PHY modules 134-1 through 134-4. Each of controller PHY modules 134-1 through 134-4 may be coupled to a respective one of memories 150-1 through 150-4 via a respective channel 190-1 through 190-4. For ease of reference, reads and writes are referred to from the perspective of host 110. For example, in a read operation, host 110 may receive stored data from one or more of memories 150-1 through 150-4 via one or more of channels 190-1 through 190-4. In a write operation, host 110 may provide data to be written into one or more of memories 150-1 through 150-4 for storage via one or more of channels 190-1 through 190-4. Memory controller 130 may be configured to control various aspects of communication with memories 150-1 through 150-4, such as logical layers. Controller PHY modules 134-1 through 134-4 may be configured to control the electrical characteristics (eg, voltage levels, phases, delays, frequencies, etc.) of signals provided or received on channels 190-1 through 190-4, respectively.

[0027] In some examples, memories 150-1 through 150-4 may be LPDDR DRAM (e.g., LPDDR5, LPDDR6). In some examples, memories 150-1 through 150-4 may each be a different type of memory, such as one LPDDR5, one LPDDR6, one flash memory, and one SRAM. Host 110, memories 150-1 through 150-4, and / or channels 190-1 through 190-4 may operate according to LPDDR (e.g., LPDDR5, LPDDR6) specifications. In some examples, each of channels 190-1 through 190-4 may include 16 bits of data (e.g., 16 DQ). In some examples, each of channels 190-1 through 190-4 may operate on 32 bits of data (e.g., 32 DQ). Although four channels are shown in FIG. 1, device 100 may include more or fewer channels, such as eight or sixteen channels.

[0028] A configuration of host 110, memory 150, and channel 190 according to some aspects of the present disclosure is more particularly illustrated in FIG. 2A. FIG. 2A shows another representation of device 100 having host 110, memory 150, and channel 190 of FIG. 1. Channel 190 between host 110 and memory 150 may include multiple connections, some of which carry data (e.g., user data or application data) and some of which carry non-data (e.g., addresses and other signaling information). For example, the non-data connections within channel 190 may include a data clock (e.g., WCK) used in providing data to each memory 150 on a byte-by-byte basis, and a read data strobe (e.g., RDQS) used in receiving data from each memory 150. Channel 190 may further include data mask (e.g., DM, sometimes referred to as data mask inverted DMI to indicate the multiple functions performed by the signal connection) signaling used to mask certain portions of data in write operations. Channel 190 may further include a command and address (eg, CA[0:n]) and associated CA clock to provide commands (eg, read commands or write commands) to memory 150.

[0029] The host 110 may include at least one processor 120, which may include a CPU 122, a GPU 123, and / or an NPU 124. The host 110 may further include a memory controller 130 having a controller PHY module 134. The memory controller 130 may be coupled to the at least one processor 120 via a bus system 115 in performing various computing functions. The term "bus system" may realize that elements coupled to a "bus system" may directly or indirectly exchange information therebetween. In different embodiments, a "bus system" may encompass multiple physical connections as well as intervening stages such as buffers, latches, registers, etc. The modules may be implemented in hardware, software, or a combination of hardware and software.

[0030] Memory controller 130 can send and / or receive blocks of data to at least one processor 120 and / or other modules, such as memory 150. Memory 150 may include memory I / O module 160 (e.g., PHY layer) configured to control electrical characteristics (e.g., voltage levels, phases, delays, frequencies, etc.) for providing or receiving signals over a connection of channel 190. For example, memory I / O module 160 may be configured to capture (e.g., sample) data, commands, and addresses from host 110 over channel 190 and output data to host 110 over channel 190. Exemplary techniques for communicating over channel 190 between memory I / O module 160 and memory controller 130 are shown in the examples of FIGS. 5A-5B and 6A-6B. Memory 150 may further include a memory array 175, which may include multiple memory cells (e.g., DRAM memory cells, MRAM memory cells, SRAM memory cells, flash memory cells) that store values. Host 110 can read data stored in and write data to memory array 175 via channel 190 and memory I / O module 160. Memory array 175 can be divided into multiple banks, with each bank organized as multiple pages.

[0031] Application data or user data may be processed by processor 120 and memory controller 130 instructed to store and / or retrieve such data from memory 150. For example, data may be generated during the execution of an application, such as a spreadsheet program that calculates values ​​based on other data. As another example, data may be generated during the execution of an application, such as by receiving user input to a spreadsheet program. As a further example, data may be generated during the execution of a gaming application that generates information regarding a representation of a scene rendered by a three-dimensional (3-D) application.

[0032] Data may be associated with metadata that provides information about the stored data. The metadata may include properties or characteristics of the data. In one example, the metadata is an error correcting code (ECC) that can be used to verify the integrity of the data after transmission and / or storage and to correct a limited number of errors in the data. The ECC is metadata because it describes the characteristics of the data with which it is associated (e.g., the value that an algorithm produces when the data is provided as input to the algorithm).

[0033] Information transmitted over channel 190 may be stored as temporary or short-term storage locations in registers in memory I / O module 160 of memory 150 prior to long-term storage in memory array 175. Memory I / O module 160 may include first and second registers that store data (e.g., user data or application data) and metadata, respectively. A first plurality of registers 182A-K store data, and a second plurality of registers 181A-N store metadata. In different embodiments, K may be equal to N, or K may be different from N, such that K is greater than N, or K is less than N. In some embodiments, N and / or K may be 1. The contents of registers 181A-N and 182A-K may then be transferred to memory array 175. In some embodiments, the contents of registers 181A-N and 182A-K may be transferred consecutively immediately after receipt to complete individual write commands. In some embodiments, the contents of registers 181A-N and 182A-K may be accumulated from multiple write commands received in memory 150, and the metadata may be transferred to memory array 175 when certain criteria are met. In some embodiments, there may be a single register 182 and / or a single register 181. For example, to reduce hardware size, there may be a single data register 182 with multiple metadata registers 181A-N. The write command may be combined with serialized data incoming from the host such that the write data (e.g., 32 bytes) is temporarily stored in 32-byte register 182. The data is then automatically written to a first portion of the memory array without any additional write commands from the host. Some example configurations of metadata registers 181A-N are shown in FIGS. 4A-4B.

[0034] The device 100 may be configured to support processing of metadata accompanying data transmitted between the host 110 and the memory 150. In one example, the metadata may be error correcting codes (ECCs) used to protect the data from at least some errors in communication and / or storage. A separate link ECC code may be transmitted over the channel 190 to protect the data and / or metadata during transmission over the channel 190. A configuration of the host 110, memory 150, and channel 190 according to some aspects of the present disclosure that supports link ECC is shown in FIG. 2B. FIG. 2B shows another representation of the device 100 having the host 110, memory 150, and channel 190 of FIG. 1 and / or FIG. 2A.

[0035] Host 110 may be configured to implement multiple ECC functions. To support system ECC functions, host 110 may include system ECC memory 137. Memory controller 130 may be coupled to system ECC memory 137 via bus system 116. Memory controller 130 may further include system ECC decoder 131 and system ECC encoder 132. Controller PHY module 134 may include link ECC decoder 135 and link ECC encoder 136.

[0036] Device 100 may implement a system ECC function to detect / correct errors that occur when performing computing functions (e.g., operating with at least one processor 120). The system ECC function may be particularly useful for applications with low error tolerance, such as automotive applications. In some examples, system ECC encoder 132 may generate a system ECC for a block of data and an ECC associated with the block of data, such as by appending ECC bits to the block of data. Memory controller 130 may send the block of data along with the system ECC to other modules, such as at least one processor 120 and / or memory 150. For example, the system ECC may be sent to memory 150, and memory 150 may store the system ECC in the same manner as the data. In some embodiments, memory 150 does not implement an ECC function based on the system ECC. In some examples, memory controller 130 may receive a block of data and an associated system ECC, for example, from processor 120 and / or memory 150. Memory controller 130 may then use the system ECC to detect / correct errors in the block of data.

[0037] The host 110 is coupled to the memory 150 via a channel 190 shown for one byte of data DQ[0:7]. The channel 190 and signaling between the host 110 and the memory 150 may be implemented in accordance with JEDEC DRAM specifications (e.g., LPDDR5, LPDDR6). As shown, the channel 190 includes signal connections for DQ, a read data strobe (RDQS), a data mask (DM), a data clock (WCK), a command and address (CA[0:n]), and a command and address clock (CK). The host 110 may use the read data strobe RDQS to strobe (e.g., clock) data in a read operation and receive data on DQ. The memory 150 may use the data mask DM to mask certain portions of data from being written in a write operation. The memory 150 may use the data clock WCK to sample data on DQ for a write operation. Memory 150 may use a command and address clock CK to clock (e.g., receive) CA. Each signal connection for signaling may include a pin at host 110, a pin at memory 150, and one or more conductive traces that electrically connect the pins. The one or more conductive traces may be part of a single integrated circuit (IC) on a silicon chip that includes processor 120 and memory 150, may be part of a package-on-package (PoP) that includes processor 120 and memory 150, or may be part of a printed circuit board (PCB) that is coupled to both processor 120 and memory 150.

[0038] Memory 150 may include memory I / O module 160 (e.g., PHY layer) configured to control electrical characteristics (e.g., voltage levels, phases, delays, frequencies, etc.) for providing or receiving signals over channel 190. For example, memory I / O module 160 may be configured to capture (e.g., sample) data, commands, and addresses from host 110 via channel 190 and output data to host 110 via channel 190.

[0039] Memory 150 may further include a memory array 175, which may include multiple memory cells (e.g., DRAM memory cells) that store information. Host 110 can read data stored in memory array 175 and write data in memory array 175 via channel 190. Additionally, memory array 175 may be configured to store metadata, such as an ECC (e.g., a system ECC or array ECC) associated with the stored data. For example, a block (e.g., a word) of data in first portion 176A of memory array 175 may be associated with a system ECC stored in second portion 176B via a shared address. For example, reading (or writing) a shared address in memory array 175 may read (or write) both the block of data at that address and the system ECC associated with that block of data.

[0040] Device 100 may include link ECC functionality to detect / correct errors resulting from data transmission within channel 190. Memory I / O module 160 may include memory link ECC decoder 161 and memory link ECC encoder 162. Link ECC information may be added during transit through channel 190, verified at either host 110 or memory 150, and then discarded. For example, in a write operation, link ECC encoder 136 may generate a link ECC associated with a block of data (e.g., write data) to be written into memory 150. Host 110 may provide write data to memory 150 via a DQ signal connection (e.g., a data connection within channel 190) and provide link ECC to memory 150 via a read data strobe RDQS signal connection (e.g., a non-data connection within channel 190). In memory 150, memory link ECC decoder 161 may use the link ECC to detect / correct errors in the write data. Because the link ECC function is resolved in memory I / O module 160, the link ECC may not be stored in memory array 175. In a read operation, memory link ECC encoder 162 may receive data (e.g., read data) stored in memory array 175 (e.g., via node 174, array ECC decoder 171, and node 164) and generate a link ECC associated with the read data. Memory I / O module 160 may provide the read data to host 110 via the DQ signal connection and provide the link ECC to host 110 via the data mask DM signal connection. In host 110, link ECC decoder 135 may use the link ECC to detect / correct errors in the read data.

[0041] Referring to metadata registers 181A-N, multiple metadata registers may be located within memory I / O module 160 of memory 150 and associated with partitioned memory spaces (e.g., within second portion 176B) of banks (e.g., within first portion 176A) within memory array 175. For example, column addresses 0x3C-0x3F within each page may be reserved for metadata such as ECC. A write operation performs 32 bytes of data to a target page and column location within first portion 176A of memory array 175 data stored within data registers 182A-K, and associated 2 bytes of metadata to a predetermined area within second portion 176B of memory array 175 metadata stored within metadata registers 181A-N. In memory 150 configured to support such write operations, the memory internal data bus (e.g., read bus 163) may remain configured for the word size of the data without separate consideration of the metadata. In some embodiments, when a previous read command executes to retrieve metadata from the memory array into a metadata register based on a read command to the metadata memory space (such as "0x3C" to "0x3F"), a read command to the normal memory space (such as "0x00" to "0x3B") executes to simultaneously retrieve 32 bytes of normal read data from the first portion 176A and 2 bytes of metadata from the second portion 176B.

[0042] Another configuration of channel 190 for communicating metadata is shown in Figure 2C. In the example of Figure 2C, channel 190 includes a dedicated system metadata bus. The data bus ("Data Bus [0:k-1]") simultaneously transfers, for example, 32 bytes of data to accompany data for write or read operations, and the system metadata bus ("System Meta [0:p-1]") simultaneously transfers, for example, 2 bytes of metadata. The data bus is an example of a data connection within channel 190, and the system metadata bus is an example of a non-data connection within channel 190.

[0043] The data and metadata transmitted over channel 190 may be transmitted over a combination of data and non-data connections. For example, user data may be transmitted over data connections DQ[0:7] and metadata transmitted over non-data connections (such as the data mask DM connection or the read strobe RDQS connection). The operation of executing a write command with data and metadata by a memory device is described in FIG. 3A.

[0044] A write command issued by a host to the memory device of method 300 causes the memory device to perform a memory device operation of receiving data from the host into a first plurality of registers over at least one data connection in block 302. For example, the data may be stored in data registers 182A-K by processing signals received over a data DQ[0:7] channel. Additionally, in block 304, the memory device receives metadata from the host into a second plurality of registers over at least one non-data connection. For example, the metadata may be stored in metadata registers 181A-N by processing signals received over a non-data read strobe RDQS channel. A data channel may be any channel that carries user data or application data for at least temporary storage in the memory array. A non-data channel may be any channel that carries data other than user data or application data.

[0045] After certain conditions are met, the write command may be completed by performing blocks 306 and 308. In block 306, data is stored from a first plurality of registers to a first portion of the memory array corresponding to a write address specified in the received write command for the received data in block 302. For example, the contents of data registers 182A-K may be stored in an area of ​​first portion 176A of memory array 175 based on the write address. In block 308, metadata is stored from a second plurality of registers to a second portion of the memory array. For example, the contents of metadata registers 181A-N may be stored in an area of ​​second portion 176B of memory array 175 corresponding to the write address (e.g., an area reserved for metadata corresponding to the data at the write address). In some examples, the execution of blocks 306 and 308 may be triggered by certain criteria, such as storing data in a single page, having a certain number of bytes of data, or registers 181A-N or 182A-K being full. In some examples, data may accumulate in registers 181A-N and / or 182A-K from two or more write commands before completing the write command by executing blocks 306 and 308. In some examples, data may accumulate in registers 181A-N and / or 182A-K while a sequence of write commands having addresses corresponding to the same page of memory is received. Registers 181A-N and / or 182A-K may be written to memory array 176 when a subsequent write command directed to a different page of memory is received. In some embodiments of a memory device having a single register 182A, the data portion (e.g., corresponding to columns 0x00-0x3B) may be written to the memory array without any delay, such that only additional write commands to the metadata portion of the memory array (e.g., corresponding to columns 0x3C-0x3F) are used to store metadata in the memory array.

[0046] An operation of executing a read command with data and metadata by the memory device is illustrated in FIG. 3B. A read command issued by the host to the memory device of method 300 causes memory 150 to perform a read operation. At block 352, metadata is received into a second plurality of registers from the memory array corresponding to the read address. At block 354, data is received into a first plurality of registers from the memory array corresponding to the read address. In some embodiments, the metadata is loaded into the second set of registers before regular data (e.g., data located in columns 0x00-0x3B) is accessed. In some embodiments, blocks 352 and 356 may be performed sequentially during a read operation to simultaneously retrieve data and metadata from the memory device to the host. When a certain amount of data accumulates in the registers, such as when the registers are full or when requested data is stored in the registers, the data may be transmitted from the registers to the host via channel 190. At block 356, the data from the first plurality of registers is transmitted to the host via at least one data connection. For example, the contents of data registers 182A-K may be modulated onto the data DQ[0:7] connections of channel 190 and received at memory controller 130 of host 110. In block 358, data from the second plurality of registers is transmitted to the host over at least one non-data connection. For example, the contents of metadata registers 181A-N may be modulated onto the non-data read strobe RDQS connections of channel 190 and received at memory controller 130 of host 110. Memory controller 130 of host 110 may process the electrical signals received via channel 190 and provided to processor 120 and / or ECC memory 137.

[0047] The metadata registers 181A-N may be associated with memory addresses in the memory array 175 according to different techniques. One exemplary memory address mapping is shown in FIG. 4A. Certain addresses within a page may be assigned to metadata, such as by partitioning the column space corresponding to 0x3C-0x3F. The metadata registers 181A-N may include n metadata registers dedicated to each column location. That is, column space 0x3C has a first set 481A of n metadata registers, column space 0x3D has a second set 481B of n metadata registers, column space 0x3E has a third set 481C of n metadata registers, and column space 0x3F has a fourth set 481D of n metadata registers. The metadata registers 181A-N may have a total of 4n registers in this exemplary configuration, with each bank's column address fully associated with n metadata registers.

[0048] Another exemplary memory address mapping is shown in FIG. 4B. N metadata registers 181A-N may be coupled to all column locations in all banks. Any metadata from reserved metadata column locations 0x3C-0x3F may be stored in or retrieved from any of the n metadata registers through a write or read operation, respectively. One exemplary command protocol for selecting one of the n metadata registers is a “CAS” + “WRITE / READ” command set, which selects one of the n metadata registers via a target column address. The “CAS” command selects one of the n metadata registers, and the “WRITE / READ” command delivers a target column address (“0x3C” or “0x3D” or “0x3E” or “0x3F”) that stores the metadata in a particular one of the registers 181A-N.

[0049] 5A and 5B illustrate waveforms of data and metadata transfer over an exemplary channel in a write operation according to some aspects of the present disclosure. The command and address clock CK may be a differential signal having a CK_t signal connection and a CK_c signal connection. The data clock WCK may be a differential signal having a WCK0_t signal connection and a WCK0_c signal connection. The read data strobe RDQS may be a differential signal having an RDQS_t signal connection and an RDQS_c signal connection. The data mask is labeled DM0 to indicate that DM0 corresponds to the lower byte of DQ (DQ[0:7]). At T0 (the rising edge of CK_c and the falling edge of CK_t), a CAS command may be provided by the host 110 for a write operation to the memory 150. At T1, a write command may be provided by the host 110 to the memory 150.

[0050] After a time period write latency (WL), the host 110 may toggle the data clocks WCK0_t and WCK0_c to provide clocking for the memory 150 to receive data for writing on the DQ signal connections. At Tc0-Tc2, the memory 150 may continuously receive 16 bytes of data, clocked by the data clocks WCK0_t and WCK0_c, on each of the DQ[0:7] signal connections. The memory 150 may continuously receive a 16-bit data mask DM0 (e.g., based on the data clocks WCK0_t and WCK0_c) to mask certain portions of the received data from the write operation. In some examples, the 16 bytes of data and the 16-bit data mask DM0 may be received by the memory 150, with each bit of the data mask DM0 masking a corresponding byte of the received data.

[0051] At Tc0-Tc2, memory 150 may receive, for example, 8 bits of ECC or other metadata on the RDQS_t signal connection based on data clocks WCK0_t and WCK0_c. During a read operation, the RDQS_t signal connection may be configured to provide a read data strobe (RDQS) from memory 150 to host 110. In some examples, ECC link data may be included on the RDQS connection in addition to the metadata, including the system ECC. Referring to FIG. 2B, memory link ECC decoder 161 may utilize the received link ECC to detect and / or correct errors in the received 16 bytes of data.

[0052] 6A and 6B show waveforms for reading data and metadata within the device 100 of FIG. 2 during a read operation, according to some aspects of the present disclosure. The command and address clock CK may be a differential signal having a CK_t signal connection and a CK_c signal connection. The data clock WCK may be a differential signal having a WCK0_t signal connection and a WCK0_c signal connection. The read data strobe RDQS may be a differential signal having a RDQS_t signal connection and a RDQS_c signal connection. The data mask is labeled DM0 to indicate that DM0 corresponds to the lower byte of DQ (DQ[0:7]). At T0 (the rising edge of CK_c and the falling edge of CK_t), a CAS command may be provided by the host 110 for a read operation to the memory 150. At T1, a read command may be provided by the host 110 to the memory 150.

[0053] After a time period read latency (RL), memory 150 may toggle read data strobe RDQS to provide clocking for host 110 to receive data for a read operation on the DQ signal connections. At Tc0-Tc2, host 110 may sequentially receive 16 bytes of data, clocked by read data strobes RDQS_t and RDQS_c, on each of the DQ[0:7] signal connections. Thus, in this example, 16 bytes of data are received by host 110.

[0054] At Tc0-Tc2, host 110 may receive, for example, 8 bits of metadata, such as system ECC, on the data mask DM0 signal connection based on (e.g., clocked by) read data strobes RDQS_t and RDQS_c. For write operations, the DM signal connection may be configured to provide a data mask from host 110 to memory 150. In some examples, link ECC may also be inserted on the DM signal connection.

[0055] 7 illustrates a first address space 742 for accessing a first portion 176A of memory array 175 and a second address space 744 for accessing a second portion 176B of memory array 175, according to some aspects of the present disclosure. In some examples, first address space 742 and second address space 744 may each include row addresses and column addresses received from a CA of channel 190. For example, first address space 742 may correspond to row addresses 0000h-FFFFh and column addresses 00h-3Ah, and second address space 744 may correspond to row addresses 0000h-FFFFh and column addresses 3Bh-3Fh. Thus, the total address space of memory array 175 ranges from row address 0000h and column address 00h to row address FFFFh and column address 3Fh.

[0056] The first portion 176A may be addressable by a first address (e.g., an address in the first address space 742), and the second portion 176B may be addressable by a second address (e.g., an address in the second address space 744). Thus, the first address and the second address may differ in terms of column addressing. While this disclosure utilizes an example of the first address space 742 and the second address space 744 varying in terms of column addressing, other examples are possible, such as the row-based example of FIG. 8.

[0057] 8 illustrates an example of a first address space 842 and a second address space 844 that differ in terms of row space, according to some aspects of the present disclosure. In FIG. 8, a first portion 176A may be accessed by a first address space 842 corresponding to row addresses 0000h to FFFDh. A second portion 176B may be accessed by a second address space 844 corresponding to row addresses FFFEh to FFFFh. In this example, the first address space 842 and the second address space 844 may differ in terms of row space, and thus a first address used to access the first portion 176A and a second address used to access the second portion 176B may differ in terms of row addressing.

[0058] FIG. 9 illustrates an example of data and address mapping according to some aspects of the present disclosure. For example, FIG. 9 illustrates that data (written into or read from first portion 176A, labeled as normal data) may be 32 bytes, and ECC (written into or read from second portion 176B) may be 16 bits or less. Unused address space (labeled “null”) is aggregated within the column address 3Fh space, although in other examples, unused address space is distributed among the column address spaces. In the execution of each read or write command, a total of 34 bytes (32 bytes of data and 2 bytes of system ECC or other metadata) may be transmitted between host 110 and memory 150 (e.g., via at least one data connection and at least one non-data connection). In such a configuration, 2 bytes of ECC may be implemented without any memory bandwidth loss. Additionally, an additional 2 bytes of ECC ("c") may be implemented to further protect the 32 bytes of data ("n") and 2 bytes of system ECC ("s").

[0059] An exemplary mapping to a portion of a memory array is shown in the table below: The column addresses for the metadata are associated with the column addresses of the corresponding data. The column addresses of the metadata are associated with a portion of the memory array reserved for metadata, such as second portion 176B of memory array 175 in Figures 2A-2B.

[0060] [Table 1]

[0061] The wireless communication device may include memory configured to receive and output data via data registers and metadata registers, as shown at least in FIGS. 2A-2C, and may be provided within or integrated within any processor-based device according to any of the aspects disclosed herein. Examples include, but are not limited to, set-top boxes, entertainment units, navigation devices, communication devices, fixed location data units, mobile location data units, global positioning system (GPS) devices, mobile phones, cellular phones, smartphones, session initiation protocol (SIP) phones, tablets, phablets, servers, computers, portable computers, mobile computing devices, wearable computing devices (e.g., smart watches, health or fitness trackers, eyewear, etc.), desktop computers, personal digital assistants (PDAs), monitors, computer monitors, televisions, tuners, radios, satellite radios, music players, digital music players, portable music players, digital video players, video players, digital video disc (DVD) players, portable digital video players, automobiles, vehicle components, avionics systems, drones, and multicopters.

[0062] In one or more aspects, the memory storage and retrieval techniques may include additional aspects, such as any single aspect or any combination of aspects, described with respect to one or more other processes or devices described below or elsewhere herein. In a first aspect, supporting data operations may include an apparatus configured to store and retrieve data from a memory array of a memory device. The apparatus may respond to commands from a host device, such as read commands and write commands, and in response provide certain data from the memory array over a channel coupling the memory device to the host device. The apparatus may include a memory array and a memory I / O module coupled to the memory array and configured to communicate with the host over a channel including multiple connections, including at least one data connection and at least one non-data connection. In some implementations, the memory device is included within a wireless device, such as a UE. In some implementations, the apparatus includes a remote server, such as a cloud-based computing solution, that includes the memory device.

[0063] In some implementations, the apparatus may include at least one processor and a memory coupled to the processor. The processor may be configured to perform the operations described herein with respect to the apparatus. In some other implementations, the apparatus may include a non-transitory computer-readable medium having program code recorded thereon, the program code being executable by a computer to cause the computer to perform the operations described herein with respect to the apparatus. In some implementations, the apparatus may include one or more means configured to perform the operations described herein. In some implementations, a method of accessing data in a memory array, including writing or reading, may include one or more operations described herein with respect to the apparatus.

[0064] In a second aspect, in combination with the first aspect, the apparatus is further configured to receive data from a host via at least one data connection into at least one first register, receive metadata from the host via at least one non-data connection into at least one second register, store the data in a first portion of the memory array, and store the metadata in a second portion of the memory array.

[0065] In a third aspect, in combination with one or more of the first or second aspects, the data and metadata are received simultaneously during a single write command.

[0066] In a fourth aspect, in combination with one or more of the first to third aspects, an apparatus may be configured to receive a first address over at least one second non-data connection corresponding to data, wherein storing the data in a first portion of the memory array is based on the first address and storing the metadata in a second portion of the memory array is to a second address corresponding to the first address.

[0067] In a fifth aspect, in combination with one or more of the first to fourth aspects, receiving metadata from the host into a second plurality of registers via at least one non-data connection includes receiving a plurality of metadata into the at least one second register, the plurality of metadata including first metadata corresponding to the first write operation and second metadata corresponding to the second write operation, wherein the plurality of metadata corresponds to a plurality of memory addresses of a page of the memory array; and storing the metadata in the second portion of the memory array includes writing the plurality of metadata into the page of the memory array from the at least one second register to complete the first write operation and the second write operation.

[0068] In a sixth aspect, in combination with one or more of the first through fifth aspects, the metadata includes an error correction code (ECC).

[0069] In a seventh aspect, in combination with one or more of the first through sixth aspects, the metadata includes a signature that authenticates data corresponding to the metadata.

[0070] In an eighth aspect, in combination with one or more of the first to seventh aspects, at least one non-data connection comprises a data mask inversion (DMI) portion of the channel, and the number of connections in the data mask inversion (DMI) portion is less than the number of connections in the at least one data connection.

[0071] In a ninth aspect, in combination with one or more of the first to eighth aspects, at least one non-data connection comprises a read data strobe (RDQS) portion of the channel, and the number of connections in the read data strobe (RDQS) portion is less than the number of connections in the at least one data connection.

[0072] In a tenth aspect in combination with one or more of the first to ninth aspects, the at least one second register has a first portion associated with a first column address and a second portion associated with a second column address, and receiving the metadata includes receiving the metadata in the first portion or the second portion based on a memory address for data associated with the metadata specified by a write command received by the memory I / O module corresponding to the data.

[0073] In an eleventh aspect, in combination with one or more of the first to tenth aspects, the at least one second register comprises a first portion and a second portion; Receiving the metadata includes receiving the metadata in the first portion or the second portion based on an indicator specified by a write command received by the memory I / O module.

[0074] In a twelfth aspect, in combination with one or more of the first aspect to the eleventh aspect, a memory I / O module may be configured to retrieve data from a first portion of a memory array into at least one first register, retrieve metadata from a second portion of the memory array into at least one second register, transmit the data from the at least one first register to a host via at least one data connection, and transmit the metadata from the at least one second register to the host via at least one non-data connection.

[0075] In a thirteenth aspect, in combination with one or more of the first to twelfth aspects, the data and metadata are retrieved simultaneously during a single read command.

[0076] In a fourteenth aspect, in combination with one or more of the first to thirteenth aspects, the memory I / O module is further configured to perform an operation including receiving a first address over at least one second non-data connection corresponding to data, wherein retrieving the data from the first portion of the memory array is based on the first address and retrieving the metadata from the second portion of the memory array is from a second address corresponding to the first address.

[0077] In a fifteenth aspect, in combination with one or more of the first aspect to the fourteenth aspect, retrieving metadata from a second portion of the memory array into at least one second register includes retrieving a plurality of metadata during a single page operation, the plurality of metadata including first metadata corresponding to the first read operation and second metadata corresponding to the second read operation, the plurality of metadata corresponding to a plurality of memory addresses of the page of the memory array, and transmitting the metadata from the second plurality of registers to the host via at least one non-data connection includes transmitting the plurality of metadata.

[0078] In a sixteenth aspect, in combination with one or more of the first to fifteenth aspects, an apparatus includes a host device configured to communicate with a memory device over a channel, the host device comprising a memory controller coupled to the channel, the memory controller configured to perform operations including transmitting data between the memory controller and at least one first register of the memory device over at least one data connection of the channel, and transmitting metadata between the memory controller and at least one second register of the memory device over at least one non-data connection of the channel.

[0079] In a seventeenth aspect, in combination with one or more of the first to sixteenth aspects, the host device is configured to signal a read command on the channel specifying a read address that retrieves data and retrieves metadata from the memory device.

[0080] In an eighteenth aspect, in combination with one or more of the first to seventeenth aspects, the read address identifies a set of at least one second register that stores the metadata.

[0081] In a nineteenth aspect, in combination with one or more of the first to eighteenth aspects, the read command includes an indicator that specifies a set of at least one second register that stores the metadata.

[0082] In a twentieth aspect, in combination with one or more of the first to nineteenth aspects, the host device is configured to signal a write command on the channel specifying a write address at which to store data and transmit the data to the memory device.

[0083] In a twenty-first aspect, in combination with one or more of the first to twentieth aspects, the write address identifies a set of at least one second register that stores the metadata.

[0084] In a twenty-second aspect, in combination with one or more of the first to twenty-first aspects, the write command includes an indicator that specifies one of the at least one second register that stores the metadata.

[0085] In describing the embodiments herein, numerous specific details are set forth, such as examples of specific components, circuits, and processes, to provide a thorough understanding of the present disclosure. As used herein, the term "coupled" means directly connected or connected via one or more intervening components or circuits. Also, in the following description, for purposes of explanation, specific terminology is set forth to provide a thorough understanding of the present disclosure. However, it will be apparent to those skilled in the art that these specific details may not be required to practice the teachings disclosed herein. In other instances, well-known circuits and devices are shown in block diagram form to avoid obscuring the teachings of the present disclosure.

[0086] Some portions of the detailed descriptions which follow are presented in terms of procedures, logic blocks, processes, and other symbolic representations of operations on data bits within a computer memory. In this disclosure, a procedure, logic block, process, etc., is conceived to be a self-consistent sequence of steps or instructions leading to a desired result. These steps require physical manipulations of physical quantities. Usually, though not necessarily, these quantities take the form of electrical or magnetic signals capable of being stored, transferred, combined, compared, and otherwise manipulated in a computer system.

[0087] In the figures, a single block may be described as performing one or more functions. The function or functions performed by that block may be implemented in a single component, across multiple components, and / or may be implemented using hardware, software, or a combination of hardware and software. To clearly illustrate this interchangeability between hardware and software, various illustrative components, blocks, modules, circuits, and steps are described below generally in terms of their functionality. Whether such functionality is implemented as hardware or software depends on the particular application and design constraints imposed on the overall system. Those skilled in the art may implement the described functionality in various ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present disclosure. Additionally, the illustrative device may include components other than those shown, including well-known components such as a processor, memory, etc.

[0088] Unless otherwise expressly stated, as will be apparent from the discussion below, it will be appreciated that throughout this application, discussions utilizing terms such as "accessing," "receiving," "sending," "using," "selecting," "determining," "normalizing," "multiplying," "averaging," "monitoring," "comparing," "applying," "updating," "measuring," "deriving," "solving," "generating," and the like refer to the actions and processes of a computer system or similar electronic computing device that manipulates data represented as physical (electronic) quantities in the computer system's registers and memory, and converts those data into other data that are similarly represented as physical quantities in the computer system's registers, memory, or other such information storage, transmission, or display device.

[0089] The terms "device" and "apparatus" are not limited to one physical object or a particular number of physical objects (such as a smartphone, a camera controller, or a processing system). A device, as used herein, may be any electronic device having one or more components capable of implementing at least some portions of the present disclosure. Although the description and examples herein use the term "device" to describe various aspects of the present disclosure, the term "device" is not limited to a particular configuration, type, or number of objects. An apparatus, as used herein, may include a device that performs the described operations, or a portion of such a device.

[0090] Some components in a device or apparatus described as “means for accessing,” “means for receiving,” “means for sending,” “means for using,” “means for selecting,” “means for determining,” “means for normalizing,” “means for multiplying,” or other similarly named terms referring to one or more operations on data such as image data may refer to processing circuitry (e.g., an application specific integrated circuit (ASIC), a digital signal processor (DSP), a graphics processing unit (GPU), a central processing unit (CPU)) configured to perform the recited functions through hardware, software, or a combination of hardware configured by software.

[0091] Those skilled in the art will appreciate that information and signals may be represented using any of a variety of different technologies and techniques. For example, the data, instructions, commands, information, signals, bits, symbols, and chips that may be referred to throughout the above description may be represented by voltages, currents, electromagnetic waves, magnetic fields or particles, optical fields or particles, or any combination thereof.

[0092] The components, functional blocks, and modules described herein with respect to Figures 1-2C include, among other examples, processors, electronic devices, hardware devices, electronic components, logic circuits, memory, software code, firmware code, or any combination thereof. Software should be construed broadly to mean, among other examples, instructions, instruction sets, code, code segments, program code, programs, subprograms, software modules, applications, software applications, software packages, routines, subroutines, objects, executable files, threads of execution, procedures, and / or functions, whether referred to as software, firmware, middleware, microcode, hardware description language, or otherwise. Additionally, features discussed herein may be implemented via dedicated processor circuitry, via executable instructions, or combinations thereof.

[0093] Those skilled in the art will appreciate that one or more blocks (or operations) described with reference to Figures 1 and 2A-2C may be combined with one or more blocks (or operations) described with reference to another of the figures. For example, one or more blocks (or operations) of Figures 3A-3B may be combined with one or more blocks (or operations) of Figures 1 and 2A-2C. As another example, one or more blocks associated with Figures 5A-5B and 6A-6B may be combined with one or more blocks (or operations) associated with Figures 1 and 2A-2C.

[0094] Those skilled in the art will further appreciate that the various illustrative logical blocks, modules, circuits, and algorithm steps described in connection with the disclosure herein may be implemented as electronic hardware, computer software, or a combination of both. To clearly illustrate this interchangeability of hardware and software, various illustrative components, blocks, modules, circuits, and steps have been described above generally in terms of their functionality. Whether such functionality is implemented as hardware or software depends on the particular application and design constraints imposed on the overall system. Those skilled in the art may implement the described functionality in various ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present disclosure. Those skilled in the art will also readily recognize that the ordering or combination of components, methods, or interactions described herein are merely examples, and that the components, methods, or interactions of various aspects of the present disclosure may be combined or performed in ways other than those shown and described herein.

[0095] The various exemplary logic, logic blocks, modules, circuits, and algorithmic processes described in connection with the implementations disclosed herein may be implemented as electronic hardware, computer software, or a combination of both. Interchangeability between hardware and software has been described generally in terms of functionality and illustrated in the various exemplary components, blocks, modules, circuits, and processes described above. Whether such functionality is implemented in hardware or software depends upon the particular application and design constraints imposed on the overall system.

[0096] The hardware and data processing devices used to implement the various example logic, logic blocks, modules, and circuits described in connection with the aspects disclosed herein may be implemented or performed using general-purpose single-chip or multi-chip processors, digital signal processors (DSPs), application-specific integrated circuits (ASICs), field programmable gate arrays (FPGAs) or other programmable logic devices, discrete gate or transistor logic, discrete hardware components, or any combination thereof designed to perform the functions described herein. A general-purpose processor may be a microprocessor, or any conventional processor, controller, microcontroller, or state machine. In some implementations, a processor may be implemented as a combination of computing devices, such as a combination of a DSP and a microprocessor, multiple microprocessors, one or more microprocessors in conjunction with a DSP core, or any other such configuration. In some implementations, particular processes and methods may be performed by circuitry specific to a given function.

[0097] In one or more aspects, the functions described may be implemented in hardware, digital electronic circuitry, computer software, firmware, or any combination thereof, including the structures disclosed herein and their structural equivalents. Implementations of the subject matter described herein may also be implemented as one or more computer programs, which may be one or more modules of computer program instructions encoded on a computer storage medium for execution by or to control the operation of a data processing apparatus.

[0098] If implemented in software, the functions may be stored on or transmitted over as one or more instructions or code on a computer-readable medium. The processes of a method or algorithm disclosed herein may be implemented in a processor-executable software module that may reside on a computer-readable medium. Computer-readable media includes both computer storage media and communication media, including any medium that may enable transfer of a computer program from one place to another. A storage medium may be any available medium that can be accessed by a computer. By way of example, and not limitation, such computer-readable media may include random access memory (RAM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), CD-ROM or other optical disk storage, magnetic disk storage or other magnetic storage devices, or any other medium that can be used to store desired program code in the form of instructions or data structures and that can be accessed by a computer. Also, any connection may be properly referred to as a computer-readable medium. As used herein, disk and disc include compact discs (CDs), laser discs, optical discs, digital versatile discs (DVDs), floppy disks, and Blu-ray discs, where disks typically reproduce data magnetically while discs reproduce data optically using lasers. Combinations of the above should also be included within the scope of computer-readable media. Additionally, the operations of a method or algorithm may reside on machine-readable and computer-readable media, which may be embodied in a computer program product as one or any combination or set of code and instructions.

[0099] Various modifications of the implementations described in this disclosure may be readily apparent to those skilled in the art, and the general principles defined herein may be applied to several other implementations without departing from the spirit or scope of the present disclosure. Thus, the claims are not intended to be limited to the implementations shown herein, but are to be accorded the widest scope consistent with the present disclosure, the principles and novel features disclosed herein.

[0100] Additionally, antonyms such as "upper" and "lower," or "front" and "back," or "top" and "bottom," may be used to facilitate description of the figures, and those skilled in the art will readily appreciate that these terms indicate relative positions corresponding to the orientation of the figure on a properly oriented page, and may not reflect the proper orientation of any device in which it may be implemented.

[0101] As used herein, the term "coupled to" in various tenses of the verb "couple" can mean that element A is directly connected to element B, or that other elements may be connected between element A and element B (i.e., element A is indirectly connected to element B) to perform a specific intended function. In the case of electrical components, the term "coupled to" is also used herein to mean that a wire, trace, or other conductive material is used to electrically connect element A and element B (and any components electrically connected therebetween). In some examples, the term "coupled to" refers to the transfer of electrical energy between element A and element B to perform a specific intended function.

[0102] In some examples, the term "electrically connected" means having or being configurable to have a current flowing between element A and element B. For example, element A and element B may be connected via a resistor, transistor, or inductor, in addition to wires, traces, or other conductive materials and components. Additionally, for radio frequency functionality, element A and element B may be "electrically connected" via a capacitor.

[0103] Terms such as "first," "second," and "third" are used for ease of reference and may not have any substantive meaning. Similarly, names of components / modules may be employed for ease of reference and may not limit the components / modules. For example, such non-limiting names may include a "read ECC" signal connection and a "write ECC" signal connection.

[0104] Some features described herein in the context of separate implementations may also be implemented in combination in a single implementation. Conversely, various features described in the context of a single implementation may also be implemented in multiple implementations separately or in any suitable subcombination. Furthermore, even if features may be described above as functioning in a particular combination and are initially claimed as such, one or more features from a claimed combination may, in some cases, be deleted from the combination, and the claimed combination may be directed to a subcombination or a variation of the subcombination.

[0105] Similarly, while acts are shown in a particular order in the figures, this should not be understood as requiring such acts to be performed in the particular order or sequential order shown, or that all of the shown acts be performed, to achieve desirable results. Furthermore, the figures may generally depict one or more exemplary processes in the form of a flow diagram. However, other acts not shown may be incorporated into the generally depicted exemplary process. For example, one or more additional acts may be performed before, after, simultaneously with, or between any of the depicted acts. In some situations, multitasking and parallel processing may be advantageous. Furthermore, the separation of various system components in the above-described implementations should not be understood as requiring such separation in all implementations, and it should be understood that the described program components and systems may generally be integrated together in a single software product or packaged within multiple software products. Additionally, some other implementations are within the scope of the following claims. In some cases, the actions recited in the claims may be performed in a different order and still achieve desirable results.

[0106] As used herein, including in the claims, the term "or," when used in a list of two or more items, means that any one of the listed items may be employed alone, or any combination of two or more of the listed items may be employed. For example, if a composition is described as containing component A, B, or C, the composition may contain A alone, B alone, C alone, a combination of A and B, a combination of A and C, a combination of B and C, or a combination of A, B, and C. Also, as used herein, including in the claims, in a list of items ending with "at least one of," "or" indicates a disjunctive list, such as, for example, a list of "at least one of A, B, or C" means either A or B or C, or AB or AC or BC, or ABC (i.e., A and B and C), or any of these in any combination thereof.

[0107] As one skilled in the art will appreciate, the term "substantially" broadly defines (and includes) what is specified; e.g., substantially 90 degrees includes 90 degrees, and substantially parallel includes parallel), but not necessarily entirely. In any disclosed implementation, the term "substantially" may be replaced with "within a percentage of" what is specified, where percentage includes 0.1 percent, 1 percent, 5 percent, or 10 percent.

[0108] The above description of the present disclosure is provided to enable any person skilled in the art to make or use the disclosure. Various modifications to the present disclosure will be readily apparent to those skilled in the art, and the general principles defined herein may be applied to other variations without departing from the spirit or scope of the present disclosure. Thus, the present disclosure is not intended to be limited to the examples and designs described herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. 1. An apparatus comprising: a memory array having a first portion and a second portion; Memory I / O module and wherein the memory I / O module is coupled to the memory array; configured to communicate with a host over a channel including a plurality of connections, including at least one data connection and at least one non-data connection; at least one first register and at least one second register; The memory I / O module: receiving data into said at least one first register from said host via said at least one data connection; receiving metadata from the host via the at least one non-data connection into the at least one second register; storing the data in the first portion of the memory array; storing the metadata in the second portion of the memory array; and The apparatus is further configured to perform operations including:

2. The apparatus of claim 1 , wherein the data and the metadata are received simultaneously during a single write command.

3. The memory I / O module: receiving a first address over at least one second non-data connection corresponding to the data; and further configured to perform operations including: storing the data in the first portion of the memory array based on the first address; storing the metadata in the second portion of the memory array to a second address corresponding to the first address; 10. The apparatus of claim 1.

4. receiving metadata from the host into the at least one second register via the at least one non-data connection includes receiving a plurality of metadata into the at least one second register, the plurality of metadata including first metadata corresponding to a first write operation and second metadata corresponding to a second write operation, the plurality of metadata corresponding to a plurality of memory addresses of a page of the memory array; storing the metadata within the second portion of the memory array includes writing the plurality of metadata from the at least one second register into the page of the memory array to complete the first write operation and the second write operation.

10. The apparatus of claim 1.

5. The apparatus of claim 1 , wherein the metadata includes an error correction code (ECC).

6. The apparatus of claim 1 , wherein the metadata includes a signature for authenticating the data corresponding to the metadata.

7. 2. The apparatus of claim 1, wherein the at least one non-data connection comprises a data mask inversion (DMI) portion of the channel, the number of connections in the data mask inversion (DMI) portion being less than the number of connections in the at least one data connection.

8. 2. The apparatus of claim 1, wherein the at least one non-data connection comprises a read data strobe (RDQS) portion of the channel, the number of connections of the read data strobe (RDQS) portion being less than the number of connections of the at least one data connection.

9. the at least one second register having a first portion associated with a first column address and a second portion associated with a second column address; receiving the metadata includes receiving the metadata in the first portion or the second portion based on a memory address for the data associated with the metadata specified by a write command received by the memory I / O module corresponding to the data.

10. The apparatus of claim 1.

10. the at least one second register comprises a first portion and a second portion; receiving the metadata includes receiving the metadata in the first portion or the second portion based on an indicator specified by a write command received by the memory I / O module.

10. The apparatus of claim 1.

11. receiving data in at least one first register from a host via at least one data connection in the memory device; receiving, in the memory device, metadata from the host via at least one non-data connection into at least one second register; storing, by the memory device, the data from the at least one first register in a first portion of a memory array; storing, by the memory device, the metadata from the at least one second register within a second portion of the memory array; A method comprising:

12. retrieving said data from said memory array into said at least one first register; retrieving the metadata from the memory array into the at least one second register; transmitting the data from the at least one first register to the host via the at least one data connection; transmitting the metadata from the at least one second register to the host over the at least one non-data connection; The method of claim 11 further comprising:

13. receiving a first address over at least one second non-data connection corresponding to the data; further comprising storing the data in the first portion of the memory array based on the first address; storing the metadata in the second portion of the memory array at a second address corresponding to the first address; The method of claim 11.

14. receiving metadata from the host into the at least one second register via the at least one non-data connection includes receiving a plurality of pieces of metadata into the at least one second register, the plurality of pieces of metadata including first metadata corresponding to a first write operation and second metadata corresponding to a second write operation, the plurality of pieces of metadata corresponding to a plurality of memory addresses of a page of the memory array; storing the metadata within the second portion of the memory array includes writing the plurality of metadata from the at least one second register into the page of the memory array to complete the first write operation and the second write operation; The method of claim 11.

15. The method of claim 11 , wherein the metadata includes an error correction code (ECC).

16. The method of claim 11 , wherein the metadata includes a signature that authenticates the data corresponding to the metadata.

17. 12. The method of claim 11, wherein the at least one non-data connection comprises a data mask inversion (DMI) portion of a channel, the number of connections in the data mask inversion (DMI) portion being less than the number of connections in the at least one data connection.

18. 12. The method of claim 11, wherein the at least one non-data connection comprises a read data strobe (RDQS) portion of a channel, and wherein the number of connections in the read data strobe (RDQS) portion is less than the number of connections in the at least one data connection.

19. at least one second register having a first portion associated with a first column address and a second portion associated with a second column address; receiving the metadata includes receiving the metadata in the first portion or the second portion based on a memory address for the data associated with the metadata specified by a write command corresponding to the data; The method of claim 11.

20. the at least one second register comprises a first portion and a second portion; receiving the metadata includes receiving the metadata in the first portion or the second portion based on an indicator specified by a write command; The method of claim 11.

21. 1. An apparatus comprising: a memory array having a first portion and a second portion; Memory I / O module and wherein the memory I / O module is coupled to the memory array; configured to communicate with a host over a channel including a plurality of connections, including at least one data connection and at least one non-data connection; at least one first register and at least one second register; The memory I / O module: Retrieving data from the first portion of the memory array into the at least one first register; retrieving metadata from the second portion of the memory array into the at least one second register; transmitting the data from the at least one first register to the host over the at least one data connection; transmitting the metadata from the at least one second register to the host over the at least one non-data connection; and The apparatus is further configured to perform operations including:

22. 22. The apparatus of claim 21, wherein the data and the metadata are retrieved simultaneously during a single read command.

23. The memory I / O module: receiving a first address over at least one second non-data connection corresponding to the data; and further configured to perform operations including: retrieving the data from the first portion of the memory array based on the first address; retrieving the metadata from the second portion of the memory array from a second address corresponding to the first address; 22. The apparatus of claim 21.

24. retrieving metadata from the second portion of the memory array into the at least one second register includes retrieving a plurality of pieces of metadata during a single page operation, the plurality of pieces of metadata including first metadata corresponding to a first read operation and second metadata corresponding to a second read operation, the plurality of pieces of metadata corresponding to a plurality of memory addresses of a page of the memory array; transmitting metadata from the at least one second register to the host over the at least one non-data connection includes transmitting the plurality of metadata.

22. The apparatus of claim 21.

25. 22. The apparatus of claim 21, wherein the metadata includes an error correction code (ECC).

26. 22. The apparatus of claim 21, wherein the metadata includes a signature that authenticates the data corresponding to the metadata.

27. 22. The apparatus of claim 21, wherein the at least one non-data connection comprises a data mask inversion (DMI) portion of the channel, the number of connections in the data mask inversion (DMI) portion being less than the number of connections in the at least one data connection.

28. 22. The apparatus of claim 21, wherein the at least one non-data connection comprises a read data strobe (RDQS) portion of the channel, the number of connections of the read data strobe (RDQS) portion being less than the number of connections of the at least one data connection.

29. the at least one second register having a first portion associated with a first column address and a second portion associated with a second column address; retrieving the metadata includes retrieving the metadata into the first portion or the second portion based on a memory address for the data associated with the metadata specified by a read command received by the memory I / O module corresponding to the data.

22. The apparatus of claim 21.

30. the at least one second register comprises a first portion and a second portion; retrieving the metadata includes retrieving the metadata into the first portion or the second portion based on an indicator specified by a read command received by the memory I / O module.

22. The apparatus of claim 21.

31. 1. A method comprising: Retrieving data from a first portion of the memory array into at least one first register; retrieving metadata from a second portion of the memory array into at least one second register; transmitting said data from said at least one first register to a host over at least one data connection; transmitting the metadata from the at least one second register to the host over at least one non-data connection; A method comprising:

32. 32. The method of claim 31 , wherein the data and the metadata are retrieved simultaneously during a single read command.

33. receiving a first address over at least one second non-data connection corresponding to the data; further comprising retrieving the data from the first portion of the memory array based on the first address; retrieving the metadata from the second portion of the memory array from a second address corresponding to the first address; 32. The method of claim 31 .

34. retrieving metadata from the second portion of the memory array into the at least one second register includes retrieving a plurality of pieces of metadata during a single page operation, the plurality of pieces of metadata including first metadata corresponding to a first read operation and second metadata corresponding to a second read operation, the plurality of pieces of metadata corresponding to a plurality of memory addresses of a page of the memory array; transmitting metadata from the at least one second register to the host over the at least one non-data connection includes transmitting the plurality of metadata.

32. The method of claim 31 .

35. 32. The method of claim 31 , wherein the metadata includes an error correction code (ECC).

36. 32. The method of claim 31, wherein the metadata includes a signature that authenticates the data corresponding to the metadata.

37. 32. The method of claim 31 , wherein the at least one non-data connection comprises a data mask inversion (DMI) portion of a channel, the number of connections in the data mask inversion (DMI) portion being less than the number of connections in the at least one data connection.

38. 32. The method of claim 31 , wherein the at least one non-data connection comprises a read data strobe (RDQS) portion of a channel, and wherein the number of connections in the read data strobe (RDQS) portion is less than the number of connections in the at least one data connection.

39. the at least one second register having a first portion associated with a first column address and a second portion associated with a second column address; retrieving the metadata includes retrieving the metadata into the first portion or the second portion based on a memory address for the data associated with the metadata specified by a read command corresponding to the data.

32. The method of claim 31 .

40. the at least one second register comprises a first portion and a second portion; retrieving the metadata includes retrieving the metadata in the first portion or the second portion based on an indicator specified by a read command.

32. The method of claim 31 .

41. 1. An apparatus comprising: Host device configured to communicate with a memory device over a channel - Patent Application 20070122997 Equipped with The host device comprises a memory controller coupled to the channel, the memory controller comprising: transmitting data between the memory controller and at least one first register of the memory device via at least one data connection of the channel; transmitting metadata between the memory controller and at least one second register of the memory device over at least one non-data connection of the channel; configured to perform operations including Device.

42. The operation is signaling a read command on the channel specifying at least one read address for retrieving the data from the memory device and for retrieving the metadata; 42. The apparatus of claim 41, comprising:

43. 43. The apparatus of claim 42, wherein the at least one read address identifies the at least one second set of registers that stores the metadata.

44. 43. The apparatus of claim 42, wherein the read command includes an indicator specifying the set of the at least one second register in which to store the metadata.

45. The operation is signaling a write command over the channel specifying a write address at which to store the data and to transmit the data to the memory device; 42. The apparatus of claim 41, comprising:

46. 46. ​​The apparatus of claim 45, wherein the write address identifies the set of at least one second register that stores the metadata.

47. 46. ​​The apparatus of claim 45, wherein the write command includes an indicator that specifies one of the at least one second register in which to store the metadata.

48. 1. A method comprising: transmitting, by a memory controller of a host device coupled to a memory device by a channel, data to at least one first register of the memory device via at least one data connection of the channel; transmitting, by the memory controller of the host device, metadata to at least one second register of the memory device over at least one non-data connection of the channel; A method comprising:

49. signaling, by the memory controller, a read command on the channel specifying a read address for retrieving the data from the memory device and retrieving the metadata.

49. The method of claim 48, further comprising:

50. 50. The method of claim 49, wherein the read address identifies the set of at least one second register that stores the metadata.

51. 50. The method of claim 49, wherein the read command includes an indicator specifying the set of at least one second register in which to store the metadata.

52. signaling a write command over the channel specifying a write address at which the data is to be stored and at which the data is to be transmitted to the memory device; 49. The method of claim 48, further comprising:

53. 53. The method of claim 52, wherein the write address identifies the set of at least one second register that stores the metadata.

54. 53. The method of claim 52, wherein the write command includes an indicator that specifies one of the at least one second register in which to store the metadata.

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