Single-layer capacitor

Abstract

The single-layer capacitor can include a substrate having a first surface and a second surface opposite the first surface. A resistive layer can be formed on at least a portion of the first surface of the substrate. A first conductive layer can be formed on at least a portion of the resistive layer. A second conductive layer can be formed on at least a portion of the second surface of the substrate. Thus, the single-layer capacitor can include a resistor and a capacitor formed in series with each other.

Description

[Technical Field]

[0001] Related Applications This application claims priority to U.S. Provisional Patent Application No. 63 / 418,107, filed October 21, 2022, which is incorporated herein by reference. [Background technology]

[0002] Single-layer capacitors (SLCs) offer various advantages, such as temperature stability, generally high breakdown voltage, and low leakage current. However, the frequency response of SLCs generally can limit their end use. Increasing the equivalent series resistance (ESR) can broaden the application of SLCs. Summary of the Invention

[0003] According to one embodiment of the present disclosure, a single-layer capacitor can include a substrate having a first surface and a second surface opposite the first surface. A resistive layer can be formed on at least a portion of the first surface of the substrate. A first conductive layer can be formed on at least a portion of the resistive layer. A second conductive layer can be formed on at least a portion of the second surface of the substrate.

[0004] According to another embodiment of the present disclosure, a method for forming a single layer capacitor can include depositing a resistive layer on at least a portion of a first surface of a substrate; depositing a first conductive layer on at least a portion of the resistive layer; and depositing a second conductive layer on at least a portion of a second surface of the substrate, the second surface opposite the first surface.

[0005] According to another embodiment of the present disclosure, an embedded capacitor assembly can include a circuit board substrate having a mounting surface and a single-layer capacitor at least partially embedded within the circuit board substrate. The single-layer capacitor can include a substrate having a first surface opposite a second surface, a resistive layer formed on at least a portion of the first surface, a first conductive layer formed on at least a portion of the resistive layer, and a second conductive layer formed on at least a portion of the second surface.

[0006] A full and enabling disclosure of the present invention, including the best mode thereof, directed to one of ordinary skill in the art, is set forth more particularly in the remainder of the specification, which makes reference to the accompanying drawings. [Brief explanation of the drawings]

[0007] [Figure 1A] FIG. 1 is a side view of a capacitor according to aspects of the present disclosure. [Figure 1B] FIG. 10 is a side view of another capacitor according to aspects of the present disclosure. [Figure 1C] FIG. 10 is a side view of yet another capacitor according to aspects of the present disclosure. [Figure 2A] FIG. 1 is a top view of a capacitor according to aspects of the present disclosure. [Figure 2B] FIG. 2B is a side view of the capacitor of FIG. 2A. [Figure 3] 1 illustrates an embedded capacitor assembly including a capacitor embedded in a circuit board substrate according to aspects of the present disclosure. [Figure 4A] FIG. 1 is an electrical diagram of a capacitor according to an aspect of the present disclosure. [Figure 4B] FIG. 1 is an electrical diagram of a high electron mobility transistor incorporating multiple capacitors according to an aspect of the present disclosure. [Figure 5] 1 is a flowchart of a method for forming a capacitor according to an aspect of the present disclosure. DETAILED DESCRIPTION OF THE INVENTION

[0008] Repeat use of reference characters in the present specification and drawings is intended to represent same or analogous features or elements of the invention.

[0009] It should be understood by those skilled in the art that this description is merely a description of exemplary embodiments and is not intended as a limitation of the broader aspects of the present invention, which broader aspects are embodied in the exemplary configurations.

[0010] Generally speaking, the present invention is directed to a single-layer capacitor having a resistive layer. For example, a single-layer capacitor (SLC or "capacitor" as used herein) can include a substrate, a resistive layer formed on at least a portion of a first surface of the substrate, a first conductive layer formed on at least a portion of the resistive layer, and a second conductive layer formed on at least a portion of a second surface of the substrate opposite the first surface of the substrate.

[0011] The effective circuit formed by a capacitor with a resistive layer is a resistor in series with the capacitor, allowing the capacitor to have a higher equivalent series resistance (ESR). Increasing the ESR reduces the Q factor or quality factor of the capacitor, which can broaden the capacitor's frequency response. The broadened frequency response of an SLC can improve the performance of bias lines for active radio frequency (RF) devices, for example, by providing a filtered voltage to the active RF device. It will be understood that the quality factor or Q factor is the reactance of a capacitor divided by the ESR of the capacitor.

[0012] Additionally or alternatively, the broadened frequency response due to increased ESR can enhance the performance of SLCs in RF shunt and noise filtering applications. For example, a bias bank for an RF active device utilizing one or more SLCs described herein can have a reduced component count compared to, for example, a bias bank that does not utilize an SLC with a resistive layer described herein. Reducing the number of components in the bias bank can increase the reliability and size of the bias bank, and improve the active device performance of the bias bank. Other applications may include VCOs, mixers, and cascaded amplifier voltage supplies.

[0013] Furthermore, lowering the Q factor of a capacitor can increase its frequency range and thus the capacitor's usefulness in broadband applications. Lowering the Q factor also facilitates the miniaturization of the capacitor.

[0014] As described above, a single-layer capacitor can include a substrate and a resistive layer formed on the substrate. In some embodiments, the substrate can be formed from a material having a dielectric constant (K) of less than about 30, in some embodiments less than about 25, in some embodiments less than about 20, and in some embodiments less than about 15, as measured in accordance with ASTM D2520-13 at an operating temperature of 25°C and a frequency of 500 MHz. However, in other embodiments, materials having a dielectric constant greater than 30 can be used to achieve higher frequencies and / or smaller components. For example, in such embodiments, the dielectric constant can range from about 30 to about 120 or more, in some embodiments from about 50 to about 100, and in some embodiments from about 70 to about 90, as determined in accordance with ASTM D2520-13 at an operating temperature of 25°C and a frequency of 500 MHz.

[0015] In still other embodiments, the substrate may be formed from a material having a relatively high dielectric constant (K), such as from about 100,000 to about 40,000, in some embodiments from about 50,000 to about 30,000, and in some embodiments, from about 100 to about 20,000.

[0016] The substrate may comprise one or more suitable ceramic materials. Suitable materials are generally electrically insulating and thermally conductive. For example, in some embodiments, the substrate may comprise sapphire, ruby, alumina (Al2O3), aluminum nitride (AlN), beryllium oxide (BeO), aluminum oxide (Al2O3), boron nitride (BN), silicon (Si), silicon carbide (SiC), silica (SiO2), silicon nitride (Si3N4), gallium arsenide (GaAs), gallium nitride (GaN), zirconium dioxide (ZrO2), mixtures thereof, oxides and / or nitrides of such materials, or any other suitable ceramic material. Further exemplary ceramic materials include barium titanate (BaTiO3), calcium titanate (CaTiO3), zinc oxide (ZnO), ceramics including low-fire glasses, or other glass-bonded materials.

[0017] Specific examples of high-dielectric-constant materials include, for example, NPO(COG) (up to about 100), X7R (about 3,000 to about 7,000), X7S, Z5U, and / or Y5V materials. It should be understood that the foregoing materials are described by industry-accepted definitions, some of which are standard classifications established by the Electronic Industries Association (EIA) and should therefore be recognized by those skilled in the art. For example, such materials may include ceramics. Such materials may include perovskites such as barium titanate and related solid solutions (e.g., barium-strontium titanate, barium calcium titanate, barium titanate zirconate, barium strontium titanate zirconate, barium calcium titanate zirconate, etc.), lead titanate and related solid solutions (e.g., lead zirconate, lead lanthanum zirconate), and bismuth sodium titanate. In one particular embodiment, for example, perovskites of the formula Ba x Sr1-x Barium strontium titanate ("BSTO") of TiO3 may be used, where x is 0 to 1, in some embodiments from about 0.15 to about 0.65, and in some embodiments from about 0.25 to about 0.6. Other suitable perovskites include, for example, Ba x Ca 1-x TiO3 (where x is from about 0.2 to about 0.8, and in some embodiments, from about 0.4 to about 0.6), Pb x Zr 1-x TiO3 ("PZT") (where x ranges from about 0.05 to about 0.4), lead lanthanum zirconium titanate ("PLZT"), lead titanate (PbTiO3), barium calcium zirconium titanate (BaCaZrTiO3), sodium nitrate (NaNO3), KNbO3, LiNbO3, LiTaO3, PbNb2O6, PbTa2O6, KSr(NbO3), and NaBa2(NbO3)5KHb2PO4. Additional complex perovskites may include A[B1 1 / 3 B2 2 / 3 ]O3 material, where A is Ba x Sr 1-x (x can be a value between 0 and 1), and B1 is Mg y Zn 1-y (where y can be a value between 0 and 1), and B2 is Ta z Nb 1-z where z can be a value between 0 and 1. In one particular embodiment, the dielectric material may include a titanate.

[0018] As used herein, a layer "formed on" an object can include a layer formed directly on the object, as well as a layer formed on one or more intermediate layers between the layer and the object. Additionally, formed "on" a bottom surface refers from the center outward of the component.

[0019] A resistive layer of the capacitor can be formed on at least a portion of the surface of the substrate. In some embodiments, the resistive layer can be a thin film resistor. The thin film resistor can be configured to exhibit various resistance values, as desired. For example, in some embodiments, the thin film resistor can have a resistance in the range of about 1 Ω to about 2,000 Ω, in some embodiments, about 2 Ω to about 1,000 Ω, in some embodiments, about 5 Ω to about 750 Ω, in some embodiments, about 10 Ω to about 500 Ω, and in some embodiments, about 25 Ω to about 400 Ω.

[0020] The resistive layer of the thin film resistor may be formed using various thin film techniques as further described herein. The resistive layer of the thin film resistor may be formed from various suitable resistive materials. For example, the resistive layer may include tantalum nitride (TaN), silicon chromium (SiCr), nickel chromium (NiCr), tantalum aluminide, chromium silicon, titanium nitride, titanium tungsten, tantalum tungsten, oxides and / or nitrides of such materials, and / or any other suitable thin film resistive material.

[0021] A first conductive layer of the capacitor can be formed on at least a portion of the resistive layer. The first conductive layer can be contained within a periphery of the resistive layer. The first conductive layer can be free of direct contact and / or direct electrical connection with the substrate.

[0022] The capacitor may also include an additional or second conductive layer. The second conductive layer may be formed on a surface of the substrate opposite the resistive layer. For example, the substrate may have a first surface and a second surface opposite the first surface, and the resistive layer may be formed on the first surface and the second conductive layer may be formed on the second surface.

[0023] The conductive layer may be formed from any of a variety of different metals, as known in the art. The electrode layer may be made from a metal, such as a conductive metal. Materials may include noble metals (e.g., silver, gold, palladium, platinum, etc.), base metals (e.g., copper, tin, nickel, chromium, titanium, tungsten, etc.), and the like, as well as various combinations thereof. Sputtered titanium / tungsten (Ti / W) alloys and sputtered layers of chromium, nickel, and gold may also be suitable. The electrodes may also be made from low-resistivity materials, such as silver, copper, gold, aluminum, and palladium. In one particular embodiment, the electrode layer may include nickel or an alloy thereof.

[0024] A capacitor can include a pair of terminals, individually designated a first terminal and a second terminal. The first terminal can be connected to a first conductive layer, or the first terminal can be connected to a first surface of the substrate. The second terminal can be connected to a second surface of the substrate (opposite the surface on which the resistive layer is formed), or the second terminal can be connected to a second conductive layer. As used herein, "connected to" can refer to components in direct physical contact. "Connected to" can also refer to items that are physically connected by one or an intermediate conductive layer such that the items are directly electrically connected (e.g., without a resistive or dielectric layer between them). For example, as described herein, the first terminal can be formed on a first conductive layer, and the second terminal can be formed on a second surface of the substrate, with or without a second conductive layer between the second terminal and the second surface.

[0025] In some embodiments, the first conductive layer and / or the second conductive layer can be one terminal of a pair of terminals, i.e., the first conductive layer can form the first terminal and / or the second conductive layer can form the second terminal, rather than the first conductive layer plus a separate first terminal and / or the second conductive layer plus a separate second terminal.

[0026] Thus, in some embodiments, the first terminal can include a conductive material in direct contact with the first surface of the substrate, and in other embodiments, the first terminal can include a conductive material in direct contact with a first conductive layer formed on the first surface of the substrate. Similarly, in some embodiments, the second terminal can include a conductive material in direct contact with the second surface of the substrate, and in other embodiments, the second terminal can include a conductive material in direct contact with a second conductive layer formed on the second surface of the substrate.

[0027] One or more protective layers may be formed on the substrate. For example, one or more protective layers may be formed on the first surface and / or the second surface of the substrate. In some embodiments, the first terminal and / or the second terminal may be exposed through the one or more protective layers for electrical connection. Examples of materials for the protective layer include benzocyclobutene (BCB), polyimide, silicon oxynitride, alumina (Al2O3), silica (SiO2), silicon nitride (Si3N4), epoxy, glass, or another suitable material.

[0028] Various thin film techniques can be used to form the thin film layers of the capacitor. For example, one or more of the first conductive layer, the second conductive layer, the resistive layer, and the terminal may be thin film layers of the capacitor. Examples of such techniques that may be used include chemical deposition (e.g., chemical vapor deposition), PECVD (plasma-enhanced chemical vapor deposition) processing, physical deposition (e.g., sputtering), or any other suitable deposition technique for forming thin film elements. Additional examples include any suitable patterning technique (e.g., photolithography), etching, and any other suitable subtractive technique for forming thin film elements.

[0029] The thin film layer can have a range of thicknesses. For example, the thin film layer can have a thickness that can range from about 0.001 micrometers (microns) to about 100 microns, in some embodiments, from about 0.0375 microns to about 40 microns, in some embodiments, from about 0.1 microns to about 30 microns, in some embodiments, from about 0.2 microns to about 20 microns, and in some embodiments, from about 0.4 microns to about 10 microns. For example, in some embodiments, the resistive layer can have a thickness of less than about 10 microns, in some embodiments, less than about 8 microns, in some embodiments, less than about 6 microns, and in some embodiments, less than about 4 microns.

[0030] In some embodiments, the conductive layer formed on the resistive layer may be relatively small compared to the resistive layer that defines the capacitive region. By providing a relatively small conductive layer, only a relatively small area is available for current to flow, thereby forcing the current through the resistive layer and increasing the resistance from the edges of the resistive layer into the relatively small conductive layer.

[0031] The relative size of the conductive layer compared to the resistive layer can be defined by the ratio of the area of ​​the resistive layer to the area of ​​the conductive layer. The area of ​​the resistive layer can be defined by the length of the resistive layer extending in the Y direction and the width of the resistive layer extending in the X direction. Similarly, the area of ​​the conductive layer can be defined by the length of the conductive layer extending in the Y direction and the width of the conductive layer extending in the X direction. In some embodiments, the ratio of the area of ​​the resistive layer to the area of ​​the conductive layer can be in the range of about 100:1, in the range of about 75:1, in the range of about 50:1, in the range of about 25:1, in the range of about 15:1, in the range of about 10:1, in the range of about 5:1, in the range of about 3:1, and in the range of about 1.5:1.

[0032] In some aspects of the present subject matter, the capacitor can be configured to be embedded within a circuit board substrate, such as a printed circuit board. For example, the first and second terminals can be exposed along opposing surfaces of the substrate, such as the top and bottom surfaces of the substrate, and can be contained within the periphery of each surface of the substrate.

[0033] The present subject matter further relates to an embedded capacitor assembly including a circuit board substrate, such as a printed circuit board, having a capacitor at least partially embedded therein. The circuit board substrate can be formed from any suitable material, such as FR4, polytetrafluoroethylene, etc. One or more electronic components, such as capacitors, resistors, transistors, switches, and / or other electronic components, can be attached to the circuit board substrate. As used herein, "attached to" a circuit board substrate can include any type of connection to the circuit board substrate that provides an electrical connection, such as surface mounting to a surface of the circuit board substrate, embedding within the circuit board substrate, etc.

[0034] The circuit board substrate can have a recessed opening on a mounting surface of the circuit board substrate, such as a top or bottom surface. The recessed opening can be configured to receive an electrical component to be embedded within the circuit board substrate. For example, a capacitor, such as the capacitors described herein, can be inserted into the recessed opening for embedding within the circuit board substrate. One or more conductive terminals of the capacitor can be coupled to the circuit board substrate. For example, one or more vias can be formed in, on, or through the termination to electrically connect the capacitor with the circuit board substrate and / or one or more conductive traces of one or more electronic components mounted on the circuit board substrate.

[0035] The first and second terminals of a capacitor can be formed from copper, such as by copper plating. Typically, solid copper is prone to oxidation upon exposure and may not be a suitable material for forming exposed terminations of electronic components. Therefore, solder materials, such as alloys of copper, tin, and gold, are often used to form electrical terminations of electronic components, such as capacitors. However, the present inventors have discovered that forming the first and second terminals of an embeddable capacitor from copper, for example, by plating solid copper onto a conductive layer and / or one or more surfaces of a substrate, can provide excellent electrical connections without the risk of oxidation when the capacitor is embedded within a circuit board substrate. For example, the first and second terminals can be laser drilled to form direct electrical connections with the circuit board substrate and / or additional electronic components attached to the circuit board substrate.

[0036] 1A is a side view of a single-layer capacitor 100 according to an embodiment of the present disclosure. The single-layer capacitor 100 may also be referred to herein as an SLC 100 or a capacitor 100. FIGURES 1B and 1C are side views of a capacitor 100 according to another embodiment of the present disclosure.

[0037] 1A, 1B, and 1C, capacitor 100 may include a substrate 102 having a first surface 104 and a second surface 106 opposite first surface 104. Substrate 102 may be formed from a dielectric material. In some embodiments, the dielectric material may have a relatively low dielectric constant (K), while in other embodiments, the dielectric material may have a relatively high dielectric constant.

[0038] The capacitor 100 may include a resistive layer 108 formed on at least a portion of the first surface 104 of the substrate 102. In some embodiments, the resistive layer 108 may have a thickness of less than about 10 microns. In some embodiments, the resistive layer 108 may be formed from tantalum nitride (TaN), and in other embodiments, the resistive layer 108 may be formed from chromium silicon (CrSi). The resistive layer 108 may have other thicknesses and / or may be formed from other materials as described elsewhere herein.

[0039] The capacitor 100 may further include a first conductive layer 110 formed on at least a portion of the resistive layer 108. The first conductive layer 110 may be contained within the periphery of the resistive layer 108. The first conductive layer 110 may not include direct contact and / or a direct electrical connection with the substrate 102.

[0040] The capacitor 100 may also include a second conductive layer 112 formed on the second surface 106 of the substrate 102. The second conductive layer 112 may extend across the entire second surface 106, as shown in Figures 1A, 1B, and 1C. Alternatively, the second conductive layer 112 may be offset from one or more edges of the substrate 102, similar to, for example, the resistive layer 108 and first conductive layer 110 formed on the first surface 104 of the substrate 102, such that the second conductive layer 112 extends over a portion of the second surface 106.

[0041] The pair of terminals 114, 116 can be connected to a capacitor. Each terminal of the pair of terminals can include a conductive material, such as gold, copper, another suitable metal, or other conductive material. In some embodiments, at least one of the first conductive layer 110 or the second conductive layer 112 is one terminal of the pair of terminals. For example, as shown in FIG. 1C , the first conductive layer 110 and the second conductive layer 112 can each form one terminal of the pair of terminals.

[0042] In other embodiments, only one of the first conductive layer 110 or the second conductive layer 112 may form one terminal of a pair of terminals, and in still other embodiments, neither the first conductive layer 110 nor the second conductive layer 112 may form a terminal of a pair of terminals. For example, as shown in Figures 1A and 1B, the first terminal 114 of the pair of terminals may be connected to the first conductive layer 110.

[0043] Furthermore, the substrate 102 can include a pair of end faces 120, 122, and the first terminal 114 can be located closer to one end face 122 of the pair of end faces 120, 122 than to the other end face 120 of the pair of end faces 120, 122. For example, the substrate can include a first end face 120 and a second end face 122 that face each other along the Y direction and are perpendicular to the first surface 104 and the second surface 106 of the substrate 102. As shown in FIGS. 1A and 1B , the first terminal 114 can be located closer to the second end face 122 than to the first end face 120. In other embodiments, the first terminal 114 can be located closer to the first end face 120 than to the second end face 122. In still other embodiments, the first terminal 114 can be located equidistant from the first end face 120 and the second end face 122 along the Y direction.

[0044] The second terminal 116 of the pair of terminals can be connected to the substrate 102 or the second conductive layer 112. For example, the capacitor 100 can include the second terminal 116 on the second surface 106 of the substrate 102. As shown in FIG. 1A , the second terminal 116 can be formed from a second conductive layer 112 formed on the second surface 106 of the substrate 102 opposite the first surface 104 in the Z direction. That is, the second conductive layer 112 can be the second terminal 116. Referring to FIG. 1B , in other embodiments, the second terminal 116 can be formed on the second conductive layer 112 such that the second conductive layer 112 is disposed between the second terminal 116 and the substrate 102. The second terminal 116 can be aligned with the first terminal 114 in the Z direction, as shown in FIG. 1B , or the second terminal 116 can be offset from the first terminal 114 in the Z direction. For example, the second terminal 116 may be formed closer to the first end face 120 than to the second end face 122 .

[0045] In yet other embodiments, each of the second conductive layer 112 and the second terminal 116 can be formed on the second surface 106 of the substrate 102 without the second terminal 116 being formed on the second conductive layer 112; for example, the second conductive layer 112 can be formed on a portion of the second surface 106 and the second terminal 116 can be formed on another separate portion of the second surface 106.

[0046] In any event, for capacitor 100, pairs of terminals 114, 116, whether formed separately from or by first conductive layer 110 and / or second conductive layer 112, are connected to various layers or substrates 102 of capacitor 100 such that capacitor 100 comprises a resistor and a capacitor formed in series with each other.

[0047] 2A and 2B, top and side views, respectively, of a capacitor 200 according to an embodiment of the present disclosure are provided. Similar reference numerals are used in FIGS. 2A and 2B as in FIGS. 1A, 1B, and 1C. For example, capacitor 200 includes a substrate 202 having a resistive layer 208 formed on at least a portion of a first surface 204 of substrate 202. A first conductive layer 210 is formed on at least a portion of resistive layer 208. A second conductive layer 212 is formed on at least a portion of a second surface 206 of substrate 202, where second surface 206 is opposite first surface 204.

[0048] 2A and 2B, as FIG. 2A shows first surface 204, first surface 204 is the top surface of capacitor 200. As described with respect to capacitor 100, first conductive layer 210 may be contained within periphery 209 of resistive layer 208. In the embodiment shown in FIG. 2A, first conductive layer 210, which in some embodiments may form first terminal 214, is relatively small compared to resistive layer 208, which defines the capacitive region. By providing a relatively small first conductive layer 210, only a relatively small area is available for current to flow, thereby forcing the current through resistive layer 208.

[0049] The relative size of the first conductive layer 210 compared to the resistive layer 208 may be defined by the ratio of the area of ​​the resistive layer 208 to the area of ​​the first conductive layer 210. The area of ​​the resistive layer 208 is determined by the length L of the resistive layer 208 extending in the Y direction between the first edge 224 and the second edge 226 of the substrate 202. R and a width W of the resistive layer 208 extending in the X direction between the first side edge 228 and the second side edge 230 of the substrate 202. R Similarly, the area of ​​the first conductive layer 210 can be defined by the length L of the first conductive layer 210 extending in the Y direction. C1 and the width W of the first conductive layer 210 extending in the X direction. C1In some embodiments, the ratio of the area of ​​resistive layer 208 to the area of ​​first conductive layer 210 may be in the range of about 100:1, in some embodiments in the range of about 75:1, in some embodiments in the range of about 50:1, in some embodiments in the range of about 25:1, in some embodiments in the range of about 15:1, in some embodiments in the range of about 10:1, in some embodiments in the range of about 5:1, in some embodiments in the range of about 3:1, and in some embodiments in the range of about 1.5:1.

[0050] FIG. 3 illustrates an embedded capacitor assembly 350 including a capacitor 100 embedded within a circuit board substrate 352 according to an embodiment of the present disclosure. The circuit board substrate 352 may be, for example, a printed circuit board and may be formed from any suitable material, such as FR4, polytetrafluoroethylene, or the like. The circuit board substrate 352 includes a mounting surface 354. The capacitor 100, 200 may be at least partially embedded within the circuit board substrate 352 of the assembly 350. For example, the mounting surface 354 may have a recessed opening 355 within the circuit board substrate 352. To minimize its height profile above the substrate, the capacitor 100 may be embedded within the opening 355 and attached to the circuit board substrate 352 using known techniques. For example, as described further herein, one or more vias may connect one or more terminals of the capacitor 100 with one or more conductive traces of the circuit board substrate 352 using known techniques.

[0051] The extent to which capacitor 100 is embedded depends on various factors, such as the thickness of circuit board substrate 352, the depth of opening 355, and the thickness of capacitor 100. The thickness of circuit board substrate 352 (not including attached electronic components) may, in some embodiments, be about 0.1 to about 5 millimeters, in some embodiments, about 0.2 to about 3 millimeters, and in some embodiments, about 0.4 to about 1.5 millimeters. Thus, depending on the particular thickness used, capacitor 100 may be embedded such that the exposed surfaces of first terminals 114 are substantially flush with or below mounting surface 354 of circuit board substrate 352. For example, capacitor 100 may be embedded and encapsulated within opening 355 in circuit board substrate 352. Alternatively, capacitor 100 may be embedded such that the exposed surfaces of first terminals 114 extend slightly above mounting surface 354 of circuit board substrate 352. Nevertheless, by at least partially embedding the capacitor 100 within the circuit board substrate 352, the height profile or thickness occupied by the capacitor 100 is reduced and can be controlled depending on the desired application.

[0052] It should be understood that various other electronic components may be mounted on circuit board substrate 352 as is known in the art, and that a single capacitor 100 is shown for illustrative purposes only. Additionally, while capacitor 100 shown in Figure 3 may generally be configured similarly to capacitor 100 of Figures 1A-1C, in other embodiments, the capacitor embedded in circuit board substrate 352 may be configured similarly to capacitor 200 of Figures 2A and 2B.

[0053] Referring to FIG. 3 , the first terminal 114 and the second terminal 116 are formed on opposing surfaces of the substrate 102 of the illustrated capacitor 100. For example, the first terminal 114 is formed on the first surface 104, which may be the top surface of the substrate 102, and the second terminal 116 is formed on the second surface 106, which may be the bottom surface of the substrate 102. As shown in FIG. 3 , a via 356 may extend from the first terminal 114 of the capacitor 100 toward the mounting surface 354 and connect to a conductive layer 358 formed on the mounting surface 354. The via 356 of the embedded capacitor assembly 350 may electrically connect the first terminal 114 to the first conductive layer 358, which may be, for example, a conductive trace of the circuit board substrate 352. Alternatively, the via 356 may extend toward the mounting surface 354 and connect to one or more intermediate layers (e.g., embedded within the circuit board substrate 352), which may further be electrically connected to the conductive layer 358. Via 356 may form at least a portion of the electrical connection between first terminal 114 of capacitor 100 and conductive layer 358 of embedded capacitor assembly 350. However, it should be understood that in other embodiments, terminal 114 may be exposed along mounting surface 354. In such embodiments, embedded capacitor assembly 350 may not have via 356.

[0054] In some embodiments, the circuit board substrate 352 can include multiple conductive layers 358, e.g., multiple conductive traces, and the capacitor 100 can include multiple terminals 114 exposed along the first surface 104. Multiple vias 356 can extend from the terminals to the conductive layers of the circuit board substrate 352, e.g., at least one via can extend from each one of the terminals 114 of the capacitor 100 to each one of the conductive layers 358 of the circuit board substrate 352.

[0055] Referring to FIGS. 4A and 4B, electrical diagrams illustrating capacitors 100, 200 described herein are provided. As shown in FIG. 4A, each capacitor 100, 200 includes a resistor R and a capacitor C arranged in series with one another. Referring to FIG. 4B, one or more of the exemplary capacitors 100, 200 described with respect to FIGS. 1A-2B may be used in various electrical systems or devices. For example, FIG. 4B illustrates an exemplary high electron mobility transistor (HEMT) according to aspects of the present subject matter. On the left side of the electrical diagram shown in FIG. 4B, multiple capacitors described herein, represented as R6 / C18, R5 / C10, and R14 / C32, are placed in a negative bias bank, and on the right side, multiple capacitors described herein, represented as R15 / C33, R3 / C8, and R4 / C17, are placed in a Vdd bias bank. The HEMT depicted in FIG. 4B is merely an example. It will be understood that the capacitors 100, 200 described herein may be used in a variety of applications.

[0056] Referring now to FIG. 5 , an aspect of the present subject matter is directed to a method 500 for forming a capacitor as described herein. Generally, method 500 is described herein with reference to capacitor 100 of FIGS. 1A, 1B, and 1C . However, it should be understood that the disclosed method 500 may be practiced with any suitable capacitor. Additionally, while FIG. 5 depicts steps performed in a particular order for purposes of illustration and explanation, the methods discussed herein are not limited to any particular order or arrangement. Using the disclosure provided herein, one skilled in the art will understand that various steps of the methods disclosed herein may be omitted, rearranged, combined, and / or adapted in various ways without departing from the scope of the present subject matter.

[0057] The method 500 may include depositing (502) a resistive layer 108 on at least a portion of the first surface 104 of the substrate 102 of the capacitor 100. The resistive layer 108 may have a thickness of less than about 10 microns. The resistive layer 108 may be formed from tantalum nitride, chromium silicon, or other suitable resistive materials as described herein.

[0058] The method 500 may include depositing (504) a first conductive layer 110 over at least a portion of the resistive layer 108. The first conductive layer 110 may be contained within a periphery of the resistive layer 108. The first conductive layer 110 may not include direct contact and / or a direct electrical connection with the substrate 102.

[0059] The method 500 may include depositing (506) a second conductive layer 112 on at least a portion of the second surface 106 of the substrate 102. The second surface 106 of the substrate 102 may be opposite the first surface 104 of the substrate 102.

[0060] The method 500 may optionally include depositing (508) a first terminal 114 on the first conductive layer 110. For example, as described herein, a separate first terminal 114 may be deposited on the first conductive layer 110, or the first conductive layer 110 may form the first terminal 114. The method may optionally include depositing (510) a second terminal 116 such that at least the substrate 102 and the resistive layer 108 are disposed between the first conductive layer 110 and the second terminal 116. For example, as described herein, in some embodiments, the second conductive layer 112 may form the second terminal 116. In other embodiments, the second terminal 116 may be deposited on the second conductive layer 112 such that the substrate 102, the resistive layer 108, and the second conductive layer 112 are disposed between the first conductive layer 110 and the second terminal 116. In either case, pairs of terminals 114, 116 are connected to various layers or substrates of capacitor 100 such that a resistor and a capacitor are formed in series with each other. Purpose

[0061] The capacitors described herein are useful in a variety of applications. For example, the single-layer capacitors described herein may be particularly useful for filtering front-end preamplifiers, HEMT V-gs, Vdd, hybrid package components, and internal package semiconductors. Furthermore, the capacitors exhibit excellent performance at high frequencies, such as frequencies above 20 GHz, and thus may be useful in devices that process wideband, high-frequency signals. Exemplary devices include mobile devices (e.g., cell phones, tables, etc.), cell phone towers, receiver optical subassemblies (ROSAs), transmit optical subassemblies (TOSAs), and other RF communication devices. Such RF devices may be particularly useful in military and space applications.

[0062] These and other modifications and variations of the present invention may be practiced by those skilled in the art without departing from the spirit and scope of the present invention. In addition, it should be understood that aspects of the various embodiments may be interchanged in whole or in part. Furthermore, those skilled in the art will appreciate that the foregoing description is merely illustrative and is not intended to limit the invention as further described in such appended claims. [Explanation of symbols]

[0063] 100 Single-layer capacitor 102 Base material 104 First Surface 106 Second Surface 108 Resistance layer 110 First conductive layer 112 second conductive layer 114 First terminal 116 Second terminal 120 first end face 122 Second end face 200 capacitors 202 Base material 204 First Surface 206 Second Surface 208 Resistance layer 209 Periphery 210 First conductive layer 212 second conductive layer 214 First Terminal 224 First Edge 226 Second Edge 228 First Side Edge 230 Second Side Edge 350 Embedded Capacitor Assembly 352 Circuit base material 354 Mounting surface 355 Opening 356 Beer 358 Conductive Layer

Claims

1. a substrate having a first surface and a second surface opposite the first surface; a resistive layer formed on at least a portion of the first surface of the substrate; a first conductive layer formed on at least a portion of the resistive layer; a second conductive layer formed on at least a portion of the second surface of the substrate; and A single-layer capacitor comprising:

2. a first terminal connected to the first conductive layer; a second terminal connected to the second conductive layer; 10. The single layer capacitor of claim 1 further comprising:

3. 10. The single layer capacitor of claim 1, wherein the resistive layer has a thickness of less than about 10 microns.

4. 10. The single layer capacitor of claim 1, wherein the resistive layer is formed from tantalum nitride.

5. 10. The single layer capacitor of claim 1, wherein the resistive layer is formed from chrome silicon.

6. a first terminal connected to the first conductive layer; a second terminal connected to the first surface of the substrate; 10. The single layer capacitor of claim 1 further comprising:

7. 10. The single layer capacitor of claim 1, wherein the ratio of the area of ​​the resistive layer to the area of ​​the first conductive layer is at least about 1.5:

1.

8. 10. The single layer capacitor of claim 1, wherein the ratio of the area of ​​the resistive layer to the area of ​​the first conductive layer is at least about 10:

1.

9. 10. The single layer capacitor of claim 1, wherein the ratio of the area of ​​the resistive layer to the area of ​​the first conductive layer is at least about 20:

1.

10. depositing a resistive layer on at least a portion of a first surface of the substrate; depositing a first conductive layer over at least a portion of the resistive layer; depositing a second conductive layer on at least a portion of a second surface of the substrate, the second surface being opposite the first surface; 1. A method for forming a single layer capacitor, comprising:

11. depositing a first terminal such that the first terminal is connected to the first conductive layer; depositing a second terminal such that the second terminal is connected to the second conductive layer; The method of claim 10 further comprising:

12. depositing a first terminal such that the first terminal is connected to the first conductive layer; depositing a second terminal such that the second terminal is connected to the substrate; The method of claim 10 further comprising:

13. a circuit board substrate having a mounting surface; a single layer capacitor at least partially embedded within the circuit board substrate, a substrate having a first surface opposite a second surface; a resistive layer formed on at least a portion of the first surface; a first conductive layer formed on at least a portion of the resistive layer; a second conductive layer formed on at least a portion of the second surface; and a single-layer capacitor comprising:

1. An embedded capacitor assembly comprising:

14. The embedded capacitor assembly of claim 13 , wherein the single layer capacitor further comprises a first terminal connected with the first conductive layer.

15. 14. The embedded capacitor assembly of claim 13, further comprising at least one via connected with a first terminal, said at least one via extending toward said mounting surface of said circuit board substrate.

16. The embedded capacitor assembly of claim 15 , wherein the circuit board substrate further includes a conductive layer, and the at least one via is connected to the conductive layer of the circuit board substrate.

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