A page rinse scheme that keeps directory pages exclusive within a single complex.

Abstract

The method includes storing an entry in a cache directory that associates the memory region with an exclusive coherency state, and, in response to a memory access directed to the memory region, sending a demotion superprobe to convert at least one cache line of the memory region from the exclusive coherency state to a shared coherency state.

Description

[Background technology]

[0001] Modern computing systems typically have multiple central processing units (CPUs) that include and rely on multiple caches in a cache hierarchy to improve processor and memory performance. Compared to main memory, caches are smaller, faster memory devices that store frequently accessed data so that the data can be accessed with low latency. Such cache devices are often implemented in static random access memory (SRAM) and typically reside between the processing unit issuing the memory request and the main memory device. A memory-side cache is a dedicated cache attached to a specific memory device or partition of memory that caches data written to and read from the memory device by other devices.

[0002] In multi-node computer systems, special precautions must be taken to maintain coherency of data being used by different processing nodes. For example, when a processor attempts to access data at a memory address, it must first determine whether the data is stored and modified in another cache. To implement this cache coherency protocol, caches typically include several status bits that indicate the status of a cache line to maintain data coherency across the system. For example, one common coherency protocol is the "MOESI" protocol, where each letter represents a state of a cache line. These states are: the cache line is modified (M); the cache line is exclusive (E) or shared (S); or the cache line is invalid (I). The owned (O) state indicates that the line has been modified in one cache, that a shared copy may exist in another cache, and that the data in memory is stale. Each cache line includes status bits in the cache directory that track cache lines currently in use by the system and indicate which MOESI state the line is in.

[0003] Managing a cache directory scheme in a multiprocessor system becomes difficult due to the various types of processing demands and the increasing size of caches and main memory.

[0004] The embodiments illustrated in the accompanying drawings herein are shown by way of example and not by way of limitation. [Brief explanation of the drawings]

[0005] [Figure 1] FIG. 1 is a block diagram of an embodiment of a computing system. [Figure 2] FIG. 1 is a block diagram of an embodiment of a core complex. [Figure 3]FIG. 1 is a block diagram of an embodiment of a multi-CPU processor system. [Figure 4] FIG. 1 is a block diagram of some embodiments of a processor system. [Figure 5] FIG. 1 is a flow diagram of a data fetch process in a processor system without demote superprobes enabled, according to an embodiment. [Figure 6] FIG. 10 is a flow diagram of a data fetching process in a processor system with demote superprobes enabled, according to an embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0006] In the following description, numerous specific details are set forth, such as examples of particular systems, components, methods, etc., to provide a thorough understanding of the embodiments. However, it will be apparent to those skilled in the art that at least some embodiments may be practiced without these specific details. In other instances, well-known components or methods are not described in detail or are presented in simplified block diagram form to avoid unnecessarily obscuring the embodiments. Thus, the specific details set forth are for illustrative purposes only. Particular embodiments may vary from these illustrative details and still be considered to be within the scope of the invention.

[0007] Computer systems typically use main memory formed from inexpensive, high-density dynamic random access memory (DRAM) chips. However, DRAM chips suffer from relatively long access times. To improve performance, data processors typically include at least one local, high-speed memory known as a cache. In multi-core data processors, each data processor core may have its own dedicated upper-level cache, while lower-level caches are shared by the data processor cores. For example, a typical configuration includes two data processor cores, each with a dedicated L1 cache and shared L2 and L3 caches.

[0008] In more advanced computing systems, each multicore processor may itself be interconnected with one or more other multicore processors using high-speed data links to form a data processing fabric. Within this data processing fabric, individual multicore processors are interconnected with each other and with their own local memories. All local memories together form a memory space available to any processor. However, because the memory is physically distributed, the memory access time seen by each processor depends on whether the memory is local or remote. This architecture is therefore known as a non-uniform memory access (NUMA) architecture.

[0009] In computer systems using NUMA architectures, special precautions must be taken to maintain coherency of data that may be used by different processing nodes. For example, when a processor attempts to access data at a memory address, the processor must first determine whether the data is stored and modified in another cache. To implement this cache coherency protocol, caches typically include several status bits that indicate the status of a cache line to maintain data coherency across the system. According to the MOESI protocol, each cache line includes status bits that indicate which MOESI state the line is in, including bits indicating that the cache line is modified (M), that the cache line is exclusive (E) or shared (S), or that the cache line is invalid (I). The owned (O) state indicates that the line is modified in one cache, that a shared copy may exist in another cache, and that the data in memory is stale.

[0010] To maintain coherency, these systems use "probes" to communicate between various caches within a computer system. A "probe" is a message passed from a coherency point (e.g., a coherency master or slave) within a computer system to one or more caches within the computer system to determine whether the cache has a copy of a data block and, optionally, indicate the state in which the cache should place the data block. After receiving a probe, a processing node responds to the probe by taking appropriate action.

[0011] In one embodiment, a memory access request directed to memory is forwarded to a cache directory, where a lookup of the requested address is performed to determine which caches have the data cached. Probes can then be sent to those caches to take appropriate action to maintain coherency. For example, the cache directory may contain information indicating that various subsystems contain shared copies of a data block. In response to a command for exclusive access to that block, an invalidation probe may be communicated to other sharing subsystems, allowing them to invalidate their respective copies of the block.

[0012] The bandwidth associated with the network interconnecting processing nodes can quickly become a performance limiting factor, especially in systems employing a large number of processors or when a large number of probes are sent in a short period of time. In such systems, the cache directory is used as a probe filter to reduce bandwidth requirements by filtering out unnecessary probes. For example, if a cache line is designated as read-only, the memory controller associated with the requesting processor core does not need to send a probe to determine whether another processing node with a copy of the cache line has modified the data. However, while probe filters can reduce system traffic and access latency, they can consume a large amount of storage space to maintain the state of all cache lines in the system. Furthermore, if the size of memory that needs to be looked up is too large, the probe filter can add a clock cycle delay between the access request and the determination that a probe does not need to be issued.

[0013] Some embodiments employ a region-based probe filter design as a compromise between area (and related issues such as power consumption, timing, yield, etc.) and accuracy. As the number of CPUs, their respective caches, and cache sizes increase, cache directories also grow to track a larger number of entries. One embodiment of the cache directory is accessed cache line by cache line to determine where the line is cached in the system and the line's current state to properly filter snoops upon receiving a memory request. In contrast, a region-based probe filter reduces the amount of chip area consumed by the cache directory by tracking regions of memory corresponding to groups of cache lines in the system, rather than single cache lines. In this way, decisions can be made collectively for entire groups of cache lines. In one embodiment, each region in the region-based probe filter is associated with one of the following coherency states:

[0014] Exclusive: All lines within a region are owned by a single core complex.

[0015] Shared: Multiple core complexes have lines within a region. The same line may be shared between multiple core complexes (true sharing), or multiple core complexes may each own different lines in the same region (false sharing).

[0016] Clean: Cannot be exclusive (e.g., "clean shared" (CS)) and is not modified against the backing data in memory.

[0017] Dirty: Can be exclusive or shared (e.g., "dirty exclusive" (DE) or "dirty shared" (DS)). Dirty lines are known or suspected to be dirty because they have been modified and may have changed without the knowledge of the probe filter.

[0018] However, the region-based probe filter design can introduce performance issues when clean data is widely shared among multiple core complexes due to the lack of line-by-line precision in coherency state tracking. A core complex brings a block of data to its cache subsystem by issuing a data fetch opcode (e.g., RdBlkL), which attempts to return an exclusive line whenever possible. However, a dedicated line may be silently modified (with its coherency state upgraded to M) without the probe filter's knowledge.

[0019] If the region is subsequently accessed from another core cache complex, the region-based probe filter cannot determine whether the block of data is clean or dirty due to a lack of line-by-line fidelity. Therefore, probes are issued to maintain accuracy unless a supporting line-based probe filter entry is available. While systems can include line-based probe filters, these are typically sized for communication variables and are thrashed by workloads with large memory footprints. The unavailability of a line-based probe filter leads to the generation of multicast probes when the region transitions to the "shared dirty" (DS) state. These probes and probe responses can cause bottlenecks in cross-die or socket links, thereby limiting performance as the design scales. In many applications, many of the probes are unnecessary because the requested lines remain clean. A widely shared clean workload can trigger a large number of multicast probes because at least one line in the region is presumed to be dirty.

[0020] In one embodiment, a computing system implements demotion superprobes to mitigate this problem. A superprobe is a probe directed to multiple destinations (e.g., all lines of a region). In such a system, a specific trigger condition preceding the above scenario may cause a demotion superprobe to be sent to any cache containing lines in the entire region where the trigger condition was detected. The demotion superprobe changes any “exclusive” (E) cache lines of the region to “shared” (S) cache lines without changing any other coherency states. The demotion superprobe also determines whether any lines in the region are “dirty” (D), and the coherency state of the region is updated accordingly in the region-based probe filter. If the demotion superprobe finds any dirty lines in the region, the coherency state of the region is corrected to a “modified shared” (MS) state. If no dirty lines are found, the region state is corrected to a “clean shared” (CS) state. Thus, the generation of excessive multicast probes is avoided for regions that are "clean shared" (CS), but probes are still appropriately generated for "modified shared" (MS) regions that are known to have modified lines.

[0021] 1 is a block diagram of one embodiment of a computing system 100 that implements a region-based probe filter with demoting superprobes. Computing system 100 includes multiple core complexes 105A-105N and multiple home nodes 130A-130N. Computing system 100 also includes an input / output (I / O) interface 120, a data fabric / bus 125, and a network interface 135. In other embodiments, computing system 100 may include other components and / or be arranged in other configurations.

[0022] In one embodiment, each core complex 105A-105N includes a processing component, such as one or more processor cores or other dedicated processing components. Each processor core within a core complex 105A-105N includes a cache subsystem with one or more levels of cache. In one embodiment, the cache subsystem includes a shared cache connected to each core complex 105A-105N (e.g., L3 cache 230 in FIG. 2 ). In some embodiments, one or more core complexes 105A-105N may include a data-parallel processor with a highly parallel architecture, such as one or more of a graphics processing unit (GPU), a digital signal processor (DSP), a field programmable gate array (FPGA), an application-specific integrated circuit (ASIC), etc. As used herein, a “core complex” may also be referred to as a “processing node,” a “CPU,” or a “CPU complex.”

[0023] In one embodiment, home node 130 may include one or more of a coherent slave, a cache directory, and a memory controller coupled to any number and type of memory devices (not shown). For example, the memory devices coupled to home node 130 may include dynamic random access memory (DRAM), static random access memory (SRAM), NAND flash memory, NOR flash memory, ferroelectric random access memory (FeRAM), etc.

[0024] I / O (input / output) interface 120 represents any number and type of I / O interfaces, such as, but not limited to, various types of Peripheral Component Interconnect (PCI) buses, Gigabit Ethernet (GBE) buses, Universal Serial Buses (USB), specialized processors (e.g., platform security processors, graphics processors), and system management logic. Various types of peripheral devices can be coupled to I / O interface 120. Such peripheral devices include (but are not limited to) displays, keyboards, mice, printers, scanners, joysticks, other types of game controllers, media recording devices, external storage devices, network interface cards, etc.

[0025] In various embodiments, computing system 100 may be a server, a desktop computer, a laptop, a mobile device, a game console, a streaming device, a wearable device, or any of a variety of other types of computing systems or devices. The number, orientation, and types of components shown in computing system 100 are exemplary only and may vary from embodiment to embodiment based on the application and system architecture.

[0026] FIG. 2 is a block diagram of one embodiment of a core complex 200, such as core complexes 105A-105N of FIG. 1. In one embodiment, core complex 200 may include four processor cores 210A-210D and a cache subsystem including L1 caches 215A-215D, L2 caches 220A-220D, and L3 cache 230. The cache subsystem may include high-speed cache memory (e.g., L1 caches 215A-215D, L2 caches 220A-220D, and L3 cache 230) configured to store blocks of data (not shown). As used herein, a "block" is a set of bytes stored in contiguous memory locations within the cache memory and treated as a unit for coherency purposes. Additionally, the terms "cache block," "block," "cache line," and "line" are interchangeable herein. In some embodiments, a block may also be the unit of cache allocation and deallocation. The block can be retrieved from other caches in the system, such as from other core complexes (e.g., core complexes 105A-105N in FIG. 1), or from main memory, such as via home node 130A in FIG. 1.

[0027] Additionally, in one embodiment, L3 cache 230 is shared by each of processor cores 210A-210D. L3 cache 230 is coupled to a coherent master for access to a data fabric (e.g., data fabric / bus 125 of FIG. 1) and a memory subsystem (not shown). In other embodiments, core complex 200 may include fewer or more processor cores (e.g., processor core 210A) and corresponding L2 caches (e.g., L2 cache 220A). In still other embodiments, core complex 200 may include other types of addressable cache subsystems that may include different numbers, types, and levels of cache memory without departing from the scope of this disclosure.

[0028] FIG. 3 is a block diagram of one embodiment of processor system 300. In one embodiment, processor system 300 includes multiple core complexes, as represented by CPUs 305A-305N. In various embodiments, the number of CPUs (e.g., CPU 305A) and the number of cores per CPU (e.g., cores 308A-308N) may vary according to design choice. Additionally, each CPU 305A-305N includes a corresponding one of cache subsystems 310A-310N. In various embodiments, cache subsystems 310A-310N may vary in size and structure, as described above with reference to FIG. 2.

[0029] In one embodiment, each CPU 305A-305N is connected to a corresponding coherent master 315A-315N, which is further connected to data fabric / bus 318. As used herein, a "coherent master" is defined as an agent that includes circuitry that handles traffic flowing over the interconnect (e.g., data fabric / bus 318) and manages cache coherency, including each coherent master (e.g., coherent masters 315A-315N) that cooperate to generate, receive, and process coherency-related messages and probes to synchronize copies of shared cache data within processor system 300.

[0030] In various embodiments, each CPU 305A-305N may be connected to one or more coherent slaves by a corresponding coherent master 315A-315N and data fabric / bus 318. For example, CPU 305A may be connected to multiple coherent slaves with access to each other's cache directories, such as coherent slaves (CS) 320A-320D and coherent slaves 321A-321D, each connected via coherent master 315A and data fabric / bus 318. Coherent slave 320A is connected to memory controller (MC) 330A and cache directory (CD) 325A, and coherent slave 321A is coupled to memory controller 331A and cache directory 326A. Each memory controller 330A-330N and 331A-331N is connected to a respective one of memory devices 340. One function of each memory controller, such as memory controller 330A, is to provide elements of processor system 300 with access to memory device 340. Although shown as a single block in various embodiments, memory device 340 may be comprised of one or more physical memories and may be of any type suitable for storing data, such as dynamic random access memory (DRAM), static random access memory (SRAM), etc.

[0031] In one embodiment, each cache directory, e.g., cache directory 325A, includes one or more entries, each entry corresponding to a region in memory 340. Each entry contains information for tracking cached data in processor system 300 that corresponds to data in the region of memory 340. The region size, sometimes referred to as the page size, may be defined by a block of addresses in memory 340A, and those addresses may vary between embodiments depending on how the memory is organized, e.g., whether the memory is interleaved across channels and memory address map bases. In one embodiment, one or more fields of an entry are configurable to change the page size of the region in memory 340 being tracked by the cache directory.

[0032] In one embodiment, the memory in device 340 is divided equally among each of memory controllers 330A-330N and 331A-331N, with each coherent slave (e.g., coherent slaves 320A-320N and 321A-321N) and their respective cache directories (e.g., cache directories 325A-325N and 326A-326N) managing a respective equal and contiguous portion of the memory. Alternatively, some or all of memory devices 340 have different memory capacities. In various embodiments, a coherent slave may have access to the cache directories of one or more other coherent slaves. For example, coherent slave 320A may have access to multiple other cache directories (e.g., 326A-326N and 325B-325N) in processor system 300.

[0033] In one embodiment, each of coherent slaves 320A-320N and 321A-321N is coupled to a respective cache directory 325A-325N and 326A-326N, which acts as a probe filter. When coherent slave 320A receives a memory request targeted to its corresponding memory controller 330A, coherent slave 320A performs a lookup in its corresponding cache directory 325A to determine whether the request targets data in a memory location contained within a region of memory 340 tracked by an entry in cache directory 325A, and whether the memory request results in a cache hit, meaning that the requested data can be found in a cache line stored in cache subsystem 310A-310N associated with the region. In one embodiment, if the lookup results in a hit, coherent slave 320A sends a probe to the CPU(s) (e.g., CPUs 305A-305N) identified in the hit entry in the cache directory. The type of probe generated by coherent slave 320A depends on the coherency state specified by the entry that was hit.

[0034] 3, in other embodiments, there may be other connections from data fabric / bus 318 to other components not shown to avoid obscuring the figure. For example, in another embodiment, data fabric / bus 318 includes one or more I / O interfaces and connections to one or more I / O devices, such as those shown in FIG.

[0035] 4 illustrates a portion of processor system 300, according to an embodiment. Cache directory 325A includes a line probe filter directory 410 and a region probe filter directory 420. Line probe filter directory 410 includes a set of entries that each identify a cache line 411 (e.g., using an address or other identifier) ​​and associate it with a coherency state 412. Region probe filter directory 420 includes a set of entries that each identify a region 421 of memory within memory device 340A and associate the region 421 with a coherency state 422. In one embodiment, the regions are memory pages. Line 411 and region 421 fields identify cache lines and regions by their addresses (e.g., base addresses) or address ranges. Coherency state fields 412 and 422 store values ​​that indicate the coherency state of the associated line or region, such as clean, dirty, or modified, and exclusive or shared. Each entry in the line probe filter directory 410 and region probe filter directory 420 may also include additional metadata about the identified line or region, such as a valid bit, a reference count of the number of cache lines of the region that are cached somewhere in the processor system, etc.

[0036] A controller device, such as coherent slave 320A, includes probe filter logic 431 that performs coherency actions in conjunction with cache directory 325A by sending probes in response to memory access requests depending on whether the requested line is cached, as indicated by cache directory 325A, and depending on the coherency state and cached location of the requested line. Coherent slave 320A also includes throttle logic and registers 430 for performing throttling of demotion superprobes. The registers are used to record metrics related to demotion superprobes (e.g., the number of outstanding demotion superprobe recommendations, the number of failed demotion superprobes, etc.), and the throttle logic compares the recorded metrics to one or more thresholds to determine whether to allow further demotion superprobes to be recommended.

[0037] 5 is a flow diagram illustrating operation of processor system 300 when the demote superprobe feature is disabled or unavailable, according to an embodiment, in which widely shared clean data can lead to congestion in the data fabric interconnect due to a lack of line-by-line precision in coherency state tracking.

[0038] In block 501, a data fetch operation allocates an “exclusive” (E) region. Data fetch opcodes (e.g., RdBlkL) attempt to return “exclusive” (E) lines whenever possible and are directed to a memory region in memory 340A when the data fetch is performed. In response to the data fetch, a probe filter implemented by coherent slave 320A and cache directory 325A returns the “exclusive” (E) line to the requesting core complex, which installs the line in its cache subsystem. Because the returned line can be silently upgraded to a “modified” (M) state without the knowledge of the probe filter, the coherency state of the region is recorded as “dirty exclusive” (DE) in the region probe filter directory 420. That is, the probe filter does not receive any indication of whether or when the line will be modified by the core complex because the line is “exclusive” (E).

[0039] In block 503, because data fetches from different core complexes are directed to the same region, the coherency state of the region transitions from "dirty exclusive" (DE) to "dirty shared" (DS) in the region probe filter directory 420. To properly maintain cache coherency, the probe filter assumes that a region is "dirty" (D) if an "exclusive" (E) line is modified without the probe filter's knowledge.

[0040] As provided in block 505, when a subsequent data fetch is received from any core complex directed to a region in the "dirty shared" (DS) state, the line probe filter directory 410 is checked for the requested line.

[0041] At block 507 , if the line probe filter 410 contains an entry for the requested line, the coherency state of the line can be determined from the entry and the process continues at block 511 .

[0042] In block 511, the line probe filter recommends a directed probe, a multicast probe, or no probe for a particular line depending on the coherency state of the line. The line is then installed in the cache subsystem of the requesting core with the appropriate coherency state depending on the coherency state associated with the line in the line probe filter directory 410.

[0043] The requested line is not found in the line probe filter directory 410, especially when a workload with a large memory footprint is being processed. The line probe filter directory 410 may be insufficiently sized (e.g., sized for communication variables), thrashing, and unable to provide coherency state for most of the requested lines. Therefore, due to a lack of line-by-line fidelity in the design, probes are issued to ensure accuracy when the line probe filter is unable to provide coherency state for a line. Thus, process 500 continues from block 507 to block 509.

[0044] This leads to the generation of a multicast probe when the region transitions to a "Dirty Shared" (DS) state and is subsequently hit by a data fetch operation. In block 509, the region probe filter recommends multicast probes directed to all lines in the region. Multicast probes and probe responses can cause bottlenecks in cross-die and / or socket links, thereby limiting performance when the design is scaled. In block 509, the probe filter allows "Exclusive" (E) lines to be installed in the cache of the requesting core complex.

[0045] In block 513, the coherency state of the cache lines of the region is updated as appropriate via the probes generated in blocks 509 or 511.

[0046] 6 is a flow diagram illustrating the operation of processor system 300 with the demote superprobe feature enabled, according to an embodiment. The operations illustrated in FIG. 6 are performed by components of processor system 300, including cache directory 325A, coherent slave 320A, memory controller 330A, etc. Generally, a data fetch opcode is issued by a core complex (e.g., CPU 305A) to fetch a line of data from memory. The data fetch is received by a coherent slave (e.g., coherent slave 320A) associated with the memory device in which the line is stored. The coherent slave retrieves the requested line from the memory device via the memory controller and provides the core complex with the line to be installed in its cache subsystem. The coherent slave also performs actions to maintain coherency of the lines stored in different caches, such as sending coherency probes.

[0047] A core complex (e.g., core complex 305A) fetches data from any memory device 340 by sending a data fetch opcode (e.g., RdBlkL) via data fabric 318. At block 601, the data fetch opcode is received by coherent slave 320A. At block 603, if the memory region is being accessed by only one core complex (e.g., the core complex issuing the data fetch is the first core complex to access the region, and no other core complexes are accessing the region), process 600 continues at block 605. At block 605, the requested line from the memory region is installed in the cache subsystem of the core complex. A data fetch opcode such as RdBlkL returns an “exclusive” (E) line if possible, and therefore the cache line is installed in an “exclusive” (E) coherency state. In this case, the line does not need to be tracked separately in the line probe filter directory. From block 605, process 600 returns to block 601 to process subsequent data fetches. Subsequent data fetches from the same core complex directed to the same region are also installed in the cache in an "exclusive" (E) state via blocks 603 and 605.

[0048] At block 603, if more than one core complex is accessing the region (e.g., a data fetch is from a second core complex accessing the region), process 600 continues at block 607. At block 607, coherent slave 320A determines whether the region has a “clean exclusive” (CE) or “clean shared” (CS) coherency state by looking up the region in region probe filter directory 420. If the region is in a “clean exclusive” (CE) or “clean shared” (CS) state, at block 609, the cache line is installed in the cache subsystem of the requesting core complex with a “shared” (S) coherency state. Because the region is “clean,” no probe is generated by coherent slave 320A. From block 609, process 600 returns to block 601 to continue processing subsequent data fetches.

[0049] If, at block 607, the region is not in a "clean exclusive" (CE) or "clean shared" (CS) coherency state, process 600 continues at block 611. At block 611, coherent slave 320A determines whether any of several trigger conditions have occurred. The trigger conditions may include, but are not limited to:

[0050] The first new core access, occurring upon the first data fetch from the second core complex to access the region, transitions the region from the "Dirty Exclusive" (DE) state to the "Dirty Shared" (DS) state.

[0051] A data fetch that hits a region in the "Dirty Shared" (DS) state and increments the Aggregate Reference Count (ARC) beyond a programmable threshold. The ARC tracks the number of lines from the region that have a cached copy in one of the caches.

[0052] The first data fetch from a remote socket hits a region in the "Dirty Shared" DS state.

[0053] In one embodiment, the coherent slave device records information about which core complex sent a data fetch to a particular region to identify when a trigger condition occurs. If a trigger condition is not detected, the requested line is installed in the cache subsystem of the requesting core complex, as provided in block 605.

[0054] If one or more of the trigger conditions are detected in block 611, the coherent slave recommends a demotion superprobe, as provided in block 613. In one embodiment, the demotion superprobe recommendation is recorded by asserting a register bit or flag. In one embodiment, the coherent slave includes a throttling function that adjusts the rate at which demotion superprobe recommendations are generated based on one or more outcome metrics of demotion operations within a monitored period. Such an embodiment may include static and dynamic throttling mechanisms for demotion superprobes. For example, a static upper limit may be set on the number of outstanding demotion superprobe recommendations at any point in time. Dynamic throttling options include counters that count the number of eligible demotion operations, recommended demotion operations, and failed demotion operations over an execution time window, and provide programmable thresholds for increasing or decreasing the rate of demotion recommendations to allow the design to dynamically adapt to the nature of the workload, thereby minimizing the number of wasted demotion superprobes. "Eligible" means that the trigger conditions for a demote superprobe were met, "Recommended" means that eligibility is qualified by dynamic throttle conditions, and "Failed" implies that the region transitioned from "Clean Share" to "Fix Share" and that a rinse action due to the failed superprobe was not warranted or was short-sighted.

[0055] In one embodiment, counter and comparison logic for performing throttling is included within coherent slave devices 320A-320N and 321A-321N, or alternatively within cache directories 325A-325N and 326A-326N. If throttling is enabled for the number of outstanding demotion superprobe recommendations, a demotion superprobe is recommended if the number of outstanding demotion superprobes is below a threshold limit. The throttle logic 430 then increments the number of outstanding demotion superprobes if a demotion superprobe is recommended.

[0056] At block 614, throttling is enabled and if the number of demote superprobe recommendations is greater than or equal to the threshold limit for throttling, the recommendation is dropped and the number of outstanding demote superprobe recommendations is decremented at block 616. The cache line is installed as provided at block 605 and process 600 returns to block 601 to continue processing the next data fetch operation.

[0057] If, at block 614, the number of demote superprobe recommendations is less than the threshold limit, process 600 continues at block 615. At block 615, normal coherency actions and concurrent operations on addresses within the same region are allowed to complete. These may include, for example, data fetch operations directed to other lines within the same region occurring in the same cycle, and their associated coherency actions, such as probes. At block 617, if the region has any dirty lines resulting from the operations of block 615, the demote superprobe recommendation is dropped at block 619. For example, a bit or flag indicating the recommendation may be deasserted. If throttling is enabled, the number of outstanding demote superprobes is decremented. The region is transitioned to a “modified-shared” (MS) coherency state, which unambiguously indicates that at least one of the lines in the region has been modified and differs from the data in backing memory 340. From block 619, process 600 returns to block 601 to continue processing data fetch operations.

[0058] If, at block 617, the region does not have any dirty lines, process 600 continues at block 621. If the region has an ambiguous "shared dirty" (DS) coherency state indicated in the region probe filter directory, this indicates that it is unknown whether any lines in the region were actually modified, as at least one of the lines may have been silently modified without an update to the cache directory 325A. If the region is not in an ambiguous "shared dirty" (DS) state, process 600 installs the requested cache line as provided at block 605. The coherency state of individual lines is appropriately tracked in the line probe filter directory 410.

[0059] At block 621, if the region is associated with an ambiguous “Dirty Shared” DS state in the region probe filter 420, the coherent slave device 320A sends a demote superprobe, as provided at block 623. A demote superprobe is a multicast coherency probe directed to all of the cache lines associated with the memory region, which demotes (i.e., converts) cache lines with an “Exclusive” (E) coherency state to a “Shared” (S) coherency state without changing other coherency states. The converted cache lines may include cache lines installed in response to data fetch opcodes issued from multiple respective core complexes. Thus, cache lines may be distributed among multiple different cache subsystems of different core complexes.

[0060] In response to the demote superprobe, the coherent master device associated with the hit cache line returns a probe response indicating whether the cache line is dirty. At block 625, if the demote superprobe finds any lines in the region to be dirty, the coherency state of the region is corrected to “modified shared” (MS) in region probe filter directory 420. If the region is in MS coherency state, the cache line is installed in “exclusive” (E) coherency state in response to the data fetch, and an entry in line probe filter 410 may be allocated to track the coherency state of the dirty cache line, as provided in block 605. At block 625, if the demote superprobe does not find any dirty lines in the region, the coherency state of the region is corrected to “clean shared” (CS) in region probe filter directory 420. From block 627 or 629, process 600 returns to block 601 to continue processing the data fetch. As provided in block 609, if the region is in the "clean shared" CS state, subsequent data fetches will not cause a probe to be issued and the cache line will be installed in the "shared" (S) coherency state.

[0061] The method includes storing an entry in a cache directory that associates the memory region with an exclusive coherency state, and in response to a memory access directed to the memory region, sending a demotion superprobe to convert at least one cache line of the memory region from the exclusive coherency state to a shared coherency state.

[0062] The method further includes, in response to the memory access, determining whether the memory region is associated with one or more dirty cache lines, and, in response to determining that the region is not associated with the one or more dirty cache lines, changing the coherency state of the memory region to a clean shared coherency state.

[0063] The method further includes installing one or more cache lines having a shared coherency state in response to a data fetch opcode directed to the memory region while the coherency state of the memory region is a clean shared coherency state.

[0064] In the method, storing an entry associating the memory region with the exclusive coherency state is responsive to a first data fetch opcode received from a first core complex directed to the memory region, and the memory access is a second data fetch opcode received from a second core complex.

[0065] In the method, the at least one cache line includes a plurality of cache lines each installed in response to a data fetch opcode issued by a different respective core complex.

[0066] The method further includes determining, in response to the memory access, whether the memory region is associated with one or more dirty cache lines, and, in response to determining that the memory region is associated with the one or more dirty cache lines, adding one or more entries to a line probe filter to track a coherency state for each of the one or more dirty cache lines.

[0067] The method further includes, after determining that the memory region is associated with one or more dirty cache lines, installing the cache line with an exclusive coherency state in response to receiving a subsequent data fetch opcode directed to the memory region.

[0068] In the method, sending a demotion super-probe is further performed in response to determining that the number of outstanding demotion super-probe recommendations is below a threshold limit.

[0069] The method further includes adjusting the rate at which demotion superprobe recommendations are generated based on one or more outcome metrics of demotion actions within the monitored time period.

[0070] The computing device includes a cache directory that stores entries associating memory regions with exclusive coherency states, and a controller device coupled to the cache directory that transmits a demotion superprobe in response to a memory access directed to the memory region to convert at least one cache line associated with the memory region from the exclusive coherency state to a shared coherency state.

[0071] In the computing device, the controller device determines, in response to a memory access, whether the memory region is associated with one or more dirty cache lines, and, in response to determining that the region is not associated with the one or more dirty cache lines, changes the coherency state of the memory region to a clean shared coherency state.

[0072] In a computing device, a controller device installs one or more cache lines having a shared coherency state in response to a data fetch opcode directed to a memory region while the coherency state of the memory region is a clean shared coherency state.

[0073] In a computing device, a cache directory stores an entry associating a memory region with an exclusive coherency state in response to a first data fetch opcode received from a first core complex directed to the memory region, and the memory access includes a second data fetch opcode received by the controller device from a second core complex.

[0074] In the computing device, the controller device determines, in response to a memory access, whether the memory region is associated with one or more dirty cache lines, and the cache directory further includes a line probe filter directory for storing one or more entries for tracking a coherency state for each of the one or more dirty cache lines when the memory region is associated with the one or more dirty cache lines.

[0075] In a computing device, a controller device determines that a memory region is associated with one or more dirty cache lines, and then installs the cache lines with an exclusive coherency state in response to receiving a subsequent data fetch opcode directed to the memory region.

[0076] At the computing device, the controller device performs transmission of a demotion super-probe in response to determining that the number of outstanding demotion super-probe recommendations is below a threshold limit.

[0077] In the computing device, a controller device adjusts the rate at which demotion superprobe recommendations are generated based on one or more outcome metrics of demotion actions within a monitored time period.

[0078] The system includes a set of processor core complexes, a cache directory coupled to the set of processor core complexes for storing entries associating memory regions with an exclusive coherency state, and a controller device coupled to the cache directory for transmitting a demotion superprobe to convert at least one cache line associated with the memory region from the exclusive coherency state to a shared coherency state in response to a memory access directed to the memory region.

[0079] In the system, the cache directory further includes a region probe filter directory that stores a first set of entries for tracking coherency states associated with a plurality of memory regions of the memory device, and a line probe filter directory that stores a second set of entries for tracking coherency states of a plurality of cache lines associated with the memory device.

[0080] In the system, each processor core complex in the set of processor core complexes includes a cache device that stores one or more cache lines associated with a memory region, and is installed in the cache device in response to one or more data fetch opcodes issued by the processor core complex.

[0081] As used herein, the term "coupled to" may mean directly or indirectly coupled via one or more intervening components. Any of the signals provided via the various buses described herein may be time-shared with other signals and provided via one or more common buses. Additionally, interconnections between circuit components or blocks may be referred to as buses or single signal lines. Each of the buses may alternatively be one or more single signal lines, and each single signal line may alternatively be a bus.

[0082] Certain embodiments may be implemented as a computer program product that may include instructions stored on a non-transitory computer-readable medium. These instructions may be used to program a general-purpose or special-purpose processor to perform the described operations. A computer-readable medium includes any mechanism for storing or transmitting information in a form (e.g., software, processing application) readable by a machine (e.g., a computer). Non-transitory computer-readable storage media may include, but are not limited to, magnetic storage media (e.g., floppy diskettes), optical storage media (e.g., CD-ROMs), magneto-optical storage media, read-only memory (ROM), random access memory (RAM), erasable programmable memory (e.g., EPROM and EEPROM), flash memory, and other types of media suitable for storing electronic instructions.

[0083] Additionally, some embodiments may be practiced in a distributed computing environment where a computer-readable medium is stored on and / or executed by one or more computer systems. Additionally, information transferred between computer systems may be either pulled or pushed through a transmission medium connecting the computer systems.

[0084] Generally, data structures representing computing system 100 and / or portions thereof embodied in computer-readable storage media may be databases or other data structures that can be read by a program and used, directly or indirectly, to manufacture hardware including computing system 100. For example, the data structure may be a behavioral-level description of the hardware's functionality in a high-level design language (HDL) such as Verilog or VHDL, or a register-transfer level (RTL) description. The description may be read by a synthesis tool that can synthesize the description to generate a netlist that includes a list of gates from a synthesis library. The netlist includes a set of gates that also represent the functionality of the hardware including computing system 100. The netlist may then be placed and routed to generate a data set that describes the geometric shapes to be applied to a mask. The mask may then be used in various semiconductor manufacturing processes to manufacture one or more semiconductor circuits corresponding to computing system 100. Alternatively, the database on the computer-readable storage medium may be a netlist (with or without a synthesis library) or a data set, or Graphic Data System (GDS) II data, as desired.

[0085] Although the operations of the methods herein are shown and described in a particular order, the order of the operations of each method may be changed such that certain operations may be performed in the reverse order or such that certain operations may be performed at least in part concurrently with other operations. In alternative embodiments, instructions or sub-operations of individual operations may be performed intermittently and / or alternately.

[0086] In the foregoing specification, embodiments have been described with reference to specific exemplary implementations thereof. However, it will be apparent that various modifications and changes can be made thereto without departing from the broader scope of the implementations as set forth in the appended claims. Accordingly, the specification and drawings should be regarded in an illustrative rather than a restrictive sense.

Claims

1. 1. A method comprising: storing an entry associating a memory region with an exclusive coherency state; transmitting a demote superprobe to convert at least one cache line of the memory region from an exclusive coherency state to a shared coherency state in response to a memory access directed to the memory region; method.

2. changing the coherency state of the memory region to a clean shared coherency state based on the memory region not being associated with one or more dirty cache lines.

10. The method of claim 1.

3. installing one or more cache lines having a shared coherency state in response to a data fetch opcode directed to the memory region while the coherency state of the memory region is the clean shared coherency state. The method of claim 2.

4. storing an entry associating the memory region with an exclusive coherency state in response to a first data fetch opcode received from a first core complex directed to the memory region; the memory access is a second data fetch opcode received from a second core complex; 10. The method of claim 1.

5. the at least one cache line includes a plurality of cache lines each installed in response to a data fetch opcode issued by a different respective core complex; 10. The method of claim 1.

6. adding one or more entries to a line probe filter to track a coherency state for each of the one or more dirty cache lines based on the memory region being associated with the one or more dirty cache lines; 10. The method of claim 1.

7. after determining that the memory region is associated with one or more dirty cache lines; installing a cache line with the exclusive coherency state in response to receiving a subsequent data fetch opcode directed to the memory region. The method of claim 6.

8. sending the demotion super-probe is performed in response to determining that the number of outstanding demotion super-probe recommendations is below a threshold limit; 10. The method of claim 1.

9. adjusting the rate at which demotion superprobe recommendations are generated based on one or more outcome metrics of demotion actions within the monitored time period; 10. The method of claim 1.

10. 1. A computing device comprising: a cache directory configured to store entries associating memory regions with exclusive coherency states; a controller device coupled to the cache directory and configured to transmit a demote superprobe in response to a memory access directed to the memory region to convert at least one cache line associated with the memory region from an exclusive coherency state to a shared coherency state; Computing devices.

11. The controller device determining, in response to the memory access, whether the memory region is associated with one or more dirty cache lines; In response to determining that the region is not associated with the one or more dirty cache lines, changing the coherency state of the memory region to a clean shared coherency state; configured to: The computing device of claim 10.

12. The controller device configured to install one or more cache lines having a shared coherency state in response to a data fetch opcode directed to the memory region while the coherency state of the memory region is the clean shared coherency state. The computing device of claim 11.

13. the cache directory is configured to store an entry associating the memory region with an exclusive coherency state in response to a first data fetch opcode received from a first core complex directed to the memory region; the memory access includes a second data fetch opcode received by the controller device from a second core complex; The computing device of claim 10.

14. the controller device is configured to determine, in response to the memory access, whether the memory region is associated with one or more dirty cache lines; the cache directory comprises a line probe filter directory configured to store one or more entries for tracking a coherency state for each of the one or more dirty cache lines when the memory region is associated with the one or more dirty cache lines; The computing device of claim 10.

15. the controller device is configured to install a cache line with the exclusive coherency state in response to receiving a subsequent data fetch opcode directed to the memory region after determining that the memory region is associated with the one or more dirty cache lines. The computing device of claim 14.

16. the controller device is configured to perform transmission of the demotion super-probe in response to determining that a number of outstanding demotion super-probe recommendations is below a threshold limit. The computing device of claim 10.

17. the controller device is configured to adjust a rate at which demotion superprobe recommendations are generated based on one or more outcome metrics of demotion actions within a monitored time period. The computing device of claim 10.

18. 1. A system comprising: a set of processor core complexes; a cache directory coupled to the set of processor core complexes and configured to store entries associating memory regions with exclusive coherency states; a controller device coupled to the cache directory and configured to transmit a demote superprobe in response to a memory access directed to the memory region to convert at least one cache line associated with the memory region from an exclusive coherency state to a shared coherency state; system.

19. The cache directory includes: a region probe filter directory configured to store a first set of entries for tracking coherency states associated with a plurality of memory regions of a memory device; a line probe filter directory configured to store a second set of entries for tracking coherency states of a plurality of cache lines associated with the memory device; 20. The system of claim 18.

20. each processor core complex in the set of processor core complexes comprises a cache device configured to store one or more cache lines; The one or more cache lines associated with the memory region, installed in the cache device in response to one or more data fetch opcodes issued by the processor core complex; 20. The system of claim 18.

Images