Silicon-based quantum processor

Abstract

A silicon-based quantum processor is disclosed that includes a plurality of unit cells having qudits of interest that can interact with each other directly or indirectly. Each unit cell includes a charge reservoir (101) and a plurality of single electron boxes (SEBs) (103a, b, c, d), which are gated charged islands separated from the charge reservoir by tunneling barriers. A first plurality of qudits (105a, b) for use as ancillary qudits is provided around each SEB. A second plurality of qudits (107a, b) for use as data qudits is provided around the first plurality. Each of the second plurality of qudits can interact with at least one of the first plurality of qudits such that the state of each of the second plurality of qudits can be read out from a neighbor of the first plurality by one of the SEBs.

Description

[Technical Field]

[0001] The present invention relates to silicon-based quantum processors. [Background technology]

[0002] Quantum processors based on silicon-based semiconductor materials (hereinafter "silicon-based quantum processors") are the leading candidates for the development of quantum computers.

[0003] Quantum processors perform operations by manipulating an array of qudits (i.e., basic units of quantum information with an integer number of d possible states—e.g., qubits with two possible states, similar to bits in classical computing). Many architectures provide ancillary qudits, whose states are directly read out and manipulated by the processor's devices, and data qudits, whose states are directly controlled or not read out, on which operations are performed. The ancillary qudits are arranged to interact with (at least some of) the data qudits, such that the data qudits and the ancillary qudits can affect each other's states. In this way, the output of an operation performed by a data qudit can be read out without directly interacting with the data qudit, and the state of a data qudit in direct communication with the ancillary qudit can be read out by measuring the ancillary qudit.

[0004] In general, each qudit can interact directly with other qudits that are closest to it in the array; for example, in a linear array of qudits, each qudit can directly interact with the nearest qudits on either side of it. In some computational applications, it is desirable for data qudits to have a high degree of two-dimensional (2D) connectivity—that is, at least some of the data qudits are in direct communication with as many other data qudits as possible. Therefore, quantum processor architectures that allow a high level of connectivity among data qudits are needed. Additionally, it is sometimes desirable that the states of most or all of the data qudits can be read out, which requires that all of the data qudits be in communication with one or more ancillary qudits. It should be clear that there is a trade-off between high connectivity, on the one hand, and the proportion of data qudits whose states can be read out, on the other. This occurs because the more data qudits are placed in interaction with at least one ancillary qudit, the fewer connections that can be made between the data qudits. A quantum processor architecture that can meet these demands is needed. Summary of the Invention [Means for solving the problem]

[0005] The present invention provides a silicon-based quantum processor comprising a plurality of unit cells having qudits of interest that can interact with each other directly or indirectly, each unit cell comprising a charge reservoir, a plurality of single electron boxes or SEBs that are gated charged islands separated from the charge reservoir by tunneling barriers, a first plurality of qudits for use as ancillary qudits disposed around each SEB such that the SEBs are detectable, the first plurality of qudits being disposed around the charge reservoir and the plurality of SEBs, and a second plurality of qudits for use as data qudits disposed around the first plurality, each of which can interact with at least one of the first plurality of qudits such that the state of each of the second plurality of qudits can be read out from adjacent ones of the first plurality by one of the plurality of SEBs.

[0006] The bath is typically an electrode or other component capable of providing charge carriers to a nearby SEB. As described above, the SEB is a gated island separated from the charge bath by a tunneling barrier. In use, a gate voltage is applied to the island, and the number of charge carriers that can reside on the island is correlated to this gate voltage. This configuration allows charge carriers to be transported between the bath and a first plurality of qudits arranged around the bath. The SEB can sense the state of the first plurality of qudits that it is capable of sensing (typically the qudits physically closest to the SEB). The SEB thus serves two purposes: to transport charge between the bath and the first plurality of qudits, and to sense the state of the first plurality of qudits.

[0007] The configurations presented above allow for the establishment of quantum processors that provide a high density of data qudits in the processor while permitting the readout of the states of these data qudits using SEBs. This is achieved in part by the inventors' recognition that multiple SEBs can be arranged around a single charge reservoir, allowing each reservoir to serve more qudits (thus reducing the number of reservoirs required) than known architectures. Unit cells are connected to each other to promote sparse 2D connectivity of the data qudits while allowing the readout of the data qudits using nearby ancillary qudits. In some configurations, it is possible to achieve readout of all data qudits in the array, thus achieving a highly desirable balance between the desire for high 2D connectivity while providing space in the processor for the states of the data qudits to be readout.

[0008] The qudits may be qudits with two possible states, or may have some other number of states. In preferred implementations, the qudits are implemented as gate-controlled semiconductor quantum dots in which charge carriers (e.g., electrons) can be confined. In these implementations, charge carriers can be confined by application of an appropriate electrostatic potential to the gate.

[0009] Preferably, at least some of the second plurality of qudits of one or more unit cells are configured to interact with at least some of the second plurality of qudits of one or more other unit cells. In this arrangement, the second plurality of qudits (which, in use, act as data qudits) of adjacent unit cells may interact with each other, thus achieving a higher 2D connectivity than exists in unit cells that are isolated from one another. In general, the more other data qudits with which each data qudit can interact, the higher the 2D connectivity of the processor.

[0010] In a preferred implementation, in each unit cell, the first plurality of qudits is arranged in a first ring around the charge reservoir and the plurality of SEBs, and the second plurality of qudits includes qudits arranged in a second ring around the first ring. In these embodiments, the ancillaqudits are arranged in a first ring around each SEB. Here, the term "ring" refers to the ancillaqudits being arranged around the perimeter formed by the SEBs and reservoirs. This arrangement allows the ancillaqudits to interact with the SEBs in the required manner. It will be appreciated that the term "ring" does not imply a particular shape, as will become apparent in consideration of the detailed examples described below. Similarly, the plurality of data qudits arranged in the second ring are arranged around the perimeter formed by the ancillaqudits. As described below, other data qudits in addition to those in the second ring may be provided.

[0011] In some preferred implementations, at least some of the qudits in the second ring of the first unit cell are configured to interact with at least some of the qudits in the second ring of the second unit cell. In embodiments such as these, in which qudits in the second rings of different unit cells are arranged to interact with one another, a significant fraction (or indeed all) of the data qudits can be read out via the first plurality of qudits (ancilla qudits), since few (or no) data qudits are not in communication with ancilla qudits.

[0012] In another preferred embodiment, the second plurality of qudits in each unit cell are arranged in a second ring and a third ring surrounding the second ring, with each qudit in the second ring being able to interact with at least one of the qudits in the third ring. By providing a third ring of qudits (which, like the qudits in the second ring, belong to the second plurality of qudits and are therefore suitable for use as data qudits) around the second ring, a high 2D connectivity of the data qudits can be achieved, as each data qudit has more neighbors with other data qudits, resulting in a high proportion of data qudits in each unit cell. Preferably, at least some of the qudits in the third ring of the first unit cell are configured to interact with at least some of the qudits in the third ring of the second unit cell. One or more additional rings of data qudits may be arranged around the third ring, which may further increase the 2D connectivity.

[0013] Advantageously, four SEBs are arranged in a rectangular configuration around a charge reservoir in each unit cell. Here, the term "rectangular" includes square and other rectangular layouts. This configuration achieves efficient space usage in the processor layout, as all sides of the reservoir may be provided with an SEB, thus allowing a large number of ancillary qudits (first plurality of qudits) and data qudits (second plurality of qudits) to be arranged around each reservoir. Preferably, in these embodiments, three of the first plurality of qudits are arranged around each of the four SEBs in each unit cell. For example, one of the first plurality of qudits may be arranged on each of three sides of the SEB, with all four sides of the SEB arranged to communicate or interact with the reservoir. As illustrated with reference to the examples below, three different qudits are not necessarily arranged for each SEB, as some of the first plurality of qudits may be arranged to interact with more than one SEB. For example, preferably eight qudits are provided in the first ring of each unit cell, and twelve second qudits are provided in the second ring of each unit cell. If each of the four first qudits is capable of interacting with two SEBs, then the condition that each SEB interacts with three of the first plurality can be met.

[0014] In a preferred embodiment, the SEB, the first plurality of qudits, and the second plurality of qudits are arranged in a regular two-dimensional array, with each SEB, each of the first plurality of qudits, and each of the second plurality of qudits disposed at a point on the array. In particular, it is preferred that the array be a square lattice, as square arrays have been found to be particularly suitable for fabrication by existing micro-fabrication techniques of the type suitable for producing silicon-based quantum processors.

[0015] Preferably, one of the first plurality of qudits is located at each of the points of the array closest to each of the points at which an SEB is located, except for the points at which the tank is located, particularly when the array is a square lattice. In the case of a square lattice where the tank is located at one point, there are four points closest to the tank and therefore four SEBs. In addition, it is preferred that one of the first plurality of qudits is located at each of the points of the array closest to each of the points at which an SEB is located, except for the points at which the tank is located. In these embodiments, eight such points (and therefore eight first plurality of qudits) are located in each unit cell. These eight qudits of the first plurality form a first ring in these embodiments (in embodiments where the first plurality is located in a first ring, as described above). More preferably, one of the second plurality of qudits is located at each of the points closest to each of the points at which the first plurality of qudits is located, except for the points at which the SEB is located. In these embodiments, each unit cell is provided with 12 such points (and thus 12 second pluralities capable of interacting with the first plurality of qudits). These 12 second pluralities may form such a ring in the preferred embodiments described above where a second ring is present. Additional qudits may be provided in the second plurality (e.g., in a third ring around the second ring), or the 12 second pluralities capable of interacting with an ancilla qudit may be the entire second plurality.

[0016] Preferably, the unit cells are arranged in a regular pattern. The pattern may be configured such that at least some of the second plurality of qudits in each unit cell can each interact with one or more of the second plurality of qudits in one or more other unit cells. The more qudits in different unit cells interact with each other in this manner, the higher the connectivity of the processor.

[0017] The invention also provides a method of using a silicon-based quantum processor as defined above, the method including a charge initialization step, which includes the steps of transferring charge carriers from a bath to a plurality of SEBs, transferring charge carriers from the plurality of SEBs to a first plurality of qudits, and transferring charge carriers from the first plurality of qudits to a second plurality of qudits. Typically, the charge initialization step is performed before the processor begins performing a calculation and need not be repeated between individual operations.

[0018] Preferably, initializing charge in the manner defined above includes, a first time, transferring charge carriers from the reservoir to the plurality of SEBs, a second time transferring charge carriers from the plurality of SEBs to a first group of the first plurality of qudits, and a third time simultaneously transferring charge carriers from the plurality of SEBs to a second group of the first plurality of qudits and transferring charge carriers from the first group of the first plurality of qudits to a first group of the second plurality of qudits.

[0019] In a preferred embodiment, the method further comprises a step of qudit spin initialization, which includes allowing an interaction between the second plurality of qudits and the first plurality of qudits. The first plurality of qudits may be placed in a known state before allowing this interaction—for example, each of the first plurality of qudits at this stage stores charge carriers in a spin-down state. Most preferably, the qudit spin initialization step is performed in a first step for a first group of the second plurality of qudits, and in a second step after the first step for a second group of the second plurality of qudits.

[0020] The method may further include a spin readout step involving exchanging charge carriers or providing spin tunneling between the second plurality of qudits and the first plurality of qudits and reading out the state of the first plurality of qudits with the SEB.

[0021] Preferably, there are three groups of data qudits in the first ring that are read out in three steps. [Brief explanation of the drawings]

[0022] [Figure 1] 1 illustrates a unit cell of a silicon-based quantum processor according to an embodiment of the invention. [Figure 2] 2 illustrates a plurality of unit cells of the type shown in FIG. 1 arranged in a silicon-based quantum processor according to an embodiment of the invention. [Figure 3] 1 and 2. FIG. 3 illustrates the sparse 2D connectivity of the processors of FIGS. [Figure 4] 4 illustrates steps in the charge initialization process in the processor of FIGS. 1-3. [Figure 5] 4 illustrates steps in the spin initialization process in the processor of FIGS. [Figure 6] 4 illustrates steps in the spin read process in the processor of FIGS. 1-3. [Figure 7] 1 illustrates sparse 2D connectivity for a silicon-based quantum processor according to a second embodiment of the invention. [Figure 8] 1 shows an example unit cell of a silicon-based quantum processor according to a third embodiment of the invention. [Figure 9] 9 illustrates steps in the charge initialization process in the embodiment of FIG. 8. [Figure 10] 9 illustrates steps in the spin initialization process in the embodiment of FIG. 8. [Figure 11] 9 illustrates steps in the spin read process for the embodiment of FIG. 8. DETAILED DESCRIPTION OF THE INVENTION

[0023] FIG. 1 shows an example of a unit cell according to embodiments of the invention. The unit cell includes a charge reservoir 101 surrounded by four single electron boxes (SEBs) 103a, 103b, 103c, and 103d arranged in a rectangular configuration. The charge reservoir provides a supply of charge carriers, typically electrons, that can be transported to the SEBs. The SEBs 103a, 103b, 103c, and 103d are gated islands, each separated from the reservoir by a corresponding tunneling barrier. Transport of charge carriers from the reservoir to the SEBs 103a, 103b, 103c, and 103d islands can be controlled by varying the gate voltage applied to the islands. In some embodiments, an SEB island can confine more than one charge carrier at a time, in which case the number of charge carriers confined to the island is a function of the applied gate voltage.

[0024] The unit cell includes a first plurality of qudits 105a, 105b, which serve as ancillary qudits during use. These eight ancillary qudits 105a, 105b are arranged in a first ring R1 around the SEBs 103a, 103b, 103c, and 103d and the charge reservoir 101. The ancillary qudits are represented in this figure by white circles. Each of the eight ancillary qudits 105a, 105b is arranged to interact with at least one of the SEBs, i.e., to exchange charge carriers and affect each other's states. For example, the ancillary qudit labeled 105a interacts with two SEBs 103a, 103b. The ancillary qudit labeled 105b interacts with only one SEB. In the arrangement shown, four ancillary qudits (including the ancillary qudit labeled 105a, located near the "corners" of the rectangle formed by the layout of SEBs 103a, 103b, 103c, and 103d) interact with two SEBs 103a, 103b, 103c, and 103d, while the other four ancillary qudits (including the ancillary qudit labeled 105b) can interact with only one SEB.

[0025] The processor also includes a second plurality of qudits 107a, 107b that, in use, serve as data qudits. In this embodiment, twelve data qudits 107a, 107b are arranged in a second ring R2 around the ancilla qudits. In this figure, the data qudits are shown as shaded circles. Each of the data qudits in the second ring R2 is arranged to interact with at least one ancilla qudit—for example, the data qudit labeled 107a is capable of interacting with two ancilla qudits 105a, 105b, while the data qudit labeled 107b is configured to interact with only one ancilla qudit 105b. Data qudits and ancilla qudits that are arranged to interact can affect each other's state, for example, by exchanging charge carriers.

[0026] The ancillary qudits and data qudits may be implemented as gated semiconductor quantum dots configured to confine charge carriers upon application of appropriate gate voltages. The states of the qudits may correspond to spin states of the charge carriers confined by the qudits, and the processor may then be subjected to a magnetic field in use to generate different energy levels of the different spin states. To this end, the processor may include a magnetic field generating component.

[0027] The reservoirs, SEBs, ancillary qudits, and data qudits are arranged according to a rectangular lattice, a type of regular two-dimensional array. The points of this lattice are arranged in rows and columns extending in orthogonal directions labeled X and Y, and are regularly spaced at equal intervals in these directions. For example, the SEB labeled 103b is located at the point of the lattice immediately adjacent to the point at which charge reservoir 101 is located. It can be seen that the arrangement of SEBs 103a, 103b, 103c, and 103d in this embodiment is such that an SEB 103a, 103b, 103c, and 103d is located at each of the lattice points (of which there are four—two above and below in the Y direction, and two on either side in the X direction) nearest the point at which the reservoir is located. Similarly, ancillary qudits 105a and 105b are located at each of the lattice points closest to SEBs 103a, 103b, 103c, and 103d, except for the one where tank 101 is located. And, data qudits 107a and 107b of second ring R2 are located at each of the lattice points closest to ancillary qudits 105a and 105b, except for the one where SEBs 103a, 103b, 103c, and 103d are located.

[0028] In alternative embodiments, the unit cell may include additional data qudits, for example arranged in a third ring around the second ring R2.

[0029] A quantum processor according to an embodiment of the invention comprises a plurality of unit cells, such as that shown in Figure 1. The unit cells may be arranged according to a regular pattern, an example of which is shown in Figure 2. While this drawing shows four unit cells 201, 202, 203, and 204, it will be appreciated that many more unit cells than shown may be incorporated into the processor. Each data qudit 107 is configured to interact with at least one ancillary qudit 105, so that the state of each of the data qudits 107 may be directly read out.

[0030] In this pattern, the charge reservoirs 101 of unit cells 201 and 203 are offset from each other by one grid point in the X direction. Similarly, the reservoirs of unit cells 202 and 204 are offset from each other by one grid point in the Y direction. This layout achieves a reasonable degree of sparse 2D connectivity while still allowing readout of all of the data qudits, as shown below with reference to Figure 3.

[0031] Figure 3 illustrates the sparse 2D connectivity of the data qudits 107 in the processor architecture of Figure 2. The lines between the data qudits 107 indicate which other data qudits each data qudit is configured to interact with. It should be noted that this drawing only shows the connections between data qudits visible in the area shown—qudits around the edge of the shown region may be connected to other data qudits not shown. In region R, where the corners of unit cells 201, 202, 203, and 204 meet and are enclosed by the central dashed box, each data qudit 107 is connected to three other data qudits. Thus, the data qudits 107 in this region have 2D connectivity. In contrast, outside this region, the data qudits 107 for which connections are shown have linear connectivity, since each data qudit is configured to interact with two other data qudits 107 and the connections are arranged in a linear fashion. This arrangement, in which regions R with 2D connectivity are separated from each other by regions of linear connectivity, is called “sparse 2D connectivity.” Although the 2D connectivity of the processor can be increased by adding additional data qudits 107 (e.g., in a third ring by unit cells around the second ring R2), these additional qudits cannot interact with any of the ancilla qudits 105 and therefore cannot be directly read out.

[0032] FIG. 4 illustrates steps in a method for initializing charge in the quantum processor of FIGS. 1-3. Charge initialization is typically performed before performing a computation using the quantum processor, with the purpose of providing charge carriers to each ansilaqudit 105 and data qudit 107. In a first step, charge carriers (e.g., electrons) are transferred from the reservoir to the SEB. Then, in a second step, the charge carriers are transported from the SEB to a first group of ansilaqudits 105, as indicated by the arrows labeled S2. In a third step, the charge carriers transferred in the second step are transported from the first group of ansilaqudits 105 to the first group of data qudits 107, as indicated by the arrows labeled S3a. In the third step, simultaneously with the transport of charge carriers to the first group by the data qudits 107, charge carriers are transported from each of the SEBs to a second group of ansilaqudits 105, as indicated by the arrows labeled S3b. The method may proceed in a similar manner until all of the data qudits 107 and ancilla qudits 105 in the unit cell have been provided with charge carriers. Typically, charge initialization is performed such that each qudit in the unit cell is loaded with a single charge carrier (e.g., an electron), although in some applications it may be desirable to load multiple charge carriers into the qudits.

[0033] FIG. 5 illustrates an example of a method for spin initialization in the processor of FIGS. 1-3. Spin initialization is performed after charge initialization (e.g., by the method illustrated in FIG. 4) and has the purpose of preparing the states of the ancilla qudit 105 and the data qudit 107 for performing operations. At the start of spin initialization, the ancilla qudit 105 is placed in a known state, e.g., spin-down. At this stage, the state of the data qudit 107 is unknown. Then, in a first step, the ancilla qudit 105 can interact with a first group of data qudits 107i. Then, in a second step, the ancilla qudit can interact with a second group of data qudits 107ii. The interaction between qudits in the spin initialization process can be spin-dependent tunneling.

[0034] After performing an operation using the quantum processor described above, a spin readout process may be performed to read out the result of the operation. Figure 6 illustrates an example process for performing spin readout using the quantum processor of Figures 1-3. Each of the three groups of data qudits (a first group of data qudits 607i, a second group of data qudits 607ii, and a third group of data qudits 607iii) can, in turn, interact with an ancilla qudit 105. This interaction may involve either transporting charge carriers from data qudits 607i, 607ii, and 607iii to ancilla qudit 105 or establishing spin tunneling (typically in a spin-dependent manner) between data qudits 607i, 607ii, and 607iii and ancilla qudit 105. The state of ancilla qudit 105 may then be read out via SEB 103, which is configured to interact with data qudit 105.

[0035] Figure 7 shows a schematic of a portion of a silicon-based quantum processor according to a further embodiment of the invention. This processor has the same unit cells as those described above with reference to Figures 1-5, but the unit cells are arranged according to a different pattern. Specifically, the charge reservoirs are arranged in alignment with each other along the rows and columns of a square lattice—e.g., charge reservoir 701a is in the same row as charge reservoir 701b. In this layout, it can be seen that some of the data qudits 707 are shared between unit cells—e.g., the data qudit labeled 707i is shared between the four unit cells shown in the figure.

[0036] In the embodiments described above, the first and second plurality of qudits are arranged in rings around the SEB and charge reservoir (e.g., first and second rings as in FIG. 1). FIG. 8 shows a unit cell of a processor according to an alternative embodiment of the invention, in which the first and second plurality of qudits are not arranged in rings. As in the previous example, the unit cell contains a charge reservoir 801 and four SEBs 803a, 803b, 803c, and 803d arranged in a rectangular configuration around the charge reservoir. A first plurality of qudits 805 (shown as white circles in this drawing) is arranged around the charge reservoir 801 and SEBs 803a, 803b, 803c, and 803d. As with the previous embodiment, the layout of this unit cell is based on a square lattice. 1 embodiment, where all of the lattice points closest to SEBs 803a, 803b, 803c, and 803d contained an ancilaqudit. Two of the lattice points closest to the SEBs (one between SEBs 803a and 803d and the other between SEBs 803b and 803c) contained qudits belonging to the second plurality of qudits 807, which were used as data qudits in use. Therefore, the two data qudits 807 closest to the SEBs are not read out by SEBs 803a, 803b, 803c, and 803d in use. The only qudits whose states are read out by SEBs 803a, 803b, 803c, and 803d are the six ancilaqudits provided by the first plurality of qudits 805. The two data qudits 807 where the ancillary qudits were in the previous embodiment are not arranged to interact with either ancillary qudits 805, and so their states cannot be read out directly. This arrangement is therefore beneficial when it is not necessary to read out the entire state of the data qudits 807, but a high density of data qudits 807 is desired. While there are no other data qudits 807 in this embodiment, in other embodiments additional data qudits 807 may be provided around the one shown.

[0037] Figure 9 shows steps in the charge initialization process for the unit cell of Figure 8, with arrows indicating the movement of charge carriers. In the first step, charge carriers move from the SEB to an ancillaqudit 805. In the second step, charge carriers simultaneously move from the SEB to data qudits 807a and 807b that are positioned to interact with SEBs 803a, 803b, 803c, and 803d, and from ancillaqudit 805 to other data qudits 807.

[0038] Figure 10 shows steps in the spin initialization process for the unit cell of Figure 8. In a first step, each of the ancillary qudits 805 can interact with a corresponding one of the data qudits 807. Also in the first step, each of the data qudits 807a, 807b, where the ancillary qudits were located in the previous embodiment, can interact with a neighboring data qudit 807. Then, in a second step, the two data qudits 807a, 807b and the two ancillary qudits 805 closest to the bath can interact with a different data qudit 805 than the one they interacted with in the first step.

[0039] Figure 11 shows steps in the spin readout process for the unit cell of Figure 8. A first group of data qudits 807 interacts with an ancillaqudit 805 (either by exchanging charge carriers or by spin tunneling), and ancillaqudit 805 is read out using SEBs 803a, 803b, 803c, and 803d. Ancillaqudit 805 then interacts with a second group of data qudits 807, and the state of ancillaqudit 805 is read out, also using SEBs 803a, 803b, 803c, and 803d. [Explanation of symbols]

[0040] 101 Charge tank 103a,b,c,d Single electron box (SEB) 105a,b Ancyracudit 107a,b,i,ii DataQDit 201 unit cell 202 unit cell 203 unit cell 204 unit cell 607i,ii,iii DataQDit 701a,b Charge tank 707,707i DataQDit 801 Charge tank 803a,b,c,d Single Electron Box (SEB) 805 Ancyracudit 807a,b DataQDit R region R1 First Ring R2 Second Ring

Claims

1. 1. A silicon-based quantum processor, comprising a plurality of unit cells each having a qudit that may interact directly or indirectly with the unit cells, Each unit cell is a charge reservoir; a plurality of SEBs, which are single electron boxes, which are gate-controlled charged islands separated from the charge reservoir by tunnel barriers; a first plurality of qudits for use as ancillary qudits around each SEB to enable the SEB to be sensed, the first plurality of qudits being arranged around the charge reservoir and the plurality of SEBs; a second plurality of qudits for use as data qudits arranged around the first plurality, each of the second plurality of qudits capable of interacting with at least one of the first plurality of qudits such that the state of each of the second plurality of qudits may be read from a neighboring one of the first plurality of qudits by one of the plurality of SEBs; 1. A silicon-based quantum processor comprising:

2. 10. The silicon-based quantum processor of claim 1, wherein at least some of the second plurality of qudits of one or more of the unit cells are configured to interact with at least some of the second plurality of qudits of one or more other unit cells.

3. In each unit cell, the first plurality of qudits are arranged in a first ring around the charge reservoir and the plurality of SEBs; 3. The silicon-based quantum processor of claim 1 or claim 2, wherein the second plurality of qudits comprises qudits arranged in a second ring around the first ring.

4. 4. The silicon-based quantum processor of claim 3, wherein at least some of the qudits in the second ring of a first unit cell are configured to interact with at least some of the qudits in the second ring of a second unit cell.

5. the second plurality of qudits of each unit cell are arranged in the second ring and in a third ring surrounding the second ring, each of the qudits in the second ring being capable of interacting with at least one of the qudits in the third ring; 4. The silicon-based quantum processor of claim 3, wherein at least some of the qudits in the third ring of a first unit cell are preferably configured to interact with at least some of the qudits in the third ring of a second unit cell.

6. 6. The silicon-based quantum processor of claim 1, wherein in each unit cell, four SEBs are provided in a rectangular configuration around the charge reservoir.

7. 7. The silicon-based quantum processor of claim 6, wherein three of the first plurality of qudits are disposed around each of the four SEBs in each unit cell.

8. 8. The silicon-based quantum processor of claim 1, wherein the SEB, the first plurality of qudits, and the second plurality of qudits are arranged in a regular two-dimensional array, preferably a square lattice, with each SEB, each of the first plurality of qudits, and each of the second plurality of qudits disposed at a respective point of the two-dimensional array.

9. 9. The silicon-based quantum processor of claim 8, wherein each of the charge reservoirs is located at a point in the two-dimensional array, and in each unit cell, one of the SEBs is located at each of the points of the lattice closest to the charge reservoir.

10. one of the first plurality of qudits is located at each of the points of the two-dimensional array that are closest to each of the points at which the SEBs are located, except for the points at which the charge reservoirs are located; 10. The silicon-based quantum processor of claim 9, wherein one of the second plurality of qudits is preferably located at each of the points closest to each of the points at which one of the first plurality of qudits is located, except for the point at which the SEB is located.

11. The silicon-based quantum processor of claim 1 , wherein the unit cells are arranged in a regular pattern.

12. transferring charge carriers from the charge reservoir to the plurality of SEBs; transferring charge carriers from the plurality of SEBs to the first plurality of qudits; transferring charge carriers from the first plurality of qudits to the second plurality of qudits; 12. A method of using a silicon-based quantum processor according to claim 1, wherein the method comprises a step of initializing charges, the step comprising:

13. 13. The method of claim 12, wherein the step of transferring charge carriers from the charge reservoir to the plurality of SEBs is performed a first time, the step of transferring charge carriers from the plurality of SEBs to the first group of the first plurality of qudits is performed a second time, and the simultaneous steps of transferring charge carriers from the plurality of SEBs to the second group of the first plurality of qudits and transferring charge carriers from the first group of the first plurality of qudits to the first group of the second plurality of qudits are performed a third time.

14. further comprising a step of qudit spin initialization including allowing an interaction between the second plurality of qudits and the first plurality of qudits; The method of claim 12 or 13, wherein the qudit spin initialization step is preferably performed in a first step for a first group of the second plurality of qudits and, after the first step, in a second step for a second group of the second plurality of qudits.

15. 15. The method of claim 12, further comprising a spin readout step involving exchanging charge carriers or providing spin tunneling between the second plurality of qudits and the first plurality of qudits and reading out the state of the first plurality of qudits with the SEB.

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