Substrate for electronic components, method for manufacturing the substrate for electronic components, and display device and semiconductor device including the same

Abstract

The present invention relates to a substrate for electronic components, which includes a substrate having one or more through-type core vias, and an adhesion promotion layer on the surface of the substrate and on the through-type core vias, wherein the hole diameter of one or more of the upper and lower surfaces of the through-type core vias is larger than the hole diameter at a point inside the hole, a method for manufacturing the substrate for electronic components, and a display device and semiconductor device including the same.The inclusion of the adhesion promotion layer not only improves the adhesion of the metal plating layer and prevents defects, but also simplifies the manufacturing process compared to conventional substrates for electronic components.

Description

[Technical Field]

[0001] The present invention relates to a substrate for electronic components including a substrate having through-type core vias, a method for manufacturing the substrate for electronic components, and a display device and a semiconductor device including the same. [Background technology]

[0002] Substrates, which are the base material for various electronic devices such as semiconductor devices and display devices, require ultra-miniaturization of semiconductor devices, simplification of processes, and systematization methods, with the goal of stacking multiple chips in a small area using 2.5D or 3D integrated circuit technology.

[0003] Through-core vias (substrate-through vias, via holes, etc.) provide electrical connections between layers in a physical electronic circuit or chip. For example, in a three-dimensional stacked integrated circuit, through-core vias enable vertical and horizontal integration of electronic components. Typically, through-core vias are used in silicon substrates. Korean Patent Publication No. 10-1459597 discloses a method for manufacturing a through-silicon via (TSV) substrate. However, glass substrates have recently been more widely used in electronic devices because glass is economically cheaper than silicon. Glass substrates can also provide improved electromagnetic loss characteristics, improved dielectric properties, a customized thermal expansion coefficient, and the ability to be provided in scalable form factors.

[0004] Korean Patent Publication No. 10-1685578 provides an electroless palladium plating method that includes providing an electroless palladium plating solution, introducing an inert gas into the electroless palladium plating solution, immersing a substrate in the electroless palladium plating solution, and electrolessly plating the substrate using the electroless palladium plating solution. However, even with this plating method, problems can arise in that the plating film does not have sufficient adhesion and reliability. This can affect the transmission of electrical signals and power, ultimately affecting device performance. Therefore, there is a need for a substrate for electronic components and a method for manufacturing the same that can improve plating adhesion, reduce process defects, and increase yield, prevent electrode lift-off even under harsh conditions, and simplify the manufacturing process. [Prior art documents] [Patent documents]

[0005] [Patent Document 1] Republic of Korea Patent Registration No. 10-1459597 [Patent Document 2] Republic of Korea Patent Registration No. 10-1685578 Summary of the Invention [Problem to be solved by the invention]

[0006] In order to solve the above problems, the object of the present invention is to provide a substrate for electronic components and a method for manufacturing the same that have improved plating adhesion in the process of plating a substrate having a through-type core via.

[0007] An object of the present invention is to provide a substrate for electronic components, which not only allows adjustment of the thickness of the plating layer and prevents electrode lift-up even under severe conditions, but also allows for a simpler manufacturing process than conventional substrates for electronic components, and a method for manufacturing the same.

[0008] Another object of the present invention is to provide a display device and a semiconductor device that include the substrate for electronic components.

[0009] However, the problems to be solved by the present invention are not limited to those mentioned above, and other problems not mentioned will be clearly understood by those skilled in the art from the following description. [Means for solving the problem]

[0010] The present invention relates to a substrate for electronic components, which comprises a substrate including one or more through-core vias, and an adhesion promoting layer on the surface of the substrate and on the through-core vias, wherein the hole diameter of one or more of the upper and lower surfaces of the through-core vias is larger than the hole diameter at a point inside the hole.

[0011] In the present invention, the through-type core via may have an angle of 1° to 25° between a line connecting a point on the upper or lower surface of the core via in a vertical cross section to a point inside the via where the hole diameter is smallest, and a line connecting a point on the upper or lower surface of the core via in a vertical direction.

[0012] In the present invention, the through-core via may have a symmetrical or asymmetrical vertical cross section.

[0013] In the present invention, the inner wall surface of the through-core via may have an uneven shape. The present invention may be characterized in that the substrate is made of glass or quartz.

[0014] In the present invention, the adhesion promoting layer may contain one or more resins selected from the group consisting of UV-curable resins having acrylic groups and polyimide-based thermosetting resins, or may be a film coated with a metal, oxide, or ceramic oxide.

[0015] In the present invention, the adhesion promoting layer may have a thickness of 250 to 6000 Å. In the present invention, the average hole diameter of at least one of the upper and lower surfaces of each of the through-type vias in the substrate may be 5 to 190 μm.

[0016] The present invention relates to a method for manufacturing a substrate for electronic components, which includes the steps of (a) forming an adhesion promotion layer on the surface of a substrate including one or more through-type core vias, and (b) plating a metal on the surface of the substrate on which the adhesion promotion layer is formed, wherein the through-type core vias have a hole diameter on one or more of their upper and lower surfaces that is larger than the hole diameter at a point inside the hole, and the plating step of (b) is performed by one or more methods selected from electrolytic plating and electroless plating.

[0017] In the present invention, the step (a) may further include a surface modification step. In the present invention, the surface modification may be carried out by one or more methods selected from the group consisting of saponification treatment, plasma treatment, corona treatment, and primer treatment.

[0018] The present invention may further include, before step (a), a step of manufacturing a through-type core via in which the hole diameter of one or more of the upper and lower surfaces is larger than the hole diameter at a point inside the hole by adjusting the etching rate of the upper and lower surfaces of the substrate.

[0019] In the present invention, step (b) may be further carried out one or more times. The present invention also relates to a display device and a semiconductor device that include the substrate for electronic components. [Effects of the Invention]

[0020] According to the substrate for electronic components and the manufacturing method thereof of the present invention, in manufacturing a substrate having through-type core vias, the adhesion promoting layer formed by a wet coating method is included, thereby improving the adhesion of the metal plating layer and preventing defects, thereby providing a high-quality substrate for electronic components.

[0021] Furthermore, according to the electronic component substrate and the method for manufacturing the same of the present invention, the thickness of the plating layer can be adjusted in an additional step, and the manufacturing process can be simplified compared to conventional electronic component substrates.

[0022] In the substrate for electronic components and the method for manufacturing the same according to the present invention, the through core via may have a hole diameter at one or more of the top and bottom surfaces that is larger than the hole diameter at a point inside the hole. This prevents the metal plated inside the core via from being subjected to a concentrated impact in either the top or bottom surface of the hole when the volume of the metal inside the through core via expands or contracts, thereby preventing the electrode from lifting up under harsh conditions.

[0023] By applying the electronic component substrate according to the present invention, it is possible to provide a highly reliable display device and semiconductor device. [Brief explanation of the drawings]

[0024] [Figure 1] 1 is a cross-sectional view illustrating a substrate including a through-core via hole according to an embodiment of the present invention (the hourglass-shaped through-core via hole is not shown). [Figure 2] 1 is a cross-sectional view of a substrate for electronic components according to the present invention, on which an adhesion promoting layer is formed (hourglass-shaped through-core via holes are not shown). [Figure 3] 1 is a cross-sectional view of a substrate for electronic components according to the present invention, on which an adhesion promoting layer and a metal electrode layer are formed (hourglass-shaped through-core via holes are not shown). [Figure 4] 1 is a cross-sectional view showing a substrate including a through-core via hole according to an embodiment of the present invention (showing an hourglass-shaped through-core via hole); [Figure 5] 1 is a cross-sectional view of a substrate for electronic components according to the present invention, on which an adhesion promoting layer is formed (showing an hourglass-shaped through-core via hole). [Figure 6] 1 is a cross-sectional view of a substrate for electronic components according to the present invention, on which an adhesion promoting layer and a metal electrode layer are formed (showing an hourglass-shaped through-core via hole). [Figure 7] 1 is a diagram showing a vertical cross section of a through-core via of the present invention, showing the hole diameter at the top, the hole diameter at a point inside the hole, and the hole diameter at the bottom. [Figure 8] This is a diagram showing a vertical cross section of a through-type core via of the present invention, showing the angle of a line connecting a point on the top or bottom surface of the core via to the point where the hole diameter inside the via is smallest, and a line connecting vertically from a point on the top or bottom surface of the core via. [Figure 9] FIG. 1 is a diagram showing a vertical cross section of a through-core via of the present invention, illustrating that the inner wall surface of the through-core via has an uneven shape. [Figure 10] 1 is a photograph of a vertical cross section of a through-core via of the present invention according to Example 1. [Figure 11] 1A and 1B are photographs of a vertical cross section of a through-core via according to Example 1 of the present invention and an enlarged view of the inner wall surface thereof. [Figure 12A] 10 is a photograph of a vertical cross section of a through-core via of the present invention according to Example 3. [Figure 12B] 10 is a photograph of a vertical cross section of a through-core via of the present invention according to Example 3. [Figure 13] 10 is a photograph of a vertical cross section of a through-core via of the present invention according to Example 4. [Figure 14] 1 is a photograph of a vertical cross section of a through-core via of the present invention according to Example 1. DETAILED DESCRIPTION OF THE INVENTION

[0025] The present invention relates to a substrate for electronic components, which includes a substrate including one or more through-type core vias, and an adhesion promotion layer on the surface of the substrate and on the through-type core vias, wherein the hole diameter of one or more of the upper and lower surfaces of the through-type core vias is larger than the hole diameter at a point inside the hole, a method for manufacturing the substrate for electronic components, and a display device and a semiconductor device including the same.

[0026] More specifically, the present invention relates to a method for manufacturing a substrate for electronic components, the method comprising the steps of (a) forming an adhesion promotion layer on a surface of a substrate including one or more through-core vias, and (b) plating the surface of the substrate with the adhesion promotion layer, wherein the through-core vias have a hole diameter at least on the top and bottom surfaces that is larger than the hole diameter at a point inside the hole, and the plating step (b) is performed by one or more methods selected from electrolytic plating and electroless plating, thereby improving plating adhesion. According to the present invention, the adhesion promotion layer may be formed by a wet coating method. This method also has the advantages of forming a more uniform thin film inside the core vias compared to a typical sputtering method, reducing the rate of defects during metal wiring formation, and reducing manufacturing and maintenance costs.

[0027] According to the substrate for electronic components and the manufacturing method thereof of the present invention, the through core via may have a hole diameter at one or more of the top and bottom surfaces that is larger than the hole diameter at a point inside the hole. This prevents the metal plated inside the core via from being subjected to a concentrated impact in either the top or bottom surface of the hole when the volume of the metal inside the through core via expands / contracts, thereby preventing the electrode from lifting up under harsh conditions.

[0028] Although the present invention has been described in terms of a display device and a semiconductor device including the substrate for electronic components through one or more embodiments, the present invention is not limited thereto and can be used without limitation in many fields in which the substrate for electronic components and the manufacturing method thereof can be applied.

[0029] Hereinafter, embodiments of the present invention will be described in more detail with reference to the drawings. However, the following drawings attached to this specification are intended to illustrate preferred embodiments of the present invention and to facilitate a better understanding of the technical concept of the present invention together with the above-described content of the invention, and therefore the present invention should not be interpreted as being limited to the details shown in such drawings.

[0030] As used herein, "comprises" and / or "comprising" and / or "having" do not exclude the presence or addition of one or more other components, steps, operations and / or elements other than the stated components, steps, operations and / or elements. Like reference numerals refer to like elements throughout the specification.

[0031] Spatially relative terms such as "below," "bottom," "lower," "upper," "top," "top," and the like can be used to easily describe the relationship of one element or component to other elements or components as depicted in the figures. Spatially relative terms should be understood to include different orientations of elements in use or operation in addition to the orientation depicted in the figures. For example, if elements depicted in the figures are turned over, an element described as "below" or "below" another element may be placed "above" the other element. Thus, the exemplary term "below" can encompass both an orientation of below and above. Elements can be oriented in other directions, thereby allowing the spatially relative terms to be interpreted accordingly.

[0032] Furthermore, the term "surface" may refer not only to the upper and lower parts of an object spatially, but also to all external parts that appear on the surface. For example, "the surface of a substrate including a through-core via" can be interpreted as a term that includes the upper and lower surfaces of the substrate as well as the inner (or internal) wall surfaces of the core via holes.

[0033] As used in this specification, "substantially" can be interpreted to include not only being completely identical or identical physically, but also being within the range of error in measurement or manufacturing processes, for example, an error range of 0.1% or less.

[0034] <Electronic component substrates> The present invention relates to a substrate for electronic components, comprising a substrate including one or more through-core vias and an adhesion promotion layer on the surface of the substrate and on the through-core vias. In particular, the substrate may comprise a material selected from glass or quartz. The substrate for electronic components manufactured according to an embodiment of the present invention may have a plating adhesion of 4B or more as a result of an adhesion test according to the international standard ASTM D3359, but is not limited thereto. The substrate for electronic components of the present invention may further comprise a metal plating layer on the adhesion promotion layer.

[0035] The through core via according to the present invention may have a hole diameter at one or more of the top and bottom surfaces that is larger than the hole diameter at a point inside the hole. This prevents the metal plated inside the core via from being subjected to a concentrated impact in either the top or bottom surface of the hole when the volume of the metal inside the through core via expands / contracts, thereby preventing the electrode from lifting up under harsh conditions.

[0036] Preferably, the substrate for electronic components of the present invention may be produced by the method described below in <Method for producing substrate for electronic components>.

[0037] substrate As the substrate for electronic components of the present invention, materials with low electrical conductivity such as glass, quartz, polyimide, etc. can be used. In particular, it is preferable to use a glass or quartz material as the substrate because of its excellent chemical durability and optical properties. From the same viewpoint, it is even more preferable to select a glass material rather than quartz.

[0038] Fig. 1 is a cross-sectional view showing a substrate including a through-type core via according to one embodiment of the present invention. Fig. 2 is a cross-sectional view of a substrate for electronic components of the present invention on which an adhesion promotion layer is formed. Fig. 3 is a cross-sectional view of a substrate for electronic components of the present invention on which an adhesion promotion layer and a metal electrode layer are formed. (Hourglass-shaped through-type core via holes, which will be described later, are not shown in Figs. 1 to 3.) According to one embodiment of the present invention, the substrate is more preferably a glass substrate 10 including one or more through-core vias, as shown in FIG. 1. The glass substrate is characterized by its versatile utility and excellent durability, and the composition for manufacturing the glass substrate is not particularly limited and can be selected according to the desired application. For example, the glass substrate may be WILLOW® glass, Eagle XG glass, manufactured by Corning Incorporated. TM The glass substrate may be formed from any glass suitable for electronic applications, including, but not limited to, glass, NSG soda lime glass, NEG Glass, or Code 2318 glass, etc. Other types of ion-exchangeable glass or fused silica may be used to form the glass substrate.

[0039] Furthermore, a substrate having through-type core vias can be manufactured by punching through-type core vias into a substrate using processes commonly used in this field. The shape and size of the substrate are not limited, and may be rectangular or circular, but a rectangular shape may be advantageous in terms of processing. The average thickness of the substrate can be selected without limitation as needed, and may be 30 μm or more to 100 μm or less in the case of UTG (ultra thin glass), or up to 1100 μm, preferably 250 to 700 μm, for substrates used in communications, displays, and semiconductors. It is preferable in terms of durability if the thickness of the substrate satisfies the above range.

[0040] The through-type core via may be a through-type having a hole formed on both the top and bottom surfaces and sidewalls, and may have a horizontal cross section that is circular, elliptical, or polygonal, but is not limited thereto. The horizontal cross sections of the top and / or bottom surfaces may be the same as or different from the horizontal cross section of the interior of the hole. Preferably, the through-type core via may have circular horizontal cross sections on the top, bottom, and interior of the hole. The through-type core via of the present invention may be designed to maintain electrical properties by allowing an electrically conductive material, such as copper or other metal, to be filled through the core via hole without inserting a component. The through-type core via may be formed in the substrate by any suitable method, for example, drilled in the substrate using a pulsed laser. The average hole diameter of at least one of the top and bottom surfaces of each through-type core via may be 5 to 190 μm, most preferably 20 to 50 μm. When the above range is satisfied, a uniform plating layer can be formed and electrical interference can be prevented. In the present invention, the "hole diameter" of a through-core via refers to the diameter when the via is circular in horizontal cross section, and if it is not circular, it may be the length of the longest line connecting any two points on the horizontal cross section of the via. In the present invention, the "cross-sectional area" of a through-core via may refer to the area of ​​the horizontal cross section of the via.

[0041] FIG. 4 is a cross-sectional view showing a substrate including a through-type core via according to an embodiment of the present invention. FIG. 5 is a cross-sectional view of a substrate for electronic components according to the present invention on which an adhesion promotion layer is formed. FIG. 6 is a cross-sectional view of a substrate for electronic components according to the present invention on which an adhesion promotion layer and a metal electrode layer are formed. (Hourglass-shaped through-type core via hole is shown.) FIG. 7 is a vertical cross-sectional view of a through-type core via according to the present invention, showing the hole diameter on the top surface, the hole diameter at a point inside the hole, and the hole diameter on the bottom surface. The core via according to the present invention may be configured on the top surface, the bottom surface, and the inside of a hole connecting the top and bottom surfaces (which has the same meaning as "inside"). In one example of the present invention, referring to FIGS. 4 to 7, the hole diameter of the core via on the top surface and the hole diameter at a point inside the hole may be smaller than the hole diameter of the core via on the top surface and the hole diameter of the core via on the bottom surface. Alternatively, in one example of the present invention, the cross-sectional areas of the core vias on the top surface and the bottom surface may be larger than the cross-sectional area of ​​a point inside the hole. More specifically, the cross-sectional area or diameter of the core via may decrease from the top and bottom surfaces toward the interior of the hole. By providing a point with a smaller cross-sectional area or diameter within the hole, when the substrate of the present invention is subjected to external physical impact or the volume of the metal inside the through-type core via expands or contracts depending on temperature / humidity, the impact is prevented from concentrating on either the top or bottom surface of the hole on the metal plated inside the core via, thereby preventing the metal from being detached from the core via. Specifically, when the substrate is subjected to external physical impact or the volume of the metal inside the hole expands or contracts depending on temperature / humidity, a conventional structure in which force is concentrated in either the top or bottom surface causes electrode detachment. In contrast, the substrate of the present invention distributes the impact in both the top and bottom surfaces from the point with the smaller cross-sectional area or diameter within the hole, preventing the metal from being detached from the core via.

[0042] In one embodiment of the present invention, the through core via of the present invention may have a symmetric or asymmetric vertical cross section. In one embodiment of the present invention, the through core via of the present invention may have an hourglass-shaped vertical cross section, and the hourglass may be symmetric or asymmetric.

[0043] When the core via of the present invention is symmetrical, the point where the cross-sectional area or diameter of the core via hole is smallest may be located at, but is not limited to, a point of 40-60% when the top surface of the line connecting the top and bottom surfaces of the core via is 0% and the bottom surface is 100%. When the core via of the present invention is asymmetrical, the point where the cross-sectional area or diameter of the core via hole is smallest may be located at, but is not limited to, a point of 15-35% or 65-75% when the top surface of the line connecting the top and bottom surfaces of the core via is 0% and the bottom surface is 100%.

[0044] More specifically, Figure 8 is a view showing a vertical cross section of a through-type core via of the present invention, showing the angle of a line connecting a point on the top or bottom surface of the core via to the point where the hole diameter inside the via is smallest, and a line connecting vertically from the point on the top or bottom surface of the core via. Referring to Figure 8, the through-type core via of the present invention can include a form in which the angle of the line connecting a point on the top or bottom surface of the core via to the point where the hole diameter inside the via is smallest, and a line connecting vertically from the point on the top or bottom surface of the core via, in the vertical cross section, is 1° to 25°, preferably 3° to 20°, and most preferably 5° to 18°. This is most advantageous for achieving the object of the present invention.

[0045] In the present invention, as described above, symmetrical / asymmetrical through-core vias, in which a point with a small cross-sectional area or hole diameter is located inside the hole, can be formed by adjusting the etching rate and ratio of the top and bottom surfaces during core via fabrication. For example, when etching the top and bottom surfaces of a substrate to form a through-core via, if both the top and bottom surfaces are simultaneously etched, the etching exposure intensity decreases as one moves from the top and bottom surfaces toward the inside of the substrate, thereby forming a symmetrical hourglass-shaped core via. In this case, a known etchant for etching a substrate can be used for the etching, and an etchant composition containing hydrofluoric acid can be used, but is not limited thereto. For example, the etchant composition can contain hydrofluoric acid, nitric acid, sulfuric acid, and additives such as a surfactant, an additive for controlling defoaming properties, and / or distilled water.

[0046] In another embodiment of the present invention, if the etching time of one of the upper and lower surfaces is increased, an asymmetric hourglass-shaped core via can be formed.

[0047] The etching time varies depending on the thickness of the substrate, but can be performed for about 3 to 4 hours for a substrate with a thickness of 400 Å to 500 Å, but is not limited to this.

[0048] Regarding the formation of symmetric or asymmetric hourglass-shaped core vias depending on the etching time, according to one example of the present invention, a symmetric hourglass-shaped core via can be formed when etching is performed to simultaneously expose the top and bottom surfaces.

[0049] Furthermore, in order to form an asymmetric hourglass-shaped core via, the exposure of the etching solution composition to the upper and lower surfaces of the substrate can be adjusted. As an example, the asymmetric ratio of the hourglass shape can be adjusted by exposing the substrate to the etching solution composition in a horizontally opposed manner to the surface of the upper or lower surface that has the shortest distance to the section with the smallest hole diameter. That is, a method can be applied in which the substrate is floated in the etching solution composition and adjusted so that the etching solution composition and the substrate are horizontally opposed to each other.

[0050] Furthermore, although the method is not particularly limited, in order to adjust the degree of exposure of the etching solution composition to be different on the upper and lower surfaces of the substrate, an acid-resistant jig (e.g., Teflon (registered trademark)) may be applied to one of the upper and lower surfaces to physically block the exposure of the etching solution composition.

[0051] In the core vias of the present invention, the hole diameter of the core via on the upper surface and the hole diameter of the core via on the lower surface may be the same or different. Furthermore, when the substrate of the present invention includes multiple core vias, the shape and hole diameter of each core via may be the same or different. For example, the core vias can be designed taking into consideration the contact area of ​​elements or wiring located on the upper and / or lower sides of the substrate of the present invention, and the connected configuration of RDL or PAD, connection terminal, etc. For example, when a large electrical contact area on the upper surface is required or a small electrical contact area on the lower surface is required, the shape of the core via can be adjusted accordingly.

[0052] 9 is a vertical cross-sectional view of a through-core via of the present invention, illustrating a configuration in which the inner wall surface of the through-core via includes irregularities. Specifically, the inner wall surface of the through-core via of the present invention may have a large surface area, or may include, for example, repeated or non-repeated irregularities. This provides a three-dimensional anchoring effect to the metal plated inside the through-core via of the present invention, thereby improving adhesion. That is, in the present invention, the roughness inside the through-core via is increased to increase the specific surface area, and by forming irregularities inside the through-core via, the interface with the increased (generated) area due to the irregularities increases the contact area when a metal electrode is formed. The anchoring effect and lay due to the waviness of the surface irregularities also contribute to the improvement of adhesion that is desired in the present invention.

[0053] More preferably, the inner wall surface of the through-core via of the present invention may have a specific surface area that is increased by 10 to 300%, preferably 50 to 300%, compared to the inner wall surface of a conventional core via that does not include irregularities, thereby providing an interface that can adhere to the metal formed inside the core. If the specific surface area is increased excessively beyond this range, the surface of the substrate may become porous, which may reduce the mechanical strength of the substrate.

[0054] In order to form the above-mentioned unevenness on the inner wall surface of the through core via of the present invention, known methods can be used. For example, the roughness of the inner wall surface of the through core via can be adjusted by adjusting the etching rate using an ultrasonic cleaning method.

[0055] More specifically, to form the aforementioned irregularities on the inner wall surface of the through-core via of the present invention, ultrasonic vibrations are applied to the sample at regular time intervals during ultrasonic cleaning, allowing for process variables such as adjusting the etched shape and increasing surface roughness. Ultrasonic cleaning is performed by repeatedly turning on and off the ultrasonic cleaning at regular time intervals, which allows for the concentration to be adjusted by adjusting the circulation of the etchant composition inside and adjusting the time for the composition to reach equilibrium. Etching occurs immediately based on this concentration, and when the concentration decreases, the circulation of the solution outside the etching area where the high-concentration etchant composition is present can be promoted, allowing for the concentration of the etchant composition to be adjusted to a constant rate. The point at which sludge, etc., is removed during etching can be used as a process parameter to appropriately adjust the timing of turning on and off the ultrasonic waves, thereby controlling the formation of the aforementioned irregularities on the inner wall surface of the through-core via.

[0056] Specifically, a higher aspect ratio (the average thickness of the substrate relative to the average diameter of the core via) can further improve the integrated circuit performance of the semiconductor device and reduce the size and stress effects of the package. However, a higher aspect ratio can make it more difficult to metallize the sidewalls of the core via, and if the diameter of the core via is too small, voids can occur during the process of filling the core via with a conductive material. Therefore, in one embodiment of the present invention, an aspect ratio of 1:10 to a maximum of 1:30 is most preferable in terms of ease of processing and semiconductor device performance.

[0057] The number of core vias is 2 It is preferable to use 1 to 5,000 core vias per cm of substrate in order to apply the core vias to a substrate for electronic components that has sufficient conductivity while maintaining low resistance, but the present invention is not limited to this, and a substrate having core vias formed therein can be used as needed. For example, when the density of the core vias is low, it is preferable to use 1 to 5,000 core vias per cm of substrate. 2 It may be 1 or more and less than 400 per unit area.

[0058] Adhesion promoting layer FIG. 2 shows an example of a substrate having an adhesion promotion layer according to the present invention. As shown in FIG. 2, the adhesion promotion layer 20 may be formed in direct contact with the surface of the substrate 10 or may be formed to improve the adhesion of a metal plating layer formed later through a plating process. The adhesion promotion layer may include at least one polymer selected from the group consisting of a UV-curable resin having an acrylic group and a polyimide-based thermosetting resin, which can be polymerized by appropriate light or heat. The adhesion promotion layer according to the present invention includes a film coated with a metal, oxide, and / or ceramic oxide. In this case, the material contained in the adhesion promotion layer is not limited to specific materials such as organic or inorganic materials, metals, and oxides, but may be formed in the form of a continuous layer of organic and / or inorganic materials. The adhesion promotion layer according to the present invention may also be a thin film deposited by methods such as sputtering or CVD, and the thin film may include ITO, IZO, AZO, IGZO, CuO, and / or TiO.

[0059] The UV-curable resin may be any material known in the art to be usable for negative photoresists, without limitation. However, a UV-curable resin having an acrylic group is more preferred in that it has excellent adhesion to the substrate surface and can ensure interfacial adhesion with the metal contained in the metal plating layer, thereby providing excellent adhesion between the upper and lower coating films relative to the adhesion-promoting layer.

[0060] The polyimide-based thermosetting resin has excellent heat resistance, solvent resistance, chemical resistance, mechanical properties, and electrical insulation properties when cured, making it more suitable for forming an adhesion promoting layer for a substrate for electronic components than the UV-curable resin. The weight-average molecular weight (measured by GPC) of the polyimide is not particularly limited, but may be, for example, from 1,000 g / mol to 200,000 g / mol, or from 10,000 g / mol to 200,000 g / mol.

[0061] The adhesion promoting layer may be prepared by coating and curing a composition containing a photopolymerizable compound, a photopolymerization initiator, a heat curing agent, a solvent, and / or an additive to the polymer material.

[0062] The photopolymerizable compound is a compound that can be polymerized by the action of the following photopolymerization initiator, and a monofunctional monomer or a difunctional or higher functional monomer can be used, and preferably a difunctional or higher functional monomer can be used.

[0063] Specific examples of the monofunctional monomer include, but are not limited to, nonylphenyl carbitol acrylate, 2-hydroxy-3-phenoxypropyl acrylate, 2-ethylhexyl carbitol acrylate, 2-hydroxyethyl acrylate, and N-vinylpyrrolidone.

[0064] Specific examples of the bifunctional or higher functional monomers include, as bifunctional monomers, 1,6-hexanediol di(meth)acrylate, ethylene glycol di(meth)acrylate, neopentyl glycol di(meth)acrylate, triethylene glycol di(meth)acrylate, bis(acryloyloxyethyl)ether of bisphenol A, and 3-methylpentanediol di(meth)acrylate, and examples of trifunctional or higher functional monomers include trimethylolpropane tri(meth)acrylate, ethoxylated trimethylolpropane tri(meth)acrylate, and ethoxylated trimethylolpropane tri(meth)acrylate. Examples of the ethoxylated dipentaerythritol hexa(meth)acrylate include, but are not limited to, dipentaerythritol tri(meth)acrylate, propoxylated trimethylolpropane tri(meth)acrylate, pentaerythritol tri(meth)acrylate, pentaerythritol tetra(meth)acrylate, dipentaerythritol penta(meth)acrylate, ethoxylated dipentaerythritol hexa(meth)acrylate, propoxylated dipentaerythritol hexa(meth)acrylate, or dipentaerythritol hexa(meth)acrylate.

[0065] The photopolymerizable compound may be contained in an amount of more than 30 wt% and less than 95 wt% of the total composition (100 wt%). Preferably, when the amount is in the range of more than 40 wt% and less than 90 wt%, the photoconversion efficiency, degree of cure, and dispersion stability are improved, which is advantageous in terms of the strength and smoothness of the pixel portion. If the photopolymerizable compound is contained in an amount less than this range, it becomes difficult to ensure fluidity for inkjetting, and if it is contained in an amount exceeding this range, problems such as reduced adhesion may occur. Therefore, it is preferable to contain the photopolymerizable compound within this range.

[0066] The photopolymerization initiator can be used without any particular limitation as long as it can polymerize the photopolymerizable compound. For example, it is preferable to use one or more compounds selected from the group consisting of acetophenone-based compounds, benzophenone-based compounds, triazine-based compounds, biimidazole-based compounds, oxime-based compounds, thioxanthone-based compounds, and phosphine oxide compounds as the photopolymerization initiator, from the viewpoints of polymerization characteristics, initiation efficiency, absorption wavelength, availability, cost, etc.

[0067] For example, the use of an oxime compound or a phosphine oxide compound can ensure better physical properties such as cured density and surface roughness of the cured film. Specific examples of the oxime compound include o-ethoxycarbonyl-α-oximino-1-phenylpropan-1-one, and representative commercially available products include Irgacure OXE 01 and OXE 02 manufactured by BASF.

[0068] Typical examples of the phosphine oxide compound include Darocur TPO and Lucirin TPO manufactured by BASF, which are trimethylbenzoylphenylphosphine oxides, and diphenyl(2,4,6-trimethylbenzoyl)phosphine oxide manufactured by TCI.

[0069] The photopolymerization initiator may be contained in an amount of 0.1 to 10 wt %, preferably 0.5 to 8 wt %, based on 100 wt % of the total composition. When the photopolymerization initiator is contained within this range, sufficient curing can be achieved by light or heat, making it possible to form an adhesion-promoting layer having excellent physical properties such as hardness, and the composition is made highly sensitive, thereby shortening the exposure time, thereby improving productivity, which is preferable.

[0070] The photopolymerization initiator may further contain a photopolymerization initiation aid to improve the sensitivity of the composition according to the present invention. When the photopolymerization initiation aid is contained, there is an advantage that the sensitivity is further increased and productivity is improved. The photopolymerization initiation aid is preferably, but is not limited to, one or more compounds selected from the group consisting of amine compounds, carboxylic acid compounds, and organic sulfur compounds having a thiol group. The photopolymerization initiation aid may be added as needed within a range that does not impair the effects of the present invention.

[0071] The thermal curing agent is activated by heat, and examples thereof include phenolic resin curing agents such as phenol novolac resin, trifunctional phenol novolac resin, cresol novolac resin, bisphenol A novolac resin, xylene novolac resin, triphenyl novolac resin, biphenyl novolac resin, dicyclopentadiene novolac resin, naphthalene novolac resin, phenol p-xylene resin, phenol 4,4'-dimethylbiphenylene resin, phenol dicyclopentadiene novolac resin, dicyclopentadiene-phenol novolac (DCPD-phenol), xylok (p-xylene modified), triazine compounds, dihydroxynaphthalene, and dihydroxybenzene; aliphatic acid anhydrides such as dodecenyl succinic anhydride (DDSA) and polyazelaic polyanhydride; and hexahydrophthalic anhydride. Examples of suitable curing agents include, but are not limited to, acid anhydride curing agents such as alicyclic acid anhydrides such as methyl tetrahydrophthalic anhydride (HHPA), methyl tetrahydrophthalic anhydride (MeTHPA), methylnadic anhydride (MNA), and aromatic acid anhydrides such as trimellitic anhydride (TMA), pyromellitic acid dianhydride (PMDA), benzophenonetetracarboxylic dianhydride (BTDA), and amine curing agents such as 4,4'-dimethylaniline (diamino diphenyl methane, DAM or DDM), diamino diphenyl sulfone (DDS), and dicyandiamide (DICY).The content of the heat curing agent can be suitably selected according to the amount generally used in this technical field, and is not particularly limited.

[0072] The solvent is not particularly limited as long as it allows the curable resin to have an appropriate viscosity, can easily dissolve the remaining components, and does not damage the substrate, and various organic solvents used in the field of manufacturing substrates for electronic components can be used.

[0073] Specific examples of the solvent include ethylene glycol monoalkyl ethers such as ethylene glycol monomethyl ether, ethylene glycol monoethyl ether, ethylene glycol monopropyl ether, and ethylene glycol monobutyl ether; diethylene glycol dialkyl ethers such as diethylene glycol dimethyl ether, diethylene glycol diethyl ether, diethylene glycol dipropyl ether, and ethylene glycol dibutyl ether; ethylene glycol alkyl ether acetates such as methyl cellosolve acetate and ethyl cellosolve acetate; propylene glycol dialkyl ethers such as propylene glycol monomethyl ether; and propylene glycol monomethyl ether. alkylene glycol alkyl ether acetates such as acetate, propylene glycol monoethyl ether acetate, propylene glycol monopropyl ether acetate, methoxybutyl acetate, and methoxypentyl acetate; aromatic hydrocarbons such as benzene, toluene, xylene, and mesitylene; ketones such as methyl ethyl ketone, acetone, methyl amyl ketone, methyl isobutyl ketone, and cyclohexanone; alcohols such as ethanol, propanol, butanol, hexanol, cyclohexanol, ethylene glycol, and glycerin; esters such as ethyl 3-ethoxypropionate and methyl 3-methoxypropionate; and cyclic esters such as γ-butyrolactone.

[0074] Of the solvents, in terms of coatability and drying property, organic solvents having a boiling point of 100 to 200°C are preferred, more preferred are alkylene glycol alkyl ether acetates, ketones, and esters such as ethyl 3-ethoxypropionate and methyl 3-methoxypropionate, and even more preferred are propylene glycol monomethyl ether, propylene glycol monomethyl ether acetate, propylene glycol monoethyl ether acetate, cyclohexanone, ethyl 3-ethoxypropionate, methyl 3-methoxypropionate, and the like.

[0075] The solvent may also include an aprotic solvent, and preferably includes one or more polar aprotic solvents selected from, for example, acetone, acetonitrile, m-cresol, tetrahydrofuran (THF), N-methylpyrrolidone (NMP), N,N-dimethylformamide (DMF), N,N-dimethylacetamide (DMAc), dimethyl sulfoxide (DMSO), and diethyl acetate.

[0076] The solvents can be used alone or in combination of two or more. When the solvent is contained in an amount of 30 to 70% by weight relative to 100% by weight of the composition, this provides an effect of improving coatability when the composition is applied using a coating device such as a roll coater, spin coater, slit and spin coater, dip coater, slit coater (sometimes called a slot die coater), or inkjet.

[0077] In addition, in order to enhance the flatness or adhesion of the adhesion promoting layer, additives commonly used in the art may be further included within the scope of the present invention. Specifically, the adhesion promoting layer may further include a leveling agent, a defoaming agent, a surfactant, an adhesion promoting agent, a UV absorber, an anti-agglomeration agent, and / or a dispersant. Similarly, the additives may be appropriately added and used by those skilled in the art within the scope of the present invention without impairing the effects of the present invention.

[0078] The surfactant may further include a fluorine-based surfactant, which can improve the flatness of the coating film. Furthermore, a mixture of two or more surfactants with different particle sizes and structures can be used to achieve uniform inkjet spraying and to protect the substrate from oxygen and moisture penetration during the process. Examples of fluorine-based surfactants that can be used include, but are not limited to, BM-1000, BM-1100 (BM Chemie), Fluorad FC-135 / FC-170C / FC-430 (Sumitomo 3M Limited), SH-28PA / -190 / -8400 / SZ-6032 (Toray Silicones Co., Ltd.), and Megaface F-554 / Megaface F-559 / Megaface F-563 (DIC Corporation).

[0079] The dispersant is a type of surfactant, which uniformly disperses solids in a solvent to provide high-density flowability and ensure optimal dispersibility in the process, and may be any dispersant commonly used in the art without limitation.

[0080] The adhesion promoter can be added to enhance adhesion to the substrate and can include, but is not limited to, a silane coupling agent having a reactive substituent selected from the group consisting of a carboxyl group, a methacryloyl group, an isocyanate group, an epoxy group, and combinations thereof. Specific examples include, but are not limited to, vinyltrimethoxysilane, vinyltriethoxysilane, vinyltris(2-methoxyethoxy)silane, N-(2-aminoethyl)-3-aminopropylmethyldimethoxysilane, N-(2-aminoethyl)-3-aminopropyltrimethoxysilane, 3-aminopropyltriethoxysilane, 3-glycidoxypropyltrimethoxysilane, 3-glycidoxypropylmethyldimethoxysilane, 2-(3,4-epoxycyclohexyl)ethyltrimethoxysilane, 3-chloropropylmethyldimethoxysilane, 3-chloropropyltrimethoxysilane, 3-methacryloyloxypropyltrimethoxysilane, and 3-mercaptopropyltrimethoxysilane.

[0081] The additives can be used in an amount of 0.01 to 10 wt %, specifically 0.02 to 8 wt %, and more specifically 0.03 to 5 wt %, based on 100 wt % of the total composition, but are not limited thereto. When the additives are used in an amount within the above range, the coating properties, flatness, adhesion, etc. of the composition can be improved, which is preferable.

[0082] In one embodiment, the thickness of the adhesion promotion layer 20 may be 250 to 6000 Å, preferably 500 to 3000 Å, and more preferably 1000 to 1500 Å. It is preferable that the thickness of the adhesion promotion layer satisfies the above range in that the adhesion of the plating layer provided on the adhesion promotion layer is improved.

[0083] The adhesion-promoting layer applied between the metal plating layer and the glass substrate can improve the adhesion of the metal plating layer to the glass substrate. When forming electrodes on a substrate containing through-vias, the improved adhesion between the electrode and the glass substrate prevents distortion and deformation of the substrate due to thermal shock and / or thermal deformation during the process, ensuring the reliability of the electrodes. It also increases physical adhesion, preventing corrosion due to moisture and / or gas, and thus improving the durability of the substrate. The plating adhesion of the substrate for electronic components of the present invention is preferably 4B or higher. If the plating adhesion of the metal plating layer is below this range, durability issues may arise for the electronic component substrate and the semiconductor package including the same. The plating adhesion may be 4B or higher, and more preferably 5B, in terms of durability, as evaluated according to ASTM D3359, an international standard. According to the evaluation criteria of the international standard, the adhesion of the metal plating layer according to one embodiment of the present invention may be such that no peeling is observed or peeling is observed in an area of ​​less than 5% of the target area during evaluation.

[0084] Metal plating layer Referring to FIG. 3, a substrate for electronic components according to an embodiment of the present invention may have a metal plating layer formed on the surface of the adhesion promoting layer.

[0085] The plating layer is not particularly limited as long as it contains a conductive metal. However, a plating layer made from a metal ink is preferred in terms of ease of processing, such as low cost, productivity, and maintenance. Specifically, when the metal plating layer is formed using the metal ink, it can form a sufficiently thick plating layer, shorten production time compared to when using a general metal, achieve low resistance, and is suitable for forming metal layers on complex structures, such as core vias, that are difficult to apply general photolithography methods to. The metal ink is a dispersion of metal nanoparticles of consistent size and shape in an alcohol and / or hydrocarbon solvent, and the metal nanoparticles are preferably contained in an amount of 3 to 50 wt% based on the total weight of the dispersion. The metal nanoparticles may be conductive silver, gold, nickel, copper, or a combination thereof. Copper is more preferred due to its economical advantages and superior electrical conductivity compared to other metals. The metal nanoparticles may have a particle size of 100 nm or less, with a particle size of 30 to 60 nm being preferred in terms of ease of processing. The solvent may include common solvents used in the art, and more preferably, alcohol-based compounds such as methanol, ethanol, isopropanol, butanol, propylene glycol, methoxy alcohol, etc.; and hydrocarbon-based compounds such as hexane, heptane, benzene, toluene, xylene, ethylene-based compounds, and acetate-based compounds; which may be used alone or in combination of two or more.

[0086] <Method of manufacturing substrates for electronic components> The method for manufacturing a substrate for electronic components of the present invention includes the steps of (a) forming an adhesion promotion layer on the surface of a substrate including one or more through-type vias, and (b) plating a metal onto the surface of the adhesion promotion layer, wherein the plating step (b) is carried out by one or more methods selected from electrolytic plating and electroless plating.

[0087] Furthermore, the method for manufacturing a substrate for electronic components according to the present invention may further include a photo process (step (c)) for realizing a circuit after step (b), or may further perform step (b) one or more times.

[0088] A method for manufacturing a substrate for electronic components according to one or more embodiments of the present invention may include (a) forming an adhesion promotion layer on a surface of a substrate including one or more through-type core vias, and (b) plating the surface of the substrate with the adhesion promotion layer with metal, thereby improving the adhesion of the metal plating layer. The through-type core vias may have a larger hole diameter at one or more of their upper and lower surfaces than the hole diameter at a point inside the hole. Furthermore, after steps (a) and (b), additional steps may be included, such as step (c) and a subsequent step including a photolithography process. Alternatively, before steps (a), (b), and (c), a step of punching through-type core vias in the substrate through a preparation process may be added. In particular, before step (a), a step of adjusting the etching rate of the upper and lower surfaces of the substrate to form through-type core vias whose hole diameter at one or more of their upper and lower surfaces is larger than the hole diameter at a point inside the hole may be further included. The preparation step is omitted here, as the same description of the substrate described above in the <Substrate for Electronic Components> is applicable.

[0089] (a) forming an adhesion promotion layer on a surface of a substrate containing one or more through-core vias; The step of forming the adhesion promoting layer of the present invention may be carried out by coating a composition for forming the adhesion promoting layer.

[0090] The composition for forming an adhesion promoting layer of the present invention may be a composition containing the resin, solvent, etc. described above in the section <Adhesion promoting layer>.

[0091] According to one or more embodiments of the present invention, the substrate on which the adhesion promotion layer is formed may be made of a material selected from glass or quartz, as described in <Substrate for electronic components>, and it is preferable to select a glass material in terms of coatability, optical properties, chemical durability, etc.

[0092] Examples of the coating method include coating processes such as spin coating, roller coating, bar coating, dip coating, gravure coating, curtain coating, die coating, spray coating, doctor coating, and kneader coating; printing processes such as screen printing, spray printing, inkjet printing, letterpress printing, intaglio printing, and lithographic printing; and deposition processes such as in-mold labeling (IML), chemical vapor deposition (CVD), physical vapor deposition (PVD), and plasma-enhanced chemical vapor deposition (PECVD). According to one embodiment of the present invention, a coating solution is applied to form a uniform coating film to form the adhesion-promoting layer. Among these methods, various wet coating methods such as slot die coating, spin coating, dip coating, bar coating, and spray coating may be used without limitation. In particular, slot die coating or spin coating is preferred in terms of coatability and processability. The present invention has the advantage that by forming an adhesion promoting layer using wet coating, the production speed is improved compared to the conventional sputtering method, ensuring productivity, and enabling a low-cost, highly efficient process.

[0093] According to one embodiment of the present invention, a surface modification process may be further included as a pretreatment prior to coating the adhesion-promoting layer. The surface modification may be performed using a saponification treatment, plasma treatment, corona treatment, primer treatment, or the like. Corona treatment is preferred for ease of processing. The coating film is then dried by heating at a temperature of 50°C to 150°C or 50°C to 100°C using a heating device such as a hot plate, a hot air circulating oven, or an infrared oven to volatilize the solvent. To heat-treat and harden the dried coating film, heat or light may be applied as appropriate depending on the type of polymeric material, i.e., UV-curable resin or thermosetting resin. The light treatment may use g-ray (wavelength: 436 nm), h-ray, i-ray (wavelength: 365 nm), or the like. The UV irradiation dose may be appropriately selected as needed, and is not limited thereto in the present invention. The heat treatment can be carried out using a heating means such as a hot plate, a hot air circulation oven, or an infrared oven at a temperature of 200°C or higher, preferably 200°C or higher and 300°C or lower, which can be appropriately selected as needed, and is not limited thereto in the present invention.

[0094] (b) plating a metal on the surface of the substrate on which the adhesion promoting layer has been formed; The plating step of the present invention may be performed by a wet coating method. In one embodiment of the present invention, this step may be performed using a metal ink. The metal ink may be any of the metal plating layer described above, without limitation.

[0095] According to one embodiment of the present invention, a seed layer is first formed by a metal ink coating and sintering process commonly used in the industry, and then a metal plating layer is formed by applying the electrolytic plating and electroless plating methods described below. By performing the above processes in a stepwise manner, a metal plating layer with excellent adhesion can be formed not only on the upper and lower surfaces of a glass substrate having a through-type core via, but also on the inner wall of the core via.

[0096] Specifically, this step may be performed by one or more methods selected from electroplating and electroless plating. In particular, the present invention includes an adhesion-promoting layer on the substrate, so that even when no current is applied in the plating step and only metal ink is used, metal plating can be performed uniformly with high adhesion even in the through-core via portion of the substrate. Of course, electroplating methods that apply current can also be applied to the present invention.

[0097] The electroplating may be any method known in the art, such as in the fields of electrical and electronic circuits, semiconductors, and / or communications, without any particular limitations. Specifically, the electroplating step may be performed by wet-coating a metal ink on the surface of the substrate on which the adhesion promotion layer is formed, followed by applying a current. When the metal ink is wet-coated on the surface of the substrate on which the adhesion promotion layer is formed, a metal seed may be formed on the adhesion promotion layer. The metal ink may be coated by a method such as spin coating.

[0098] The substrate on which the metal seed is formed by the metal ink coating can be electroplated by applying an electric current to an electrolytic solution. The electrolytic solution is not particularly limited as long as it contains an electrolytic substance such as chloride ions, lithium ions, CuSO4, or H2SO4. The electric current is 0.5 to 20 ASD (amps / dm 2 If the thickness is less than the above range, the plating crystal grains become coarse and the adhesion of the metal plating layer decreases, and if the thickness is more than the above range, an edge burning phenomenon occurs when excess plating current is concentrated at the edge, which may cause the work to be unsmooth.

[0099] The electroless plating method may be performed by wet coating a metal ink onto the surface of the substrate on which the adhesion promoting layer is formed, or may be performed without additional electrolyte treatment and / or application of current. Substrates without an adhesion promoting layer have low adhesion, making it impossible to achieve plating with sufficient adhesion and uniformity on the upper surface of a glass substrate using electroless plating alone. However, in the present invention, the introduction of an adhesion promoting layer on the substrate makes it possible to achieve uniform, highly adhesive plating using electroless wet plating alone without application of current.

[0100] In the present invention, step (b) may be repeated one or more times. When step (b) is repeated multiple times, a multi-layer laminate can be formed, and in this case, an insulating film may be further included between the multi-layer laminates. Any configurations or techniques commonly used in the art related to the multi-layer laminate and / or the insulating film can be applied to the present invention without limitation. This allows the film thickness of the metal plating layer to be adjusted as desired. Specifically, step (b) can be performed one or more times to produce a metal plating layer with a thickness of approximately 10 μm. The final thickness of the recovered and metal plating layer may vary depending on the content of the metal ink and / or the coating method.

[0101] (c) Subsequent steps The method for manufacturing a substrate for electronic components according to the present invention may further include a photolithography process for realizing a circuit after step (b). The photolithography process may be a known method for forming a pattern on a metal plating layer, such as a printed circuit board (PCB), a chip-on-glass (COG) for micro LEDs, or a front-end module (FEM) substrate for high-frequency RF. Examples of the photolithography process include sputtering processes such as physical vapor deposition (PVD), chemical vapor deposition (CVD), and plasma-enhanced chemical vapor deposition (PECVD), direct printing processes such as screen printing, gravure printing, gravure offset printing, and inkjet printing, coating processes, and wet or dry plating processes. In particular, photoetching is preferably used to achieve the desired pattern shape.

[0102] The photoetching method is a method for forming a pattern through a series of steps known in the art, in which a photoresist is applied to a layer to be patterned, the applied photoresist is selectively hardened using a mask, the unhardened photoresist is developed and removed, and then etching is performed to form a pattern, followed by removing the hardened photoresist. Photoresists can be classified into positive-type and negative-type photoresists. Positive-type photoresists are photoresists that become soluble in a developer upon exposure to UV, while negative-type photoresists are photoresists that become insoluble in a developer upon exposure to UV. Therefore, when a positive-type photoresist is used, the UV-exposed portion can be developed and a pattern can be formed through a subsequent process, while negative-type photoresists are developed and a pattern can be formed through a subsequent process, in which case the non-UV-exposed portion can be developed and a pattern can be formed through a subsequent process. The conditions for hardening the photoresist are not particularly limited, and may be, for example, 0.01 to 10 J / cm. 2 The UV can be irradiated for 1 to 500 seconds, preferably at 0.05 to 1 J / cm 2 UV can be irradiated for 1 to 120 seconds.

[0103] <Display device and semiconductor device including the substrate for electronic components> In addition to the substrate for electronic components, the present invention includes a display device and / or a semiconductor device manufactured through post-processing including known processes for manufacturing a display device and / or a semiconductor device.

[0104] The display devices and semiconductor devices are not particularly limited as long as they are manufactured by a method known in the art. Display devices manufactured using the electronic component substrate include, for example, liquid crystal displays (LCDs), plasma display panels (PDPs), field emission displays (FEDs), electroluminescent displays (ELDs), and organic light emitting diodes (OLEDs), including not only conventional liquid crystal displays but also various other image display devices such as electroluminescent displays, plasma displays, and field emission displays. Semiconductor packages, semiconductor devices, and display devices manufactured using the electronic component substrate have excellent integration density and electrical properties, and can be applied to various devices commonly used in the art, demonstrating excellent performance. [Example]

[0105] Examples of the present invention will be described below in detail. However, the present invention is not limited to the examples disclosed below and can be realized in various different forms. Furthermore, these examples are provided solely to ensure complete disclosure of the present invention and to fully convey the scope of the invention to those skilled in the art to which the present invention pertains, and the present invention is defined solely by the scope of the claims. In the examples, "%" and "parts" refer to % by mass and parts by mass, respectively, unless otherwise specified.

[0106] <Manufacturing of substrates for electronic components> Example 1: Angle 5-10°, hourglass shape, 3D effect (specific surface area increase type) (1) Preparation process - Manufacturing process of the substrate with core vias A glass substrate (BDA-E, 0.5 mm thick, Nippon Electric Glass Co., Ltd.) with a flat surface was prepared and cleaned in an ultrasonic bath for 8 minutes at 70°C with 2.5 vol% PK-LCG225X-1 detergent. Subsequently, it was rinsed with deionized water to remove organic residues, and defects were formed on the glass surface at predetermined locations for core via formation. Specifically, core vias were fabricated on the glass substrate as follows: a 30 W laser with a wavelength of 904-1065 nm in the IR region was selectively irradiated onto the etching location of the glass substrate for the core via. The glass substrate was then etched using a hydrofluoric acid etchant using a deep-etching method, washed with ultrapure water, and dried to produce a glass substrate with a through-type core via.

[0107] The number of core vias is 1 cm 2 The outer diameter of the core vias was a maximum of 87.3 μm, and the smallest internal diameter of the via hole was 45 μm. The substrates with the core vias thus formed were scribed on the glass using a CNC laser device or a diamond glass cutter, and then broken to reveal a vertical cross section. The results were observed using an Olympus microscope, model STM7-MFA, and are shown in Figures 10, 11, and 14. The hourglass angle inside the core vias was confirmed to be 5 to 10 degrees, confirming an inner wall with an increased specific surface area.

[0108] (2) Formation of adhesion-promoting layer (step (a): wet coating) Next, the glass substrate with the through-core vias formed thereon was subjected to a corona treatment using a corona treatment device (CTW series, WEDGE CO., LTD) for surface modification. Specifically, the treatment was carried out once under the conditions of an output (treatment intensity) of 0.3 kW and a treatment speed of 3 m / min.

[0109] Next, an adhesion promotion layer material containing Pd filler particles and polyimide resin was spin-coated (1H-DX2, MIKASA) onto the glass substrate at 2000 RPM for 20 seconds to a final thickness of 1.5 μm, and then cured on a hot plate at 120°C for 30 minutes. The thickness of the formed adhesion promotion layer was measured using a FE-SEM (HITACHI, SU-8010), and the average thickness of the adhesion promotion layer formed on the top and bottom surfaces of the glass substrate was measured to be 5,300 Å.

[0110] (3) Metal plating process (step (b): electroplating) A copper ink mixture was prepared by adding 40 wt% copper nanoparticles (average particle size 50 nm) to an acetate-based solvent containing a portion of butyl carbitol acetate and dispersing them. The copper ink mixture was then spin-coated onto the glass substrate with the vias formed thereon at 2000 RPM for 20 seconds using a spin coater (1H-DX2, MIKASA) and then baked in an oven at 80°C for 5 minutes. The dried copper ink pattern was then irradiated with light using a Xenon lamp (PulseForge 1300, NovaCentrix) to sinter it. The light source was driven at a voltage of 650 V and an intensity of approximately 8.91 J / cm. 2 The irradiation pulse time was set to 1000 μsec.

[0111] The substrate was washed at room temperature for 10 seconds with a cleaning agent made by mixing EVP 221C (Dupont, 5 vol%) and 47% H2SO4 (14.0 vol%). Thereafter, it was washed with DI water for about 2 minutes at room temperature, and then acid washed with 47% H2SO4 (28.0 vol%) for 10 seconds. Subsequently, electroplating was performed to form a copper plating film on the surface of the glass substrate and inside the core via. Specifically, the plating solution was CuSO 4.5 The solution contained H2O (75 g / L), H2SO4 (190 g / L), Cl- (50 mg / L), and ST-901C (0.5 vol%), and was heated at room temperature for 35 minutes at 2 ASD (Amps / dm 2 ) and plating was carried out.

[0112] After plating, the sample was washed with DI water for approximately 2 minutes at room temperature, and then treated with OXIBAN60 (0.5 vol%) for 30 seconds to prevent rust. After that, it was washed again with DI water for approximately 1 minute at room temperature, dried, and then annealed in a convection oven at 120°C for 30 minutes.

[0113] Example 2: Angle 12-18°, hourglass shape, 3D effect (specific surface area increase type) The number of core vias is 1 cm 2 The maximum outer diameter of the core via was 80 μm, and the smallest diameter inside the via hole was 56 μm. Using the method described above, it was confirmed that the angle of the hourglass shape inside the core via was 12 to 18°, and the inner wall with an increased specific surface area was confirmed.

[0114] Example 3: Angle 10-15°, asymmetric hourglass shape, 3D effect (increased specific surface area) The number of core vias is 1 cm 2 The core vias were formed so that 4,000 per via hole were formed, and the diameter of the upper surface was 190 μm, the diameter of the lower surface was 49 μm, and the diameter of the smallest part inside the via hole was 35 μm. The substrate with the core vias thus formed was cut in the same manner as above to reveal the vertical cross section, which was then observed in the same manner as above, as shown in Figures 12A and 12B. It was confirmed that the hourglass shape inside the core via was asymmetric with an angle of 10 to 15 degrees, and an inner wall with an increased specific surface area was confirmed.

[0115] Example 4: Angle 25°, no specific surface area adjustment The number of core vias is 1 cm 2 The outer diameter of the core via was a maximum of 80 μm, and the smallest diameter inside the via hole was 56 μm.

[0116] The substrate with the core via thus fabricated was subjected to the above-described method to obtain a vertical cross section, which was then observed as shown in Figure 13. It was confirmed that the hourglass shape inside the core via was symmetrical with an angle of 25°, and that the inner wall did not increase in specific surface area.

[0117] Comparative Example 1 A substrate for electronic components of Comparative Example 1 was manufactured using the same method as the manufacturing method for the substrate for electronic components of Example 1, except that step (a) of forming the adhesion promoting layer was omitted.

[0118] Comparative Example 2 The substrate for electronic components of Comparative Example 2 was manufactured using the same method as the manufacturing method of the substrate for electronic components of Example 1, except that step (a), which is the adhesion promotion layer forming process, was omitted and the following sputtering method (step (b')) was applied instead of step (b).

[0119] Step (b'): Plating process - sputtering method After cleaning the glass substrate with the adhesion-promoting layer using a standard cleaning process, Ti was applied twice to the front and back surfaces of the glass substrate using a DC magnetron sputter to form a layer. Subsequently, a 500 Å thick film was formed by applying an Ar partial pressure of 10 sccm, a sputtering pressure of 3 mTorr, and a DC power of 100 W. The film thickness was confirmed using an SEM. After the Ti layer was completed, Cu was applied in the same manner as above to form a layer with a thickness of 10,000 Å.

[0120] The substrate was washed at room temperature for 10 seconds with a cleaning agent consisting of EVP 221C (Dupont, 5 vol%) and 47% H2SO4 (14.0 vol%). Thereafter, it was washed with DI water at room temperature for about 2 minutes, and then acid washed with 47% H2SO4 (28.0 vol%) for 10 seconds.

[0121] Next, electroplating was performed to form a copper plating film on the surface of the glass substrate and inside the core via hole. Specifically, the plating solution was CuSO 4.5The solution contained H2O (75 g / L), H2SO4 (190 g / L), Cl- (50 mg / L), and ST-901C (0.5 vol%), and was heated at room temperature for 35 minutes at 2 ASD (Amps / dm 2 ) and plating was carried out.

[0122] After plating, the sample was washed with DI water for approximately 2 minutes at room temperature, and then treated with OXIBAN60 (0.5 vol%) for 30 seconds to prevent rust. After that, it was washed again with DI water for approximately 1 minute at room temperature, dried, and then annealed in a convection oven at 120°C for 30 minutes.

[0123] Comparative Example 3: Angle 0 - Cylindrical The number of core vias is 1 cm 2 The outer diameter of the upper and lower surfaces of the core via and the inner diameter of the via hole were 56 μm.

[0124] Experimental Example (1) Plating adhesion evaluation The surfaces of the substrates for electronic components manufactured according to the examples and comparative examples were subjected to an adhesion test in accordance with the international standard ASTM D3359 for cross-cut testing. Specifically, the degree of peeling after a tape adhesion test was observed for 100 1mm x 1mm grids formed on the surface of the substrate for electronic components, and the degree of adhesion was evaluated using a scale of 0B to 5B. The results are shown in Table 1 below.

[0125] <Evaluation criteria> 5B: No peeling occurred in the entire area of ​​the test piece.

[0126] 4B: Peeling occurred in less than 5% of the entire area of ​​the test piece. 3B: Peeling occurred in an area of ​​5% or more but less than 15% of the entire area of ​​the test piece.

[0127] 2B: Peeling occurred in an area of ​​15% or more but less than 35% of the entire area of ​​the test piece. 1B: Peeling occurred in 35% or more but less than 65% of the entire area of ​​the test piece.

[0128] 0B: The state where peeling occurs in 65% or more of the entire area of the test piece. Also, the above results were judged according to the following criteria and described in Table 1 below.

[0129] <Judgment Criteria> OK: Plating adhesion 4B or more NG: Plating adhesion less than 4B (2) Average thickness of the plating layer The average thickness of the plating layer confirmed by SEM was measured and described in Table 1 below.

[0130]

Table 1

[0131] (3) Reliability evaluation The reliability of each of the examples and comparative examples was evaluated by the following KS test method and shown in Table 2.

[0132] When electrode lifting and / or electrode corrosion are confirmed, it is marked as NG, and otherwise as OK.

[0133] <KS Test Method> High temperature and high humidity 500HR 60 / 93: IEC60068-2-3 (high temperature and high humidity test), KS C 0222 (high temperature and high humidity test) Low temperature test 240HR: IEC60068-2-1 (low temperature test), KS C 0220 (low temperature test) High temperature test 240HR: IEC60068-2-2 (high temperature test), KS C 0221 (high temperature test) Temperature and humidity cycle test -20~60℃ 72HR: IEC60068-2-30 (temperature and humidity cycle test), Ks C 0227 (temperature and humidity cycle test) Salt spray: IEC600682.11 (salt spray test), KS C 0223 (salt spray test)

[0134]

Table 2

[0135] According to the experimental data in Table 1, the electronic component substrates manufactured according to the examples of the present invention exhibited excellent plating adhesion. In contrast, Comparative Example 1, in which copper ink was plated using a conventional sputtering method rather than a wet coating method, and Comparative Example 2, in which an adhesion-promoting layer was not applied, did not meet the criteria for plating adhesion, and peeling was observed over a wide area. Furthermore, according to the experimental data in Table 2, the electronic component substrates manufactured according to Examples 1 to 4 of the present invention, which include through-type core vias in which the diameter of one or more of the upper and lower surfaces is larger than the diameter of a single point inside the hole, did not exhibit electrode lift-up under harsh conditions of high and low temperatures. In particular, the electronic component substrates of Examples 1 to 3, in which the inner surface of the core via was hourglass-shaped and the specific surface area of ​​the inner wall was increased, did not exhibit electrode lift-up under all harsh conditions, including high temperature / high humidity, high temperature, low temperature, and saltwater treatment, demonstrating superior performance. In contrast, the electronic component substrate of Comparative Example 3, which included a cylindrical core via, exhibited poor electrode lift-up under all conditions. [Industrial Applicability]

[0136] According to the substrate for electronic components and the manufacturing method thereof of the present invention, in manufacturing a substrate having through-type core vias, the adhesion promoting layer formed by a wet coating method is included, thereby improving the adhesion of the metal plating layer and preventing defects, thereby providing a high-quality substrate for electronic components. [Explanation of symbols]

[0137] 10: Circuit board 20: Adhesion promoting layer 30: Metal electrode layer

Claims

1. a substrate including one or more through-core vias; an adhesion promoting layer on a surface of the substrate and a surface of the through-core via; The through-core via has a hole diameter at least at its upper surface and lower surface that is larger than the hole diameter at a point inside the hole. Substrate for electronic components.

2. 2. The substrate for electronic components according to claim 1, wherein the through-type core via has an angle of 1° to 25° between a line connecting a point on the top or bottom surface of the core via in a vertical cross section to a point inside the via with the smallest hole diameter, and a line connecting the point on the top or bottom surface of the core via in a vertical direction.

3. 2. The substrate for electronic components according to claim 1, wherein the through-type core via has a vertical cross section that is symmetrical or asymmetrical.

4. 2. The substrate for electronic components according to claim 1, wherein the inner wall surface of the through-type core via has an uneven shape.

5. 2. The substrate for electronic components according to claim 1, wherein the substrate is made of glass or quartz.

6. 2. The substrate for electronic components according to claim 1, wherein the adhesion promoting layer comprises at least one selected from the group consisting of a UV-curable resin having an acrylic group and a polyimide-based thermosetting resin, or is a film coated with a metal, an oxide, or a ceramic oxide.

7. 2. The substrate for electronic components according to claim 1, wherein the adhesion promoting layer has a thickness of 250 to 6000 Å.

8. 2. The substrate for electronic components according to claim 1, wherein the average hole diameter of at least one of the upper and lower surfaces of each of the through-type core vias of the substrate is 5 to 190 μm.

9. (a) forming an adhesion promotion layer on a surface of a substrate containing one or more through-core vias; (b) plating a metal on the surface of the substrate on which the adhesion promotion layer is formed; The through-type core via has a hole diameter at least at the top surface and the bottom surface that is larger than the hole diameter at a point inside the hole, The method for producing a substrate for electronic components, wherein the plating step (b) is carried out by one or more methods selected from electrolytic plating and electroless plating.

10. The method for manufacturing a substrate for electronic components according to claim 9 , wherein the step (a) further includes a surface modification step.

11. The method for producing a substrate for electronic components according to claim 10, wherein the surface modification is carried out by one or more methods selected from the group consisting of saponification treatment, plasma treatment, corona treatment, and primer treatment.

12. 10. The method for manufacturing a substrate for electronic components according to claim 9, further comprising, before step (a), a step of manufacturing a through-type core via in which the hole diameter of one or more of the upper and lower surfaces is larger than the hole diameter at a point inside the hole by adjusting the etching rate of the upper and lower surfaces of the substrate.

13. The method for producing a substrate for electronic components according to claim 9 , wherein the step (b) is further carried out one or more times.

14. A display device comprising the substrate for electronic components according to any one of claims 1 to 8.

15. A semiconductor device comprising the substrate for electronic components according to any one of claims 1 to 8.

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