Adjacent buried power rails for stacked field effect transistor architectures

Abstract

One or more systems, devices, and / or methods of manufacture provided herein relate to adjacent buried power rails for stacked field effect transistor architectures. A semiconductor device may include a first transistor stacked on a second transistor, where the first transistor is laterally offset from the second transistor, and a first buried power rail and a second buried power rail, where the first buried power rail is coupled to the first transistor and the second buried power rail is coupled to the second transistor.

Description

[Technical Field]

[0001] The present disclosure relates to stacked field-effect transistors (FETs), and more particularly to stacked FETs with buried power rail connections. Summary of the Invention

[0002] The following presents a summary to provide a basic understanding of one or more embodiments of the invention. This summary is not intended to identify key or critical elements or to delineate the scope of particular embodiments or the scope of the claims. Its sole purpose is to present concepts in a simplified form as a prelude to the more detailed description that is presented later.

[0003] According to one embodiment, a semiconductor device may include a first transistor stacked on a second transistor, where the first transistor is laterally offset from the second transistor, and a power rail layer having a first buried power rail and a second buried power rail, where the first buried power rail is coupled to the first transistor and the second buried power rail is coupled to the second transistor. An advantage of such a device is that by laterally offsetting the first transistor and the second transistor, both the first transistor and the second transistor may be coupled to a power supply system on the underside of the semiconductor device.

[0004] In some embodiments of the devices described above, the first buried power rail and the second buried power rail may be unevenly spaced within the cell. An advantage of such devices is that unevenly spaced power rails may increase decoupling capacitance, resulting in better performance of the semiconductor device.

[0005] According to another embodiment, a method for manufacturing a semiconductor device by a manufacturing system may include forming, by the manufacturing system, a transistor region on a substrate; forming, by the manufacturing system, an interconnect layer on top of the transistor region; forming, by the manufacturing system, a carrier wafer above the interconnect layer; flipping, by the manufacturing system, the semiconductor device onto the carrier wafer; removing, by the manufacturing system, the substrate; and forming, by the manufacturing system, two or more buried power rails in a cell.

[0006] In some embodiments of the methods described above, the transistor region may comprise a first transistor stacked on a second transistor, the first transistor being laterally offset from the second transistor. An advantage of such a method is that by laterally offsetting the first and second transistors, both the first and second transistors may be coupled to a power supply system on the underside of the semiconductor device.

[0007] According to another embodiment, a method for manufacturing a semiconductor device by a manufacturing system may include stacking, by the manufacturing system, a first transistor of the semiconductor device over a second transistor of the semiconductor device, where the first transistor is laterally offset from the second transistor; forming, by the manufacturing system, a power rail layer having a first buried power rail and a second buried power rail; and coupling, by the manufacturing system, the first buried power rail to the first transistor and the second buried power rail to the second transistor. An advantage of such a device is that by laterally offsetting the first transistor and the second transistor, both the first transistor and the second transistor can be coupled to a power supply system on the underside of the semiconductor device. [Brief explanation of the drawings]

[0008] [Figure 1] (a) is a top view of a conventional stacked FET architecture device, and (b) is a cross-sectional view of the conventional stacked FET architecture device. [Figure 2] 1A is a top view of an exemplary, non-limiting stacked FET architecture device with buried power rails according to one or more embodiments described herein; 1B is a cross-sectional view of an exemplary, non-limiting stacked FET architecture device with buried power rails according to one or more embodiments described herein; and 1C is a cross-sectional view of an exemplary, non-limiting stacked FET architecture device with buried power rails according to one or more embodiments described herein. [Figure 3] 1A is a top view of an exemplary, non-limiting stacked FET architecture device with buried power rails according to one or more embodiments described herein; 1B is a cross-sectional view of an exemplary, non-limiting stacked FET architecture device with buried power rails according to one or more embodiments described herein; and 1C is a cross-sectional view of an exemplary, non-limiting stacked FET architecture device with buried power rails according to one or more embodiments described herein. [Figure 4] 1A is a top view of a cell of an existing stacked FET architecture device, FIG. 1B is a top view of an exemplary, non-limiting stacked FET architecture device cell with buried power rails, and FIG. 1C is a top view of an exemplary, non-limiting stacked FET architecture device cell with unevenly spaced buried power rails, according to one or more embodiments described herein. [Figure 5] FIG. 1 is a side view of an exemplary, non-limiting stacked FET architecture device with embedded power rails, according to one or more embodiments described herein. [Figure 6]FIG. 1 is an exemplary, non-limiting flow diagram of a method of fabricating a stacked FET semiconductor device with embedded power rails according to one or more embodiments described herein. [Figure 7] 1A-1C are diagrams of exemplary, non-limiting stages in the production of a stacked FET device with embedded power rails, according to one or more embodiments described herein. [Figure 8] FIG. 1 is an exemplary, non-limiting flow diagram of a method of fabricating a stacked FET semiconductor device with embedded power rails according to one or more embodiments described herein. [Figure 9] 1 is a top view of a first stage of production of a semiconductor device according to one or more embodiments described herein. [Figure 10] (a) is a cross-sectional view of a first stage of production of a semiconductor device according to one or more embodiments described herein, (b) is a cross-sectional view of a first stage of production of a semiconductor device according to one or more embodiments described herein, and (c) is a cross-sectional view of a first stage of production of a semiconductor device according to one or more embodiments described herein. [Figure 11] (a) is a cross-sectional view of a second stage of production of a semiconductor device according to one or more embodiments described herein, (b) is a cross-sectional view of a second stage of production of a semiconductor device according to one or more embodiments described herein, and (c) is a cross-sectional view of a second stage of production of a semiconductor device according to one or more embodiments described herein. [Figure 12] (a) is a cross-sectional view of a third stage of production of a semiconductor device according to one or more embodiments described herein, (b) is a cross-sectional view of a third stage of production of a semiconductor device according to one or more embodiments described herein, and (c) is a cross-sectional view of a third stage of production of a semiconductor device according to one or more embodiments described herein. [Figure 13]1A, 1B, and 1C are cross-sectional views of a fourth stage of production of a semiconductor device according to one or more embodiments described herein, respectively; (a) a cross-sectional view of a fourth stage of production of a semiconductor device according to one or more embodiments described herein, respectively; (b) a cross-sectional view of a fourth stage of production of a semiconductor device according to one or more embodiments described herein, respectively; and (c) a cross-sectional view of a fourth stage of production of a semiconductor device according to one or more embodiments described herein. [Figure 14] 1A, 1B, and 1C are cross-sectional views of a fifth stage of production of a semiconductor device according to one or more embodiments described herein, respectively; (a) a cross-sectional view of a fifth stage of production of a semiconductor device according to one or more embodiments described herein, respectively; and (b) a cross-sectional view of a fifth stage of production of a semiconductor device according to one or more embodiments described herein, respectively. [Figure 15] 1A, 1B, and 1C are cross-sectional views of a sixth stage of production of a semiconductor device according to one or more embodiments described herein, respectively; (a) a cross-sectional view of a sixth stage of production of a semiconductor device according to one or more embodiments described herein, respectively; and (c) a cross-sectional view of a sixth stage of production of a semiconductor device according to one or more embodiments described herein. [Figure 16A] FIG. 10 is a cross-sectional view of a seventh stage of production of a semiconductor device according to one or more embodiments described herein. [Figure 16B] FIG. 10 is a cross-sectional view of a seventh stage of production of a semiconductor device according to one or more embodiments described herein. [Figure 16C] FIG. 10 is a cross-sectional view of a seventh stage of production of a semiconductor device according to one or more embodiments described herein. [Figure 17A] FIG. 10 is a cross-sectional view of an eighth stage of production of a semiconductor device according to one or more embodiments described herein. [Figure 17B] FIG. 10 is a cross-sectional view of an eighth stage of production of a semiconductor device according to one or more embodiments described herein. [Figure 17C]FIG. 10 is a cross-sectional view of an eighth stage of production of a semiconductor device according to one or more embodiments described herein. [Figure 18A] FIG. 10 is a cross-sectional view of a ninth stage of production of a semiconductor device according to one or more embodiments described herein. [Figure 18B] FIG. 10 is a cross-sectional view of a ninth stage of production of a semiconductor device according to one or more embodiments described herein. [Figure 18C] FIG. 10 is a cross-sectional view of a ninth stage of production of a semiconductor device according to one or more embodiments described herein. [Figure 19A] FIG. 10 is a cross-sectional view of a tenth stage of production of a semiconductor device according to one or more embodiments described herein. [Figure 19B] FIG. 10 is a cross-sectional view of a tenth stage of production of a semiconductor device according to one or more embodiments described herein. [Figure 19C] FIG. 10 is a cross-sectional view of a tenth stage of production of a semiconductor device according to one or more embodiments described herein. [Figure 20A] FIG. 10 is a cross-sectional view of an eleventh stage of production of a semiconductor device according to one or more embodiments described herein. [Figure 20B] FIG. 10 is a cross-sectional view of an eleventh stage of production of a semiconductor device according to one or more embodiments described herein. [Figure 20C] FIG. 10 is a cross-sectional view of an eleventh stage of production of a semiconductor device according to one or more embodiments described herein. [Figure 21A] FIG. 13 is a cross-sectional view of a twelfth stage of production of a semiconductor device according to one or more embodiments described herein. [Figure 21B] FIG. 13 is a cross-sectional view of a twelfth stage of production of a semiconductor device according to one or more embodiments described herein. [Figure 21C] FIG. 13 is a cross-sectional view of a twelfth stage of production of a semiconductor device according to one or more embodiments described herein. DETAILED DESCRIPTION OF THE INVENTION

[0009] The following detailed description is merely exemplary and is not intended to limit the embodiments and / or the application or uses of the embodiments, nor is it intended to be bound by any express or implied information presented in the preceding "Background" or "Summary" sections or in the "Detailed Description" section.

[0010] Buried power rails offer an opportunity to increase decoupling capacitance in semiconductor devices, thus reducing power supply noise. These decoupling capacitances can be further increased by reducing the spacing between power rails. However, existing stacked FET architectures require buried power rails to be located at cell boundaries, which in turn results in low decoupling capacitance due to the separation between the buried power rails. In existing stacked FET architectures, n-channel field-effect transistors (NFETs) are stacked above p-channel field-effect transistors (PFETs). Because the PFETs are stacked directly below the NFETs, it is not possible to connect the NFETs to the buried power rails, thus limiting the ability to group buried power rails together to increase decoupling capacitance.

[0011] In consideration of the aforementioned problems with current stacked FET devices, the described subject matter illustrates a semiconductor device and method of fabricating a semiconductor device capable of providing increased decoupling capacitance. For example, as described in more detail below, a semiconductor device may include a first transistor stacked on a second transistor, where the first transistor is laterally offset from the second transistor; and a buried power rail layer having a first buried power rail and a second buried power rail, where the first buried power rail is coupled to the first transistor and the second buried power rail is coupled to the second transistor. Because the first transistor and the second transistor are laterally offset from each other, the second transistor does not interfere with the buried power rail connection of the first transistor, as is the case in existing stacked FET devices. Thus, both the first transistor and the second transistor may be coupled to the buried power rail, which in turn may increase decoupling capacitance.

[0012] FIG. 1(a) illustrates a top view of an existing stacked FET architecture device 100. As shown, device 100 includes an NFET 101, a PFET 101 stacked above NFET 102, a VCC (voltage common collector) 103, a VSS (voltage source supply) 104, a gate 105, and a VOUT (voltage out) 106. FIG. 1(b) illustrates a cross-sectional view of device 100 along line 110. As shown by FIG. 1(b), in the existing stacked FET architecture, NFET 102 prevents PFET 101 from being connectable to a buried power rail located below device 100.

[0013] FIG. 2(a) illustrates a top view of an exemplary, non-limiting stacked FET architecture device 200 with buried power rails. As shown, device 200 may include an NFET 201, a PFET 202 stacked above NFET 201, VCC 203, VSS 204, a gate 205, and VOUT 206. FIG. 2(b) illustrates a cross-sectional view of device 200 along line 210. As shown, PFET 202 is stacked above NFET 201; however, PFET 202 and NFET 201 are laterally offset from each other so that NFET 201 does not block the bottom of PFET 202. Additionally, as shown, PFET 202 is coupled to a first buried power rail 212, and NFET 201 is coupled to a second buried power rail 214. Additionally, as shown, PFET 202 and NFET 201 may receive power from buried power rails 212 and 214, respectively. Figure 2(c) illustrates a cross-sectional view of device 200 along line 220. As shown, both PFET 202 and NFET 201 may be coupled to VOUT 206.

[0014] FIG. 3(a) illustrates a top view of stacked FET architecture device 200 with cut lines 310 and 320. FIG. 3(b) illustrates a cross-sectional view of device 200 along line 310. As shown, PFET 202 is coupled to a first buried power rail 212 and gate 205. FIG. 3(c) illustrates a cross-sectional view of device 200 along line 320. As shown, NFET 201 is coupled to a second buried power rail 214 and gate 205. As illustrated by FIGS. 3(a), 3(b), and 3(c), in one or more embodiments, gate 205 may be oriented perpendicular to PFET 202 and NFET 201. Further, in one or more embodiments, gate 205 may comprise a p-type metal region 302 coupled to PFET 202 and an n-type metal region 301 coupled to NFET 201.

[0015] FIG. 4( a) is a top view of a cell 400 of an existing stacked FET architecture device. As shown, device 400 includes VCC 403, VSS 404, gate 405, VOUT 406, first power source 401, and second power source 402. As described above with reference to FIG. 1, in existing stacked FET devices, the NFET blocks access to the bottom of the PFET. Thus, as shown by device 400, power sources 401 and 402 are located at the edge of cell boundary 420, and local interconnects 412 and 414 provide power from first power source 401 and second power source 402 to VCC 403 and VSS 404, respectively. This distance between power sources 401 and 402 limits the decoupling capacitance of device 400.

[0016] FIG. 4(b) illustrates a top view of a cell of a non-limiting stacked FET architecture device 430 with buried power rails. As shown, the device 430 includes VCC 423, VSS 424, GATE 425, VOUT 426, a first buried power rail 421, and a second buried power rail 422. By laterally offsetting the PFET and NFET, as described above with reference to FIG. 2, the NFET does not block access to the bottom of the PFET, allowing the first buried power rail 421 to power the PFET. Thus, the first and second buried power rails can be positioned closer to each other within the cell boundary 420, thereby increasing decoupling capacitance. FIG. 4(c) illustrates a top view of a cell of a non-limiting stacked FET architecture device 440 with unevenly spaced buried power rails. As shown, first buried power rail 441 and second buried power rail 442 are unevenly spaced within cell boundary 420 (eg, not centered within cell boundary 420).

[0017] FIG. 5 illustrates a side view of an exemplary, non-limiting stacked FET architecture device 500 with buried power rails. As shown, device 500 may include a back end of line (BEOL) region 501 (e.g., an interconnect layer) coupled to a device region 502. In one embodiment, BEOL region 501 may enable coupling of device region 502 to one or more additional devices. In one embodiment, device region 502 may include one or more cells, where one or more cells include a first transistor stacked on a second transistor, where the first and second transistors are laterally offset. One or more cells may further include two or more buried power rails 504, where a first of the two or more buried power rails 504 may be coupled to the first transistor and a second of the two or more buried power rails 504 may be coupled to the second transistor. As shown by FIG. 5, the first buried power rail and the second buried power rail may be unevenly spaced within the cell (e.g., not centered within width 503) and may be located close to each other (e.g., at a distance less than the height of the cell) to increase decoupling capacitance.

[0018] FIG. 6 illustrates an exemplary, non-limiting flow diagram 600 of a method of fabricating a stacked FET device with embedded power rails according to one or more embodiments described herein.

[0019] At 602, method 600 may include forming, by a manufacturing system, a transistor region on a substrate. In one embodiment, the transistor region may include a first transistor stacked above a second transistor, the first transistor being laterally offset from the second transistor. In a further embodiment, the first transistor and the second transistor may comprise at least one of a PFET or an NFET. For example, the first transistor may comprise a PFET and the second transistor may comprise an NFET. In another example, the first transistor may comprise an NFET and the second transistor may comprise a PFET. In one embodiment, the transistor region may be formed by a nanosheet production method.

[0020] At 604, the method 600 may include forming, by a fabrication system, an interconnect hierarchy on top of the transistor region. In one embodiment, a back-end-of-line process may be utilized to form the interconnect hierarchy. Further, in one embodiment, the interconnect hierarchy may provide operative coupling between the transistor region and one or more additional devices.

[0021] At 606, the method 600 may include forming, by a manufacturing system, a carrier wafer above the interconnect hierarchy. For example, the wafer may be formed above the interconnect hierarchy by a wafer bonding or deposition process.

[0022] At 608, the method 600 may include flipping the semiconductor device onto the carrier wafer by the manufacturing system. Further, a portion of the substrate may be removed by an etching process to form a thin substrate.

[0023] At 610, method 600 may include forming, by a manufacturing system, two or more buried power rails in the cell. In one embodiment, channels may be etched into the substrate for the two or more buried rails, and a metallization process may be utilized to form the two or more buried power rails in the channels. In one embodiment, the channels may be positioned to allow a first of the two or more buried power rails to be coupled to a first transistor, and a second of the two or more buried power rails to be coupled to a second transistor. In a further embodiment, the buried power rails may be coupled to vias, and the vias may be coupled to the transistors.

[0024] At 612, method 600 may include coupling, by a manufacturing system, two or more buried power rails to a backside power supply network. For example, by coupling the two or more buried power rails to the backside power supply network, the two or more buried power rails may provide power from the underside of the semiconductor device to a transistor region.

[0025] FIG. 7 illustrates exemplary, non-limiting stages in the production of a stacked FET device with embedded power rails. In stage 710, a transistor region 702 may be formed on a substrate 703. In one embodiment, the transistor region 702 may comprise a first transistor stacked on a second transistor, with the first and second transistors laterally offset. For example, the transistor region 702 may comprise one or more cells comprising the stacked FET architecture illustrated in more detail above with reference to FIGS. 2(a), 2(b), 2(c), 3(a), 3(b), and 3(c). In stage 720, a back-end-of-life (BEOL) region 704 may be formed above the transistor region 702. In one embodiment, the back-end-of-life (BEOL) region 704 may enable operative coupling between the transistor region 702 and one or more additional devices. In stage 730, the substrate 703 may be thinned to produce a substrate 705. For example, the device may be flipped upside down and substrate 703 may be thinned to produce substrate 705. In stage 740, two or more buried power rails may be formed. For example, one or more channels may be etched through substrate 705. A metallization process may then be utilized to produce two or more buried power rails. In one embodiment, the two or more buried power rails may be adjacent to one another, as described in more detail above with reference to FIGS. 2(a)-4(b).

[0026] FIG. 8 illustrates an exemplary, non-limiting flow diagram 800 of a method of fabricating a stacked FET semiconductor device with embedded power rails according to one or more embodiments described herein.

[0027] At 802, the method 800 may include stacking, by a manufacturing system, a first transistor over a second transistor, the first transistor being laterally offset from the second transistor. For example, the first transistor and the second transistor may be laterally offset as described in more detail above with reference to FIGS. 2(a)-3(c). In further embodiments, the first transistor and the second transistor may comprise at least one of an NFET or a PFET. For example, the first transistor may comprise a PFET and the second transistor may comprise an NFET. In a further example, the first transistor may comprise an NFET and the second transistor may comprise a PFET.

[0028] At 804, method 800 may include forming, by a manufacturing system, a power rail layer comprising a first buried power rail and a second buried power rail. In one embodiment, the first buried power rail and the second buried power rail may be formed by etching two or more channels into a substrate and filling the two or more channels with a metallization process. In a further embodiment, the first buried power rail and the second buried power rail may be unevenly spaced within the cell, as described in more detail above with reference to FIG. 4(c).

[0029] At 806, method 800 may include coupling, by a manufacturing system, the first buried power rail to the first transistor and the second buried power rail to the second transistor. In one embodiment, the channels used to form the first buried power rail and the second buried power rail may be arranged such that the first buried power rail directly couples to the first transistor and the second buried power rail directly couples to the second transistor. In a further embodiment, the buried power rails may be coupled to vias, which are coupled to the transistors.

[0030] At 808, the method 800 may include coupling, by a manufacturing system, a first end of the gate structure to a first transistor. For example, if the first transistor comprises a PFET, then the first end of the gate structure may comprise a P-WFM (positive work function metal). In another example, if the first transistor comprises an NFET, then the first end of the gate structure may comprise an N-WFM (negative work function metal).

[0031] At 810, the method 800 may include coupling, by a manufacturing system, a second end of the gate structure to a second transistor. For example, if the second transistor comprises a PFET, then the second end of the gate structure may comprise a P-WFM. In another example, if the second transistor comprises an NFET, then the second end of the gate structure may comprise an N-WFM.

[0032] 9 illustrates a top view of a first stage of production of a semiconductor device 900 according to one or more embodiments described herein. As shown, device 900 may include one or more substrate sections 904. As described in more detail below, substrate section 904 may include a first transistor and a dummy gate. Lines 901, 902, and 903 illustrate various directions of a cross-section that are utilized to describe further production of device 900 as described in more detail below.

[0033] 10(a), 10(b), and 10(c) illustrate cross-sectional views of a first stage of production of a semiconductor device 900 according to one or more embodiments described herein. FIG. 10(a) illustrates a cross-sectional view of device 900 along line 901. As shown, FIG. 10(a) includes an etch stop layer 1001 (e.g., bonding oxide or SiO), an interlayer dielectric 1002, a bottom dielectric insulator (BDI), and one or more source / drain epi 1004. FIG. 10(b) illustrates a cross-sectional view of device 900 along line 902. As shown, FIG. 10(b) includes a first transistor device 1007 and a dummy gate 1005. In one embodiment, the first transistor device 1007 may include a PFET or an NFET. In one embodiment, the first transistor device 1007 may comprise alternating layers of Si and SiGe. Figure 10(c) illustrates a cross-sectional view of device 900 along line 903. As shown, Figure 10(c) includes an alternative view of the dummy gate 1005, the first transistor device 1007, and the source / drain epi 1004.

[0034] 11(a), 11(b), and 11(c) illustrate cross-sectional views of a second stage of production of device 900 according to one or more embodiments described herein. FIG. 11(b) illustrates a cross-sectional view of device 900 along line 902. FIG. 11(b) includes one or more bottom gate notches 1101 that allow for production of a gate for first transistor device 1007.

[0035] 12(a), 12(b), and 12(c) illustrate cross-sectional views of a third stage of production of device 900 according to one or more embodiments described herein. At this stage of production, a second wafer comprising a second transistor device 1207 may be wafer bonded onto the dummy gate 1005. FIG. 12(a) illustrates a cross-sectional view of device 900 along line 901. FIG. 12(a) includes a bonding oxide 1201, a second interlayer dielectric 1202, and a second set of source / drain epi 1204 that may bond the second wafer to the first wafer. FIG. 12(b) illustrates a cross-sectional view of device 900 along line 902. FIG. 12(b) includes a second dummy gate 1205 and a second transistor device 1207. In one embodiment, the second transistor device 1207 may comprise a PFET or an NFET. In one embodiment, the second transistor device 1207 may comprise alternating layers of Si and SiGe. In some embodiments, the first transistor device 1007 and the second transistor device 1207 may comprise the same number of Si layers, while in other embodiments, the first transistor device and the second transistor device may comprise a different number of Si layers. It should be understood that the first transistor device 1007 is laterally offset from the second transistor device 1207 as shown. FIG. 12(c) illustrates a cross-sectional view of device 900 along line 903.

[0036] 13(a), 13(b), and 13(c) illustrate cross-sectional views of a fourth stage of production of device 900 according to one or more embodiments described herein. Figure 13(b) illustrates a cross-sectional view of device 900 along line 902. Figure 13(b) includes one or more gate patterning notches 1301 that allow for the formation of a gate.

[0037] 14(a), 14(b), and 14(c) illustrate cross-sectional views of a fifth stage of production of device 900 according to one or more embodiments described herein. FIG. 14(b) illustrates a cross-sectional view of device 900 along line 902. As shown by FIGS. 14(b) and 14(c), the dummy gate 1005, the second dummy gate 1205, and the layers of SiGe from the first transistor device 1007 and the second transistor device 1207 may be removed, and a high-k metal gate 1401 may be formed.

[0038] 15(a), 15(b), and 15(c) are cross-sectional views of a sixth stage of production of device 900 according to one or more embodiments described herein. Figure 15(b) illustrates a cross-sectional view of device 900 along line 902. Figure 15(b) includes one or more top gate notches 1501 that allow for production of a gate for second transistor device 1207.

[0039] 16A, 16B, and 16C illustrate cross-sectional views of a seventh stage of production of device 900 according to one or more embodiments described herein. FIG. 16A illustrates a cross-sectional view of device 900 along line 901. FIG. 16A includes a first middle-of-line (MOL) connector 1601 connecting to source / drain epi 1004 and a second MOL connector 1603 connecting to gate 1401. FIG. 16A further includes lower BEOL formation 1602. Lower BEOL formation 1602 may include one or more vias and one or more connector lines. FIG. 16B illustrates a cross-sectional view of device 900 along line 902. As FIG. 16B illustrates, second MOL connector 1603 may connect lower BEOL formation 1602 to metal gate 1401. 16C illustrates a cross-sectional view of device 900 along line 903. As FIG. 16C illustrates, a first MOL connector 1601 can connect source / drain epi 1204 to a lower BEOL formation 1602.

[0040] 17A, 17B, and 17C illustrate cross-sectional views of an eighth stage of production of device 900 according to one or more embodiments described herein, including lower BEOL formation portion 1602 and interconnect wiring 1701 connecting to carrier wafer 1702.

[0041] 18A, 18B, and 18C illustrate cross-sectional views of a ninth stage of production of device 900 according to one or more embodiments described herein. As shown by FIGS. 18A, 18B, and 18C, device 900 may be flipped over so that carrier wafer 1702 is on the bottom. An etching process may then expose etch stop layer 1001.

[0042] 19A, 19B, and 19C illustrate cross-sectional views of a tenth stage of production of device 900 according to one or more embodiments described herein. As shown by Figures 19A and 19B, etch stop layer 1001 and any remaining substrate may be removed to expose shallow trench isolation regions 1901.

[0043] 20A, 20B, and 20C illustrate cross-sectional views of an eleventh stage of production of device 900 according to one or more embodiments described herein. FIG. 20A illustrates a cross-sectional view of device 900 across line 901. As shown by FIG. 20A, a first backside connector 2001 may be patterned to connect one or more second transistor devices to source / drain epi 1204, and a second backside connector 2002 may be patterned to connect second transistor device 1207 to first source / drain epi 1004.

[0044] 21A, 21B, and 21C illustrate cross-sectional views of a twelfth stage of production of device 900 according to one or more embodiments described herein. As shown by FIGS. 21A, 21B, and 21C, a buried power rail layer 2101 comprising one or more buried power rails can be patterned to provide power to first transistor device 1007 and second transistor device 1207.

[0045] An advantage of such methods, devices, and / or systems is that they enable semiconductor devices with increased decoupling capacitance, which in turn reduces power supply noise. For example, by laterally offsetting stacked FETs, both FETs can be coupled to a buried power rail, whereas existing devices and methods only coupled a single FET. By allowing multiple FETs to receive power from the buried power rail, the buried power rails can be placed closer together than in existing designs, thus increasing decoupling capacitance when compared to existing designs. A practical application of the devices described above is that they provide improved performance due to increased decoupling capacitance and reduced power supply noise.

Claims

1. a first transistor stacked on a second transistor, wherein the first transistor is laterally offset from the second transistor; and a power rail layer having a first buried power rail and a second buried power rail, wherein the first buried power rail is coupled to the first transistor and the second buried power rail is coupled to the second transistor; A semiconductor device comprising:

2. The semiconductor device of claim 1 , wherein the first transistor is a p-channel field effect transistor (PFET).

3. The semiconductor device of claim 1 , wherein the second transistor is an n-channel field effect transistor (NFET).

4. a gate structure coupling the first transistor to the second transistor; and The semiconductor device of claim 1 , further comprising a shared output, the shared output coupled to the first transistor and the second transistor.

5. 10. The semiconductor device of claim 1, wherein the power rail layer is coupled to a powered backside supply network located on a backside of the semiconductor device.

6. 10. The semiconductor device of claim 1, wherein the first buried power rail and the second buried power rail are unevenly spaced within a cell.

7. 1. A method for manufacturing a semiconductor device by a manufacturing system, the method comprising: forming a transistor region on a substrate with the manufacturing system; forming, with the fabrication system, an interconnect layer on top of the transistor region; forming, by the manufacturing system, a carrier wafer above the interconnect hierarchy; flipping, by the manufacturing system, the semiconductor device onto the carrier wafer; removing the substrate by the manufacturing system; and forming two or more buried power rails in the cell with the manufacturing system; A method comprising:

8. coupling, by the manufacturing system, the two or more buried power rails to a powered backside supply network located on a backside of the semiconductor device. The method of claim 7 further comprising:

9. 8. The method of claim 7, wherein the transistor region comprises a first transistor stacked on a second transistor, the first transistor being laterally offset from the second transistor.

10. coupling, by the manufacturing system, a first buried power rail of the two or more buried power rails to the first transistor; and coupling, by the manufacturing system, a second buried power rail of the two or more buried power rails to the second transistor. The method of claim 9 further comprising:

11. 10. The method of claim 9, wherein the first transistor comprises at least one of a PFET or an NFET.

12. 10. The method of claim 9, wherein the second transistor comprises at least one of an NFET or a PFET.

13. 10. The method of claim 9, wherein the transistor region further comprises a gate structure coupling the first transistor to the second transistor.

14. 11. The method of claim 10, wherein the first buried power rail and the second buried power rail are unevenly spaced within the cell.

15. 1. A method for manufacturing a semiconductor device by a manufacturing system, the method comprising: stacking, by the manufacturing system, a first transistor of the semiconductor device over a second transistor of the semiconductor device, wherein the first transistor is laterally offset from the second transistor; forming, by the manufacturing system, a power rail layer having a first buried power rail and a second buried power rail; and coupling, by the manufacturing system, the first buried power rail to the first transistor and the second buried power rail to the second transistor. A method comprising:

16. coupling, by the manufacturing system, a first end of a gate structure to the first transistor; and coupling a second end of the gate structure to the second transistor by the manufacturing system. The method of claim 15 further comprising:

17. 16. The method of claim 15, wherein the first transistor is a p-channel field effect transistor (PFET).

18. 16. The method of claim 15, wherein the second transistor is an n-channel field effect transistor (NFET).

19. coupling said power rail layer to a powered backside supply network by said manufacturing system. The method of claim 15 further comprising:

20. 16. The method of claim 15, wherein the first buried power rail and the second buried power rail are unevenly spaced within a cell.

Images