Back contact solar cell and its manufacturing method

Abstract

The present invention relates to a back-contact solar cell and a method for fabricating the same. The method includes forming a porous lattice in a tunnel layer located in a first region on the backside of a silicon wafer having a first region and a second region, and forming a doped polysilicon layer on the surface of the tunnel layer facing away from the silicon wafer, with the doping concentration gradually decreasing in the direction away from the tunnel layer. In this application, forming multiple holes in the tunnel layer creates carrier tunneling paths within the tunnel layer, while doped atoms in the doped polysilicon layer form atomic-level "pinholes" on the surface of the tunnel layer, thereby reducing tunnel contact resistance. Furthermore, the region of the doped polysilicon layer in contact with the tunnel layer has the highest doping concentration, which, together with the tunnel layer, forms a higher asymmetric shift barrier layer, allowing majority carriers to pass through but blocking minority carriers. This allows for more uniform and smooth collection of majority carriers, enhancing the passivation effect and further improving solar cell efficiency.

Description

[Technical Field]

[0001] This application claims priority from a Chinese patent application bearing application number 202310217369.7 and entitled "Back-contact solar cell and manufacturing method thereof," filed with the State Intellectual Property Office of the People's Republic of China on March 2, 2023, the entire contents of which are incorporated herein by reference.

[0002] The present invention is in the field of photovoltaics, and more particularly relates to back-contact solar cells and methods for fabricating the same. [Background technology]

[0003] In an IBC (Interdigitated back contact) battery, positive and negative metal electrodes are arranged in an interdigitated pattern on the back of the battery, and the front side is not blocked by a metal electrode, allowing maximum use of light incident on the front of the battery, increasing the current density of the battery and further improving the photoelectric conversion efficiency of the battery.

[0004] Taking a P-type IBC battery as an example, the N-type region on the back side of the battery is covered with SiO x A tunnel layer and an N-type doped polycrystalline silicon layer are formed. x The tunnel layer is generally deposited by LPCVD (low pressure chemical vapor deposition) or PECVD (plasma enhanced chemical vapor deposition), and is made of SiO xThe uneven thickness of the tunnel layer easily leads to many problems, such as excessively large tunnel resistance, poor passivation effect, and low carrier selectivity, which reduces the cell efficiency and even results in a certain percentage of inefficient or defective cells. Furthermore, the doping elements in the N-type doped polysilicon layer are not uniformly distributed throughout the doped polysilicon layer, resulting in a large tunnel contact resistance between the N-type doped polysilicon layer and the tunnel layer, which inhibits the collection of majority carriers, thereby limiting the cell efficiency.

[0005] Therefore, engineers are paying attention to how to solve the above technical problems. Summary of the Invention [Problem to be solved by the invention]

[0006] The present application aims to provide a back-contact solar cell and a method for manufacturing the same in order to improve the cell passivation effect and cell efficiency. [Means for solving the problem]

[0007] In order to solve the above technical problems, the present application provides the following method for manufacturing a back-contact solar cell. The method for manufacturing this back contact solar cell includes: forming a porous lattice in a tunnel layer located in the first region of a backside of a silicon wafer having a first region and a second region; and forming a doped polycrystalline silicon layer on a surface of the tunnel layer facing away from the silicon wafer, the doping concentration therein decreasing in a direction away from the tunnel layer.

[0008] Optionally, forming a porous lattice in the tunnel layer located in the first region of the backside of the silicon wafer includes etching the tunnel layer to form a porous lattice in the tunnel layer that does not extend completely through the tunnel layer.

[0009] Optionally, forming a porous lattice in a tunnel layer located in a first region on the backside of the silicon wafer includes etching the tunnel layer using laser light or an erosion liquid containing an additive to form a porous lattice in the tunnel layer.

[0010] Optionally, the step of forming a doped polycrystalline silicon layer on a surface of the tunnel layer facing away from the silicon wafer comprises: depositing an intrinsic polycrystalline silicon layer on a surface of the tunnel layer facing away from the silicon wafer; doping the intrinsic polycrystalline silicon layer by multiple diffusions to form the doped polycrystalline silicon layer.

[0011] Optionally, a region of the doped polycrystalline silicon layer adjacent to the tunnel layer has a doping concentration of 1E20 to 6E20 atoms / cm 3 and the doping concentration in the region of the doped polycrystalline silicon layer farthest from the tunnel layer is 1E19 to 3E20 atoms / cm 3 is.

[0012] As an option, when the tunnel layer is etched using a laser beam, the pulse width of the laser beam is in the range of 1 ps to 50 ns, and the wavelength of the laser beam is in the range of 200 to 800 nm.

[0013] Optionally, if an additive-containing erosion fluid is used to etch the tunnel layer, the concentration of the erosion fluid is in the range of 0.5% to 15%.

[0014] Optionally, prior to the step of forming a porous lattice in the tunnel layer located in the first region of the backside of the silicon wafer, The method further includes depositing the tunnel layer selected from the group consisting of a silicon carbide layer, a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, an aluminum oxide layer, and any combination thereof, on the backside of the silicon wafer.

[0015] Optionally, depositing the tunneling layer in the first region of the backside of the silicon wafer comprises: depositing the tunnel layer on the backside of the silicon wafer by a method selected from PECVD, PEALD, LPCVD, PVD, ALD, and any combination thereof.

[0016] According to the present application, there is further provided a back-contact solar cell comprising a silicon wafer, the back surface of which has first and second regions with different doping types, the first region being provided with a tunnel layer having a porous lattice and a doped polycrystalline silicon layer, the doping concentration in the doped polycrystalline silicon layer gradually decreasing in a direction away from the tunnel layer.

[0017] Optionally, the porous lattice does not penetrate completely through the tunnel layer. Optionally, the tunnel layer is selected from the group consisting of a silicon carbide layer, a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, an aluminum oxide layer, and any combination thereof.

[0018] A method for manufacturing a back-contact solar cell according to the present application includes forming a porous lattice in a tunnel layer located in a first region on the backside of a silicon wafer having the first region and a second region, and forming a doped polycrystalline silicon layer on a surface of the tunnel layer facing away from the silicon wafer, the doping concentration therein gradually decreasing in a direction away from the tunnel layer.

[0019] Thus, in the manufacturing process of the battery of the present application, the formation of holes in the tunnel layer creates carrier tunneling paths on the surface of the tunnel layer, and the doped atoms in the doped polysilicon layer form atomic-level "pinholes" on the surface of the tunnel layer, resulting in a low tunnel contact resistance. Furthermore, the region of the doped polysilicon layer in contact with the tunnel layer has the highest doping concentration, which, together with the tunnel layer, forms a higher asymmetric shift barrier layer, allowing majority carriers to pass through but preventing minority carriers from passing through. This means that majority carriers can be collected more uniformly and smoothly, enhancing the passivation effect and further improving the efficiency of the solar cell.

[0020] The present application also provides a back-contact solar cell having the above advantages.

[0021] In order to more clearly explain the technical solutions of the embodiments of the present application or the prior art, the following briefly introduces drawings necessary for the description of the embodiments or the prior art. It should be apparent that the drawings in the following description are only some embodiments of the present application, and those skilled in the art can also obtain other drawings based on these drawings without exerting creative labor. [Brief explanation of the drawings]

[0022] [Figure 1] 1 is a flow chart of a method for manufacturing a back contact solar cell according to an embodiment of the present application. [Figure 2] 1 is a structural schematic diagram of a back-contact solar cell according to an embodiment of the present application; [Figure 3] 1 is a structural schematic diagram of a non-completely penetrating hole in a tunnel layer according to an embodiment of the present application; DETAILED DESCRIPTION OF THE INVENTION

[0023] In order to allow those skilled in the art to better understand the technical solution of the present application, the present application will be described in more detail below in combination with the accompanying drawings and specific embodiments. Obviously, the embodiments described herein are only some of the embodiments of the present application, and are not all of the embodiments. Based on the embodiments of the present application, all other embodiments that those skilled in the art can obtain without creative work are all within the technical scope of the present application.

[0024] In the following description, numerous specific details are set forth to provide a thorough understanding of the present invention, but the present invention may be embodied in other forms not described herein, and the present invention is not limited to the specific embodiments described below, since those skilled in the art may make similar extensions without departing from the spirit of the present invention.

[0025] As mentioned in the background section, currently, back-contact solar cells often suffer from many problems, such as high tunnel resistance, poor passivation effect, and low carrier selectivity, due to the uneven thickness of the tunnel layer, resulting in low cell efficiency. In addition, the high tunnel contact resistance between the N-type doped polysilicon layer and the tunnel layer inhibits majority carrier collection, limiting cell efficiency.

[0026] In view of the above problems, the present application provides a method for manufacturing a back-contact solar cell, which includes the following steps, as shown in FIG.

[0027] Step S101: Form a porous lattice in a tunnel layer located in a first region of a back surface of a silicon wafer having a first region and a second region distributed at an interval.

[0028] The porous lattice contains many holes. There are two types of holes: holes that penetrate the tunnel layer, and holes that do not penetrate the tunnel layer completely. To improve carrier selectivity while satisfying passivation and contact requirements, it is preferable that the holes in the porous lattice do not penetrate the tunnel layer completely. A structural schematic diagram of a hole 21 that does not penetrate the tunnel layer 2 is shown in Figure 3.

[0029] It should be noted that the method for forming the porous lattice is not limited in this application.

[0030] In one embodiment, the step of forming a porous lattice in a tunnel layer located in a first region of a backside of the silicon wafer includes: Etching the tunneling layer with laser light to form a porous lattice in the tunneling layer.

[0031] Here, when the tunnel layer is ablated using a laser beam, the pulse width of the laser beam may be set to 1 ps to 50 ns, and the wavelength of the laser beam may be set to 200 to 800 nm. Regular lattice micropores are formed in the tunnel layer so that the size of the micropores is 0.1 μm to 50 μm and the spacing between the micropores is 0.5 μm to 4 mm.

[0032] To improve carrier selectivity while satisfying passivation and contact requirements, holes that do not completely penetrate the tunnel layer can be formed on the surface of the tunnel layer by adjusting the wavelength, power, and pulse width of the laser light.

[0033] In another embodiment, the step of forming a porous lattice in the tunnel layer located in the first region of the backside of the silicon wafer includes: Etching the tunnel layer with an additive-containing erosion liquid to form a porous lattice in the tunnel layer.

[0034] The additives protect localized areas on the surface of the tunnel layer from corrosion by selective erosion with the erosion liquid, forming a porous lattice. The thickness of the tunnel layer after erosion is controlled to 0.1 nm to 10 nm.

[0035] The erosion liquid may be an acidic solution or an alkaline solution, both of which are within the scope of protection of the present application.

[0036] The organic / inorganic functional groups contained in the additive materials can effectively bond with the surface of the tunnel layer, but the bonding strength differs, which results in a certain degree of difference in surface protection, and thus in acid and alkali resistance. Therefore, when acid or alkali is used, a porous lattice, which is a micro-etch pit, can be formed.

[0037] To form a hole that does not completely penetrate the tunnel layer, a protective additive is used to protect the tunnel layer so that the reaction rate of the erosion solution to the tunnel layer is slowed down, and then the tunnel layer is etched to form a hole that does not completely penetrate the tunnel layer, thereby improving carrier selectivity while satisfying passivation and contact requirements.

[0038] When the tunnel layer is eroded using an additive-containing erosion liquid, the concentration of the acidic erosion liquid or alkaline erosion liquid may be 0.5% to 15%, but can be specifically set depending on the additive, temperature, and reaction time.

[0039] In this embodiment, the silicon wafer is a P-type silicon wafer, and after subsequent N-type doping (phosphorus doping), the first region corresponds to the N-type region of the cell, and the second region corresponds to the P-type region of the cell. If the silicon wafer is an N-type silicon wafer, a doped polycrystalline silicon layer is located over the entire back surface of the silicon wafer. However, the doping type corresponding to the N-type region of the doped polycrystalline silicon layer is opposite to the doping type corresponding to the P-type region.

[0040] Optionally, in one embodiment of the present application, before the step of forming the porous lattice in the tunnel layer, double-side polishing the silicon wafer; The method further includes forming a tunnel layer on the surface of the silicon wafer.

[0041] The purpose of polishing is to remove cutting damage from the surface of silicon wafers, smooth the surface, and reduce surface defects. Polishing is performed using standard alkalis such as 5-20% potassium hydroxide solution, sodium hydroxide solution, or TMAH (tetramethylammonium hydroxide) solution, and the chemical reaction can be carried out at 60-90°C. Polishing additives can also be added to the solution, which is advantageous for further smoothing the silicon wafer surface. Polishing additives can be purchased directly.

[0042] The materials and specific manufacturing methods for the tunnel layer will be introduced in the following examples. Step S102: forming a doped polycrystalline silicon layer on the surface of the tunnel layer facing away from the silicon wafer, the doping concentration in the doped polycrystalline silicon layer gradually decreasing in the direction away from the tunnel layer.

[0043] To enhance carrier selectivity and further improve cell efficiency, the region of the doped polysilicon layer adjacent to the tunnel layer has a doping concentration of 1E20 to 6E20 atoms / cm 3 and the region of the doped polycrystalline silicon layer farthest from the tunnel layer has a doping concentration of 1E19 to 3E20 atoms / cm 3 is.

[0044] It should be noted that the present application does not limit the method for forming the doped polycrystalline silicon layer.

[0045] In one embodiment, the step of forming a doped polycrystalline silicon layer on a surface of the tunnel layer facing away from the silicon wafer comprises: a step S102a1 of depositing an intrinsic polycrystalline silicon layer on a surface of the tunnel layer facing away from the silicon wafer; and Step S102a2 of doping the intrinsic polycrystalline silicon layer by multiple diffusions to form the doped polycrystalline silicon layer.

[0046] The doping concentration of the doped polycrystalline silicon layer gradually decreases away from the tunnel layer, and can be controlled in three ways: dopant source concentration, sintering temperature, and diffusion time. For example, the dopant source concentration may be gradually decreased, the sintering temperature may be gradually decreased, and the diffusion time may be gradually shortened during multiple diffusions.

[0047] The diffusion in this process is mainly divided into three stages. After the first stage of diffusion, the diffusion concentration is 5E20cm -3 After two stages of diffusion, the diffusion concentration reaches 3E20cm -3 After three stages of diffusion, the diffusion concentration reaches 1E20cm -3 reached.

[0048] The thickness of the intrinsic polycrystalline silicon layer may be 30 nm to 300 nm. Examples of the deposition method include LPCVD, PEALD, and PVD (Physical Vapor Deposition).

[0049] In another embodiment, the step of forming a doped polycrystalline silicon layer on a surface of the tunnel layer facing away from the silicon wafer comprises: Step S102b1 depositing an intrinsic polycrystalline silicon layer on a surface of the tunnel layer facing away from the silicon wafer; and Step S102b2 of doping the intrinsic polycrystalline silicon layer by performing ion implantation multiple times to form the doped polycrystalline silicon layer.

[0050] The doping concentration of the doped polycrystalline silicon layer can be gradually decreased in the direction away from the tunnel layer by controlling the amount of implantation, implantation time, etc. The intrinsic polycrystalline silicon layer may have a thickness of 30 nm to 300 nm.

[0051] Step S103: Remove the doped polycrystalline silicon layer corresponding to the second region on the back surface of the silicon wafer.

[0052] Note that the method further includes a step of removing a portion of the oxidizing media layer on the back surface using laser light, before step S103 and after step S102. Here, the proportion of the P-type region may be 10% to 40%, with the remainder being N-type. The pulse width of the laser light used is 1 ps to 15 ps, and the corresponding laser wavelength is generally 355 nm. Here, the oxidizing media layer is formed when doping the intrinsic polycrystalline silicon layer. For example, when the silicon wafer is a P-type silicon wafer and phosphorus is doped into the intrinsic polycrystalline silicon layer, the oxidizing media layer is phosphosilicate glass.

[0053] By using an alkaline solution (e.g., 5-20% potassium hydroxide solution, sodium hydroxide solution, TMAH solution, etc.) at 60-90°C, the doped polycrystalline silicon layer corresponding to the P-type region can be removed, while at the same time laser damage can be removed, the surface can be smoothed, and surface defects can be reduced. A polishing additive can also be added to the alkaline solution, as this contributes to further smoothing the surface.

[0054] Step S104: The oxide layer on the front side of the silicon wafer is removed. The method for removing the oxidizing medium layer on the front side may be to perform single-sided etching using an in-line etching machine with HF solution, a mixture of HF and HCl, HNO3 solution, etc.

[0055] Step S105: Deposit a passivation layer on the front and back surfaces of the silicon wafer respectively. The passivation layer serves the purpose of chemical passivation. The front passivation layer may be a stack of aluminum oxide, silicon nitride, and silicon oxide layers, with corresponding thicknesses of 2-20 nm, 50-80 nm, and 5-20 nm, and may be fabricated by methods including, but not limited to, PECVD, ALD (atomic layer deposition), and PEALD (plasma enhanced atomic layer deposition). The back passivation layer may be a stack of aluminum oxide and silicon nitride layers, with corresponding thicknesses of 2-20 nm and 60-200 nm, and may be fabricated by methods including, but not limited to, PECVD, ALD, and PEALD.

[0056] Step S106: Electrodes are fabricated in the first and second regions on the back surface of the silicon wafer, respectively, to obtain a back-contact solar cell. The first region corresponds to the N-type region, and the second region corresponds to the P-type region. Local openings are made in the N-type region using laser light or acidic etching materials. The openings can be dotted, spaced dots, lines, spaced lines, or dotted and spaced lines, with a diameter or width of 10 to 50 μm. The openings are designed to remove only the passivation layer without damaging the underlying doped polycrystalline silicon layer. A low-corrosion silver paste or silver-aluminum paste is printed above the openings in the N-type region, with a line width of 50 to 100 μm, to establish electrical contact with the doped polycrystalline silicon layer. When a corrosive silver paste is printed above the doped polycrystalline silicon layer, the glass frit in the corrosive silver paste opens the passivation layer, allowing the silver to come into contact with the doped polycrystalline silicon layer. In the P-type region, electrode paste is printed directly on the passivation layer and co-sintered at 600-800°C to form the electrode.

[0057] In the fabrication process of the present invention, holes are formed in the tunnel layer to form carrier tunneling paths on the surface of the tunnel layer, and at the same time, doped atoms in the doped polysilicon layer form atomic-level "pinholes" on the surface of the tunnel layer, thereby reducing the tunnel contact resistance. Furthermore, the region of the doped polysilicon layer that contacts the tunnel layer has the highest doping concentration, which, together with the tunnel layer, forms a higher asymmetric shift barrier layer, allowing majority carriers to pass through but preventing minority carriers from passing through. This means that majority carriers can be collected more uniformly and smoothly, enhancing the passivation effect and further improving the efficiency of the solar cell.

[0058] In addition to the above embodiments, in one embodiment of the present application, after the step of forming a doped polycrystalline silicon layer on the surface of the tunnel layer away from the silicon wafer, The method further includes a step of texturing the silicon wafer.

[0059] Specifically, the texturing process is performed after removing the oxide layer on the front side of the silicon wafer and before creating the passivation layer.

[0060] The texturing process can be performed using an alkaline solution, such as a 5-20% potassium hydroxide solution, sodium hydroxide solution, or TMAH solution, under the action of a texturing additive. By forming pyramidal structures in areas not protected by an oxidizing medium layer, i.e., by forming a pyramidal texture on the entire front surface, a light trapping effect can be achieved. Furthermore, texturing can also remove the polycrystalline silicon (poly-Si) on the front surface.

[0061] To avoid the formation of pyramidal structures on the backside, a process can be performed in which the doped polycrystalline silicon layer corresponding to the P-type region on the backside of the silicon wafer is removed, and then the backside of the silicon wafer is oxidized to form a protective layer. Here, the oxidation method can be a thermal oxidation degradation method or an ultraviolet-ozone treatment method. The oxide layer is removed with an acid solution after the texturing process.

[0062] In the above embodiment, in one embodiment of the present application, before the step of forming a porous lattice in the tunnel layer located in the first region on the back surface of the silicon wafer, The method further includes depositing the tunnel layer selected from the group consisting of a silicon carbide layer, a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, an aluminum oxide layer, and any combination thereof, on the backside of the silicon wafer.

[0063] The thickness of the tunnel layer may be 0.1 nm to 10 nm. The material of the tunnel layer in the prior art is silicon oxide, but the material of the tunnel layer in the present application may be silicon carbide, silicon nitride, a silicon oxynitride layer, or an aluminum oxide layer in addition to silicon oxide, and have the same tunneling effect.

[0064] Optionally, depositing the tunneling layer on the backside of the silicon wafer comprises: depositing the tunnel layer on the backside of the silicon wafer by a method selected from PECVD, PEALD, LPCVD, PVD, ALD, and any combination thereof.

[0065] When depositing the tunnel layer, it may be deposited over the entire surface, and then the portion corresponding to the second region may be removed. The manufacturing method in this application will be explained below using a P-type silicon wafer as an example.

[0066] Step 1: Double-sided polishing of P-type silicon wafer Regular alkaline polishing is performed using 5-20% potassium hydroxide, sodium hydroxide, TMAH solution, etc. containing polishing additives, and a chemical reaction is carried out at 60-90°C to achieve double-sided polishing.

[0067] Step 2: Deposition of the tunnel layer on the backside A tunnel layer is deposited by any one of LPCVD, PECVD, PEALD, PVD, and ALD methods, where the tunnel layer is one or more selected from oxides, nitrides, oxynitrides, and aluminum oxides of Si, and has a thickness of 0.1 nm to 10 nm.

[0068] Step 3: Laser microablation or wet microetching of the tunnel layer When using a dry method to microablate the surface of the tunnel layer using laser light, the pulse width of the laser light is set to 1 ps to 50 ns, and the wavelength is set to 200 to 800 nm. Regular lattice micropores corresponding to the surface of the tunnel layer are formed with a pore size of 0.1 μm to 50 μm and a micropore spacing of 0.5 μm to 4 mm.

[0069] On the other hand, when the tunnel layer is treated using a wet method in which micro-etching is performed on the tunnel layer using an acidic or alkaline solution containing an additive, a porous structure is formed on the surface of the tunnel layer while controlling the thickness of the tunnel layer after etching to be 0.1 nm to 10 nm.

[0070] Step 4: Deposition of intrinsic amorphous silicon layer An intrinsic amorphous silicon layer is deposited on the surface of the tunnel layer to a thickness of 30 nm to 300 nm using any one of the LPCVD method, the PEALD method, and the PVD method.

[0071] Step 5: n-type doping The corresponding P doping concentration near the tunnel layer is 1E20 to 6E20 atoms / cm 3 , the corresponding P doping concentration away from the tunnel layer is 1E19~3E20 atoms / cm3 P doping is performed by a multi-stage P (phosphorus) diffusion method so that

[0072] Step 6: Laser patterning A portion of the PSG layer on the back surface is removed using picosecond laser processing so that the P-type region occupies 10% to 40% and the remainder becomes N-type. The pulse width of the laser light used is 1ps to 15ps, and the corresponding laser wavelength is 355nm.

[0073] Step 7: Alkaline cleaning + oxidation Polishing is performed with conventional alkalis such as 5-20% potassium hydroxide, sodium hydroxide, or TMAH solution, and the chemical reaction is carried out at 60-90°C. Adding a polishing additive to the reaction contributes to surface planarization, with the objective of removing laser damage on the surface and the N-type doped polycrystalline silicon layer in the P region, smoothing the surface, and reducing surface defects.

[0074] To avoid creating a textured surface during the texturing process, a protective layer is formed in the area to be back-polished by means of hot acid or ultraviolet-ozone.

[0075] Step 8: PSG removal + texturing The PSG layer on the front side is removed by etching one side with an acid solution in an in-line etching machine. A texturing process is performed using a 5-20% solution of potassium hydroxide, sodium hydroxide, and TMAH, and a pyramidal structure is formed in the area not covered and protected by the PSG layer so that the entire front surface becomes a pyramidal textured surface, thereby exerting an optical trapping effect, and the polycrystalline silicon on the front surface is also removed by the texturing process.

[0076] Step 9: Front and back lamination and passivation A hydrogen-containing dielectric layer is deposited on the front and back surfaces so that the back surface is a laminated film of alumina + silicon nitride and the front surface is a laminated film of alumina + silicon nitride + silicon oxide, thereby serving to chemically passivate the front and back surfaces.

[0077] Step 10: Metallizing the backside In the N-type region, a local opening is made using laser light or acid etching materials without damaging the underlying doped polycrystalline silicon layer. A low-corrosion silver paste or silver-aluminum paste is printed above the opening area in the N-type region, and a corrosive silver paste is printed above the N-type polycrystalline silicon. The glass frit in the corrosive silver paste opens the passivation layer, allowing the silver to come into contact with the doped polycrystalline silicon layer. In the P-type region, an electrode paste is printed directly on the passivation layer and co-sintered at 600-800°C to form an electrode.

[0078] The present application further provides a back-contact solar cell as shown in Figure 2. The solar cell comprises a silicon wafer 1, the back surface of which is provided with first and second spaced apart regions of different doping types, the first region being provided with a tunnel layer 2 having a porous lattice and a doped polycrystalline silicon layer 3, the doping concentration of which gradually decreases in the direction away from the tunnel layer 2.

[0079] The back contact solar cell further includes a front passivation layer 5 provided on the front side of the silicon wafer 1, a back passivation layer 4 provided on the back side of the silicon wafer 1, and an electrode 6. Here, the front passivation layer 5 may be a stack of an aluminum oxide layer, a silicon nitride layer, and a silicon oxide layer, and the back passivation layer 4 may be a stack of an aluminum oxide layer and a silicon nitride layer.

[0080] The silicon wafer 1 may be a P-type silicon wafer, the doping type of the doped polycrystalline silicon layer 3 may be N-type doping, and the doping element may be phosphorus. Correspondingly, the first region is an N-type region and the second region is a P-type region.

[0081] The tunnel layer 2 may be any one or any combination selected from a silicon carbide layer, a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, and an aluminum oxide layer, but is not limited to these.

[0082] The porous lattice contains many holes. There are two types of holes: holes that penetrate the tunnel layer and holes that do not penetrate the tunnel layer completely. To improve carrier selectivity while satisfying passivation and contact requirements, it is preferable that the holes in the porous lattice do not penetrate the tunnel layer completely.

[0083] Each embodiment in this specification was created by gradually adding details. Although the description of each embodiment focuses on the differences between other embodiments, the same or similar parts between the embodiments may be mutually referenced.

[0084] The back-contact solar cell and its manufacturing method according to the present application have been described in detail above. While specific examples have been used in this specification to describe the principles and embodiments of the present application, the description of the above examples is merely intended to aid in understanding the method and essential concept of the present application. Those skilled in the art may make various improvements and modifications to the present application without departing from the principles of the present application, and these improvements and modifications are also within the technical scope of the claims of the present application.

Claims

1. forming a porous lattice in a tunnel layer located in the first region of a backside of a silicon wafer having a first region and a second region; forming a doped polycrystalline silicon layer on a surface of said tunnel layer facing away from said silicon wafer, said doping concentration therein gradually decreasing in a direction away from said tunnel layer.

2. forming a porous lattice in the tunnel layer located in the first region of the backside of the silicon wafer, 10. The method of claim 1, further comprising the step of etching said tunneling layer to form a lattice of holes in said tunneling layer that does not penetrate completely through said tunneling layer.

3. forming a porous lattice in the tunnel layer located in the first region of the backside of the silicon wafer, 3. The method for manufacturing a back contact solar cell according to claim 1, further comprising the step of etching the tunnel layer using a laser beam or an erosion solution containing an additive to form a porous lattice in the tunnel layer.

4. forming a doped polycrystalline silicon layer on a surface of the tunnel layer facing away from the silicon wafer, depositing an intrinsic polycrystalline silicon layer on a surface of the tunnel layer facing away from the silicon wafer; 2. The method of claim 1, further comprising the step of doping the intrinsic polycrystalline silicon layer by multiple diffusions to form the doped polycrystalline silicon layer.

5. The region of the doped polycrystalline silicon layer adjacent to the tunnel layer has a doping concentration of 1E20 to 6E20 atoms / cm ３ and The region of the doped polycrystalline silicon layer farthest from the tunnel layer has a doping concentration of 1E19 to 3E20 atoms / cm ３ 2. The method for producing a back contact solar cell according to claim 1, wherein:

6. 3. The method for manufacturing a back-contact solar cell according to claim 2, wherein when the tunnel layer is etched using laser light, the pulse width of the laser light is in the range of 1 ps to 50 ns and the wavelength of the laser light is in the range of 200 to 800 nm.

7. 4. The method for manufacturing a back contact solar cell according to claim 3, wherein when the tunnel layer is etched using an erosion solution containing an additive, the concentration of the erosion solution is in the range of 0.5% to 15%.

8. Before the step of forming a porous lattice in the tunnel layer located in the first region on the back surface of the silicon wafer, 10. The method of claim 1, further comprising depositing a tunneling layer selected from the group consisting of a silicon carbide layer, a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, an aluminum oxide layer, and any combination thereof, on the backside of the silicon wafer.

9. depositing the tunnel layer in the first region of the backside of the silicon wafer; 10. The method of claim 8, further comprising depositing the tunnel layer on the backside of the silicon wafer by a method selected from PECVD, PEALD, LPCVD, PVD, ALD, and any combination thereof.

10. A solar cell comprising a silicon wafer, The back surface of the silicon wafer has a first region and a second region having different doping types, a tunnel layer having a porous lattice and a doped polycrystalline silicon layer are provided in the first region; A back-contact solar cell, characterized in that the doping concentration in said doped polycrystalline silicon layer gradually decreases in a direction away from said tunnel layer.

11. 11. The back contact solar cell of claim 10, wherein said porous lattice does not penetrate completely through said tunneling layer.

12. 12. The back contact solar cell of claim 10 or 11, wherein the tunneling layer is selected from the group consisting of a silicon carbide layer, a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, an aluminum oxide layer, and any combination thereof.

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