OPTOELECTRONIC DEVICE HAVING ELECTRICAL INTERCONNECT LAYERS - Patent application

Abstract

1. An optoelectronic device (5) comprising: an optoelectronic emitter assembly (15) comprising a plurality of optoelectron emitters (20a, 20b, 20c); a controller assembly (16) comprising a plurality of driver circuits (70) for supplying current to the plurality of optoelectron emitters; and at least one electrical interconnect layer (500) disposed between the optoelectron emitter assembly and the controller assembly, the electrical interconnect layer being configured to provide electrical connections between one or more of the driver circuits and each of the plurality of optoelectron emitters; wherein the at least one electrical interconnect layer comprises at least one conductor layer (511) and at least one insulator layer (540) extending across at least a portion of the conductor layer.

Description

[Technical Field]

[0001] The present invention relates to optoelectronic devices and methods for fabricating optoelectronic devices. In particular, the present invention relates to improved optoelectronic devices having electrical interconnect layers and methods for fabricating such devices. [Background technology]

[0002] One type of known optoelectronic device is the light-emitting diode ("LED"). LEDs typically have an n-type doped semiconductor material, a p-type doped semiconductor material, and a light-emitting or active region disposed between the n-type and p-type doped semiconductor materials. Light is emitted when an LED is supplied with a current across the light-emitting region, forward biasing the diode. Variations of simple LEDs are known, with specific material architectures in which the wavelength of light emitted depends on the specific material composition and arrangement of the LED.

[0003] III-V semiconductor materials are important to LED design, particularly the family of III-nitride semiconductor materials. "III-V" semiconductors include binary, ternary, and quaternary alloys of group III elements, such as Ga, Al, and In, with group V elements, such as N, P, As, and Sb, while "III-nitride" materials include gallium nitride (GaN), indium nitride (InN), and aluminum nitride (AlN), along with their ternary and quaternary alloys. (Al,In)GaN is a term that encompasses AlGaN, InGaN, and GaN.

[0004] There is a great demand for LEDs that emit at all visible wavelengths, particularly at longer wavelengths toward green, yellow, and red. However, manufacturers have historically encountered more challenges in producing LEDs that emit at longer wavelengths. One of the major challenges facing the growth of long-wavelength LEDs, such as green, yellow, and red LEDs on GaN-based platforms, is the need to use a high indium (In) content to reduce the bandgap of the light-emitting or active region to a suitable level for long-wavelength emission. However, varying the In content of a material also affects the in-plane lattice constant of the semiconductor. The required InGaN light-emitting or active region has a larger lattice parameter than the underlying GaN. This creates problems in device designs where it is desirable to deposit active semiconductor layers on substrate layers with different lattice dimensions. Lattice mismatch at layer boundaries introduces strain into the lattice, causing the formation of defects in the material that act as non-radiative recombination centers and degrade device performance.

[0005] Micro LEDs are known to be fabricated using techniques such as conventional LED epitaxial growth, laser lift-off, electrostatic carry, and elastomer stamping for transfer.

[0006] LEDs have a variety of uses. One type of optoelectronic device that uses LEDs is known as a display screen. An LED display screen typically includes an array of pixels, with each pixel divided into three subpixels, each including an LED. Each LED in a pixel emits light of one of three wavelengths: red, green, or blue. Power to the LED display screen can be controlled by a matrix of driver circuits, with each LED having its own driver circuit that controls the current supplied to the LED. One exemplary driver circuit includes a metal-oxide-semiconductor field-effect transistor (MOSFET) device. MOSFET devices can include p-type metal-oxide-semiconductor (PMOS) or n-type metal-oxide-semiconductor (NMOS). In some cases, both NMOS and PMOS devices are provided together, collectively referred to as complementary metal-oxide-semiconductor field-effect transistors (CMOS). Such devices are known in the art. Summary of the Invention [Problem to be solved by the invention]

[0007] When assembling an LED display screen, it is known to position the LED assembly above a CMOS driver circuit to electrically connect the LEDs to the driver circuit. To date, this assembly method has required matching the LED pixel design to the CMOS driver circuit. For example, each LED subpixel had to be overlaid and matched to a CMOS driver circuit so that the number of CMOS driver circuits matched the number of LEDs. The CMOS driver circuit for each LED also typically had to have the same pitch as the LEDs, and the voltage and current specifications were determined by the individual CMOS driver circuit. This resulted in significant constraints on the design of the LED display.

[0008] It is desirable to provide improved optoelectronic devices and methods for manufacturing optoelectronic devices. [Means for solving the problem]

[0009] In the present invention, an electrical interconnect layer comprising at least one conductor layer and at least one insulator layer extending across at least a portion of the conductor layer enables electrical interconnection between one or more driver circuits of the controller assembly and each optoelectronic emitter of the optoelectronic emitter assembly. By using such an electrical interconnect layer, the size, shape, and location of the interconnects are not limited by the size, shape, and location of the optoelectronic emitters or driver circuits.

[0010] The invention is defined in the independent claims, to which reference should now be made. Preferred or advantageous features of the invention are set out in the dependent claims.

[0011] In a first aspect of the present invention, there is provided an optoelectronic device, the optoelectronic device comprising: a photoelectron emitter assembly comprising a plurality of photoelectron emitters; a controller assembly including a plurality of driver circuits for supplying current to the plurality of photoemitters; at least one electrical interconnect layer disposed between the photoelectron emitter assembly and the controller assembly, the at least one redistribution or electrical interconnect layer configured to provide electrical connections between one or more of the driver circuits and each of the plurality of photoelectron emitters; Equipped with The at least one electrical interconnect layer comprises at least one conductor layer and at least one insulator layer extending across at least a portion of the conductor layer.

[0012] The at least one electrical interconnect layer may have a connection area that is larger than the electrical contact area of ​​the optoelectronic emitter or driver circuit to which the at least one electrical interconnect layer is connected, the advantage of which is that the effective area for connection is increased, facilitating interconnection.

[0013] The conductor layer may comprise a plurality of interconnect contacts. At least one interconnect contact may have a connection area that is larger than the electrical contact area of ​​the optoelectron emitter or driver circuit to which the at least one interconnect contact is connected. This has the advantage of improving the yield of bonding or connection between the optoelectron emitter assembly and the controller assembly. Increasing the size of the connection area of ​​the interconnect contact improves the ease and yield of bonding between the optoelectron emitter and the controller assembly.

[0014] The location of the at least one interconnect contact may be laterally offset from the location of the optoelectron emitter or driver circuit to which the at least one interconnect contact is connected, which has the advantage of allowing greater freedom in designing the circuitry of the optoelectron emitter and controller assembly, such that the location of the interconnect contact is not tied to the location of either the optoelectron emitter or the driver circuit.

[0015] At least one photoelectron emitter may be connected to multiple driver circuits via an electrical interconnect layer, which has the advantage of improving the current output from the driver circuit or circuits and enabling a higher current density difference between the at least one photoelectron emitter and the other photoelectron emitters.

[0016] Embodiment 1 In a first preferred embodiment of the present invention, an electrical interconnect layer is formed on an optoelectron emitter assembly comprising a plurality of optoelectron emitters. When forming the electrical interconnect layer on the optoelectron emitter assembly, the electrical interconnect layer may be deposited on the optoelectron emitter assembly. In this way, the electrical interconnect layer may have a microstructure indicative of having been deposited on the optoelectron emitter assembly.

[0017] The conductor layer may include a plurality of interconnect contacts for connection to one or more driver circuits. Each interconnect contact may be connected to a respective one of the plurality of photoemitters. Each interconnect contact may have a connection area that is larger than the electrical contact area of ​​the photoemitter. Increasing the size of the connection area of ​​the interconnect contacts relative to the electrical contact area of ​​the photoemitter improves ease and yield of bonding to the photoemitter.

[0018] At least one interconnect contact may have a connection area that is larger than the electrical contact area of ​​the driver circuit, which has the advantage of making bonding to the driver circuit easier.

[0019] At least one interconnect contact may have a connection area that is larger than the electrical contact areas of the multiple driver circuits, which allows multiple driver circuits to be connected to the interconnect contact, which has the advantage of improving the current output from the driver circuits.

[0020] An insulator layer may be disposed between the plurality of photoelectron emitters and the plurality of interconnect contacts, and the insulator layer may have a plurality of through holes to allow electrical interconnection between the plurality of photoelectron emitters and the plurality of interconnect contacts.

[0021] The electrical interconnect layer may include a first conductor layer and a second conductor layer. The second conductor layer may include a plurality of interconnect contacts for connecting to one or more driver circuits. The first conductor layer may be disposed between the second conductor layer and the plurality of photoemitters. Each interconnect contact may be connected to a respective one of the plurality of photoemitters via the first conductor layer. This has the advantage of providing greater flexibility in the design process and formation of the interconnects.

[0022] At least one interconnect contact may be laterally offset from its corresponding photoelectron emitter, which has the advantage of allowing greater freedom in designing the circuitry of the photoelectron emitters, as the location of the interconnect contact is not tied to the location of the photoelectron emitter.

[0023] First and second insulator layers may be disposed between the first and second conductor layers. The first and second insulator layers may be disposed between the second conductor layer and the plurality of photoemitters, respectively. The first and second insulator layers may have a plurality of through holes to allow electrical interconnection between the plurality of photoemitters, the second conductor layer, and the plurality of interconnect contacts.

[0024] Embodiment 2 In a second preferred embodiment of the present invention, an electrical interconnection layer is formed on a controller assembly including a plurality of driver circuits. When forming the electrical interconnection layer on the controller assembly, the electrical interconnection layer may be deposited on the controller assembly. In this way, the electrical interconnection layer may have a microstructure that indicates that it has been deposited on the controller assembly.

[0025] The conductor layer may include a plurality of interconnect contacts for connecting to each photoelectron emitter of the plurality of photoelectron emitters, each interconnect contact being connectable to one or more of the driver circuits.

[0026] At least one interconnect contact may have a connection area that is larger than the electrical contact area of ​​the driver circuit. Increasing the size of the connection area of ​​the interconnect contact relative to the electrical contact area of ​​the driver circuit improves ease and yield of bonding to the driver circuit.

[0027] At least one interconnect contact may have a connection area that is larger than the electrical contact areas of the multiple driver circuits, which allows multiple driver circuits to be connected to the interconnect contact, which has the advantage of improving the current output from the driver circuits.

[0028] Embodiment 3 In a third preferred embodiment of the present invention, a first electrical interconnect layer is formed on an optoelectron emitter assembly including an optoelectron emitter, and a second electrical interconnect layer is formed on a controller assembly including a plurality of driver circuits.

[0029] The first electrical interconnect layer may comprise a first conductor layer having a plurality of first interconnect contacts for connecting to one or more driver circuits. Each of the first interconnect contacts may be connected to a respective one of the plurality of photoelectron emitters. The second electrical interconnect layer may comprise a second conductor layer having a plurality of second interconnect contacts for connecting to each photoelectron emitter of the plurality of photoelectron emitters. Each of the second interconnect contacts may be connected to one or more of the driver circuits. The connection area and location of each of the first interconnect contacts may be the same as the connection area and location of a corresponding one of the second interconnect contacts. An advantage of this is that ease and yield of bonding between the photoelectron emitters and the controller assembly is improved.

[0030] Common characteristics The following features apply to both the first, second and third embodiments described above.

[0031] At least one of the plurality of driver circuits may comprise a CMOS driver circuit. The plurality of driver circuits may be a plurality of CMOS driver circuits.

[0032] The conductor layer may comprise any suitable conductive material, including a metal or metal alloy, which may be or include one or more of titanium, platinum, chromium, aluminum, nickel, and gold.

[0033] The conductor layer may comprise any suitable transparent conductive material, including but not limited to indium tin oxide and graphene.

[0034] The insulator layer may comprise a dielectric material, preferably one or more of SiO2, SiN or SiNx.

[0035] The photoelectric emitter assembly may be an LED assembly comprising a plurality of LEDs, at least one of which is an n-type doped portion; a p-type doped portion; a light emitting or active region disposed between the n-type doped portion and the p-type doped portion; a porous region of a III-nitride material; may also be provided.

[0036] The LEDs described herein are preferably formed from III-V semiconductor materials, and particularly preferably from III-nitride semiconductor materials. Preferably, the LEDs are formed from GaN semiconductor material, although other III-nitride materials may be used. As noted above, fabricating LEDs emitting at longer wavelengths, such as green, yellow, and red LEDs, on a GaN-based platform can be challenging due to the need for high indium (In) content to reduce the bandgap of the light-emitting or active region to a suitable level for long-wavelength emission. The required InGaN active region has a larger lattice parameter than the underlying GaN, and the resulting strain leads to the formation of defects in the material that act as non-radiative recombination centers, degrading device performance.

[0037] The inventors have discovered that the use of a porous region of III-nitride material in a semiconductor structure provides "strain relaxation," which reduces the strain in the layers of the semiconductor structure. Thus, by providing an LED with a porous region of III-nitride material, the n-doped portion, the light-emitting region, and the p-doped portion can be grown on the porous region with lower strain than would be possible without the porous region. Thus, the porous region can promote higher indium incorporation into the layers of the LED grown on the porous region, improving light emission at longer wavelengths.

[0038] The inventors have also found that growing an LED structure over a porous region of III-nitride material results in a significant shift in emission wavelength toward longer wavelengths compared to the same LED structure grown on a non-porous substrate. While the magnitude of the red shift can vary between different LED structures, in preferred embodiments, the porous region produces a red shift of a typical wavelength of 15 nm to 80 nm, or preferably 15 nm to 50 nm, and particularly preferably 30 nm to 50 nm or 30 nm to 40 nm.

[0039] Thus, the present invention allows for conventional, easily manufacturable LED structures to be shifted to longer wavelength emission, so that structures previously used as shorter wavelength (e.g., violet or blue) LEDs can be made into longer wavelength LEDs by incorporating porous regions into the structure, which can advantageously allow for LEDs to be manufactured without many of the technical problems experienced in prior art designs.

[0040] The layers of the LED structure may be made porous by electrochemical etching as described in International Patent Application No. PCT / GB2017 / 052895 (published as WO 2019 / 063957) and International Patent Application No. PCT / GB2019 / 050213 (published as WO 2019 / 145728).

[0041] The n-type portion, light-emitting region, and p-type portion (sometimes referred to as the LED structure) are preferably grown on a semiconductor template that includes a porous region. The semiconductor template may also include several layers of semiconductor material arranged to provide a suitable substrate for overgrowth of the LED structure. However, once the n-type region, light-emitting region, and p-type region are grown on the template, both the LED structure and the template form part of the LED.

[0042] The porous region may have a thickness of at least 1 nm, preferably at least 10 nm, particularly preferably at least 50 nm, for example, between 1 nm and 10,000 nm.

[0043] The porous region may have a porosity of 1% to 99%, or a porosity of 10% to 80%, or a porosity of 20% to 70%, or a porosity of 30% to 60%. The porosity of a porous region may be measured as the volume of all pores relative to the volume of the entire porous region.

[0044] Porosity has been shown to affect the magnitude of the wavelength shift induced by the porous region: generally, the higher the percentage porosity, the greater the wavelength shift of the LED compared to the same LED structure on a non-porous template.

[0045] The porous region is preferably formed from one of GaN, InGaN, AlGaN, AlInGaN or AlN.

[0046] The LED may include a connection layer of III-nitride material disposed between the n-doped portion and the porous region. Preferably, the connection layer is at least 100 nm thick, although thinner or thicker thicknesses may be used. The connection layer is preferably one of GaN, InGaN, AlGaN, AlInGaN, or AlN.

[0047] The LED preferably includes a non-porous intermediate layer of III-nitride material porous region between the porous region and the light-emitting region. The porous region is preferably formed by electrochemical porosification through the non-porous layer of III-nitride material, so that the non-porous layer of III-nitride material typically forms a non-porous intermediate layer that remains on the porous region. The non-porous intermediate layer advantageously provides a smooth surface for overgrowth of additional layers during fabrication.

[0048] Preferably, the LED comprises a non-porous intermediate layer of III-nitride material disposed between the porous region and the connection layer, which may preferably be the non-porous layer through which the electrochemical etching of the porous region is carried out.

[0049] The non-porous intermediate layer may preferably be one of GaN, InGaN, AlGaN, AlInGaN or AlN.

[0050] The porous region may be a porous layer, such that the light emitting diode comprises a porous layer of III-nitride material. Preferably, the porous region may be a continuously porous layer, for example formed from a continuous layer of porous III-nitride material.

[0051] The porous region may comprise multiple porous layers and, optionally, multiple non-porous layers. In preferred embodiments of the invention, the porous region is a stack of alternating porous and non-porous layers, with an upper surface of the stack defining an upper portion of the porous region and a lower surface of the stack defining a lower portion of the porous region. The light emitting region may be formed over the porous region comprising a stack of porous layers of III-nitride materials.

[0052] In some embodiments, the light emitting region is disposed on a stack of multiple porous layers of III-nitride material. Thus, rather than being a single porous layer of III-nitride material, the porous region may be a stack of layers of III-nitride material, at least some of which are porous. The stack of porous layers may preferably be a stack of alternating porous and non-porous layers.

[0053] Alternatively, the porous region may be a layer of III-nitride material that includes one or more porous regions, such as one or more porous regions within an otherwise non-porous layer of III-nitride material, in other words, the porous region need not be a continuous layer of porous material.

[0054] In preferred embodiments, the porous region or layer may have a lateral dimension (width or length) comparable to the lateral dimension of the substrate on which the porous layer or region is grown. For example, conventional substrate wafer sizes may have a variety of sizes, such as 1 cm, or 2-inch, 4-inch, 6-inch, 8-inch, 12-inch, or 16-inch diameters. However, smaller porous regions that do not span the entire substrate may also be formed by patterning one or more layers and / or depositing regions of different charge carrier concentrations in the same layer. Thus, the lateral dimensions of the porous layer or region may vary from about 1 / 10 of a pixel (e.g., 0.1 μm) to the lateral dimensions of the substrate itself.

[0055] The n-type doped portion preferably comprises an n-type doped Group III-nitride layer.

[0056] Preferably, the n-type doped portion and / or the n-type doped layer comprises n-GaN, or n-InGaN, or a stack of alternating layers of n-GaN / n-InGaN, or a stack of alternating layers of n-InGaN / n-InGaN with different concentrations of indium.

[0057] The n-type doped portion may comprise a single-crystalline n-type doped III-nitride portion, and preferably the n-type doped portion comprises a single-crystalline n-type doped III-nitride layer having a flat upper surface.

[0058] The porous region and each layer between the porous region and the single-crystal n-type doped III-nitride layer may be a planar layer having a respective upper surface and a respective lower surface parallel to the planar upper surface of the single-crystal n-type doped III-nitride layer.

[0059] The light emitting layer preferably comprises one or more InGaN quantum wells, preferably 1 to 7 quantum wells.

[0060] The light emitting layer may be a nanostructured layer of InGaN comprising quantum structures such as quantum dots, fragmented quantum wells, or discontinuous quantum wells.

[0061] The light emitting layer and / or quantum well preferably has a composition In x Ga 1-x N, and 0.07≦x≦0.35, preferably 0.12≦x≦0.30 or 0.22≦x≦0.30, particularly preferably 0.22≦x≦0.27.

[0062] The LED preferably comprises a III-nitride layer disposed on the light emitting layer, and a III-nitride barrier layer disposed on the III-nitride layer.

[0063] The III-nitride layer on the light-emitting layer may be referred to as a "capping layer," which is used to 1) increase the quantum-confined Stark effect for band bending and thus the red shift, resulting in longer wavelength emission, and 2) protect the high In % in InGaN to ensure that sufficient In % is incorporated to obtain the long wavelength and also provide a larger barrier.

[0064] The LED preferably comprises a cap layer of a III-nitride material between the quantum well and the p-doped region, which may be GaN, InGaN, AlGaN or AlN.

[0065] The LED preferably comprises a barrier layer of a III-nitride material between the quantum well and the p-doped region, which may be GaN, InGaN, AlGaN or AlN.

[0066] The p-type doped region may comprise a p-type doped Group III nitride layer and a p-type doped aluminum gallium nitride layer disposed between the p-type doped Group III nitride layer and the light emitting region. The p-type doped aluminum nitride layer is preferably an electron blocking layer (EBL) disposed between the cap layer and the p-type layer, the electron blocking layer containing 5-25 atomic % aluminum, and preferably having a thickness of 10-50 nm.

[0067] The light-emitting area and / or LED may have lateral dimensions (width and length) greater than 100 μm and less than 300 μm. In this case, the LED may be referred to as a "mini-LED." In preferred embodiments, the mini-LED may be square or circular, or square with circular corners, and may have dimensions of 300 μm x 300 μm, 200 μm x 200 μm, 100 μm x 100 μm, etc.

[0068] Alternatively, the light-emitting region and / or LED may have lateral dimensions (width and length) of less than 100 μm, in which case the LED may be referred to as a "micro-LED." Micro-LEDs may preferably have lateral dimensions of less than 80 μm, or 70 μm, or 60 μm, or 50 μm, or 30 μm, or 25 μm, or 20 μm, or 15 μm, or 10 μm, or 5 μm, or 3 μm, or 1 μm, or 500 nm, or 200 nm, or 100 nm, or 50 nm.

[0069] In preferred embodiments, the micro LEDs may be square or circular, or square with circular corners, and may have dimensions of 75 μm×75 μm, 50 μm×50 μm, 40 μm×40 μm, 30 μm×30 μm, 25 μm×25 μm, 20 μm×20 μm, or 10 μm×10 μm, or 5 μm×5 μm, or 2 μm×2 μm, or 1 μm×1 μm, or 500 nm×500 nm, or smaller.

[0070] The LEDs can be circular, square, rectangular, hexagonal, or triangular in shape. If the pixel design is irregular, at least one dimension must fall within the dimensions defined above in order for the LED to be classified as a mini LED or micro LED. For example, the width or diameter of the LED is preferably less than 100 μm for the LED to be classified as a micro LED.

[0071] At least one electrical interconnect layer may be disposed on a side of the LED structure closest to the n-type doped portion. The at least one electrical interconnect layer may be disposed to provide an electrical connection between one or more driver circuits and the n-type doped portion of each of the plurality of LEDs. The electrical interconnect layer may comprise a common cathode for each of the plurality of LEDs. Alternatively, the at least one electrical interconnect layer may be disposed on a side of the LED structure closest to the p-type doped portion. The at least one electrical interconnect layer may be disposed to provide an electrical connection between one or more of the driver circuits and the p-type doped portion of each of the plurality of LEDs. The electrical interconnect layer may comprise a common anode for each of the plurality of LEDs.

[0072] The optoelectron emitter assembly can be a laser assembly including a plurality of lasers, which can be a plurality of vertical cavity surface emitting lasers, and one, more, or each of the lasers can include a current confinement layer to increase carrier density.

[0073] The optoelectronic device may be provided in a display. The display may be a display screen which may comprise a plurality of pixels. The plurality of optoelectronic emitters may be arranged in an array, i.e. the plurality of optoelectronic emitters may be arranged in a grid or regular pattern.

[0074] In embodiments in which the optoelectronic emitters are LEDs, the plurality of LEDs may include at least one LED configured to emit light at red wavelengths, at least one LED configured to emit light at green wavelengths, and at least one LED configured to emit light at blue wavelengths. The plurality of LEDs may include multiple LEDs of each of these colors. A pixel of the optoelectronic device may include at least one red LED, at least one green LED, and at least one blue LED. The red LED may be larger than the green and blue LEDs.

[0075] Manufacturing method In a second aspect of the present invention, there is provided a method of manufacturing an optoelectronic device, which may comprise integrating an optoelectronic emitter assembly with a controller assembly comprising a plurality of driver circuits.

[0076] A second aspect of the present invention is a method of manufacturing an optoelectronic device, comprising the steps of: providing a photoelectron emitter assembly comprising a plurality of photoelectron emitters; providing a controller assembly comprising a plurality of driver circuits for supplying current to a plurality of photoelectron emitters; forming at least one electrical interconnect layer on the photoelectron emitter assembly and / or the controller assembly, the at least one electrical interconnect layer comprising at least one conductor layer and at least one insulator layer extending across at least a portion of the conductor layer; connecting the optoelectronic emitter assemblies and the controller assembly to one another via the electrical interconnect layer such that the electrical interconnect layer is disposed between the optoelectronic emitter assemblies and the controller assembly and provides an electrical connection between one or more of the driver circuits and each of the plurality of optoelectronic emitters; The present invention provides a method comprising:

[0077] The optoelectronic device of the first aspect of the present invention is preferably a device manufactured by the method of the second aspect of the present invention, and therefore any features described in relation to the first aspect are also applicable to the second aspect of the present invention, and vice versa.

[0078] In the method of the second aspect, the or at least one electrical interconnect layer may be formed on an optoelectronic emitter assembly. The or at least one electrical interconnect layer may be formed on a controller assembly.

[0079] The step of forming an interconnect layer includes: depositing a masking material; patterning the masking material; removing the patterned areas of the masking material; depositing a conductor layer material; Includes.

[0080] These steps may be performed in the order listed.The masking material may be an insulating layer.

[0081] Specific embodiments of the present invention will now be described with reference to the drawings. [Brief explanation of the drawings]

[0082] [Figure 1] FIG. 1 is a schematic cross-sectional view of a controller assembly for an optoelectronic device having an electrical interconnect layer, according to one embodiment of the present invention. [Figure 2] FIG. 2 is a schematic cross-sectional view of an LED assembly for an optoelectronic device having an electrical interconnect layer according to an embodiment of the present invention. [Figure 3] FIG. 3 is a schematic cross-sectional view of an LED assembly for an optoelectronic device having an electrical interconnect layer according to an embodiment of the present invention. [Figure 4] FIG. 4 is a schematic cross-sectional view of an optoelectronic device according to an embodiment of the present invention. [Figure 5] FIG. 5 is a schematic cross-sectional view of an optoelectronic device according to an embodiment of the present invention. [Figure 6] FIG. 6 is a schematic cross-sectional view of an optoelectronic device according to an embodiment of the present invention. [Figure 7] FIG. 7 is a schematic cross-sectional view of an LED for an optoelectronic device according to one embodiment of the present invention. [Figure 8] FIG. 8 is a flow chart illustrating a method of fabricating an optoelectronic device according to one embodiment of the present invention.

[0083] It will be understood that the figures in this application are schematic and that some features have been omitted for clarity. Furthermore, features in the drawings may not be drawn to scale. DETAILED DESCRIPTION OF THE INVENTION

[0084] The following detailed description and drawings provide examples of how the present invention may be implemented. They should not be considered limiting examples, but rather illustrations of how various features of electrical interconnect layers and other components of optoelectronic devices may be implemented. Other optional variations will become apparent from reading the following description in light of the drawings.

[0085] As used herein, an "electrical connection" may be a conductive path through which electrical current can flow. The electrical connection may be used to provide power to a light-emitting component, such as an LED.

[0086] FIG. 1 is a schematic diagram illustrating a controller assembly 1 including a controller for controlling multiple LEDs (not shown) in an optoelectronic device. The controller assembly 1 is configured to be connected to an optoelectronic emitter assembly, such as an LED assembly including multiple LEDs. For clarity, the LED assembly is omitted from FIG. 1 but is shown in FIGS. 2 and 3. The controller assembly 1 of FIG. 1 includes a substrate 60 having multiple driver circuits 70 disposed thereon or above it. The substrate 60 may be made of any suitable material, such as silicon, and may be part of a larger wafer including multiple controller assemblies. The multiple driver circuits 70 form part of the controller. While FIG. 1 shows only four driver circuits, it will be understood that in practice, the controller may include a much larger number of driver circuits, i.e., at least one driver circuit for each LED to be driven. In the example of FIG. 1, each driver circuit includes a CMOS device, and thus the controller is a CMOS-based controller. Electrical contacts 31 are disposed on or above each driver circuit 70, and several portions of insulating material 40 are disposed between each driver circuit 70.

[0087] The controller assembly 1 includes a redistribution layer (RDL) or electrical interconnect layer 100 formed on the controller assembly 1, i.e., above the plurality of driver circuits 70 and the electrical contacts 31. By being formed on the controller assembly 1, the electrical interconnect layer 100 has a microstructure indicative of having been formed, e.g., deposited, on the controller assembly 1. Any known thin film deposition method can be used for such a deposition step. Known material characterization methods can be used to determine that the electrical interconnect layer 100 has been formed on the controller assembly 1. Such known methods can include, for example, electron microscopy and defect identification. The electrical interconnect layer 100 may have been formed using the fabrication methods described herein.

[0088] The electrical interconnect layer 100 is configured to provide an electrical connection between one or more of the driver circuits 70 and each of a plurality of LEDs (not shown). Specifically, when a controller assembly is connected to an LED assembly having a plurality of LEDs, the electrical interconnect layer 100 is disposed between the LED assembly and the controller assembly, and the electrical interconnect layer 100 is configured to provide an electrical connection between one or more of the driver circuits 70 and each of the plurality of LEDs. When a controller assembly is connected to an LED assembly having a plurality of LEDs, the electrical interconnect layer 100 may connect at least one LED to the plurality of driver circuits 70. The electrical connection between the driver circuit 70 and the LEDs is made by the conductor layers 110, 130 of the electrical interconnect layer 100.

[0089] 1 shows four driver circuits 70 electrically connected to each other and configured to connect to the LEDs using the electrical interconnect layer 100. However, it will be understood that any suitable number of multiple driver circuits 70, such as two, three, four, or more driver circuits 70, may be electrically connected to each other for connection to the LEDs using the electrical interconnect layer 100. By electrically connecting multiple driver circuits 70, a greater power output can be provided to the LEDs. For example, two driver circuits 70 can provide a greater current to the LEDs than a single driver circuit 70.

[0090] 1 has a controller-facing surface 101 electrically connected to a plurality of driver circuits 70 via electrical contacts 31. Specifically, each driver circuit 70 is connected to a corresponding electrical contact 31, which is then connected to the controller-facing surface 101 of the electrical interconnect layer 100. It will be appreciated that the controller-facing surface 101 may alternatively be configured to directly connect to one or more driver circuits 70. At least one controller-facing surface 101 may be substantially flat.

[0091] The electrical interconnect layer 100 of FIG. 1 includes interconnect contacts 102. The interconnect contacts 102 are configured to electrically connect to the LEDs when the LED assembly and the controller assembly 1 are connected to each other via the electrical interconnect layer 100. The interconnect contacts 102 may be substantially planar. The interconnect contacts 102 are distal, specifically, on the most distal surface, from the driver circuit 70. It will be appreciated that there may be multiple interconnect contacts 102. It will also be appreciated that the interconnect contacts 102 do not have to be on the most distal or distal surface from the driver circuit 70.

[0092] The electrical interconnect layer 100 in FIG. 1 has a connection area on its controller-facing surface 101 that is larger than the electrical contact area of ​​each driver circuit 70 to which it is connected. The connection area in FIG. 1 is also larger than the electrical contact areas of the multiple driver circuits 70 to which the electrical interconnect layer 100 is connected. In other words, the connection area on the controller-facing surface 101 of the electrical interconnect layer is sufficient to span multiple driver circuits 70. This allows multiple driver circuits 70 to be connected to an LED. In the embodiment shown in FIG. 1 , four driver circuits 70 can be connected to a single LED by contacting the interconnect contacts 102 to an LED assembly having the LED. In this configuration, current from the four driver circuits 70 can be supplied to a single LED.

[0093] 1, the interconnect contacts 102 are laterally offset from the location of each driver circuit 70 to which they are connected. Specifically, the horizontal locations of the interconnect contacts 102 are different from the horizontal locations of the driver circuits 70. This has the effect of enabling the driver circuits 70 to be electrically connected to LEDs that are located at different lateral locations than the driver circuits 70. In other words, this provides greater flexibility in the design of the optoelectronic device.

[0094] The electrical interconnect layer 100 comprises multiple conductor layers, namely, a first conductor layer 110 and a second conductor layer 130, with an insulator layer 140 extending across at least a portion of the first conductor layer 110, i.e., between the first conductor layer 110 and the second conductor layer 130. Conductive vias 120 are disposed within through holes 105 in the insulator layer 140 and provide electrical connections between the first conductor layer 110 and the second conductor layer 130. The second conductor layer 130 is patterned by etching away portions of the second conductor layer 130 to form interconnect contacts 102. Although not shown in FIG. 1 , the first conductor layer 110 may also be patterned to provide electrical interconnections between any suitable number and arrangement of driver circuits 70. The insulator layer 140 supports the second conductor layer 130 and provides electrical insulation between the first conductor layer 110 and the second conductor layer 130, except where the conductive vias 120 penetrate the insulator layer 140. The insulator layer 140 may also be patterned to provide electrical interconnections between the first conductor layer 110 and the second conductor layer 130 at desired locations.

[0095] The conductor layers 110, 130 may include at least one of a metal, a metal alloy, and indium tin oxide. The metal or metal alloy may be or include one or more of titanium, platinum, chromium, aluminum, nickel, and gold. The insulator layer 140 may include a dielectric, preferably one or more of SiO2, SiN, or SiNx, or a polymer such as polyimide.

[0096] Although the electrical interconnect layer may be formed on the controller assembly as shown in FIG. 1, the electrical interconnect layer may additionally or alternatively be formed on the LED assembly. FIG. 2 shows a schematic diagram of an LED assembly 2 having an electrical interconnect layer 200 disposed thereon. The LED assembly 2 may be combined with a controller assembly including multiple driver circuits to provide an optoelectronic device. For clarity, the controller assembly is omitted from FIG. 2.

[0097] The LED assembly 2 of FIG. 2 includes a substrate 10, which may be part of a larger carrier wafer that includes multiple LED assemblies. The substrate 10 may be made of any suitable material; for example, the substrate may be made of a transparent material such as sapphire. A plurality of LEDs 20 are disposed on or above the substrate 10. In the embodiment of FIG. 2, the LEDs 20 are substantially identical to one another in terms of cross-sectional shape and size. The LEDs 20 may be substantially identical to one another in terms of three-dimensional shape, three-dimensional size, material composition, chemical composition, layer structure, and / or range of light wavelengths emitted at a particular applied voltage. The LEDs 20 of FIG. 2 are arranged in a regular array. The LEDs 20 are arranged with equal gaps between them, and the LEDs 20 are laterally connected by an insulator layer 40.

[0098] Each LED 20 in Figure 2 has an electrical contact 30. Each electrical contact 30 has substantially the same lateral dimension or area as the LED 20 to which it is attached. It will be appreciated that the electrical contacts 30 may have different lateral dimensions or areas than the LEDs 20 to which they are connected. Alternatively, the electrical interconnect layer 200 may be directly connected to each LED 20.

[0099] The electrical interconnect layer 200 comprises a conductor layer 212 and an insulator layer 40. The insulator layer 40 extends down to the substrate 10, filling the spaces between the LEDs 20 and electrically insulating each LED 20. The insulator layer 40 is patterned to provide a plurality of through holes 45 in the area of ​​the LEDs 20, through which the conductor layer 212 extends to form conductive vias 211, allowing electrical interconnection between the LEDs 20 and the conductor layer 212.

[0100] The conductor layer 212 is patterned, and some portions of the conductor layer 212 are etched away so that only some sections of the conductor layer 212 remain. Each section of the conductor layer 212 of the electrical interconnect layer 200 includes an LED-facing surface 201 and an interconnect contact 202. Each interconnect contact 202 is electrically connected to a respective one of the plurality of LEDs 20. Each interconnect contact 202 is configured to electrically connect to one or more driver circuits with the electrical interconnect layer 200 disposed therebetween when the LED assembly is connected to a controller assembly (not shown). Each interconnect contact 202 has a connection area larger than the electrical contact area of ​​the LED 20. In this manner, the conductor layer 212 includes a plurality of interconnect contacts 202 for connection to one or more driver circuits 70, and each interconnect contact 202 is connected to a respective one of the plurality of LEDs 20 and has a connection area larger than the electrical contact area of ​​the LED 20. An advantage of each interconnect contact 202 having a connection area larger than the electrical contact area of ​​the LED 20 to be connected is that the LED 20 can be more easily connected to the driver circuit 70. When a bonding process is used to connect the LEDs 20, the yield of the bonding process can be increased as a result of the interconnect contacts 202 having a larger area than their corresponding LEDs. In such a bonding process, the interconnect contacts 202 form an interface between the LEDs 20 and the components to which they are connected, such as a driver circuit. In particular, they form a connection or bonding surface to which a controller assembly can be connected.

[0101] 2, the interconnect contacts 202 are arranged in an array such that each interconnect contact 202 overlies and is aligned with its corresponding LED in the array of underlying LEDs 20. However, electrical interconnect layer 200 may additionally or alternatively have an arrangement in which each interconnect contact is not aligned with its underlying LED, i.e., at least some of the interconnect contacts are laterally offset from their underlying LED. Such an arrangement is shown in FIG.

[0102] FIG. 3 is a schematic diagram illustrating an LED assembly 3 having an electrical interconnect layer 300 disposed thereon. The LED assembly 3 can be combined with a controller assembly including multiple driver circuits to provide an optoelectronic device. The LED assembly 3 of FIG. 3 has substantially the same structure as the LED assembly 2 of FIG. 2, except that the electrical interconnect layer 300 includes two conductor layers: a first conductor layer 332 and a second conductor layer 334. Similar reference numerals are used in FIGS. 2 and 3 to refer to components common to both figures. The second conductor layer 334 of the electrical interconnect layer 302 is patterned by etching away portions of the layer to form multiple interconnect contacts 302. The use of two conductor layers in the electrical interconnect layer 300 allows for the position, size, and spacing of the interconnect contacts 302 relative to their corresponding LEDs 20 to be varied. It will be appreciated that electrical interconnect layer 300 may have more than two conductor layers, for example, electrical interconnect layer 300 may have three, four, five or more conductor layers, and indeed any suitable number of conductor layers may be used.

[0103] In the embodiment of FIG. 3 , the electrical interconnect layer 300 includes a first insulator layer 40 disposed on or above the LEDs 20 and between the LEDs and a first conductor layer 332. The first insulator layer 40 extends down to the substrate 10, filling the spaces between the LEDs 20 and electrically insulating them. The first insulator layer 40 is patterned to provide a plurality of through-holes 45 in the area of ​​the LEDs 20, through which the first conductor layer 332 extends to form conductive vias 331. The first conductor layer 332 is patterned by etching away portions of the first conductor layer 332 to form a plurality of interconnect portions 335 extending laterally within the plane of the first conductor layer 332. The interconnect portions 335 can extend on either side of their corresponding conductive vias 331, as shown, for example, for the interconnect portion 335 connected to the middle LED 20 in FIG. 3 . Alternatively, the interconnect portions 335 can extend on one side of their corresponding conductive vias 331, as shown, for example, for the interconnect portions 335 connected to the leftmost and rightmost LEDs 20 in FIG. 3. Furthermore, the interconnect portions 335 can extend different distances on one side of their corresponding conductive vias 331. Multiple interconnect portions 335 are electrically connected to their corresponding LEDs by the conductive vias 331. Portions of dielectric material 41 are disposed between the interconnect portions 335 to electrically insulate the interconnect portions from one another.

[0104] The electrical interconnect layer 300 of FIG. 3 further includes a second insulator layer 42 disposed on or above the first conductor layer 332 and between the first conductor layer 332 and the second conductor layer 334. The second insulator layer 42 is patterned to provide a plurality of through-holes 45 in the region of the interconnect portions 335, through which the second conductor layer 334 extends to form conductive vias 333. As described above, the second conductor layer 334 is patterned by etching away portions of the layer to form a plurality of interconnect contacts 302. The interconnect contacts 302 are electrically connected to their corresponding interconnect portions 335 of the first conductor layer 332 by the conductive vias 333. Thus, an electrical path is established between the interconnect contacts 302 and the electrical contacts of each LED 20 through the conductive vias 333, the interconnect portions 335, and the conductive vias 331.

[0105] As described above, conductive vias 333 are formed in the region of the interconnect portion 335. The conductive vias 333 may be aligned with the underlying conductive vias 335 and LEDs 20, for example, as shown for the conductive vias 333 connected to the middle LED 20 in FIG. 3 . In this arrangement, the interconnect contacts 302 are substantially aligned with their underlying LEDs 20. Alternatively, the conductive vias 333 may be laterally offset from their corresponding underlying conductive vias 335 and LEDs 20, for example, as shown for the conductive vias 333 connected to the leftmost and rightmost LEDs 20 in FIG. 3 . In this arrangement, the interconnect contacts 302 are laterally offset from their corresponding underlying LEDs, and the interconnect portion 335 of the first conductor layer 332 provides an electrical connection over the distance the conductive vias are offset, i.e., provides an electrical connection between the conductive vias 331 and their corresponding laterally offset conductive vias 333. Laterally offsetting the interconnect contacts 302 from their corresponding LEDs 20 means that connections to the LEDs 20 are not limited to the actual location of the LEDs 20, but rather the interconnect contacts 302 can be spread out to provide more space between the interconnect contacts 302 compared to the space between the LEDs 20, allowing for more freedom in the design of the display.

[0106] 4 is a schematic diagram of an optoelectronic device 4. The optoelectronic device 4 comprises an LED assembly 11 comprising a plurality of LEDs 20, and a controller assembly 13 comprising a plurality of driver circuits 70 for supplying current to the plurality of LEDs 20.

[0107] The LED assembly 11 of FIG. 4 may be fabricated in the orientation described in FIGS. 2 and 3 , i.e., by forming layers of materials on the substrate 10. The controller assembly 13 of FIG. 4 may be fabricated in the orientation described in FIG. 1 , i.e., by forming layers of materials on the substrate 60. To obtain the optoelectronic device 4 of FIG. 4 , the LED assembly 11 is flipped 180 degrees from an orientation in which the substrate 10 is below the LED assembly 11 to an orientation in which the substrate 10 is above the LED assembly 11. After the LED assembly 11 is flipped, it is aligned with, placed above, and fixedly attached to the controller assembly 13, with the electrical interconnect layers disposed between the LED assembly 11 and the controller assembly 13. It will be appreciated that instead of flipping the LED assembly 11, the controller assembly 13 may be flipped from an orientation in which the substrate 60 is below the controller assembly 13 to an orientation in which the substrate 60 is above the controller assembly 13, in order to overlay the controller assembly 13 on top of the LED assembly 11 when the assemblies are connected to form the optoelectronic device.

[0108] In the embodiment of FIG. 4, the optoelectronic device 4 comprises a first electrical interconnect layer 410 and a second electrical interconnect layer 400 .

[0109] The first electrical interconnect layer 410 is formed on the LED assembly 11 including the LEDs 20. The first electrical interconnect layer 410 has a structure similar to that of the electrical interconnect layer shown in FIG. 2. The first electrical interconnect layer 410 includes an insulator layer 440 and a conductor layer 411. The conductor layer 411 is patterned by etching away specific portions of the conductor layer 411 to leave only certain sections of the conductor layer 411. The sections of the conductor layer 411 provide a plurality of first interconnect contacts 412 for connection to one or more driver circuits 70 of the controller assembly 13 when the LED assembly 11 and the controller assembly 13 are connected. Each of the first interconnect contacts 412 is electrically connected to a respective one of the plurality of LEDs 20 through a through-hole 445 formed in the insulator layer 440. The sections of the first electrical interconnect layer 410 are substantially identical in shape, size, orientation, and material composition.

[0110] The second electrical interconnect layer 400 is formed on the controller assembly 13, which includes the plurality of driver circuits 70. The second electrical interconnect layer 400 includes a patterned conductor layer 403 that is etched away to leave sections 405, 406, and 407 of the conductor layer 411, which provide a plurality of second interconnect contacts 402. The second interconnect contacts 402 are configured to connect one or more of the driver circuits 70 of the controller assembly 13 to each LED of the LED assembly 11 when the LED assembly 11 and the controller assembly 13 are connected. Each of the second interconnect contacts 402 shown in FIG. 4 has a connection area larger than the electrical contact area of ​​the driver circuit 70. Two of the interconnect contacts 402 each have a connection area larger than the electrical contact area of ​​the plurality of driver circuits 70. The second electrical interconnect layer 400 may also include an insulator layer (not shown). In another example, the second electrical interconnect layer 400 may have a structure similar to that of the controller assembly of FIG. 1.

[0111] While the first and second electrical interconnect layers 400, 410 shown in FIG. 4 are separated by a gap for clarity, it will be understood that in the assembled optoelectronic device, they contact each other and are fixedly attached, i.e., bonded, to each other. When connected, the first and second electrical interconnect layers 400, 410 collectively form an electrical connection between one or more of the driver circuits 70 and each of the plurality of LEDs 20. When the LED assembly 11 and the controller assembly 13 are assembled together to form the optoelectronic device, the LED assembly 11 and the controller assembly 13 are aligned such that the position of each of the first interconnect contacts 412 is the same as the corresponding position of each of the second interconnect contacts 402. This enables the formation of an electrical connection between the first and second electrical interconnect layers 410, 400.

[0112] The LED assembly 11 shown in FIG. 4 differs from the LED assemblies shown in FIGS. 2 and 3 in that it includes multiple LEDs 20 of different sizes. Specifically, the LED assembly includes a first LED 20a, a second LED 20b, and a third LED 20c, all of which have different lateral areas, i.e., areas when viewed in a plan view. The third LED 20c is larger than the first LED 20a, and the second LED 20b is larger than the third LED 20c. The first LED 20a may be a blue LED, i.e., may emit light in a blue wavelength range. The second LED 20b may be a red LED, i.e., may emit light in a red wavelength range. The third LED 20c may be a green LED, i.e., may emit light in a green wavelength range.

[0113] The first LED 20a is connected to four driver circuits 70 via the electrical interconnect layers 400, 410. The second LED 20b is connected to one driver circuit 70 via the electrical interconnect layers 400, 410. The third LED 20c is connected to four driver circuits 70 via the electrical interconnect layers 400, 410. This difference in the number of driver circuits connected to each LED can be easily achieved by varying the sizes of the different sections 405, 406, 407 of the conductor layer 403 of the second electrical interconnect layer 400. The first section 405 of the second electrical interconnect layer 400, which is on the left in FIG. 4, connects four driver circuits 70 to the first LED 21. The second section 406 of the second electrical interconnect layer 400, which is in the middle in FIG. 4, connects one driver circuit 70 to the second LED 22. 4 of the second electrical interconnect layer 400 connects four driver circuits 70 to the third LED 23. By connecting different numbers of driver circuits 70 to individual LEDs 20, the amount of current supplied to the LEDs can be varied, such that LEDs 20 connected to multiple driver circuits 70 receive more current than LEDs 20 connected to a single driver circuit 70. This allows the LED's light emission characteristics, such as brightness and wavelength, to be customized.

[0114] Figure 5 is a schematic diagram of an optoelectronic device 5. The optoelectronic device 5 includes an LED assembly 15 including a plurality of LEDs 20 and a controller assembly 16 including a plurality of driver circuits 70 for supplying current to the plurality of LEDs 20 via an electrical interconnect layer 500. The substrate 10 and the first, second, and third LEDs 20a, 20b, and 20c are the same as the substrate 10 and the first, second, and third LEDs 20a, 20b, and 20c described in connection with Figure 4. Similar reference numbers are used in Figures 4, 5, and 6 to refer to components common to both figures.

[0115] The electrical interconnect layer 500 is formed on the LED assembly 15, which includes the LEDs 20. The electrical interconnect layer 500 forms electrical connections between one or more of the driver circuits 70 and each of the plurality of LEDs 20. The electrical interconnect layer 500 includes an insulator layer 540 and a conductor layer 511. The conductor layer 511 is patterned by etching away certain portions to leave sections 505, 506, and 507 of the conductor layer 511. The sections 505, 506, and 507 of the conductor layer 511 each define an interconnect contact 512. In the embodiment of FIG. 5, each interconnect contact 512 has a connection area larger than the electrical contact area of ​​the driver circuit 70 to which it connects. In the embodiment of FIG. 5, the interconnect contacts 512 of the first and third sections 505 and 507 have a connection area larger than the electrical contact areas of the plurality of driver circuits 70 to which they connect. The first LED 20a is connected to four driver circuits 70 via a first section 505 of the conductor layer 511 of the electrical interconnect layer 500. The second LED 20b is connected to one driver circuit 70 via a second section 506 of the conductor layer 511 of the electrical interconnect layer 500. The third LED 20c is connected to four driver circuits 70 via a third section 507 of the conductor layer 511 of the electrical interconnect layer 500.

[0116] Each driver circuit 70 is connected to an electrical contact 411 that electrically connects to the electrical interconnect layer 500. Each electrical contact 411 has a larger lateral dimension than the driver circuit 70 it connects to. The electrical contacts 411 may be identical to one another with respect to shape, size, orientation, and material composition. It will be appreciated that the electrical contacts 411 may comprise interconnect contacts of a separate electrical interconnect layer formed on the controller assembly 16. The electrical interconnect layer may further comprise an insulator layer. It will be appreciated that, alternatively, each driver circuit 70 may be directly connected to the electrical interconnect layer 500.

[0117] Figure 6 is a schematic diagram of an optoelectronic device 6 including an LED assembly 15 having a plurality of LEDs 20 and a controller assembly 13 having a plurality of driver circuits 70 for supplying current to the plurality of LEDs 20. The LED assembly 15 of Figure 6 is the same as the LED assembly 15 of Figure 5, and includes a first electrical interconnect layer 500 formed on the LED assembly 15. The controller assembly 13 of Figure 6 is the same as the controller assembly 13 of Figure 4, and includes a second electrical interconnect layer 400 formed on the controller assembly 13.

[0118] The first and second electrical interconnect layers 500, 400 form electrical connections between one or more of the driver circuits 70 and each of the plurality of LEDs 20. The first electrical interconnect layer 500 has a first section 505, a second section 506, and a third section 507, each defining an interconnect contact 512. The sections 505, 506, and 507 and the interconnect contacts 512 of the first electrical interconnect layer 500 are as described in connection with FIG. 5. The second electrical interconnect layer 400 has a first section 405, a second section 406, and a third section 407, each defining an interconnect contact 402. The sections 405, 406, and 407 of the second electrical interconnect layer 400 are as described in connection with FIG. 4.

[0119] The size and location of the interconnect contacts 512 of the first electrical interconnect layer 500 match the size and location of the interconnect contacts 402 of the second electrical interconnect layer 400. The interconnect contacts 402 provided by the first section 405 of the second electrical interconnect layer 400 connect four driver circuits 70 to the interconnect contacts 512 provided by the first section 505 of the first electrical interconnect layer 500 that is connected to the first LED 20 a. The interconnect contacts 402 provided by the second section 406 of the second electrical interconnect layer 400 connect one driver circuit 70 to the interconnect contact 512 provided by the second section 506 of the first electrical interconnect layer 500 that is connected to the second LED 20 b. Interconnect contacts 402 provided by the third section 407 of the second electrical interconnect layer 400 connect the four driver circuits 70 to interconnect contacts 512 provided by the third section 507 of the first electrical interconnect layer 500, which are connected to the third LED 20c.

[0120] While a single pixel having one red, one green, and one blue LED is shown in Figures 4-6, it will be understood that the LED assembly can include a much larger number of LEDs 20 and the controller assembly can include a much larger number of driver circuits 70. It will also be understood that an electrical interconnect layer appropriately formed on the LED assembly or controller assembly of Figures 4-6 can have a much larger number of interconnect contacts.

[0121] The LEDs described herein can be fabricated according to any suitable method. An example of a method for fabricating an LED assembly described herein is shown in FIG. 7. FIG. 7 is a schematic diagram of an LED assembly having a substrate, a porous region, a connecting layer 1001, an n-type doped portion 1002, a light-emitting region 1003, an n-type doped cap layer 1004, a p-type doped portion 1006, a transparent conductive layer 1007, a passivation layer 1008, an electrical p-type contact 1009, and an electrical n-type contact 1010. The porous region may be a porous region of a III-nitride material. The LED may be constructed or fabricated to have any of the features of WO 2022 / 029434. In the LED of FIG. 7, the electrical interconnect layer would be located on the anode or p-type doped portion side of the LED. However, it will be understood that the electrical interconnect layer may be located on the cathode or n-type doped portion side of the LED.

[0122] A method for manufacturing an optoelectronic device is shown in the flow chart of Figure 8. In a first step 71, the method includes providing an LED assembly comprising a plurality of LEDs. The provided LED assembly may be as described in relation to any of Figures 2 to 7.

[0123] In a second step 72, the method includes providing a controller assembly comprising a controller, the controller having a plurality of driver circuits for supplying current to a plurality of LEDs of the LED assembly. The provided controller assembly may be as described in relation to any of Figures 1 and 4-6.

[0124] In a third step 73, the method includes forming at least one electrical interconnect layer on the LED assembly and / or the controller assembly, the at least one electrical interconnect layer comprising at least one conductor layer and at least one insulator layer extending across at least a portion of the conductor layer.

[0125] In a fourth step 74, the method includes connecting the LED assembly and the controller assembly to each other via one or more electrical interconnect layers such that one or more electrical interconnect layers are disposed between the LED assembly and the controller assembly and provide electrical connections between one or more of the driver circuits and each of the plurality of LEDs.

[0126] It will be appreciated that the method does not have to be performed in the order of steps shown in Figure 8. In particular, the first step 71 through the third step 73 may be performed in any suitable order.

[0127] Before the fourth step 74, the LED assembly or the controller assembly may be flipped from the orientation in which it was manufactured to the orientation in which it will be assembled into the optoelectronic device.

[0128] The third step 73 of forming the electrical interconnect layer may include depositing a masking material, patterning the masking material, removing the patterned areas of the masking material, and depositing a conductor layer material. The masking material may be a polymer that is completely removed from the resulting optoelectronic device, or it may be an insulator layer of the electrical interconnect layer. For example, referring to FIG. 2, the masking material may be an insulator 40 that has been selectively etched to define areas where the conductive vias 211 will be deposited. Referring to FIG. 3, the masking material may be a first or second insulator layer 40, 42, where areas in the first or second insulator layer, i.e., through-holes 45, are selectively etched to define areas where the conductive vias 331, 333 will be deposited. In this configuration, the insulator layer extends across at least a portion of the conductor layer.

[0129] It will be appreciated that there are a variety of suitable methods for manufacturing the optoelectronic devices described herein.

Claims

1. a photoelectron emitter assembly comprising a plurality of photoelectron emitters; a controller assembly comprising a plurality of driver circuits for supplying current to the plurality of photoelectron emitters; at least one electrical interconnect layer disposed between the optoelectronic emitter assembly and the controller assembly, the at least one electrical interconnect layer configured to provide an electrical connection between one or more of the driver circuits and each of the plurality of optoelectronic emitters; An optoelectronic device comprising: An optoelectronic device, wherein the at least one electrical interconnect layer comprises at least one conductor layer and at least one insulator layer extending across at least a portion of the conductor layer.

2. 10. The optoelectronic device of claim 1, wherein said at least one electrical interconnect layer has a connection area that is larger than an electrical contact area of ​​said optoelectronic emitter or said driver circuit to which said at least one electrical interconnect layer is connected.

3. 3. An optoelectronic device according to claim 1 or 2, wherein the conductor layer comprises a plurality of interconnect contacts.

4. 4. The optoelectronic device of claim 3, wherein said at least one interconnect contact has a connection area that is larger than an electrical contact area of ​​said optoelectronic emitter or said driver circuit to which said at least one interconnect contact is connected.

5. 5. An optoelectronic device according to claim 3 or 4, wherein the position of said at least one interconnect contact is laterally offset from the position of said optoelectronic emitter or said driver circuit to which said at least one interconnect contact is connected.

6. The optoelectronic device of any one of claims 1 to 5, wherein at least one said optoelectronic emitter is connected to a plurality of driver circuits via said electrical interconnect layer.

7. The optoelectronic device of claim 1 , wherein the electrical interconnect layer is formed on the optoelectron emitter assembly comprising the plurality of optoelectron emitters.

8. 8. The optoelectronic device of claim 7, wherein the conductor layer comprises a plurality of interconnect contacts for connection to one or more driver circuits, each of the interconnect contacts being connected to a respective one of the plurality of photoelectron emitters and having a connection area greater than an electrical contact area of ​​the photoelectron emitter.

9. 8. The optoelectronic device of claim 7, wherein at least one interconnect contact has a connection area that is greater than an electrical contact area of ​​the driver circuit.

10. 10. The optoelectronic device of claim 9, wherein the at least one interconnect contact has a connection area that is greater than the electrical contact areas of a plurality of driver circuits.

11. 11. The optoelectronic device of claim 7, wherein the insulator layer is disposed between the plurality of photoelectron emitters and the plurality of interconnect contacts, and has a plurality of through holes that allow electrical interconnection between the plurality of photoelectron emitters and the plurality of interconnect contacts.

12. 8. The optoelectronic device of claim 7, wherein the electrical interconnect layer comprises a first conductor layer and a second conductor layer, the second conductor layer comprising a plurality of interconnect contacts for connection to one or more driver circuits, the first conductor layer being disposed between the second conductor layer and the plurality of optoelectron emitters, each of the interconnect contacts being connected to a respective one of the plurality of optoelectron emitters through the first conductor layer.

13. The optoelectronic device of claim 12 , wherein at least one interconnect contact is laterally offset from its corresponding optoelectron emitter.

14. 14. The optoelectronic device of claim 12 or 13, wherein a first insulator layer and a second insulator layer are respectively disposed between the first conductor layer and the second conductor layer and between the second conductor layer and the plurality of photoemitters, and the first insulator layer and the second insulator layer have a plurality of through holes that allow electrical interconnection between the plurality of photoemitters, the second conductor layer and the plurality of interconnect contacts.

15. The optoelectronic device of claim 1 , wherein the electrical interconnect layer is formed on the controller assembly that includes the plurality of driver circuits.

16. 16. The optoelectronic device of claim 15, wherein the conductor layer comprises a plurality of interconnect contacts for connecting to each optoelectron emitter in the plurality of optoelectron emitters, each of the interconnect contacts being connected to one or more of the driver circuits.

17. 17. The optoelectronic device of claim 16, wherein at least one interconnect contact has a connection area that is greater than an electrical contact area of ​​the driver circuit.

18. 17. The optoelectronic device of claim 16, wherein at least one interconnect contact has a connection area that is greater than the electrical contact areas of a plurality of driver circuits.

19. 10. The optoelectronic device of claim 1, wherein a first electrical interconnect layer is formed on the optoelectron emitter assembly comprising the optoelectron emitters, and a second electrical interconnect layer is formed on the controller assembly comprising the plurality of driver circuits.

20. 20. The optoelectronic device of claim 19, wherein the first electrical interconnect layer comprises a first conductor layer having a plurality of first interconnect contacts for connecting to one or more driver circuits, each of the first interconnect contacts connected to a respective one of the plurality of optoelectron emitters, and the second electrical interconnect layer comprises a second conductor layer having a plurality of second interconnect contacts for connecting to a respective optoelectron emitter in the plurality of optoelectron emitters, each of the second interconnect contacts connected to one or more of the driver circuits, and wherein a connection area and position of each of the first interconnect contacts is the same as a connection area and position of a corresponding one of the second interconnect contacts.

21. An optoelectronic device according to any preceding claim, wherein at least one of the plurality of driver circuits comprises a CMOS driver circuit.

22. An optoelectronic device according to any preceding claim, wherein the conductor layer comprises at least one of a metal, a metal alloy, indium tin oxide, and graphene.

23. 23. The optoelectronic device of claim 22, wherein the metal or metal alloy is or includes one or more of titanium, platinum, chromium, aluminum, nickel, and gold.

24. The insulator layer is a dielectric material, preferably SiO ２ 24. An optoelectronic device according to any preceding claim, comprising one or more of the following: SiN or SiNx.

25. An optoelectronic device according to any preceding claim, wherein the optoelectronic emitter assembly is an LED assembly comprising a plurality of LEDs.

26. At least one of the plurality of LEDs an n-type doped portion; a p-type doped portion; a light emitting region disposed between the n-type doped portion and the p-type doped portion; a porous region of a Group III nitride material; 26. The optoelectronic device of claim 25, comprising:

27. An optoelectronic device according to any one of the preceding claims, wherein the optoelectronic emitter assembly is a laser assembly comprising a plurality of lasers.

28. 30. The optoelectronic device of claim 27, wherein the plurality of lasers are a plurality of vertical cavity surface emitting lasers.

29. A display comprising an optoelectronic device according to any one of claims 1 to 28.

30. 1. A method of manufacturing an optoelectronic device, comprising: providing a photoelectron emitter assembly comprising a plurality of photoelectron emitters; providing a controller assembly comprising a plurality of driver circuits for supplying current to the plurality of photoelectron emitters; forming at least one electrical interconnect layer on the photoelectron emitter assembly and / or the controller assembly, the at least one electrical interconnect layer comprising at least one conductor layer and at least one insulator layer extending across at least a portion of the conductor layer; connecting the optoelectronic emitter assemblies and the controller assembly to one another via the electrical interconnect layer such that the electrical interconnect layer is disposed between the optoelectronic emitter assemblies and the controller assembly and provides an electrical connection between one or more of the driver circuits and each of the plurality of optoelectronic emitters; A method comprising:

31. 31. The method of claim 30, wherein the at least one electrical interconnect layer is formed on the optoelectron emitter assembly.

32. 32. The method of claim 30 or 31, wherein the at least one electrical interconnect layer is formed on the controller assembly.

33. The step of forming the interconnect layer comprises: depositing a masking material; patterning the masking material; removing the patterned areas of the masking material; depositing a conductor layer material; The method of any one of claims 30 to 32, comprising:

34. 34. The method of claim 33, wherein the masking material comprises the insulating layer.

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