Multi-chip memory system including DRAM chips with integrated comparator arrays and method of operation thereof

Abstract

A memory system includes a first chip having a first processor and a second chip having a DRAM sector, the DRAM sector including a plurality of DRAM arrays, an output circuit for storing a plurality of data values ​​read from the DRAM arrays, a first set of through-silicon vias (TSVs) connecting the first processor to the first DRAM sector and transmitting a first plurality of weighted data values ​​from the first processor to the first DRAM sector, a plurality of comparator arrays coupled to receive the plurality of weighted data values ​​and the plurality of data values ​​read from the DRAM arrays and to generate a plurality of comparison output values ​​in response thereto, and a second set of TSVs connecting the first processor to the first DRAM sector and transmitting the first plurality of comparison output values ​​from the first DRAM sector to the first processor.

Description

[Technical Field]

[0001] (CROSS-REFERENCE TO RELATED APPLICATIONS) This application claims priority to U.S. Non-provisional Patent Application No. 18 / 509,056, filed November 14, 2023, by Richard Stephen Roy, entitled "Multi-chip Memory System Including DRAM Chips with Integrated Comparator Arrays and Methods of Operation Thereof," and U.S. Provisional Patent Application No. 63 / 383,961, filed November 16, 2022, by Richard Stephen Roy, entitled "DRAM Architecture with On-Chip Comparators and Related Methods."

[0002] The present disclosure relates generally to semiconductor devices, and more particularly to semiconductor memory devices configured to perform comparison operations. [Background technology]

[0003] Machine learning and artificial intelligence (AI) rely on the ability to quickly perform large numbers of comparison operations. For example, facial recognition applications are performed by comparing streaming video image data with known facial image data. Therefore, it is desirable to have circuits and methods for quickly and efficiently performing large numbers of comparison operations.

[0004] Dynamic random access memory (DRAM) is often used to store data values ​​used in comparison operations. One of the key requirements for DRAM (Dynamic Random Access Memory) devices is the ability to retain data while in an inactive state, with minimal power consumption. This power consumption comes from the need to refresh the data stored in the bit cells of selected parts of the memory, as well as leakage in other peripheral circuitry. The specification for such refresh is called IDD6, which directly affects the battery life of devices such as smartphones and laptops after a charge. Another important parameter for DRAM devices is latency. Latency refers to the delay between selecting a random location in the memory device and the selected data reaching the output.

[0005] One particularly advantageous memory device is disclosed in U.S. Patent No. 7,659,539 to Kreps et al., which is assigned to the present assignee and incorporated herein by reference in its entirety. This patent discloses a semiconductor device including a semiconductor substrate and at least one nonvolatile memory cell. The at least one nonvolatile memory cell may include a superlattice channel including spaced-apart source and drain regions and a group of layers stacked on the semiconductor substrate between the source and drain regions. Each of the group of layers of the superlattice channel may include a plurality of stacked base semiconductor monolayers defining a base semiconductor portion and an energy band-modifying layer disposed thereon, and may include at least one non-semiconductor monolayer constrained within the crystal lattice of an adjacent base semiconductor portion. A floating gate may be adjacent to the superlattice channel, and a control gate may be adjacent to a second gate insulating layer.

[0006] An advantageous DRAM architecture is disclosed in U.S. Patent No. 10,109,342 to Roy. It includes a plurality of memory cells and at least one peripheral circuit connected to the plurality of memory cells and comprising a superlattice. The superlattice includes a plurality of stacked layers, each of which includes a plurality of stacked base semiconductor monolayers defining a base semiconductor portion and at least one overlying non-semiconductor monolayer constrained within the crystal lattice of an adjacent base semiconductor portion. The semiconductor device further includes a first power switching device configured to connect the at least one peripheral circuit to a first voltage supply source during a first operating mode, and a second power switching device configured to connect the at least one peripheral circuit to a second voltage supply source lower than the first voltage supply source during a second operating mode.

[0007] The above-described DRAM devices incorporating superlattice channels can be used to provide comparison data values ​​in a power-efficient manner. Despite the advantages offered by such DRAM devices, further development of memory system structures and methods of operation is required to optimize the operation of applications requiring a large number of comparison operations. [Brief explanation of the drawings]

[0008] [Figure 1] 1 is a greatly enlarged schematic cross-sectional view of a superlattice used in a semiconductor device according to one embodiment; [Figure 2] FIG. 2 is a perspective schematic atomic diagram of a portion of the superlattice shown in FIG. 1. [Figure 3] 1 is a schematic cross-sectional view of a superlattice according to one embodiment, greatly enlarged in another embodiment; [Figure 4A] 3 is a graph of the band structure calculated from the gamma point (G) for both bulk silicon in the prior art and the 4:1 Si:O superlattice shown in FIGS. 1-2. [Figure 4B] 3 is a graph of the band structure calculated from the Z point for both bulk silicon in the prior art and the 4:1 Si:O superlattice shown in FIGS. [Figure 4C] 4 is a graph of the band structure calculated from both the gamma and Z points for both bulk silicon in the prior art and the 5:1:3:1:Si:O superlattice shown in FIG. 3. [Figure 5] 1 is a schematic block diagram of a memory system including a control / interface ASIC, multiple multi-threaded DRAM chips, and a power control integrated circuit, according to one embodiment of the present invention. [Figure 6] FIG. 6 is a plan view of an exemplary DRAM sector configuration implemented on the multi-threaded DRAM chip of FIG. 5 according to one embodiment of the present invention. [Figure 7] 6 is a plan view illustrating an example processor configuration on the control / interface ASIC of FIG. 5 according to one embodiment of the present invention. [Figure 8] FIG. 7 is a plan view of the DRAM sector of FIG. 6 according to one embodiment of the present invention. [Figure 9A] FIG. 8 is a schematic block diagram of a comparator array implemented in the DRAM sector of FIG. 7, according to various embodiments of the present invention. [Figure 9B] FIG. 8 is a schematic block diagram of a comparator array implemented in the DRAM sector of FIG. 7, according to various embodiments of the present invention. [Figure 10] FIG. 9C is a circuit schematic diagram of a latch usable in the comparator array of FIGS. 9A and 9B, according to various embodiments of the present invention. [Figure 11] FIG. 9C is a circuit schematic diagram illustrating an example implementation of the comparator array of FIGS. 9A and 9B, according to one embodiment of the present invention. DETAILED DESCRIPTION OF THE INVENTION

[0009] Exemplary embodiments will now be described in more detail with reference to the accompanying drawings, in which exemplary embodiments are shown. However, embodiments may be embodied in many different forms and should not be construed as limited to the specific examples set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete. Like numbers refer to like elements throughout, and prime notation is used to indicate like elements in different embodiments.

[0010] Generally, the present disclosure relates to the formation of semiconductor devices utilizing enhanced semiconductor superlattices, which may be referred to in the present disclosure as "MST" layers / films or "MST technology."

[0011] More specifically, MST technology relates to advanced semiconductor materials, such as superlattices 25, as further described below. Applicant theorizes, without wishing to be bound thereby, that certain superlattices, such as those described herein, reduce the effective mass of charge carriers, thereby increasing charge carrier mobility. Effective mass has been described in various definitions in the literature. As a measure of effective mass improvement, Applicant uses the M for electrons and holes, respectively, as defined below. e -1 and M h -1 For electrons, we use the "inverse conductivity effective mass tensor":

[0012]

number

[0013] and for holes,

[0014]

number

[0015] where f is the Fermi-Dirac distribution, E Fis the Fermi energy, T is the temperature, E(k,n) is the energy of the electron in the state corresponding to wave vector k and the nth energy band, and the subscripts i and j denote the Cartesian coordinates x, y, and z. The integrals are performed in the Brillouin zone (BZ), and the sums are calculated over the bands with energies above and below the Fermi energy for electrons and holes, respectively.

[0016] Applicant's definition of the inverse conductivity effective mass tensor is that the greater the value of the corresponding component of the inverse conductivity effective mass tensor, the greater the tensor component of the material's conductivity. Applicant also theorizes, without intending to be bound thereby, that the superlattices described herein set the value of the inverse conductivity effective mass tensor to enhance the material's conductive properties, typically the preferred direction of charge carrier transport. The reciprocal of the appropriate tensor component is referred to as the conductivity effective mass. In other words, to characterize semiconductor material structures, the electron / hole conductivity effective mass, as described above and calculated in the intended direction of carrier transport, is used to distinguish improved materials.

[0017] Applicants have identified improved materials or structures for use in semiconductor devices. More specifically, Applicants have identified materials or structures having an energy band structure in which the appropriate conductivity effective mass of electrons and / or holes is significantly smaller than the corresponding value for silicon. In addition to improving mobility characteristics, these structures can also be formed or used to provide piezoelectric, pyroelectric, and / or ferroelectric properties, which are advantageous for use in various types of devices, as further described below.

[0018] 1 and 2, the material or structure is in the form of a superlattice 25 whose structure is controlled at the atomic or molecular level and is formed using known techniques of atomic or molecular layer deposition. Superlattice 25 includes a plurality of layers 45a-45n arranged in a stacked structure, as can best be understood with particular reference to the schematic cross-sectional view of FIG.

[0019] Each layer group 45a-45n of superlattice 25 illustratively includes a plurality of stacked base semiconductor monolayers 46 defining respective base semiconductor portions 46a-46n, followed by an energy band-modifying layer 50. Energy band-modifying layer 50 is shown in stippled form in Figure 1 for clarity.

[0020] The energy band-modifying layer 50 illustratively comprises one non-semiconductor monolayer constrained within the crystal lattice of an adjacent base semiconductor portion. "Constrained within the crystal lattice of an adjacent base semiconductor portion" means that at least some of the semiconductor atoms of the opposing base semiconductor portions 46a-46n are chemically bonded to one another via the non-semiconductor monolayer 50 disposed between them, as shown in FIG. 2. Generally speaking, this configuration is achieved by controlling the amount of non-semiconductor material deposited on the semiconductor portions 46a-46n by atomic layer deposition techniques, as described below, so that not all available semiconductor bonding sites are occupied by bonds to non-semiconductor atoms (i.e., coverage is not complete or less than 100%). Thus, as additional monolayers 46 of semiconductor material are deposited on or over the non-semiconductor monolayer 50, the newly deposited semiconductor atoms will occupy the remaining vacancy bonding sites of the semiconductor atoms disposed below the non-semiconductor monolayer.

[0021] In other embodiments, there may be multiple such non-semiconductor monolayers. It should be noted that, as used herein, the terms non-semiconductor monolayer or semiconductor monolayer mean that the material used in the monolayer is non-semiconductor or semiconductor when formed in bulk. That is, a monolayer of a material such as silicon may not exhibit the same properties as when formed in bulk or in a relatively thick layer, as will be understood by those skilled in the art.

[0022] Applicants theorize, without being bound thereto, that energy band-modifying layer 50 and adjacent base semiconductor portions 46a-46n cause superlattice 25 to have a lower effective conductivity mass for charge carriers in the parallel layer direction than would otherwise be the case. Viewed another way, this parallel direction is perpendicular to the stacking direction. Band-modifying layer 50 may also advantageously function as an insulator between vertically upper and lower layers or regions of the superlattice while providing superlattice 25 with a common energy band structure.

[0023] Additionally, the superlattice structure may also advantageously act as a barrier to diffusion of dopants and / or materials between layers vertically above and below superlattice 25. Thus, as will be appreciated by those skilled in the art, these properties may advantageously reduce the diffusion of high-K materials into the channel region as well as provide an interface to superlattice 25 for a high-K dielectric that reduces unwanted scattering effects and improves device mobility.

[0024] It is also believed that semiconductor devices including superlattice 25 may enjoy higher charge carrier mobility than other devices due to the lower effective conductive mass. In some embodiments, as a result of the band engineering achieved by the present invention, superlattice 25 may further have a substantially direct energy bandgap, which may be particularly advantageous for, for example, optoelectronic devices.

[0025] Superlattice 25 also includes a capping layer 52 on top of upper layer group 45n, as shown. Capping layer 52 may include a plurality of base semiconductor monolayers 46. By way of example, capping layer 52 may include 1 to 100 monolayers 46 of the base semiconductor, and more preferably 10 to 50 monolayers. However, depending on the application, capping layer 52 may be omitted or may have a thickness greater than 100 monolayers.

[0026] Each of the base semiconductor portions 46a-46n may include a base semiconductor selected from the group consisting of Group IV semiconductors, Group III-V semiconductors, and Group II-VI semiconductors. Of course, as will be understood by those skilled in the art, the term Group IV semiconductor also includes Group IV-IV semiconductors. More specifically, the base semiconductor may include at least one of silicon and germanium, for example.

[0027] Each energy band-modifying layer 50 may be comprised of a non-semiconductor selected from the group consisting of, for example, oxygen, nitrogen, fluorine, carbon, and carbon-oxygen. The non-semiconductor is also desirably thermally stable throughout the deposition of subsequent layers, thereby facilitating fabrication. In other embodiments, the non-semiconductor may be other inorganic or organic elements or compounds compatible with a given semiconductor process, as will be appreciated by those skilled in the art. More particularly, the base semiconductor may be comprised of, for example, silicon and / or germanium.

[0028] It should be noted that the term monolayer is meant to include a single atomic layer and a single molecular layer. It should also be noted that an energy band-modifying layer 50 provided by a single monolayer includes a monolayer in which not all of the available sites are occupied (i.e., the coverage is not complete or less than 100%). For example, with particular reference to the atomic diagram of Figure 2, which illustrates a 4:1 repeating structure for silicon as the base semiconductor material and oxygen as the energy band-modifying material. In the illustrated example, only half of the available oxygen sites are occupied.

[0029] In other embodiments and / or with different materials, this half occupancy ratio may not necessarily be applicable, as will be appreciated by those skilled in the art. Indeed, as can be seen in this schematic, the individual oxygen atoms in a monolayer do not align precisely along a flat plane, as will be appreciated by those skilled in the art of atomic deposition. By way of example, a preferred range of occupancy is approximately one-eighth to one-half of the available oxygen sites, although other values ​​may be used in certain embodiments.

[0030] Silicon and oxygen are currently widely used in conventional semiconductor processing, allowing manufacturers to readily utilize these materials as described herein. Atomic layer deposition, or monolayer deposition, is also now widely used. Thus, semiconductor devices incorporating superlattices 25 according to the present invention can be readily adapted and implemented, as will be appreciated by those skilled in the art.

[0031] Applicant theorizes, without being bound thereto, that in the case of a superlattice, such as a Si:O superlattice, the number of silicon monolayers should be seven or less to achieve the desired benefits, so that the energy bands of the superlattice are common or relatively uniform throughout. The 4:1 Si:O repeat structure shown in Figures 1 and 2 has been modeled to demonstrate enhanced electron and hole mobility in the X direction. For example, the calculated electron conductivity effective mass (isotropic for bulk silicon) is 0.26 and 0.12 in the X direction for a 4:1 SiO superlattice, resulting in a ratio of 0.46. Similarly, hole calculations yield values ​​of 0.36 for bulk silicon and 0.16 for a 4:1 Si:O superlattice, resulting in a ratio of 0.44.

[0032] While such directional advantageous features may be desirable in certain semiconductor devices, other devices may benefit from a more uniform increase in mobility in any direction parallel to the layers. As will be appreciated by those skilled in the art, it may be beneficial to increase the mobility of both electrons and holes, or to increase the mobility of just one of these types of charge carriers.

[0033] The low conductivity effective mass for the 4:1 Si:O embodiment of superlattice 25 can be less than two-thirds the conductivity effective mass otherwise, and this applies to both electrons and holes. Of course, as will be appreciated by those skilled in the art, superlattice 25 may also include at least one conductivity dopant.

[0034] Indeed, with further reference to FIG. 3, another embodiment of a superlattice 25′ according to the present invention having different characteristics is now described. This embodiment shows a 3:1:5:1 repeating pattern. More specifically, the lowest base semiconductor portion 46a′ has three monolayers, and the next-lower base semiconductor portion 46b′ has five monolayers. This pattern is repeated throughout the superlattice 25′. The energy band-modifying layers 50′ may each comprise a single monolayer. For such a superlattice 25′ including Si versus O, charge carrier mobility enhancement is independent of in-plane orientation of the layers. Other elements not specifically mentioned in FIG. 3 are similar to those previously described with reference to FIG. 1 and need not be further described here.

[0035] In some device embodiments, all of the base semiconductor portions of the superlattice may be the same number of monolayers thick. In other embodiments, at least some of the base semiconductor portions may be a different number of monolayers thick. In still other embodiments, all of the base semiconductor portions may be a different number of monolayers thick.

[0036] Figures 4A-4C show the band structures calculated using density functional theory (DFT). It is well known to those skilled in the art that DFT underestimates the absolute value of the band gap. Therefore, all bands above the gap can be shifted by appropriate "scissors corrections." On the other hand, the band shapes are known to be more reliable. The vertical energy axis should be interpreted in this light.

[0037] FIG. 4A shows the calculated band structures from the gamma point (G) for both bulk silicon (represented by a continuous line) and the 4:1 Si:O superlattice 25 shown in FIG. 1 (represented by a dotted line). While the directions refer to the unit cell of the 4:1 Si:O structure, not to the unit cell of conventional Si, the (001) direction in the figure corresponds to the (001) direction of the conventional Si unit cell and thus indicates the expected location of the minimum in the Si conduction band. The (100) and (010) directions in the figure correspond to the (110) and (-110) directions of the conventional Si unit cell. Those skilled in the art will understand that the Si bands in the figure have been folded to represent the appropriate reciprocal lattice directions of the 4:1 Si:O structure.

[0038] It can be seen that the conduction band minimum of the 4:1 Si:O structure is located at the gamma point in contrast to bulk silicon (Si), while the valence band minimum occurs at the edge of the Brillouin zone in the (001) direction, referred to as the Z point. It is also noted that the curvature of the conduction band minimum of the 4:1 Si:O structure is larger than that of Si, due to the band splitting caused by the perturbation introduced by the additional oxygen layer.

[0039] Figure 4B shows the band structures calculated from the Z point for both bulk silicon (continuous line) and a 4:1 Si:O superlattice 25 (dotted line), which shows an increased curvature of the valence band in the (100) direction.

[0040] Figure 4C shows the calculated band structures from both the gamma (G) and Z points for both bulk silicon (continuous line) and the 5:1:3:1 Si:O structure of superlattice 25' in Figure 3 (dotted line). Due to the symmetry of the 5:1:3:1 Si:O structure, the calculated band structures in the (100) and (010) directions are equivalent. Therefore, the conductivity effective mass and mobility are expected to be isotropic in the plane parallel to the layers, i.e., perpendicular to the (001) stacking direction. Note that in the 5:1:3:1 Si:O example, both the conduction band minimum and the valence band maximum are at or near the Z point.

[0041] While increasing curvature indicates a decrease in effective mass, a suitable comparison or distinction can be made by calculating the inverse effective mass tensor of electrical conductivity. From this, applicants further theorize that the 5:1:3:1 superlattice 25' should be substantially direct bandgap. As will be appreciated by those skilled in the art, the appropriate matrix element for the optical transition is another indicator of the distinction between direct and indirect bandgap behavior.

[0042] A further advantage of MST technology is that high and low threshold voltage (Vt) devices can be separately optimized on the same chip. Optimizing the high Vt devices to minimize leakage allows them to be used as headers to reduce leakage to the rest of the periphery in standby mode, while optimizing the low Vt devices in these paths can achieve even greater speeds in active mode than the 70% improvement mentioned earlier. Further details regarding DRAM memories incorporating MST films to achieve these technical advantages are described in the aforementioned U.S. Pat. No. 10,109,342 and U.S. Pat. No. 10,107,854 to Roy, both of which are incorporated herein by reference in their entireties.

[0043] 5 is a block diagram of a memory system 100, illustratively including a stack 101 of four multi-threaded DRAM (MTDRAM) chips 501-504, a control / interface ASIC 102 (fabricated with an advanced logic process), and a power management circuit (PMIC) 103. While the illustrated example includes four MTDRAM chips 501-504 in the stack 101, it should be understood that in other embodiments, the stack 101 may include other numbers of MTDRAM chips. As shown in FIG. 5, the PMIC 103 provides multiple supply / control voltages (i.e., Vddp, Vddgate, Vddturbo, Vnwell, Vdd2, Vrefglobal, Vrefbit, GND, Vswloff, and Vneg) in response to received supply voltages (Vddp, Vddturbo, Vdd2, and GND). Further details regarding the voltages supplied to and output by the PMIC 103 are described in commonly owned, pending U.S. patent application Ser. No. 18 / 311,465, filed May 3, 2023, and incorporated herein by reference. Some supply / control voltages (i.e., Vswloff, Vrefbit, and Vddp) are supplied only to the MTDRAM chips 501-504, while other supply / control voltages are shared by both the MTDRAM chips 501-504 and the control / interface ASIC 102 and are used to support new logic levels in the control / interface ASIC 102. The various supply / control voltages are routed between the PMIC 103, the stack 101, and the control / interface ASIC 102 using multiple through-silicon via (TSV) structures 105.

[0044] In this example, the MTDRAM chips 501-504 have an architecture enhanced with the MST film and its properties (e.g., improved bandwidth) described above. FIG. 6 is a block diagram illustrating the layout of an example MTDRAM chip 501 in a 32-Gbit configuration. The MTDRAM chip 501 includes sixteen 2-Gbit DRAM sectors 600-615, as shown, which are configured not to communicate with each other on-chip. Rather, communication between the DRAM sectors 600-615 of the same MTDRAM chip 501 (or between the DRAM sectors 600-615 of the MTDRAM chip 501 and various sectors of the other MTDRAM chips 502-504) is handled by the control / interface ASIC 102, as described in more detail below. While the MTDRAM chip 501 is described according to a 32-Gbit configuration including sixteen 2-Gbit DRAM sectors, it should be understood that other embodiments may use different memory sizes and configurations.

[0045] Each DRAM sector 600-615 includes a corresponding number of through-silicon vias (TSVs) for communicating with the control / interface ASIC 102. For example, the DRAM sector 600 includes a number of TSVs 106 for communicating with the control / interface ASIC 102. The number of TSVs 106 typically includes a TSV set 620 for transmitting control and address information from the control / interface ASIC 102 to the DRAM sector 600, a TSV set 621 for transmitting data from the control / interface ASIC 102 to the DRAM sector 600, and a TSV set 622 for transmitting data from the DRAM sector 600 to the control / interface ASIC 102. The control and address information transmitted in the TSVs 620 specifies read, write, and compare operations to be performed within the DRAM sector 600. The data transmitted in the TSVs 621 may include data values ​​to be written to the DRAM sector 600 and weight data values ​​used in the compare operations. The data transmitted in TSV 622 may include a data value read from DRAM sector 600 or data representing the result of a compare operation. The various TSVs 620-622 contained in the plurality of TSVs 106 are described in further detail below. Each DRAM sector 600-615 contains a corresponding set of identical TSVs, allowing each DRAM sector 600-615 to be individually accessible by control / interface ASIC 102.

[0046] 6 shows only the layout of MTDRAM chip 501, it should be understood that MTDRAM chips 501-504 all have the same configuration. Thus, MTDRAM chips 502-504 each include sixteen 2-Gbit DRAM sectors similar to DRAM sectors 600-615 of MTDRAM chip 501.

[0047] 7 is a block diagram illustrating the layout of the control / interface ASIC 102 according to one embodiment. The control / interface ASIC 102 includes multiple independent processors 700-715, each connected to a corresponding DRAM sector 600-615 of the MTDRAM chip 501 via a corresponding TSV set. For example, the processor 700 of the control / interface ASIC 102 is connected to the DRAM sector 600 of the MTDRAM chip 501 via the TSV set 106 described above. In this manner, each of the processors 700-715 can access (e.g., read, write, or compare) the corresponding DRAM sector 600-615 of the MTDRAM chip 501. Furthermore, each of the processors 701-715 is connected to a corresponding one of the 16 DRAM sectors of each of the MTDRAM chips 502-504. 5 is a schematic diagram illustrating TSV structures 106, 107, 108, and 109 that provide connectivity between processor 700 of control / interface ASIC 102 and corresponding DRAM sectors 600, 6001, 6002, and 6003 in each of MTDRAM chips 501, 502, 503, and 504. It should be appreciated that similar TSV structures provide connectivity between the remaining processors 701-715 of control / interface ASIC 102 and corresponding DRAM sectors in each of MTDRAM chips 501-504.

[0048] The interconnect structure of Control / Interface ASIC 102 is configured to allow complete and robust interconnection between all of processors 700-715. As a result, data obtained by a processor from its corresponding MTDRAM sector can be shared with all other processors in Control / Interface ASIC 102. An example of this interconnect structure is shown in FIG. 7, which illustrates that data obtained by processor 705 from MTDRAM sector 605 can be shared with any of the other processors 700-704 and 706-715 as part of the interconnect structure included in Control / Interface ASIC 102 by interconnect network 7051. Note that the data obtained from MTDRAM sector 605 may be data read directly from the DRAM bank of MTDRAM sector 605 or may correspond to the result of a compare operation performed within MTDRAM sector 605, as will be described in more detail below. 7 only shows the interconnection network 7051 between processor 705 and the other processors 700-704 and 706-715, it should be understood that each of the other processors 701-704 and 706-715 has a similar corresponding interconnection network, thereby enabling each of processors 700-715 to transfer data to and from each of the other processors 700-715. It should be noted that the advanced logic processes used to fabricate control / interface ASIC 102 may typically include eight to ten metal layers (although other embodiments may use a different number of metal layers), making it easier to implement multiple metal interconnect layers in control / interface ASIC 102 than in MTDRAM chip 501. Furthermore, the achievable dimensions of the circuitry in control / interface ASIC 102 tend to be much smaller than those achievable in processes typically used to fabricate DRAM devices. For example, while a 5nm (or even 3nm) process can be used to manufacture the logic circuits of an ASIC, the processes typically used to manufacture DRAM devices are usually one or more generations behind in size.Furthermore, the size of TSVs used in the process of manufacturing ASIC logic circuits is approximately 1 μm, while the size of TSVs used in the process of manufacturing DRAM devices is approximately 30 μm. Therefore, by using TSVs directly between each DRAM sector 600-615 of the MTDRAM chip 501 and the control / interface ASIC 102 and incorporating the connections between the sectors into the control / interface ASIC 102, it is possible to run multiple different processes in parallel in different sectors, similar to the structure of the human brain. In this respect, this architecture is particularly suitable for artificial intelligence (AI) applications, but can also be used for other applications.

[0049] 8 is a schematic diagram illustrating the signal interconnection configuration of a 2-Gbit DRAM sector 600 in one embodiment. The 2-Gbit DRAM sector 600 is logically divided into eight DRAM arrays 800-807, each containing 16 DRAM banks (i.e., the 2-Gbit DRAM sector 600 contains a total of 128 DRAM banks). Each of these DRAM banks contains a 4096 x 4096 DRAM memory cell array. The interconnect components of DRAM sector 600 include control / secondary address TSVs 1201-1202, compare output TSVs 1211-1214, comparator arrays 1221-1224, output circuits 1231-1234, raw output TSVs 1241-1244, data input TSVs 1251-1254, data input circuits 1261-1262, and primary address TSV 127. Generally, processor 700 of control / interface ASIC 102 provides control / address information to DRAM sector 600 via TSVs 1201-1202 and 127 (shown generally as multiple TSVs 620 in FIGS. 6 and 7). This control / address information specifies the read, write, and compare operations to be performed by DRAM sector 600. A read operation is performed by reading data from one or more of the DRAM arrays 800-807 based on address information provided by TSVs 1201-1202 and 127. The read data is routed from the DRAM arrays 800-807 to output circuits 1231-1234. This read data is routed from the output circuits 1231-1234 to the processor 700 (control / interface ASIC 102) via raw output TSVs 1241-1244 (which are generally shown as multiple output data TSVs 622 in FIGS. 6-7). To perform a write operation, the processor 700 of the control / interface ASIC 102 sends write data to data input circuits 1261-1262 of the DRAM sector 600 via data input TSVs 1251-1254 (which are generally shown as multiple input data TSVs 621 in FIGS. 6-7).The data input circuits 1261-1262 write the received write data to one or more DRAM arrays 800-807 based on the write address information provided by the processor 700 to the TSVs 1201-1202 and 127.

[0050] As described in more detail below, processor 700 of control / interface ASIC 102 initiates a compare operation on a corresponding DRAM sector 600 by sending control / address information (i.e., a compare instruction) specifying the compare operation via TSVs 1201-1202 and 1207. The compare instruction includes address information specifying data values ​​to be read from DRAM arrays 801-807 and provided to comparator arrays 1221-1224 for the compare operation. In conjunction with the compare instruction, processor 700 provides weight data values ​​(via data input TSVs 1251-1254 and data input circuits 1261-1262) to comparator arrays 1221-1224. In response, comparator arrays 1221-1224 perform the compare operation and provide compare output signals to control / interface ASIC 102 via compare output TSVs 1211-1214 (which are generally shown schematically in FIGS. 6-7 as a plurality of output data TSVs 622).

[0051] Input data to DRAM sector 600 is routed through data input TSVs 1251-1254, while output data from DRAM sector 600 is routed through separate data output TSVs 1241-1244 and 1211-1214, rather than using the common shared I / O lines of conventional DRAMs. Additionally, data output circuits 1231-1234 can be controlled to route data received from DRAM arrays 801-807 to data output TSVs 1241-1244 and / or comparator arrays 1221-1224, providing flexibility in how output data from DRAM arrays 801-807 is routed. Similarly, data input circuits 1261-1262 can be controlled to route data received from processor 700 to DRAM arrays 801-807 and / or comparator arrays 1221-1224, providing flexibility in how input data from processor 700 is routed within DRAM sector 600.

[0052] In the illustrated embodiment, the on-chip logic required for DRAM sector 600 is limited to comparator array 1221-1224, data output circuits 1231-1234, and data input circuits 1261-1262, with the remaining logic components incorporated into control / interface ASIC 102.

[0053] The comparison operations performed by DRAM sector 600 according to one embodiment of the present invention are described below. Figure 9A is a block diagram illustrating comparator array 1221 shown in Figure 8 according to one embodiment of the present invention. In the illustrated embodiment, comparator array 1221 includes a plurality of comparator circuits 1320-1322. 127 and multiple input data digital-to-analog converters (qDACs) 1310-131 31 and multiple weighted data digital-to-analog converters (wDACs) 1300 to 130 65 , and a plurality of weight data latches (wLatch) 1330 to 1333 65 Includes qDAC1310~131 31are configured to receive q data values ​​q[127:0] read from DRAM arrays 800 and / or 804. More specifically, each qDAC 131n is configured to receive four bits, q[(4n+3):(4n)], of the q data values ​​q[127:0]. Thus, qDAC 1310 receives bits q[3:0], qDAC 1311 receives bits q[7:4], and qDAC 131 31 receive bits q[127:124] of q data value q[127:0], respectively.

[0054] wLatch1330~133 65 are the corresponding 4-bit weight data values ​​w0[3:0] to w 65 [3:0], which are provided sequentially on weight input data bus win[7:0] by processor 700 of control / interface ASIC 102 via data input TSV 1251 and data input circuit 1261. 32 [3:0] are sequentially provided on the weight input data bus win[3:0], and are respectively input to the wLatch 1330 to 1333 in response to the corresponding load address signals LOAD[0] to LOAD

[32] . 32 Similarly, the weight data value w 33 [3:0]~w 65 [3:0] are sequentially provided to the weight input data bus win[7:4], and are respectively connected to the wLatch 133 in response to the corresponding load address signals LOAD[0] to LOAD

[32] . 33 ~133 65 is written to.

[0055] In one embodiment, the load address signals LOAD[0] through LOAD

[32] are provided by the processor 700 of the control / interface ASIC 102 via the control / secondary address TSV 1201. In another embodiment, the load address signals LOAD[0] through LOAD

[32] are generated in the MTDRAM chip 501 by decoding a 5-bit load address value provided by the processor 700 of the control / interface ASIC 102 via the control / secondary address TSV 1201.

[0056] In one embodiment, only one of the load address signals LOAD[0] through LOAD

[32] is activated at a time. For example, the desired weight data values ​​w0[3:0] and w 33 [3:0] are provided on the input data buses win[3:0] and win[7:0], respectively, and the load address signal LOAD[0] is activated to provide the desired weight data values ​​w0[3:0] and w 33 [3:0] are wLatch1330 and 133 33 The desired weight data values ​​w1[3:0] and w 34 [3:0] are provided on the input data buses win[3:0] and win[7:0], respectively, and the next load address signal LOAD[1] is activated to provide the desired weight data values ​​w1[3:0] and w 34 [3:0] are wLatch13 31 and 133 34 This process is repeated, with the load address signals LOAD[0] through LOAD

[32] being activated sequentially to simultaneously write all of the desired weight data values ​​w0[3:0] through w 65 [3:0] corresponds to wLatch1330~133 65 In one embodiment, the wLatch 1330-1333 65 Write operations to the Latch are performed at a relatively high rate of 2 GHz. 65A circuit for implementing is described in more detail below with reference to FIG.

[0057] wLatch1330~133 65 The 4-bit weight data values ​​w0[3:0] to w 65 [3:0] are the corresponding wDAC1300~130 65 and is used to perform a comparison operation, the method of which is described in more detail below.

[0058] Comparator circuits 1320-132 127 As shown, qDAC1310~131 31 and wDAC1300~130 65 qDAC1310~131 31 are arranged in a row, and on the left side of these qDACs are comparator circuits 1320 to 132 63 are arranged in a row, and on the right side is a comparator circuit 132 64 ~132 127 are arranged in a row. qDAC1310~131 31 Each of the four comparator circuits 1320 to 1322 outputs an analog signal representing a corresponding 4-bit q data value to the four comparator circuits 1320 to 1322. 127 For example, the qDAC 1310 supplies an analog signal representing q[3:0] to the comparator circuits 1320, 1321, and 1322. 64 , 132 65 This has the advantage that each 4-bit q data value can be used simultaneously in four comparison operations.

[0059] wDAC1300~130 32 The comparator circuits 1320 to 132 63 Located in the first row to the left of the wDAC130 33 ~130 65 is a comparator circuit 132 64 ~132 127 They are located in the second row to the right of the wDAC1301~130 31, which respectively output analog signals representing corresponding 4-bit weight data values ​​to the comparator circuits 1321 to 1322. 62 Two of these are provided (also: wDAC1300 and 130 32 Each of the comparators 1320 and 1322 outputs an analog signal representing a corresponding 4-bit weighted data value to the comparator circuits 1320 and 1323, respectively. 63 For example, wDAC 1301 provides an analog signal representing a corresponding 4-bit weight data value w1[3:0] to comparator circuits 1321 and 1322.

[0060] Similarly, each wDAC130 34 ~130 64 outputs an analog signal representing the corresponding 4-bit weight data value to the comparator circuit 132. 65 ~132 126 (Also, wDAC130 33 and 130 65 Each of these outputs an analog signal representing a 4-bit weighted data value to a comparator circuit 132. 64 and 132 127 (For example, wDAC130 34 outputs an analog signal representing the corresponding 4-bit weight data value w34[3:0] to the comparator circuit 132 65 and 132 66 This is advantageous because it allows most of the 4-bit weight data values ​​to be used simultaneously in two comparison operations.

[0061] Comparator circuits 1320 to 132 127 Each of the comparator circuits 1320 to 1322 outputs a corresponding comparison output signal out[0] to out

[0127] , which indicates the result of the comparison operation performed by the corresponding comparator circuit. 127 , qDAC1310~131 31 , and wDAC1300~130 65 The circuitry used to perform the comparison operation by is described in more detail below with reference to FIG.

[0062] In the embodiment shown in FIG. 9A, qDACs 1310-131 31 Column 1, comparator circuit 1320~132 63 and 132 64 ~132 127 Two rows of wDAC1300~130 33 and 130 34 ~130 64 (and the corresponding wLatch1330~133 33 and 133 34 ~133 65 ), it should be understood that this configuration can be expanded horizontally to include more columns. Examples of such column expansion are described below.

[0063] FIG. 9B is a block diagram illustrating the comparator array 1221 of FIG. 8, including an additional column 131 of qDACs, according to one embodiment of the present invention. 32 ~131 63 , two additional columns of comparator circuits 132 128 ~132 191 and 132 192 ~132 255 , as well as the additional column 130 in wDAC 66 ~130 98 (and the corresponding wLatch column 133 66 ~133 98 ) The first five columns of the comparator array of FIG. 9B are identical to (and therefore have the same reference numbers as) the first five columns of the comparator array of FIG. 9A. Generally, comparator array 1221 alternates between columns of wDACs and columns of qDACs, with columns of comparator circuits disposed between adjacent columns of wDACs and columns of qDACs.

[0064] Furthermore, in addition to the connections described with reference to FIG. 9A, 34 ~130 64 Each of the analog signals representing the corresponding 4-bit weighted data value is input to a comparator circuit 132. 129 ~132 190(Also, wDAC130 33 and 130 65 Each of the four bits of the weight data value is input to the comparator circuit 132. 128 and 132 191 (For example, wDAC130 34 The 4-bit weight data value w34[3:0] is input to the comparator circuit 132. 129 and 132 130 This provides a 4-bit weight data value w 33 [3:0]~w 65 This has the advantage that [3:0] can be used for four comparison operations at the same time.

[0065] Additional qDAC columns 131 32 ~131 63 is configured to store the q data values ​​q1[127:0] read from the DRAM arrays 800 and / or 804. 32 ~131 63 Each of these stores 4 bits of q data of the q data value q1[127:0] (this is the qDAC1310 to 131 31 stores the 4-bit q data of q data value q[127:0]. In one embodiment, q data values ​​q[127:0] and q1[127:0] are different data values ​​read from DRA arrays 800 and / or 804. In another embodiment, q data value q1[127:0] stores the 4-bit q data value of q data value q[127:0] in the 131 column of the second column of the qDAC. 32 ~131 63 These configurations are formed by rearranging the comparator circuit 132 128 ~132 191 The comparator circuit 132 64 ~132 127 This is necessary to avoid overlapping the comparisons performed by each qDAC131. 32 ~131 63 converts an analog signal representing a corresponding 4-bit q data value to a comparator circuit 132 as shown in the figure. 128 ~132191 Two of these and the comparator circuit 132 192 and 132 255 The NI PXI-8110 is configured to output to two of the following:

[0066] Additional wDAC130 66 ~130 98 Column and wLatch133 66 ~133 98 The column is wLatch133 66 ~133 98 are the weight data values ​​w 66 [3:0]~w 98 These weight data values ​​w[3:0] are stored. 66 [3:0]~w 98 [3:0] is the weight input data bus win[11:8] from the corresponding wLatch133 66 ~133 98 are sequentially written to the wLatch 1331, 1332, respectively, in response to the load address signal LOAD[0] through LOAD

[32] being sequentially activated. For example, weight data values ​​provided to the weight input data buses win[3:0], win[7:4], and win[11:4] are sequentially written to the wLatch 1331, 1332, respectively, in response to the load address signal LOAD[1] being activated. 34 and 133 67 are written as weight data values ​​w1[3:0], w34[3:0] and w67[3:0], respectively.

[0067] wDAC130 67 ~130 97 Each of the comparators 132 outputs an analog output signal representing a corresponding 4-bit weighted data value. 193 ~132 254 (Also, wDAC130 66 and 130 98 outputs an analog signal representing a corresponding 4-bit weighted data value to a comparator circuit 132. 192 and 132 255 output to

[0068] Each comparator circuit 132 128 ~132 255 Each of the comparators 1221 provides a corresponding output signal out

[0128] through out

[0255] , which specifies the result of the comparison operation performed by the comparator circuit. Thus, expanding the width of the comparator array 1221 in the configuration shown in FIG. 9B doubles the number of comparison results available. In one embodiment, the comparator array 1221 can be further expanded (doubling) to provide 512 output results (i.e., out[0:511]).

[0069] 10 is a circuit diagram showing a wLatch 1330 according to one embodiment of the present invention. 98 has the same circuit structure as the wLatch 1330, but each of the wLatch 1330 to 133 98 receive different input values. Specifically, wLatch1330~133 32 are configured to receive the load address signals LOAD[0] to LOAD

[32] , respectively. 32 is further configured to receive a 4-bit weight data value provided on a weight input data bus win[3:0]. 33 ~133 65 are configured to receive the load address signals LOAD[0] to LOAD

[32] , respectively. 33 ~133 65 is further configured to receive a 4-bit weight data value provided on a weight input data bus win[7:4]. 66 ~133 98 are configured to receive the load address signals LOAD[0] to LOAD

[32] , respectively. 66 ~133 98 Each of the weight inputs is further configured to receive a 4-bit weight data value provided on a weight input data bus win[11:8].

[0070] By providing a predetermined 4-bit weight data value to the weight input data buses win[3:0], win[7:4], win[11:8] and activating the load address signal LOAD[0], the weight data value is transferred to the wLatch 1330, 1333 33 , 133 66 The weight data values ​​are then simultaneously written to the wLatch 1331, 1333 by providing a predetermined 4-bit weight data value to the weight input data buses win[3:0], win[7:4], win[11:8] and activating the load address signal LOAD[1]. 34 , 133 67 This pattern continues (for a total of 33 write cycles) until a given weight data value is written to all wLatch1330-1333. 98 is written to.

[0071] 10, wLatch 1330 includes four latch circuits 1000-1003. Latch circuit 1000 includes an n-channel pass-gate transistor 201, a storage capacitor 204, and an inverter 205 (including a p-channel transistor 202 and an n-channel transistor 203, connected together as shown). The weight data value on weight input data bus line win[0] is supplied to the source of pass-gate transistor 201, and a load address signal LOAD[0] is supplied to the gate of pass-gate transistor 201.

[0072] To load weight data bit win[0] into latch circuit 1000, load address signal LOAD[0] (normally low) is activated high, which turns on pass gate transistor 201. Under these conditions, the voltage applied to storage capacitor 204 depends on the value of weight data bit win[0].

[0073] When weight data bit win[0] is logic "1" (i.e., win[0]=Vdd), storage capacitor 204 is charged to the Vdd supply voltage minus the threshold voltage (Vt) of pass-gate transistor 201. This voltage must be higher than the trip point of inverter 205. Under this condition, transistor 203 turns on (because transistor 202 is off), and weight data bit w0[0] is pulled down to ground.

[0074] If weight data bit win[0] is a logic "0" value (i.e., win[0]=0V), storage capacitor 204 is discharged to ground. Under these conditions, transistor 202 is turned on (transistor 203 is off), and weight data bit w0[0] is pulled up to Vdd.

[0075] Although only the circuit configuration of latch circuit 1000 is shown, it should be understood that latch circuits 1000-1003 all have the same circuit configuration. Latch circuits 1001, 1002, and 1003 latch weight data bits win[1], win[2], and win[3], respectively, in response to load signal LOAD[0], thereby providing output weight data bits w0[1], w0[2], and w0[3], respectively.

[0076] According to one embodiment, the wLatch 1330-133 98 The wLatches 1330-1333 store weight data values ​​that are relatively stable compared to the q data values ​​that are obtained at a much higher bandwidth from the DRAM arrays 800-807. As a result, the weight input data bus win[11:0] can operate at a relatively low frequency. The LOAD[32:0] signals are activated sequentially at a rate corresponding to the input clock signal, allowing the wLatches 1330-1333 to operate at a relatively low frequency. 9810, using a dynamic latch to store the weight data values ​​in wLatch requires periodic refresh, but consumes negligible power while providing significant area savings and voltage headroom reduction compared to SRAM-based latches. The refresh interval for latch circuit 1000 can be extended by increasing the value of capacitor 204.

[0077] 11 is a circuit diagram illustrating, in one embodiment, wDACs 1300, qDACs 1310, and comparator circuits 1320. It should be understood that the remaining wDACs, qDACs, and comparator circuits of comparator array 1221 have the same circuit configuration as shown in FIG.

[0078] qDAC 1310 includes n-channel charge transistors 140-143, p-channel precharge transistor 144, n-channel output transistor 145, capacitor structures 146-150, constant current source 151, and n-channel precharge transistors 156-159. N-channel charge transistors 140, 141, 142, and 143 have gates connected to receive q data signals q[0], q[1], q[2], and q[3], respectively, drains connected to node N1, and sources connected to capacitor structures 146, 147, 148, and 149, respectively. Capacitor structures 146-149 are further connected to ground. Capacitor structure 150 is connected between node N1 and ground. P-channel precharge transistor 144 has a gate connected to receive precharge control signal PRE#, a source connected to receive Vdd power supply voltage, and a drain connected to node N1. N-channel precharge transistors 156-159 have gates connected to receive complementary precharge control signals PRE, sources connected to ground, and drains connected to capacitor structures 146, 147, 148, and 149, respectively, as shown. Output transistor 145 has a gate connected to node N1, a source connected to the Vdd power supply voltage, and a drain connected to a constant current source 151. The voltage at the drain of output transistor 145 is provided to comparator 1320 as analog input voltage Vq.

[0079] wDAC 1300 includes n-channel charge transistors 160-163, p-channel pre-charge transistor 164, n-channel output transistor 165, n-channel offset transistor 181, capacitor structures 166-170 and 182, constant current source 171, and n-channel pre-charge transistors 176-180. N-channel transistors 160, 161, 162, and 163 have gates connected to receive weighted input data bits w[0], w[1], w[2], and w[3], respectively, drains connected to node N2, and sources connected to capacitor structures 166, 167, 168, and 169, respectively. Capacitor structures 166-169 are further connected to ground. Capacitor structure 170 is connected between node N2 and ground. Offset transistor 181 has a gate connected to receive an offset control signal (OS), a source connected to node N2, and a source connected to capacitor structure 182 (which is further connected to ground). P-channel precharge transistor 164 has a gate connected to receive precharge control signal PRE#, a source connected to receive the Vdd supply voltage, and a drain connected to node N2. As shown, n-channel precharge transistors 176-180 have a gate connected to receive precharge control signal PRE, a source connected to ground, and a drain connected to capacitor structures 166, 167, 168, 169, and 182, respectively. Output transistor 165 has a gate connected to node N2, a source connected to receive the Vdd supply voltage, and a drain connected to constant current source 171. The voltage at the drain of output transistor 165 is provided to comparator 1320 as analog input voltage Vw.

[0080] In the illustrated embodiment, the capacitor structures and transistors included in the wDAC 1300 and qDAC 1310 are all high threshold voltage devices fabricated based on MST technology.

[0081] According to one embodiment, capacitor structures 146-150, 166-170, and 182 are fabricated using capacitors with the same structure as the storage capacitors included in the DRAM cells of DRAM arrays 800-807. Different capacitor structures include different numbers of capacitors, weighting the voltages they provide when charged. The number of capacitors included in each capacitor structure 146-150, 166-170, and 182 is indicated in parentheses next to the capacitor structure. Thus, capacitor structures 146-150 include 2, 4, 8, 16, and 32 capacitors, respectively, and capacitor structures 166-170 and 182 include 2, 4, 8, 16, 32, and 1 capacitor, respectively, with the capacitors within each capacitor structure connected in parallel. Note that capacitor structures with the same weight have the same structure. For example, capacitor structures 146 and 166 are identical, and capacitors 148 and 168 are identical. In this manner, the capacitance of capacitor structures 146-150, 166-170, and 182 is precisely controlled.

[0082] Comparator 1320 includes pass gate circuits 190 and 191 and a differential comparator 1100. Each pass gate circuit 190 and 191 includes an n-channel transistor connected at its gate to receive a comparator enable signal EN and a p-channel transistor connected at its gate to receive a complementary enable signal EN#. When enabled, pass gate circuits 190 and 191 transmit the Vq and Vw voltages, respectively, to comparator circuit 1100. Differential comparator 1100 may be implemented using any of several known comparator circuits, such as, but not limited to, a DRAM sense amplifier circuit, a static RAM (SRAM) sense amplifier circuit, or an operational amplifier.

[0083] Next, wDAC1300, qDAC13 10, and the operation of the comparator circuit 1320. Before performing a comparison operation, all q data values ​​(i.e., q[127:0]) and w data values ​​(i.e., wLatches 1301 to 1302) are compared. 65 ) from comparator array 1221. In one embodiment, a first plurality of pass gate transistors (not shown) are provided to selectively provide (or isolate) the weight data values ​​w[0:3] in the corresponding wLatch 1330 to the gates of transistors 160-163, respectively. Similarly, a second plurality of pass gate transistors (not shown) are provided to selectively provide (or isolate) the q data values ​​q[0:3] provided from DRAM arrays 800-807 to the gates of transistors 140-143, respectively. A precharge control signal PRE# is activated low, thereby turning on p-channel precharge transistors 144 and 164 and providing the Vdd supply voltage to nodes N1 and N2. Complementary precharge control signal PRE is activated high, which turns on n-channel precharge transistors 156-159 and 176-180 and discharges capacitors 146-149, 166-169, and 182 to ground. Under this condition, n-channel transistors 140-143, 160-163, and 181 are turned off, which isolates capacitors 146-149 from node N1 and capacitors 166-169 and 182 from node N2, respectively. Capacitors 150 and 170, which are connected to nodes N1 and N2, respectively, are charged to the full Vdd supply voltage.

[0084] At this time, the voltage V of node N1 N1 is the voltage V at node N2 N2 These equal voltages V N1 and V N2 In response, output transistors 145 and 165 provide voltages Vq and Vw to pass gate circuits 190 and 191, respectively. These voltages Vw and Vq are respectively connected to the precharge voltage V PREDuring this period, the comparator enable signals EN / EN# are inactivated (i.e., EN is a logic low voltage and EN# is a logic high voltage), which turns off the pass gate circuits 190 and 191 and prevents the voltages Vq and Vw from being input to the comparator 1100. On the other hand, if the comparator 1100 is implemented using a DRAM sense amplifier, then during this period the input terminals of the DRAM sense amplifier are respectively at the precharge voltage V PRE It should be appreciated that comparator 1100 is initialized so that it is precharged to .

[0085] Next, precharge signal PRE# is deactivated high, turning off p-channel precharge transistors 144 and 164. The complementary precharge signal PRE is simultaneously deactivated low, turning off n-channel precharge transistors 156-159, 166-169, and 182. Next, offset control voltage OS is activated high, turning on offset transistor 181. The q data values ​​q[0:3] and weight data values ​​w[0:3] obtained in the manner described above are applied to transistors 140-143 and 160-163, respectively (e.g., by turning on first and second pluralities of pass gate transistors). q data bits q[0], q[1], q[2], and q[3] having a logic "1" value turn on corresponding charge transistors 140, 141, 142, and 143, respectively, thereby connecting corresponding capacitors 146, 147, 148, and 149, respectively, to node N1. Similarly, w data bits w[0], w[1], w[2], and w[3] having a logic "1" value turn on corresponding transistors 160, 161, 162, and 163, respectively, thereby connecting corresponding capacitors 166, 167, 168, and 169, respectively, to node N2.

[0086] The voltage at node N1 is pulled down by one of capacitors 146-149 connected to node N1. More specifically, in response to the logic high q data bit q[3:0], the charge previously stored in capacitor 150 is discharged to one of capacitors 146-149 connected to node N1. Depending on the weight values ​​assigned to capacitors 146-149, these capacitors 146, 147, 148, and 149 pull down the voltage at node N1 by 2, 4, 8, and 16 voltage units, respectively.

[0087] The voltage at node N2 is pulled down by offset capacitor 182 and one of capacitors 146-149 connected to node N2. More specifically, in accordance with the weight data bit w[3:0] of a logic high, the charge previously stored in capacitor 170 is discharged to offset capacitor 182 and one of capacitors 166-169 connected to node N2. Depending on the weight values ​​assigned to capacitors 182 and 166-169, these capacitors 182, 166, 167, 168, and 169 pull down the voltage at node N2 by 1, 2, 4, 8, and 16 voltage units, respectively.

[0088] The weight of the offset capacitor 182 is determined by the voltage at node N1 (V N1 ) is the voltage at node N2 (V N2 ). When the q data value q[3:0] is equal to the weight data value w[3:0], the voltage at node N2 will be one voltage unit lower than the voltage at node N1. When the q data value q[3:0] is less than the weight data value w[3:0], the voltage at node N2 will be lower than the voltage at node N1 (e.g., when q[3:0]="0011" and w[3:0]="0101", V N2 The voltage at is pulled down by capacitor 168 of weight (8), capacitor 166 of weight (2), and capacitor 182 of weight (1), while V N1The voltage at node N1 is pulled down by capacitor 147 of weight (4) and capacitor 146 of weight (2). If the q data value q[3:0] is greater than the weight data value w[3:0], the voltage at node N1 will be lower than the voltage at node N2 (for example, if q[3:0]="1000" and w[3:0]="0111", then V N2 The voltage at is pulled down by capacitor 168 of weight (8), capacitor 167 of weight (4), capacitor 166 of weight (2), and capacitor 182 of weight (1), while V N1 The voltage at is pulled down by the capacitor 149 of the weight (16).

[0089] Voltage V N1 and V N2 are applied to the gates of transistors 145 and 165, respectively. In response, transistors 145 and 165 provide analog voltages Vq and Vw to pass gate circuits 190 and 191, respectively. After the Vq and Vw voltages are generated, enable signal EN / EN# is activated, turning on pass gate circuits 190 and 191, thereby inputting the analog Vq and Vw voltages to differential comparator 1100. If the q data value q[3:0] is greater than the weight data value w[3:0], then V N1 The voltage at N2 , causing the voltage at Vq to be less than the voltage at Vw. Under this condition, the differential comparator 1100 latches a logic high voltage (Vdd), which is provided as the comparison output out[0]. According to one embodiment, a "match" condition is specified when the q data value q[3:0] is greater than the weight data value w[3:0].

[0090] If the q data value q[3:0] is not greater than the weight data value w[3:0], V N1 The voltage at N2 , which causes the voltage at Vq to be greater than the voltage at Vw. In this state, differential comparator 1100 latches a logic low voltage (ground), which is provided as the comparator output, out[0].

[0091] The differential comparator 1100 is designed to perform a latching operation in response to a voltage difference equal to or greater than a capacitor with a weight of 1. In one embodiment, the transistors that make up the differential comparator 1100 are low threshold voltage transistors fabricated using MST technology, and are designed to perform a latching operation reliably in this manner.

[0092] As described above, wDAC 1300 and qDAC 1310 operate as simple digital-to-analog converters (DACs) for 4-bit input data values ​​w[3:0] and q[3:0], respectively, generating 16 analog values ​​stored on capacitors 150 and 170 (i.e., nodes N1 and N2). wDAC 1300 includes an additional offset capacitor 182, half the size of least significant bit capacitor 166, to significantly reduce the likelihood of a metastable condition occurring when w[3:0] and q[3:0] have identical values. The analog voltages on nodes N1 and N2 are forwarded to comparator 1320, and the resulting comparison output (e.g., out[0]) is buffered and sent to comparison output TSV 1211. This mimics the behavior of neurons in the brain much more efficiently than the transistor-based neuron structures used in typical machine learning implementations.

[0093] Current silicon implementations require orders of magnitude more power and larger chips to achieve the same processing power as a human brain, which consumes only roughly 20 watts of power. Because power is a key constraint, an advantage of using the inventive structure in artificial intelligence (AI) applications is that, similar to how a brain operates, the default state of the compare outputs is "no match." Power is only required to drive the TSV outputs 1211 if the compare outputs match, which, like a brain, rarely happens.

[0094] As described above, the processor 700 of the control / interface ASIC 102 obtains data from the DRAM arrays 800 and 804 of the DRAM chip 501 and transmits it to the qDACs 1310-1311. 63 Load it into the processor 700 and use it to 98 In one embodiment, the weight data loaded into the wDAC1300-130 98 The stored weight data to be loaded into is image data, and qDAC1310~131 63 The data loaded into the comparator circuits 1320-1322 may be data related to a video feed being searched for object (e.g., face) recognition. 255 indicates whether a match occurs for each set of 4-bit values ​​based on a comparison of the voltage levels from wDAC 130 and qDAC 131, as will be understood by those skilled in the art. In the embodiment described herein, the actual processing of the entire set of comparison outputs output on TSV 1211 is performed in control / interface ASIC chip 102.

[0095] In the above embodiments, the data granularity is 64-bit or 128-bit. Further granularity is possible at the control / interface ASIC 102 level. Note that data output from the DRAM arrays 800-807 may be broadcast to both the standard output data paths 1241-1244 and the comparator arrays 1221-1224. The inputs of each path may be selected / deselected, and the comparator data output paths 1211-1214 may be enabled simultaneously with the standard data output paths 1241-1244, if desired. Note also that the size of the comparator arrays 1221-1224 is flexible and can be adjusted depending on the application.

[0096] In comparison, in typical machine learning configurations, the bit lines of an SRAM are used as inputs to a comparator, but the bit line / bit cell system has a large nonlinearity, resulting in a discriminative resolution of 3 bits (2 3However, the above configuration can be limited to 4 bits (2 = 8 stages) by using MST devices, especially at the comparator input stage. 4 16)。 Also, although the comparator array 1221-1224 has been described above with reference to a DRAM implementation (i.e., in relation to q data inputs received from DRAM arrays 800-807), it should be noted that the comparator array may be used in other circuit configurations, such as, for example, a logic chip or flash memory implementation.

[0097] While the present invention has been described in connection with several embodiments, it is to be understood that the invention is not limited to the disclosed embodiments, but is capable of various modifications apparent to those skilled in the art. Accordingly, the invention is limited only by the following claims.

Claims

1. a first integrated circuit chip including a first processor; a second integrated circuit chip comprising a first dynamic random access memory (DRAM) sector; The first dynamic random access memory (DRAM) sector comprises: a first plurality of DRAM arrays; a first output circuit configured to store a first plurality of data values ​​read from the first plurality of DRAM arrays; a first set of through silicon vias (TSVs) connecting the first processor to the first DRAM sector and for transmitting a first plurality of weight data values ​​from the first processor to the first DRAM sector; a first plurality of comparator arrays connected to receive the first plurality of weighted data values ​​and the first plurality of data values ​​read from the first plurality of DRAM arrays and to generate a first plurality of comparison output values ​​in response thereto; and a second set of through-silicon vias connecting the first processor to the first DRAM sector and for transmitting the first plurality of compare output values ​​from the first DRAM sector to the first processor.

2. a third set of through-silicon vias (TSVs) connecting the first processor to the first DRAM sector; 2. The memory system of claim 1, wherein the first processor transmits addresses on the third set of through silicon vias to read the first plurality of data values ​​from the first plurality of DRAM arrays.

3. the first integrated circuit chip further comprising: a second processor; an interconnect structure connecting the first processor to the second processor; the second integrated circuit chip further having a second dynamic random access memory (DRAM) sector; the second dynamic random access memory (DRAM) sector comprises: a second plurality of DRAM arrays; a second output circuit configured to store a second plurality of data values ​​read from the second plurality of DRAM arrays; a third set of silicon vias (TSVs) connecting the second processor to the second DRAM sector and for the second processor to transmit a second plurality of weight data values ​​to the second DRAM sector; a second plurality of comparator arrays that receive the second plurality of weighted data values ​​and the second plurality of data values ​​read from the second plurality of DRAM arrays and generate a second plurality of comparison output values ​​in response thereto; and 2. The memory system of claim 1, further comprising a fourth set of through silicon vias for connecting the second processor to the second DRAM sector and transmitting the second plurality of compare output values ​​from the second DRAM sector to the second processor.

4. 4. The memory system of claim 3, wherein said first DRAM sector is configured not to communicate with said second DRAM sector in said second integrated circuit chip.

5. a third integrated circuit chip having a second dynamic random access memory (DRAM) sector; the second dynamic random access memory (DRAM) sector comprises: a second plurality of DRAM arrays; a second output circuit configured to store a second plurality of data values ​​read from the second plurality of DRAM arrays; a third set of through-silicon vias (TSVs) connecting the first processor to the second DRAM sector and for the first processor to transmit a second plurality of weight data values ​​to the second DRAM sector; a second plurality of comparator arrays that receive the second plurality of weighted data values ​​and the second plurality of data values ​​read from the second plurality of DRAM arrays and generate a second plurality of comparison output values ​​in response thereto; a fourth set of through silicon vias connecting the first processor to the second DRAM sector and for transmitting the second plurality of compare output values ​​from the second DRAM sector to the first processor.

6. 2. The memory system of claim 1, further comprising a third integrated circuit chip connected to the first integrated circuit chip and the second integrated circuit chip by a third set of through silicon vias (TSVs) and supplying multiple power supply voltages to the first integrated circuit chip and the second integrated circuit chip at the third set of through silicon vias.

7. the first array of multiple comparators comprising: a first digital-to-analog converter (DAC) configured to receive multi-bit weighted data values ​​from the first plurality of weighted data values ​​and to generate a first analog output signal in response thereto; a second digital-to-analog converter configured to receive a multi-bit data value of the first plurality of data values ​​read from the first plurality of DRAM arrays and to generate a second analog output signal in response thereto; a comparator circuit configured to receive the first analog output signal and the second analog output signal and to provide one of the first plurality of comparison output values ​​in response thereto.

8. the first digital-to-analog converter: a first capacitor structure directly connected to the first node; a first plurality of capacitor structures; a first plurality of transistors; 8. The memory system of claim 7, wherein each of the first plurality of capacitor structures is connected to the first node through a corresponding one of the first plurality of transistors, each of the plurality of transistors having a gate connected to receive a corresponding bit of the multi-bit weighted data value.

9. 9. The memory system of claim 8, wherein the first capacitor structure and the first plurality of capacitor structures each include a different number of identical capacitors.

10. the first digital-to-analog converter: an offset capacitor structure; 10. The memory system of claim 9, further comprising: an offset transistor connecting said offset capacitor structure to said first node and having a gate connected to receive an offset control signal.

11. the second digital-to-analog converter: a second capacitor structure directly connected to a second node and having the same structure as the first capacitor structure; a second plurality of capacitor structures having the same structure as the first plurality of capacitor structures; a second plurality of transistors; 9. The memory system of claim 8, wherein each of the second plurality of capacitor structures is connected to the second node by a corresponding one of the second plurality of transistors, each of the second plurality of transistors having a gate connected to receive a corresponding bit of the multi-bit data value.

12. the first digital-to-analog converter includes a first output circuit that generates the first analog output signal in response to a voltage at the first node; 12. The memory system of claim 11, wherein the second digital-to-analog converter includes a second output circuit that generates the second analog output signal in response to a voltage at the second node.

13. 13. The memory system of claim 12, wherein the comparator circuit includes a differential comparator responsive to the first analog output signal and the second analog output signal to latch one of the first plurality of comparison output values.

14. 8. The memory system of claim 7, wherein the comparator circuit activates one of the first plurality of comparison output values ​​to a logic high voltage state only if the multi-bit data value is greater than the multi-bit weighted data value.

15. 2. The memory system of claim 1, wherein said first plurality of comparator arrays includes a plurality of latches for storing said plurality of weight data values ​​and into which said plurality of weight data values ​​are sequentially loaded.

16. The plurality of comparator arrays include: a plurality of rows of q data digital-to-analog converters, each connected to receive a corresponding plurality of bits of the first plurality of data values; a plurality of rows of weight data digital-to-analog converters, each connected to receive a corresponding plurality of bits of said plurality of weight data values; 2. The memory system of claim 1, further comprising: a plurality of columns of comparator circuits, each column of comparator circuits being disposed between one of the columns of q data digital-to-analog converters and one of the columns of weight data digital-to-analog converters.

17. transmitting a first comparison instruction and a corresponding first plurality of weight data values ​​from a first processor in a first integrated circuit chip to a first dynamic random access memory (DRAM) sector having a first plurality of DRAM arrays in a second integrated circuit chip; reading a first plurality of data values ​​from the first plurality of DRAM arrays in response to the first compare command; generating a first plurality of comparison output values ​​in response to the first plurality of data values ​​and the first plurality of weighted data values; transmitting the first plurality of compare output values ​​from the first DRAM sector to the first processor.

18. transmitting the first compare instruction and the first plurality of weight data values ​​over a first set of through silicon vias (TSVs) connecting the first processor and a first DRAM sector; 20. The method of claim 17, further comprising: transmitting the first plurality of compare output values ​​over a second set of through silicon vias connecting the first processor and a first DRAM sector.

19. generating a first analog output signal in response to multi-bit weight data values ​​included in the first plurality of weight data values; generating a second analog output signal in response to multi-bit data values ​​included in the first plurality of data values ​​read from the first plurality of DRAM arrays; and generating one of the first plurality of comparison output values ​​in response to the first analog output signal and the second analog output signal.

20. transmitting, from a second processor in the first integrated circuit chip, a second comparison instruction and a corresponding second plurality of weight data values ​​to a second dynamic random access memory (DRAM) sector having a second plurality of DRAM arrays in the second integrated circuit chip; reading a second plurality of data values ​​from the second plurality of DRAM arrays in response to the second compare command; generating a second plurality of comparison output values ​​in response to the second plurality of data values ​​and the second plurality of weighted data values; and transmitting the second plurality of compare output values ​​from the second DRAM sector to the second processor.

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