Method for testing the robustness of semiconductor wafers made of single-crystal silicon against thermal stress

Abstract

1. A method for testing the robustness of semiconductor wafers made of single crystal silicon against thermal stress, comprising: subjecting the semiconductor wafers to a heat treatment in a vertical furnace that is consistent with the properties of the semiconductor material; the semiconductor wafers having a diameter and being placed on contact sites of several fingers of a boat; the distance of the contact sites from an edge of the semiconductor wafer being greater than or equal to 5% and less than or equal to 40% of the diameter of the semiconductor wafer; and performing a BFA analysis of one or more regions of the semiconductor wafer surrounding the contact sites using a SIRD system; the shortest distance of the one or more regions from the edge of the semiconductor wafer being greater than or equal to 1 mm and less than or equal to 33% of the diameter of the semiconductor wafer.

Description

[Technical Field]

[0001] The present invention provides a method for testing semiconductor wafers made of single crystal silicon for their resistance to thermally induced stress, which can lead to plastic deformation of the semiconductor wafer and adversely affect the yield of semiconductor components. [Background technology]

[0002] Prior art / issues Manufacturers of electronic devices require semiconductor wafers that are mechanically robust in high temperature processes and therefore require their semiconductor wafer suppliers to provide reliable information regarding the robustness of semiconductor wafers to thermal stresses.

[0003] US Patent Application Publication No. 20100015817 states that thermal processing of semiconductor wafers in a vertical furnace can cause thermal slippage due to contact stress of the fingers of the boat on which the semiconductor wafers rest during thermal processing (wafer support).

[0004] US Patent Application Publication No. 20020119641 describes high temperature processing of silicon substrates in which a boat with polysilicon fingers is used.

[0005] US Patent Application Publication No. 20040021097 describes how SIRD (Scanning Infrared Depolarization) can be used to investigate mechanical stress in semiconductor wafers.

[0006] JP 2015-73049 A shows that thermal stress and strain can be quantitatively explained by SIRD and BFA (Bad Fraction Area).

[0007] According to JP 2006269896 A, the duration and temperature of the heat treatment affect the generation of thermal stress.

[0008] US Patent Application Publication No. 20160247694 describes a method for evaluating the quality of silicon semiconductor wafers with respect to their robustness to thermal stress. One of the findings was that the higher the concentration of interstitial oxygen and the lower the temperature of the heat treatment applied to the semiconductor wafer under test to induce stress, the higher the critical stress. Summary of the Invention [Problem to be solved by the invention]

[0009] The object of the present invention is to provide a method that allows evaluation of the robustness of silicon semiconductor wafers against thermal stress in a simple manner with high reliability and reproducibility. [Means for solving the problem]

[0010] The object of the present invention is to provide a method for testing the robustness of semiconductor wafers made of monocrystalline silicon against thermal stresses, comprising the steps of: A method for manufacturing a semiconductor wafer in a vertical furnace, the method comprising: subjecting a semiconductor wafer to a heat treatment suitable for the characteristics of the semiconductor material in a vertical furnace; the semiconductor wafer having a diameter and placed on contact portions of some fingers of a boat; and a distance from an edge of the semiconductor wafer to the contact portions being 5% or more and 40% or less of the diameter of the semiconductor wafer; This is achieved by a method comprising performing a BFA analysis of one or more regions of a semiconductor wafer surrounding the contact site using a SIRD system, wherein the shortest distance from the edge of the semiconductor wafer to the one or more regions is greater than or equal to 1 mm and less than or equal to 33% of the diameter of the semiconductor wafer.

[0011] The inventors of the present invention have discovered that an easily performed and reproducible test can be designed when a heat treatment consistent with the semiconductor material being tested is performed in a vertical furnace, the semiconductor wafer being tested is placed on the fingers of a long-finger boat, and the distance of the contact sites from the edge of the semiconductor wafer is relatively long. This increases the distance that thermal dislocations must travel to reach the edge of the semiconductor wafer, preventing edge effects from affecting the test results. The positions of the contact sites where the semiconductor wafer being tested contacts the fingers of the boat are the same for all semiconductor wafers being tested. The number of fingers, and therefore the number of contact sites, is at least three, and preferably three or four.

[0012] The semiconductor wafers to be tested consist of monocrystalline silicon and preferably have a diameter of at least 200 mm. For example, it is possible to test substrate wafers made of monocrystalline silicon with polished side surfaces, or substrate wafers with an additional epitaxial layer deposited on the upper surface, or SOI (silicon-on-insulator) wafers.

[0013] Regarding the properties of semiconductor materials that are important for the design of thermal processes, the parameters considered are, in principle, all parameters that affect the mechanical stability of the semiconductor material under thermal stress. In the case of semiconductor wafers made of silicon, these are, for example, the concentration of interstitial oxygen (Oi) and the electrical resistivity, which depends on the concentration of electrically active dopants.

[0014] The duration and temperature of the heat treatment are tailored to the characteristics of the semiconductor material of the semiconductor wafer being tested. The heat treatment is intended to induce stress, the extent of which remains in the depolarization map in the region in the form of slip lines, which are analyzed by BFA analysis. Of course, it is also possible to test semiconductor wafers whose semiconductor material characteristics are unknown. If a test with the selected heat treatment proves unsatisfactory, it may be necessary to perform a test on the same type of semiconductor wafer, but with a different heat treatment. The heat treatment is designed so that its duration at the target temperature is long enough to induce thermal dislocations / slip, but short enough to be economical and avoid the formation of slip lines that extend to the edge of the semiconductor wafer. The duration of the heat treatment at the target temperature is preferably 5 to 30 minutes. The atmosphere in which the heat treatment is performed may be selected independently of the semiconductor material. Suitable examples are oxygen, nitrogen, or a noble gas such as argon, or a combination of the aforementioned gases.

[0015] Prior to this heat treatment, the semiconductor wafer under test may have already been subjected to a previous heat treatment (pre-annealing), such as a heat treatment for developing oxygen precipitate nuclei into bulk micro defects (BMDs) or a rapid thermal anneal (RTA) treatment. If the previous heat treatment is also performed on a boat in a vertical furnace, it is preferable that the contacts of the boat do not overlap. To achieve this, the semiconductor wafer may be rotated after the previous heat treatment and placed in the boat. The previous heat treatment for BMD development preferably involves heating the semiconductor wafer in an oxygen atmosphere at a temperature of 780°C for 3 hours, then at a temperature of 1000°C for 16 hours.

[0016] It is proposed to provide at least two different heat treatments for semiconductor wafers made from monocrystalline silicon doped p-type with boron. One heat treatment is for the relatively lightly doped (p -The other heat treatment corresponds to a semiconductor material containing a relatively large amount of dopants (p + This applies to doped (non-doped) semiconductor materials, i.e., semiconductor materials with a specific electrical resistivity of 100 mOhm-cm or less. Simple experimentation can reveal whether and how the heat treatment conditions need to be adjusted when additional dopants or dopants other than boron are present in the semiconductor wafer. The design of the boat area at the contact site also affects the mechanical stress on the semiconductor wafer, and such testing should take this fact into account, if necessary. The purpose of the test is to induce stress / glide dislocations through the heat treatment, the extent of which remains within a specific region around the boat contact site and can be characterized using the SIRD system.

[0017] Table 1 below contains the temperature steps (change temperatures) and the rate of temperature change (change rate) for two preferred heat treatments in oxygen and nitrogen atmospheres, namely Program 1 (left) and Program 2 (right), which differ in particular by different target temperatures of 1100°C and 1200°C. Program 1 is - Particularly suited to testing semiconductor wafers made of doped 300 mm diameter monocrystalline silicon, Program 2 is p + Doped semiconductor wafer or pp + It is particularly suited to testing epitaxially coated semiconductor wafers made of single crystal silicon of the type. The heat treatment is optimized for use with polysilicon boats sold by Ferrotec Material Technologies Corporation.

[0018] [Table 1]

[0019] After the heat treatment and any preceding heat treatments, BFA analysis is performed using a SIRD system. The SIRD system provides a diagram of the stress field in the form of a depolarization map (whole wafer map), optionally smoothed by a high-pass filter, that represents the depolarization as a function of position on the region of the semiconductor wafer. It is preferable to use the highest resolution offered by the SIRD system. The process of the present invention contemplates evaluation of depolarization limited to one or more regions around the boat contact points where contact occurred between the semiconductor wafer and the boat fingers during the heat treatment. The distance of the contact site from the edge of the semiconductor wafer is between 5% and 40% of the diameter of the semiconductor wafer, preferably between 10% and 35% of the diameter of the semiconductor wafer, and more preferably 45 mm or more for a 300 mm diameter semiconductor wafer. The shortest distance of the one or more regions from the edge of the semiconductor wafer is between 1 mm and 33% of the diameter of the semiconductor wafer, preferably between 3 mm and 25% of the diameter of the semiconductor wafer, and more preferably 10 mm or more for a 300 mm diameter semiconductor wafer. Such a distance from the edge is advantageous because it makes it possible to almost completely eliminate the influence of the edge on the depolarization, so that the measurement result essentially depends on the properties of the semiconductor material itself.

[0020] The one or more regions are preferably circular, and if more than one of them is used, their radii are preferably the same. Circular regions with a contact site at their center or with two or more contact sites can be used. Shapes other than circular are also possible, such as rectangular or square region(s), or regions with a triangular or ring shape.

[0021] During the BFA analysis, depolarization is determined for cells of a virtual grid placed on the depolarization map. The grid preferably consists of square cells, each with a side length of preferably 2 mm. If the depolarization value of a cell within a region exceeds a set threshold, the cell is counted as a defective cell. The set threshold preferably has upper and lower limits of ±10 DU to ±30 DU. The ratio of the number of defective cells to the number of all evaluated cells is a measure of the semiconductor wafer's resistance to thermal stress. Cells that are not entirely within a region are counted only if their area is at least 50%. This evaluation can be selectively achieved by determining this ratio for one, two, or more, or each of one or more regions, and optionally averaging a portion of the results. Additionally, the distribution of defective cells within one or more regions can be statistically evaluated to describe the degree or uniformity of the stress field within one or more regions.

[0022] Analysis of highly doped semiconductor wafers made of silicon with SIRD systems has physical limitations: above a resistivity in the region of less than 6 mOhm cm, absorption by free charge carriers begins to impede the transmission of IR radiation.

[0023] The invention will be further explained below, by way of example, with reference to the drawings, in which: [Brief explanation of the drawings]

[0024] [Figure 1] A typical depolarization map is shown highlighting the circular area where the BFA analysis was performed. [Figure 2] One of the regions is shown with a virtual grid superimposed on it. [Figure 3] 1 shows the results of BFA analysis of various groups of single crystal silicon semiconductor wafers. DETAILED DESCRIPTION OF THE INVENTION

[0025] Detailed Description of Embodiments of the Invention FIG. 1 shows a depolarization map of a semiconductor wafer 1 made of single-crystal silicon, highlighting three circular regions 2 where BFA analysis was performed. The center of region 2 is the contact site 2, where contact occurred between the semiconductor wafer 1 and the boat finger during thermal treatment. The distance of contact site 3 from the edge 4 of the semiconductor wafer is a required length. As a result of thermal stresses and gravitational mechanical stresses at and around the contact site, slip / dislocation lines 5 extend toward the edge 4 of the semiconductor wafer 1 along energetically favorable crystallographic planes. The distance between the edge 4 of the semiconductor wafer 1 and region 2 is a required length so that defects propagating from the edge 4, which affect the stress field, have little effect on the depolarization in region 2. Additionally, the thermal treatment is tailored to the properties of the semiconductor material so that the slip lines 5 do not extend to the edge 4 and do not exit region 2. For example, a higher target temperature and / or a longer duration of the thermal treatment may result in the slip lines extending to the edge of the semiconductor wafer.

[0026] Figure 2 shows one of the circular areas 2 with a virtual grid 6 superimposed thereon for evaluation by BFA analysis. Cells counted as bad cells are represented by dots.

[0027] Example The thermal stress robustness of semiconductor wafers made of single-crystal silicon was tested in three test runs, with six groups of five semiconductor wafers each. All semiconductor wafers had a diameter of 300 mm and were doped with boron.

[0028] The material properties of the semiconductor wafers with respect to the degree of doping with boron and the concentration of interstitial oxygen are entered in Table 2. The semiconductor wafers of groups 1 to 3 were substrate wafers with polished side surfaces, while the semiconductor wafers of groups 4 to 6 additionally had an epitaxially deposited p-doped layer of silicon on the upper surface.

[0029] [Table 2]

[0030] Each semiconductor wafer was placed on three fingers of a long-finger boat manufactured by Ferrotec Materials Technologies Corporation, and the semiconductor wafers in groups 1 to 4 were subjected to a heat treatment according to Program 1, and the semiconductor wafers in groups 5 and 6 were subjected to a heat treatment according to Program 2 in a vertical furnace manufactured by ASM International NV.

[0031] Subsequently, BFA analysis was performed on a circular area with a radius of 40 mm around the contact site where contact between the semiconductor wafer and the boat fingers existed during the heat treatment using a SIRD system from PVA Metrology & Plasma Solutions GmbH. The shortest distance of the three areas from the edge of the semiconductor wafer was optimal in each case to be approximately 10 mm.

[0032] The high-pass filtered depolarization maps provided by the SIRD system were evaluated in these regions; for this purpose, a depolarization threshold of ±10 DU (depolarization unit) was fixed. The results of the BFA analysis are the percentage ratios bcf (bad cell fraction) of the number of bad cells in the three regions to the number of cells in the three regions.

[0033] Figure 3 shows this result for semiconductor wafers from groups 1 to 6, for each test run. As expected, robustness to thermal stress increases with the concentration of interstitial oxygen, and p + In the case of doped semiconductor wafers, - This is more pronounced than for the doped semiconductor wafers. The variability of the measurement results from test runs is small, indicating good reproducibility of the test method. The obvious outliers in the results for semiconductor wafers from Group 6 were explained by the fact that the corresponding semiconductor wafers were obtained from single crystals grown from different sources. [Explanation of symbols]

[0034] List of reference numbers used 1. Semiconductor wafer 2 areas 3 Contact area 4. Edge 5. Sliding Line 6 lattice

Claims

1. 1. A method for testing the thermal stress robustness of a semiconductor wafer made of single crystal silicon, comprising: A method for manufacturing a semiconductor wafer in a vertical furnace, the method comprising: performing a heat treatment on a semiconductor wafer in accordance with characteristics of the semiconductor material, the semiconductor wafer having a diameter and being placed on contact portions of some fingers of a boat, the distance from an edge of the semiconductor wafer to the contact portions being 5% or more and 40% or less of the diameter of the semiconductor wafer; performing a BFA analysis of one or more regions of the semiconductor wafer surrounding the contact site with a SIRD system, wherein a shortest distance of the one or more regions from the edge of the semiconductor wafer is greater than or equal to 1 mm and less than or equal to 33% of the diameter of the semiconductor wafer.

2. 10. The method of claim 1, comprising selecting the heat treatment depending on the concentration of interstitial oxygen and / or the electrical resistivity of the semiconductor wafer.

3. performing a heat treatment prior to the heat treatment; The method of claim 1 or 2, wherein the semiconductor wafer is placed on the fingers of the boat at a further contact site, the contact site and the further contact site not overlapping.

4. 4. The method according to claim 1, wherein the semiconductor wafer has a diameter of 300 mm, and the distance from the edge of the semiconductor wafer to the contact location is 45 mm or more.

5. 5. The method according to claim 1, wherein the semiconductor wafer has a diameter of 300 mm, and the shortest distance from the edge of the semiconductor wafer to each of the regions is 10 mm or more.

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