Reactive series resistance reduction for magnetoresistive random access memory devices

Abstract

A semiconductor device includes a substrate, a crystalline bottom electrode layer on an upper side of the semiconductor substrate, a conductive crystalline metal layer above the crystalline bottom electrode layer, and a conductive oxide layer above the conductive crystalline metal layer. The conductive oxide layer has low resistance. The semiconductor device also includes a magnetic tunnel junction (MTJ) above the conductive crystalline metal layer, the MTJ including a tunnel barrier layer, a free layer on a first side of the tunnel barrier layer, and a reference layer on a second side of the tunnel barrier layer opposite the first side.

Description

[Technical Field]

[0001] FIELD OF THE DISCLOSURE This disclosure relates generally to structures and methods of fabricating semiconductor devices including magnetoresistive random-access memory (MRAM), and more particularly to structures and methods of fabricating semiconductor devices including magnetic tunnel junctions (MTJs) having ordered alloy layers forming the reference and / or free layers of the MTJs. [Background technology]

[0002] MRAM cells utilize the quantum mechanical effect of electron tunneling through an insulating layer disposed between two ferromagnetic layers, a free layer and a reference layer. The tunnel magnetoresistance (TMR) of an MRAM cell can be switched between a first state of low resistance, in which the two ferromagnetic layers have parallel magnetic dipole moments, and a second state of high resistance, in which the two ferromagnetic layers have antiparallel magnetic dipole moments. Switching the free layer magnetic dipole moment is achieved by changing the magnetic dipole moment of the free ferromagnetic layer of the MRAM cell. The change occurs when a write current is passed through the MRAM cell stack.

[0003] For a standard connected MRAM cell stack, TMR can be calculated as the AP state resistance minus the parallel state resistance divided by the parallel state resistance plus any circuit parasitic series resistance. The parasitic series resistance is due to circuit elements located between the MRAM cell stack and the associated access transistor. Resistance increases with the distance between the MRAM cell stack and the transistor because the amount of material through which the write current passes increases. To read an MRAM cell, a known voltage is applied to the cell and the current passing through the cell is detected. The AP and P states each result in a different current. The higher the TMR, the greater the difference between the two read currents, and the greater the degree of sensing capability of the MRAM cell.

[0004] A typical MRAM cell may comprise an array of MTJs connected by bit lines and word lines to form a circuit. The seed layer structure for the bottom free layer of the MTJ stack faces several challenges, including the need for a highly textured and ordered seed layer material, such as a Heusler material. Furthermore, a good retention vs. write current tradeoff involves the device free layer being grown on a leaky oxide layer to reduce spin pumping while avoiding adding series resistance to the device. Summary of the Invention

[0005] According to an embodiment of the present disclosure, a semiconductor device is provided. The semiconductor device includes a substrate extending along a first axis defining a length, a second axis orthogonal to the first axis defining a width, and a third axis orthogonal to the first and second axes defining a height. Also present is a crystalline bottom electrode layer on an upper side of the semiconductor substrate, a conductive crystalline metal layer above the crystalline bottom electrode layer, and a conductive oxide layer above the conductive crystalline metal layer. The conductive oxide layer has a low resistance as described herein. Above the conductive crystalline metal layer is a magnetic tunnel junction (MTJ), the MTJ including a tunnel barrier layer, a free layer on a first side of the tunnel barrier layer, and a reference layer on a second side of the tunnel barrier layer opposite the first side. As a result, structures for advanced MRAM devices and memory and cache for server chips can be obtained. The semiconductor device can also be easily detectable due to tracking elements in the conductive oxide layer.

[0006] In one embodiment, the free layer is an ordered alloy.

[0007] In one embodiment, the reference layer is an ordered alloy.

[0008] In one embodiment, the conductive oxide layer is a shunted MgO layer and further comprises a material such as lithium (Li), aluminum (Al), scandium (Sc), or other rare earth metals such as gadolinium (Gd) or yttrium (Y).

[0009] In one embodiment, the ordered alloy is a Heusler alloy or a tetragonal material.

[0010] In one embodiment, a method for manufacturing a semiconductor device is disclosed. The method includes depositing an amorphous bottom electrode layer on a semiconductor substrate. A conductive amorphous metal layer is deposited on the amorphous bottom electrode layer. An amorphous reactive material is deposited on the conductive amorphous metal layer. An insulating oxide layer is deposited on the amorphous reactive template. An ordered alloy structure including a free layer or a reference layer is deposited on the insulating oxide layer. A tunnel barrier layer is then deposited on the ordered alloy structure, and a stack annealing process is performed on the semiconductor device. During the stack annealing process, the amorphous reactive material reacts with and shunts the insulating oxide layer to form a conductive oxide layer. The conductive amorphous metal layer is initially deposited as an amorphous structure and becomes crystalline after the stack annealing process. Similarly, the amorphous bottom electrode layer can be initially deposited as an amorphous structure and become crystalline after the stack annealing process. Advantageously, advanced MRAM devices, as well as memories and caches for server chips, can be formed from this method, and the associated series resistance introduced into the MRAM stack from the relatively thick insulating oxide layer can be significantly reduced.

[0011] In one embodiment, the ordered alloy structure includes a base / seed layer, and the method includes depositing the base / seed layer on an insulating oxide layer before depositing a free layer or reference layer on the base / seed layer.

[0012] In one embodiment, the free layer is deposited on a base / seed layer, and following the steps of depositing the free layer on the base / seed layer and the tunnel barrier layer on the free layer, another conductive amorphous metal layer is deposited on the tunnel barrier layer, a synthetic antiferromagnetic (SAF) layer is deposited on the other conductive amorphous metal layer, and a reference layer is deposited on the SAF to provide a bottom free layer MTJ device.

[0013] In one embodiment, a reference layer is deposited on the base / seed layer. Following deposition of the reference layer on the base / seed layer and the tunnel barrier layer on the reference layer, a free layer is deposited on the tunnel barrier layer. An oxide cap layer is deposited on the free layer, and a top electrode layer is deposited on the oxide cap layer to provide a top free layer MTJ device.

[0014] The techniques described herein may be implemented in many ways. An example implementation is shown below with reference to the following figure. [Brief explanation of the drawings]

[0015] The drawings are of exemplary embodiments. The drawings do not depict all embodiments. Other embodiments may be used in addition or instead. Details that may be obvious or unnecessary may be omitted to save space or for a more effective illustration. Some embodiments may be practiced with additional components or steps and / or without all components or steps shown. When the same numeral appears in different drawings, it refers to the same or similar components or steps.

[0016] [Figure 1] 1A-1D illustrate cross-sectional views of a semiconductor device at intermediate and final stages showing an ordered alloy free layer configuration, according to an exemplary embodiment.

[0017] [Figure 2]1A-1C illustrate cross-sectional views of a semiconductor device in intermediate and final stages showing a bottom free layer MTJ device with an ordered alloy free layer configuration according to an exemplary embodiment.

[0018] [Figure 3] 1A-1C illustrate cross-sectional views of a semiconductor device at intermediate and final stages showing a top free layer MTJ device with an ordered alloy reference layer configuration according to an exemplary embodiment.

[0019] [Figure 4] 1 illustrates a cross-sectional view of a semiconductor device showing a starting substrate with an amorphous bottom electrode layer according to an illustrative embodiment.

[0020] [Figure 5] 1A-1C illustrate cross-sectional views of a semiconductor device after various manufacturing processes are applied to a starting substrate and an amorphous bottom electrode layer, according to an exemplary embodiment.

[0021] [Figure 6] 1 illustrates a cross-sectional view of a semiconductor device following deposition of an amorphous reactive material, according to an illustrative embodiment.

[0022] [Figure 7] 1 illustrates a cross-sectional view of a semiconductor device following deposition of an insulating oxide layer, according to an illustrative embodiment.

[0023] [Figure 8] 1 illustrates a cross-sectional view of a semiconductor device following deposition of an ordered alloy structure, according to an exemplary embodiment.

[0024] [Figure 9] 2 illustrates a cross-sectional view of a semiconductor device following deposition of a tunnel barrier layer, according to an illustrative embodiment.

[0025] [Figure 10] 1 illustrates a cross-sectional view of a semiconductor device following deposition of a reference layer and one or more subsequent manufacturing processes, according to an exemplary embodiment.

[0026] [Figure 11] 1 illustrates a cross-sectional view of a semiconductor device following a stack annealing process, according to an exemplary embodiment.

[0027] [Figure 12] 1A-1C illustrate cross-sectional views of a semiconductor device at intermediate and final stages showing a top free layer magnetic tunnel junction device with an L10 ordered alloy reference layer configuration according to an exemplary embodiment.

[0028] [Figure 13] 1A-1D show cross-sectional views of a semiconductor device in intermediate and final stages illustrating a bottom free layer magnetic tunnel junction device with an ordered alloy free layer configuration according to an exemplary embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0029] [overview] In the following detailed description, numerous specific details are set forth by way of example in order to provide a thorough understanding of the relevant teachings. However, it should be apparent that the present teachings may be practiced without such details. In other instances, well-known methods, procedures, components, and / or circuits have been described at a relatively high-level, without detailed description, in order to avoid unnecessarily obscuring aspects of the present teachings.

[0030] In one aspect, spatially related terms such as "front," "back," "top," "bottom," "beneath," "below," "lower," "above," "upper," "side," "left," "right," and the like, are used with reference to the orientation of the figures being described. Because components of the embodiments of the present disclosure can be positioned in several different orientations, the orientation terms are used for purposes of illustration and not limitation. Thus, it will be understood that the spatial terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if a device in the figures were turned over, elements described as being "below" or "beneath" other elements or features would then be oriented "above" the other elements or features. Thus, for example, the term "below" can encompass both an orientation of above as well as below. The device may be oriented differently (rotated 90 degrees or viewed or referenced in other directions) and the spatial descriptors used herein should be interpreted accordingly.

[0031] As used herein, the terms "lateral" and "horizontal" describe an orientation parallel to the first surface of the chip.

[0032] As used herein, the term "vertical" describes an orientation that is disposed perpendicular to the first surface of the chip, chip carrier, or semiconductor body.

[0033] As used herein, the terms "coupled" and / or "electrically coupled" are not intended to imply that elements must be directly coupled together; intervening elements may be provided between the "coupled" or "electrically coupled" elements. In contrast, when an element is referred to as being "directly connected" or "directly coupled" to another element, there are no intervening elements present. The term "electrically connected" refers to a low ohmic electrical connection between elements that are electrically connected together.

[0034] Terms such as "first," "second," and the like may be used herein to describe various elements, but these elements should not be limited by these terms. These terms are used only to distinguish one element from another. For example, a first element may be referred to as a second element, and similarly, a second element may be referred to as a first element, without departing from the scope of the exemplary embodiments. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0035] Example embodiments are described herein with reference to cross-section illustrations that are schematic illustrations of idealized or simplified embodiments (and intermediate structures). As such, variations from the shapes of the illustrations due, for example, to manufacturing techniques and / or tolerances, are to be expected. Accordingly, the regions illustrated in the figures are schematic in nature and their shapes are not necessarily indicative of the actual shape of the regions of a device and do not limit its scope.

[0036] It is to be understood that other embodiments may be used and structural or logical changes may be made without departing from the spirit and scope as defined by the claims. The description of the embodiments is not intended to be limiting. In particular, elements of the embodiments described below may be combined with elements of different embodiments.

[0037] For the sake of brevity, conventional techniques for the manufacture of semiconductor devices and integrated circuits (ICs) may or may not be described in detail herein. Moreover, various tasks and process steps described herein may be incorporated into more comprehensive procedures or processes having additional steps or functionality not described in detail herein. In particular, because the various steps in the manufacture of semiconductor devices and semiconductor-based ICs are well known, for the sake of brevity, many conventional steps will only be briefly described herein or will be omitted entirely without providing well-known process details.

[0038] Fabrication of the structures described herein may comprise a multi-step sequence of photolithographic and / or chemical processing steps that facilitate the gradual creation of electronic-based systems, devices, components, and / or circuits within, for example, semiconductor and / or superconducting devices (e.g., integrated circuits). For example, devices herein may be formed on one or more substrates (e.g., silicon (Si) substrates and / or other substrates) using techniques including, but not limited to, photolithography, microlithography, nanolithography, nanoimprint lithography, photomasking techniques, patterning techniques, photoresist techniques (e.g., positive photoresist, negative photoresist, hybrid photoresist, and / or other photoresist techniques), etching techniques (e.g., reactive ion etching (RIE), dry etching, wet etching, ion beam etching, plasma etching, laser ablation, and / or other etching techniques), evaporation techniques, sputtering techniques, plasma ashing techniques, thermal treatments (e.g., rapid thermal annealing, furnace annealing, thermal oxidation, and / or other thermal treatments), chemical vapor deposition (CVD), atomic layer deposition (ALD), physical vapor deposition (PVD), molecular beam epitaxy (MBE), and / or other techniques. The semiconductor device may be fabricated by utilizing techniques including molecular beam epitaxy (MBE), electrochemical deposition (ECD), chemical-mechanical planarization (CMP), backgrinding techniques, and / or other techniques for fabricating integrated circuits.

[0039] Referring here to an overview of the technology commonly associated with the present teachings, MRAM devices store data bits using magnetic states enabled by pairs of ferromagnetic metal plates separated by thin insulating material layers. The two plates and the insulating layer form a MTJ having one plate that is a reference layer that is fixed since its magnetic direction does not change, and another plate that is a free layer that is changeable since its magnetic direction can change when an applied bias is applied to the MTJ. The MRAM device can include a seed layer on which the free layer has grown. The seed layer structure for the bottom free layer of the MTJ stack faces several difficulties including magnetic alloys such as Heusler materials that can be used as regular alloys within the MRAM device and may require a highly textured and ordered seed layer material. Further, a good retention-to-write current trade-off can include a device free layer to be grown on a leakage oxide layer to reduce spin pumping while avoiding addition of series resistance to the device. The series resistance can increase as the thickness of the oxide layer increases. Thin oxide layers such as MgO-based oxides (<2 unit cell thickness of MgO, ~0.8 nm) can have leakage and can prevent spin pumping in a reasonable way to reduce the write current. However, their texture and crystal ordering can be insufficient for additional seed layer or template growth of regular magnetic alloys. Relatively thicker oxide layers such as MgO-based oxides (>2 unit cell thickness, ~0.8 nm) can have a higher degree of texture and ordering and can induce the crystal symmetry and ordering targeted for additional seed layer or regular magnetic alloys. Relatively thicker oxide layers can also be efficient in preventing spin pumping but can act as a second tunnel barrier in series with the main tunnel barrier and thus add resistance, lower the read signal, and increase the write voltage. Still further, highly regular magnetic alloys can be good candidates for the reference layer of the magnetic tunnel junction stack (a thick MgO seed layer can be, for example, an ideal layer to template the growth of Co-Pt having L10 symmetry). However, this can also create series resistance that can impede device performance if not prevented.

[0040] Various non-limiting embodiments of the present disclosure provide fabrication methods and resulting semiconductor devices implementing ordered alloy MTJ structures with a conductive oxide layer, such as a conductive MgO layer, where the ordered alloy forms the free and / or reference layers. An ordered alloy has a defined crystalline structure and is composed of at least two types of atoms that alternate positions with some regularity. Disposed below the ordered alloy layer can be a conductive oxide layer (e.g., a conductive MgO layer formed by reaction between an amorphous reactive material and an insulating oxide layer, e.g., a pre-reacted MgO material). Disposed above the ordered alloy layer can be a tunnel barrier layer, e.g., comprising an MgO layer. It may be desirable for the insulating oxide layer to be much thicker than a few monolayers (e.g., between 10-50 Å) during stack deposition to develop good crystallinity and texture. The crystalline insulating oxide layer acts as a template / seed for the subsequently deposited ordered alloy layer. Exemplary embodiments increase the effective thickness of the insulating oxide layer by disposing an amorphous reactive material below the insulating oxide layer during stack deposition. However, after stack deposition, the presence of a thick insulating oxide layer may no longer be necessary. The associated increased series resistance of the device caused by the thick insulating oxide layer may result in degraded performance of the MRAM device. Exemplary embodiments disclose a stack anneal post-processing routine in which the associated series resistance of the device may be significantly reduced by a reaction between the amorphous reactive material and the insulating oxide layer, which results in the formation of a conductive oxide layer with relatively low resistance. As a result, the associated series resistance of the device may be reduced, the growth of the free or reference layer material during deposition may be improved, and a thicker graded layer may be formed to lattice-match the advanced free / reference layer material. [Example Architecture]

[0041] 1 illustrates cross-sectional views of a semiconductor device 102 at intermediate and final stages of an ordered alloy free layer configuration consistent with an exemplary embodiment. The semiconductor device 102 includes a semiconductor substrate 104 extending along a first axis (e.g., an X-axis) to define a length, a second axis (e.g., a Y-axis) orthogonal to the X-axis to define a width, and a third axis (e.g., a Z-axis) orthogonal to the first and second axes to define a height. The semiconductor substrate 104 may be formed from a semiconductor material such as silicon (Si).

[0042] The term "semiconductor material" is used throughout this application to denote a material having semiconducting properties. The semiconductor material may be any suitable substrate material, such as single crystal silicon, silicon germanium alloy (SiGe), III-V compound semiconductors, II-VI compound semiconductors, or semiconductor-on-insulator (SOI). III-V compound semiconductors include materials having at least one group III element and at least one group V element, such as, for example, one or more of aluminum gallium arsenide (AlGaAs), aluminum gallium nitride (AlGaN), aluminum arsenide (AlAs), aluminum indium arsenide (AlIAs), aluminum nitride (AlN), gallium antimonide (GaSb), aluminum gallium antimonide (GaAlSb), gallium arsenide (GaAs), gallium arsenide antimonide (GaAsSb), gallium nitride (GaN), indium antimonide (InSb), indium arsenide (InAs), indium gallium arsenide (InGaAs), indium gallium arsenide phosphide (InGaAsP), indium gallium nitride (InGaN), indium nitride (InN), indium phosphide (InP), and combinations of alloys comprising at least one of the foregoing materials. Alloy combinations can include binary (two elements, e.g., gallium(III) arsenide (GaAs)), ternary (three elements, e.g., InGaAs), and quaternary (four elements, e.g., aluminum gallium indium phosphide (AlInGaP)) alloys.

[0043] The semiconductor device 102 may further comprise, at an intermediate stage, an amorphous bottom electrode layer 106 deposited on the top side of the semiconductor substrate 104. The amorphous bottom electrode layer 106 may be formed from depositing an amorphous material, such as amorphous Ta(N), deposited by chemical vapor deposition (CVD), physical vapor deposition (PVD), or a similar method. The amorphous material may crystallize after the annealing process described herein.

[0044] As shown in the figure, the deposition further includes a series of layers deposited on the amorphous bottom electrode layer 106 to form a perpendicular magnetic tunnel junction (MTJ) stack of the MRAM cell. In an embodiment, the MTJ stack shown includes a simplified MTJ formed from the amorphous bottom electrode layer 106, the reference layer 120 (i.e., a layer with a fixed magnetic dipole moment), the tunnel barrier layer 116, and the free layer 206 (the layer with a switchable magnetic dipole moment shown in FIG. 2), where the free layer 206 and the reference layer 120 can have perpendicular magnetic anisotropy.

[0045] More specifically, the conductive amorphous metal layer 110 is deposited above the amorphous bottom electrode layer 106 and may comprise an amorphous material such as a cobalt-iron-boron alloy (CoFeB) or a zirconium-cobalt (ZrCo) alloy. 2A conductive oxide layer 122 having a resistivity (ohm times micrometer squared) can be formed above the conductive amorphous metal layer 110 by the reaction between the amorphous reactive material 112 and the insulating oxide layer 114 as a result of the stack annealing process described herein. The low resistivity can provide a conductive oxide layer with negligible impact on the overall resistance of the device. During the post-processing stack anneal, the amorphous reactive material 112 reacts with the insulating oxide layer 114, making it more conductive. In the stack annealing process, the annealing temperature can be maintained, for example, at 300-425°C for a period of time (e.g., 30 seconds to 10 hours, or 60-120 minutes) before cooling. This reaction shorts the insulating oxide layer 114, reducing its insulating properties and thus significantly reducing the series resistance of the stack. For example, the resistance area product can be in the range >1 Ohm μm 2 (or typically 10-1000 Ohm μm 2 ) to 0.5 Ohm μm 2 Less than (or <0.1 Ohm μm 2 The amorphous reactive material 112 may be substantially (e.g., completely) consumed, leaving a target conductive crystalline metal layer 124 disposed directly beneath the newly formed conductive oxide layer 122. More specifically, the conductive amorphous metal layer 110 and the amorphous bottom electrode layer 106 become the conductive crystalline metal layer 124 and the crystalline bottom electrode layer 126, respectively, after the stack annealing process (e.g., amorphous CoFeB becomes crystalline CoFe). In various embodiments, the conductive oxide layer 122 may have a thickness of 1.5-3 nm.

[0046] In one or more non-limiting embodiments, the amorphous reactive material 112 comprises lithium-boron (LiB), aluminum-boron (AlB), scandium-boron (ScB), or other reactive rare earth metal-boron alloys (e.g., boron-erbium (Er-B), boron-samarium (Sa-B)). The boron in the alloy can ensure that the reactive material remains amorphous during and after deposition. Alternatively, the reactive material can be alloyed within or on top of the conductive amorphous metal layer 110. For example, in the case of a conductive amorphous metal layer 110 comprising CoFeB, an additional CoFeLiB, CoFeAlB, or CoFeScB layer can be formed on top of the original CoFeB layer, or the reactive material can be alloyed directly to the original CoFeB layer. The alloy can be CoFe-XB with a boron content of 40 to 60%. With the remaining 40-60% CoFeX alloy metal, X can be 10-60% or 25-45%. A high boron content is required to ensure that the complex alloy remains amorphous and has no magnetic moment.

[0047] The semiconductor device 102 may further comprise an MTJ including a tunnel barrier layer 116, a free layer 206 disposed on a first side of the tunnel barrier layer 116, and a reference layer 120 disposed on a second side of the tunnel barrier layer opposite the first side. The tunnel barrier layer 116 may comprise a non-magnetic insulating material such as magnesium oxide (MgO). The free layer 206 may be formed from an ordered alloy to provide an ordered alloy free layer. Similarly, the reference layer 120 may be formed from an ordered alloy to provide an ordered alloy reference layer. Thus, in the semiconductor device 102, at least one of the free layer 206 and the reference layer 120 may comprise an ordered alloy.

[0048] Additionally, the ordered alloy structure 108 may comprise a free layer 206 and a corresponding template or otherwise base / seed layer 202 for the free layer 206 (as shown in FIG. 2). The ordered alloy structure 108 may similarly comprise a reference layer 120 and a corresponding base / seed layer 202 for the reference layer 120, as shown in FIG. 3. More specifically, the ordered alloy layer of the ordered alloy structure 108 may comprise a seed, template, or wetting layer for growth on an insulating oxide layer / lattice. In one or more embodiments, the base / seed layer 202 may be CoAl.

[0049] In one or more embodiments, the ordered alloy may be a tetragonal material such as a Heusler alloy or AlMnGe. The Heusler alloy may include, for example, MnAl, MnCoSi, MnCoAl, MnCoAl, MnCuSi, MnCoGe, MnMnAl, CoCrAl, MnFeSb, MnCoSi, CoCrGe, CoCrSi, CoMnSi, CoMnSb, CoMnGe, MnCoAs, MnFeAs, FeMnSi, or MnMnAs.

[0050] Referring to FIG. 2 , cross-sectional views of a semiconductor device at intermediate and final stages are shown. The final stage shows the semiconductor device 102 after completion of an annealing process. FIG. 2 illustrates a bottom free layer MTJ device with an ordered alloy free layer configuration, according to an exemplary embodiment. In this configuration, the ordered alloy may form the free layer 206 disposed below the tunnel barrier layer 116. The reference layer 120 may be disposed above the tunnel barrier layer 116, with the conductive amorphous metal layer 110 and synthetic antiferromagnetic layer 118 deposited therebetween. The reference layer in FIG. 2 may include, for example, one or more interfacial layers, or spacers 204, and other layers 208, such as ruthenium, cobalt, palladium, tantalum, iron, boron, cobalt-platinum, or cobalt-palladium, in multilayers or mixtures.

[0051] FIG. 3 shows cross-sectional views of a semiconductor device at intermediate and final stages illustrating a top free layer MTJ device with an ordered alloy reference layer configuration, according to an exemplary embodiment. The final stage shows the semiconductor device 102 after completion of an annealing process. In this configuration, the locations of the reference layer and free layer are reversed, resulting in an MRAM cell with an inverted structure. The ordered alloy may form the reference layer 120, which is disposed below the tunnel barrier layer 116. The free layer 206 may be disposed above the tunnel barrier layer 116, followed by an oxide cap layer 302 and a top electrode layer 304. The oxide cap layer 302 may facilitate spin pumping. In this embodiment, the free layer 206 may include, for example, a cobalt-iron-boron alloy (CoFeB), and the reference layer may include, for example, Mn3Ge. In one or more embodiments, the reference layer has high perpendicular magnetic anisotropy (PMA), e.g., PMA > 1 Tesla, high spin polarization, and low magnetization (e.g., < 600 emu / cm 3 ) can be any ordered alloy (Heusler or tetragonal) with low moments. In one or more embodiments, the free layer can be any free layer design, i.e., structures such as CoFeB, Co, Fe, etc. Alternatively, the free layer can be an ordered alloy free layer.

[0052] The top electrode layer 304 may include TaN or TiN or similar materials. Each layer may be formed by CVD, PVD, or similar methods. Of course, these examples are not intended to be limiting, and other configurations may be obtained in light of the description and illustrations. For example, a semiconductor device may have both a reference layer and a free layer and comprise an ordered alloy.

[0053] Reference is now made to Figures 4-9, which provide schematic cross-sectional views of exemplary semiconductor devices or MRAM cell stacks at intermediate stages of fabrication in accordance with one or more embodiments of the present invention. The figures provide a front cross-section viewed along the X-Z plane. The figures provide schematic representations of devices of the present disclosure and are not to be considered accurate or limiting with respect to the scale of device elements.

[0054] 4 shows the semiconductor device 102 after deposition of an amorphous bottom electrode layer 106 on the semiconductor substrate 104. The amorphous bottom electrode layer 106 may be a Ta(N) layer.

[0055] 5, a conductive amorphous metal layer 110 is deposited on the amorphous bottom electrode layer 106. The conductive amorphous metal layer 110 may comprise, for example, CoFeB. Furthermore, the amorphous bottom electrode layer 106 and the conductive amorphous metal layer 110 may be amorphous at this stage of deposition.

[0056] 6, an amorphous reactive material 112 is deposited, which may comprise LiB, AlB, ScB, or other rare earth boron alloys. The boron in the alloy may ensure that the reactive material remains amorphous during and after deposition.

[0057] As shown in FIG. 7, an insulating oxide layer 114 is deposited following the deposition of the amorphous reactive material 112. As described herein, an exemplary insulating oxide layer 114 can be MgO. When MgO is deposited on an amorphous surface, it can form (100)-oriented crystallites on its own. During stack deposition, it may be desirable for the bottom MgO to be as thick as possible to develop good crystallinity and texture.

[0058] 8, an ordered alloy structure 108 is deposited on an insulating oxide layer 114. In this particular configuration, the ordered alloy structure 108 may comprise a free layer 206, thus providing a bottom free layer MTJ device. Following deposition of the ordered alloy structure 108, a tunnel barrier layer 116 is deposited on the ordered alloy structure 108, as shown in FIG.

[0059] FIG. 10 shows the deposition of a conductive amorphous metal layer 110 on the tunnel barrier layer 116, the subsequent deposition of a synthetic antiferromagnetic layer 118 on the conductive amorphous metal layer 110, and the subsequent deposition of a reference layer 120 on the synthetic antiferromagnetic layer 118.

[0060] Of course, in another embodiment, the positions of the reference layer 120 and the free layer 206 may be switched, where the reference layer 120 may be deposited on an insulating oxide layer, and in response to depositing the reference layer on the insulating oxide layer, the tunnel barrier layer 116 may be deposited on the reference layer 120, and the free layer 206 may be deposited on the tunnel barrier layer 116. An oxide cap layer 302 may further be deposited on the free layer 206, and a top electrode layer 304 may be deposited on the oxide cap layer 302, providing a top free layer MTJ device, as shown in FIG.

[0061] Referring now to FIG. 11 , a stack anneal process is performed to produce a conductive oxide layer 122 from the amorphous reactive material 112 and insulating oxide layer 114 of FIG. 10 . The stack anneal is performed in a post-processing routine at a temperature of 300-425° C., in which the amorphous reactive material 112 reacts with the insulating oxide layer 114, rendering it relatively conductive. The reaction can result in shorting the insulating oxide layer 114 and significantly reducing the series resistance of the MRAM cell stack. After consumption of the amorphous reactive material 112, an interface from the conductive crystalline metal layer to the conductive oxide layer, such as a CoFe-MgO interface, can be formed. Forming a conductive oxide layer 122 from the reaction at this stage may be feasible because the insulating oxide layer 114 may have served its purpose as a template, the ordered alloy structure 108 has its desired crystalline structure, and the crystallinity of the insulating oxide layer 114 is no longer necessary.

[0062] In one or more embodiments, the reference layer can be an ordered alloy reference layer, as shown in FIG. 12 . The ordered alloy reference layer can comprise a tetragonal L10 structure alloy, such as CoPt, CoPd, FePt, FePd, or MnAl. In contrast to the configuration of FIG. 3 , a base / seed layer is not shown here. The ordered alloy reference layer can benefit from a thick crystalline MgO template. A thick MgO seed layer, for example, can be a possible seed layer for the growth of Co-Pt with L10 symmetry.

[0063] Referring now to FIG. 13 , cross-sectional views of a semiconductor device at intermediate and final stages are shown illustrating a bottom free layer MTJ device with an ordered alloy free layer configuration. In this example, an amorphous reactive material can be alloyed with a conductive amorphous metal layer to form a reactive material and conductive amorphous metal layer alloy 1302. For example, Li, Al, or Sc can be alloyed with a CoFeB alloy to form a CoFeLiB, CoFeAlB, or CoFeScB layer. The amorphous reactive material can react with the insulating oxide layer 114 to form a conductive oxide layer 122, leaving behind a conductive crystalline metal layer 124. In a specific example, Sc from the CoFeScB layer can react with an MgO insulating oxide layer to form a conductive MgO:Sc layer, leaving behind a CoFe layer.

[0064] While fabrication of semiconductor devices or MRAM cell stacks using MTJs is described, it will be understood that other configurations such as SOT-MRAM (spin-orbit torque MRAM), double MTJs, and those having multiple MRAM cell stacks and MTJs are supported by the teachings herein.

[0065] In one aspect, the methods and structures described above can be used in the manufacture of integrated circuit chips. The resulting integrated circuit chips can be provided by the manufacturer in raw wafer (i.e., as a single wafer having multiple unpackaged chips), bare die form, or packaged form. In the latter case, the chips can be mounted in a single-chip package (such as a plastic carrier with leads secured to a motherboard or other higher-level carrier) or a multi-chip package (such as a ceramic carrier with either surface interconnects or embedded interconnects, or both). In either case, the chips can then be integrated with other chips, discrete circuit elements, and / or other signal processing devices as part of either (a) an intermediate product such as a motherboard, or (b) a final product. The final product can be any product that includes integrated circuit chips, ranging from low-end applications such as toys to sophisticated computer products with displays, keyboards or other input devices, and central processing units. [Conclusion]

[0066] The description of various embodiments of the present teachings has been presented for purposes of illustration and is not intended to be exhaustive or limited to the disclosed embodiments. Many modifications and variations will be apparent to those skilled in the art without departing from the scope and spirit of the described embodiments. The terminology used herein has been selected to best explain the principles of the embodiments, practical applications, or technical improvements over commercially available technologies, or to enable others skilled in the art to understand the embodiments disclosed herein.

[0067] While the foregoing has set forth what is believed to be best mode and / or other examples, it is understood that various modifications may be made thereto and that the subject matter disclosed herein may be implemented in a variety of forms and examples, and that the teachings may be applied in numerous applications, only some of which are described herein. It is intended by the following claims to claim any and all applications, modifications, and variations that fall within the true scope of the present teachings.

[0068] The components, steps, features, objects, benefits, and advantages described herein are exemplary only. Neither they nor the descriptions associated therewith are intended to limit the scope of protection. While various advantages have been described herein, it will be understood that not all embodiments necessarily include all advantages. Unless otherwise stated, all measurements, values, ratings, positions, dimensions, sizes, and other specifications described herein, including the following claims, are approximate and not exact. They are intended to have a reasonable range consistent with the functions to which they relate and with customary practices in the art to which they pertain.

[0069] Numerous other embodiments are contemplated, including embodiments having fewer, additional, and / or different components, steps, features, objects, benefits, and advantages, including embodiments in which the components and / or steps are configured and / or ordered differently.

[0070] While the foregoing has been described in conjunction with exemplary embodiments, it is understood that the term "exemplary" is intended as an example only, and not as best or optimal. Except as noted immediately above, nothing described or illustrated is intended to, and should be construed as, providing to the public any component, step, feature, object, benefit, advantage, or equivalent, whether claimed or not.

[0071] It will be understood that the terms and phrases used herein have the ordinary meanings ascribed to such terms and phrases with respect to their corresponding respective fields of investigation and study, unless a specific meaning is otherwise stated herein. Relative terms such as first and second may be used solely to distinguish one entity or action from another, without necessarily requiring or implying any actual relationship or order between such entities or actions. The terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that includes a list of elements does not include only those elements, but may include other elements not inherent in or not expressly listed within such process, method, article, or apparatus. An element preceded by "a" or "an" does not, in the absence of further constraints, exclude the presence of additional identical elements in the process, method, article, or apparatus that includes that element.

[0072] An Abstract is provided to allow the reader to quickly ascertain the nature of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims. In addition, the foregoing Detailed Description recognizes that various features are grouped together in various embodiments for the purpose of streamlining the disclosure. This method of disclosure is not to be interpreted as reflecting an intention that the claimed embodiments have more features than are expressly recited in each claim. Rather, as the following claims reflect, inventive subject matter lies in less than all features of a single disclosed embodiment. Accordingly, the following claims are hereby incorporated into the Detailed Description, with each claim standing on its own as separately claimed subject matter.

Claims

1. a substrate extending along a first axis to define a length, a second axis orthogonal to the first axis to define a width, and a third axis orthogonal to the first and second axes to define a height; a crystalline bottom electrode layer overlying the semiconductor substrate; a conductive crystalline metal layer disposed above the crystalline bottom electrode layer; a conductive oxide layer having a low resistance disposed above the conductive crystalline metal layer; and a magnetic tunnel junction (MTJ) disposed above the conductive crystalline metal layer, the MTJ having a tunnel barrier layer, a free layer disposed on a first side of the tunnel barrier layer, and a reference layer disposed on a second side of the tunnel barrier layer opposite the first side; A semiconductor device comprising:

2. The semiconductor device of claim 1 , wherein the free layer comprises an ordered alloy.

3. The semiconductor device of claim 1 , wherein the reference layer comprises an ordered alloy.

4. 10. The semiconductor device of claim 1, wherein said crystalline bottom electrode layer is formed from an amorphous Ta(N) layer.

5. The low resistance is 0.5 Ohm μm ２ 10. The semiconductor device of claim 1, wherein the resistance area product (RA) is less than 100 Ω.

6. The semiconductor device of claim 1 , wherein the conductive crystalline metal layer is produced from annealing an amorphous metal layer comprising CoFeB or ZrCo.

7. 10. The semiconductor device of claim 1, wherein the conductive oxide layer is a shunted MgO layer and further comprises a material selected from the list consisting of lithium, aluminum, scandium, and other rare earth metals.

8. the conductive oxide layer contains the other rare earth metal; The other rare earth metal is gadolinium or yttrium. The semiconductor device of claim 7.

9. 2. The semiconductor device of claim 1, wherein the conductive oxide layer has one or more shunting paths, and the conductive oxide layer has a thickness of 1.5 nm-3 nm.

10. 10. The semiconductor device of claim 1, wherein the ordered alloy forms the free layer and the reference layer includes one or more interface layers or spacers and one or more other layers, each of the one or more other layers including a material selected from the list consisting of cobalt, platinum, palladium, ruthenium, tantalum, iron, boron, cobalt-platinum, or cobalt-palladium.

11. The semiconductor device of claim 1 , wherein the ordered alloy forms the reference layer and the free layer comprises CoFe.

12. The semiconductor device of claim 1 , wherein the ordered alloy is a Heusler alloy or a tetragonal material.

13. 1. A method for manufacturing a semiconductor device, comprising: depositing an amorphous bottom electrode layer over a semiconductor substrate; depositing a conductive amorphous metal layer over the amorphous bottom electrode layer; depositing an amorphous reactive material over the conductive amorphous metal layer; depositing an insulating oxide layer over the amorphous reactive template; depositing an ordered alloy structure comprising a free layer or a reference layer on the insulating oxide layer; depositing a tunnel barrier layer over the ordered alloy structure; and performing a stack anneal process on the semiconductor device, in response to which the amorphous reactive material reacts with and shunts the insulating oxide layer to form a conductive oxide layer. A method comprising:

14. The method of claim 13 , wherein the ordered alloy structure further comprises a seed layer.

15. 15. The method of claim 14, further comprising depositing the seed layer on the insulating oxide layer before depositing the free layer or the reference layer on the seed layer.

16. the free layer is deposited over the seed layer; in response to depositing the free layer on the seed layer and the tunnel barrier layer on the free layer; depositing another conductive amorphous metal layer over the tunnel barrier layer; depositing a synthetic antiferromagnetic (SAF) layer over the another conductive amorphous metal layer; and depositing the reference layer over the SAF to provide a bottom free layer MTJ device. The method of claim 15 further comprising:

17. the reference layer is deposited over the seed layer; in response to depositing the reference layer on the seed layer and the tunnel barrier layer on the reference layer; depositing the free layer over the tunnel barrier layer; depositing an oxide cap layer over the free layer; and depositing a top electrode layer over the oxide cap layer to provide a top free layer MTJ device. The method of claim 15 further comprising:

18. 14. The method of claim 13, wherein the conductive amorphous metal layer is deposited as a CoFeB or ZrCo layer.

19. 14. The method of claim 13, wherein the amorphous reactive material is deposited as a material selected from the list including lithium boron alloy (LiB), aluminum boron alloy (AlB), scandium boron alloy (ScB), and other rare earth boron alloys.

20. The method of claim 13, wherein the stack annealing is performed at a temperature of 300-425°C.

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