Clocking architecture for communicating a clock signal over a communication interface - Patents.com

Abstract

The integrated circuit (IC) device includes a first IC chip (110), a second IC chip (120), and a chip-to-chip interface (112) connected between the first IC chip (110) and the second IC chip (120). The chip-to-chip interface (120) communicates an interface clock signal and a logic clock signal between the first IC chip (110) and the second IC chip (120). The interface clock signal is synchronous with a data signal received by one of the first IC chip (110) and the second IC chip (120). The logic clock signal is asynchronous with the data signal.

Description

[Technical Field]

[0001] Examples of the present disclosure generally relate to clocking interfaces for high-speed integrated circuit inter-chip communication interfaces. [Background technology]

[0002] As computer systems become more densely integrated, integrated circuit (IC) chip-to-IC chip (C2C) interfaces are becoming more widely used. One such computing system is an anchor IC chip (e.g., a processor, application specific integrated circuit (ASIC), field programmable gate array (FPGA), or system on a chip (SOC)) that uses a C2C interface to communicate with one or more chiplets (e.g., high-speed I / O or high-bandwidth memory (HBM)) or another anchor IC chip. The C2C interface is constrained by the area of ​​the beachfront (e.g., the side of the anchor chip), which limits the number of signals and wires that can pass through the interface. Therefore, the required bandwidth is achieved by operating the interface at a high data rate.

[0003] A C2C interface employs multiple clock signals to communicate parallel data between IC chips. Typically, a C2C interface implements a clocking technique to support the communication of parallel data between IC chips. However, such a C2C interface is specific to a particular implementation and does not support multiple different C2C modes. Summary of the Invention [Means for solving the problem]

[0004] In one example, an integrated circuit (IC) device includes a first IC chip, a second IC chip, and a chip-to-chip interface connected between the first IC chip and the second IC chip. The chip-to-chip interface communicates an interface clock signal and a logic clock signal between the first IC chip and the second IC chip. The interface clock signal is synchronous with a data signal received by one of the first IC chip and the second IC chip. The logic clock signal is asynchronous with the data signal.

[0005] In one example, the chip-to-chip interface communicates an interface clock signal between a first IC chip and a second IC chip. The first IC chip and the second IC chip are connected to each other via the chip-to-chip interface. The interface clock signal is synchronous with a data signal. The data signal is received by one of the first IC chip and the second IC chip. The chip-to-chip interface further communicates a logic clock signal between the first IC chip and the second IC chip. The logic clock signal is asynchronous with the data signal.

[0006] In one example, the IC chip includes a chip-to-chip interface circuit connected to a second IC chip. The chip-to-chip interface circuit is configured to communicate an interface clock signal to the second IC chip. The interface clock signal is synchronous with data signals received by the IC chip. The chip-to-chip interface further communicates a logic clock signal to the second IC chip. The logic clock signal is asynchronous with the data signals.

[0007] BRIEF DESCRIPTION OF THE DRAWINGS In a manner in which the above-recited features may be understood in detail, a more particular description briefly summarized above may be made by reference to exemplary implementations, some of which are illustrated in the accompanying drawings. It should be noted, however, that the accompanying drawings illustrate only typical exemplary implementations and therefore should not be considered limiting of the scope thereof. [Brief explanation of the drawings]

[0008] [Figure 1] 1 is a block diagram of a multiple integrated circuit (IC) chip device, according to an example. [Figure 2] 1 is a block diagram of a multiple IC chip device, according to an example. [Figure 3] 1 is a block diagram of a multiple IC chip device configured as a receiver of a transceiver device, according to an example. [Figure 4] 1 is a block diagram of a multiple IC chip device configured as a transmitter of a transceiver device, according to an example. [Figure 5] 1 is a block diagram of a multiple IC chip device configured as a receiver of a transceiver device, according to an example. [Figure 6] 1 is a block diagram of a multiple IC chip device configured as a transmitter of a transceiver device, according to an example. [Figure 7] 1 illustrates control signals for a multiple IC chip device, according to an example. [Figure 8] 1 is a block diagram of a multiple IC chip device comprising multiple anchor IC chips, according to an example. [Figure 9] FIG. 1 is a block diagram of a multiple IC chip device in which the interface circuitry is bypassed. [Figure 10] FIG. 2 is a block diagram of a clock generation circuit, according to an example. DETAILED DESCRIPTION OF THE INVENTION

[0009] Various features are described below with reference to the drawings. It should be noted that the drawings may or may not be drawn to scale, and that elements of similar structure or function are represented by similar reference numerals throughout the drawings. It should be noted that the drawings are intended only to facilitate the description of features. They are not intended as an exhaustive description of features or as limitations on the scope of the claims. In addition, the illustrated example need not have all aspects or advantages shown. An aspect or advantage described in connection with a particular embodiment is not necessarily limited to that embodiment and may be implemented in any other embodiment, even if not so illustrated or explicitly described.

[0010] Embodiments herein describe clocking techniques for chip-to-chip (C2C) interfaces. The clocking techniques described herein can be used for a variety of different C2C interface modes. For example, the C2C interface employs a low-latency streaming mode, a flow control mode, and a low-latency synchronous communication mode.

[0011] A C2C interface includes wires that connect two or more integrated circuit (IC) chips to each other. The wires may be referred to as a module or a DWORD. In one example, a module is the basic unit of a C2C interface. A module includes one or more wires that function as an interface between IC chips. In full module mode, all of the wires of the C2C interface are used for communication. Furthermore, all of the wires of the C2C interface in a full module are driven by the same clock signal. In half module mode, fewer than all of the wires of the C2C interface are used.

[0012] In many cases, the clock signal used to transmit data over the C2C interface and the clock signal used by the IC chip's functional circuits are both generated from the data signal. Therefore, the control signal used to transmit the clock signal for the functional circuit is paused when the data signal is no longer received and the clock signal for the functional circuit is unavailable. The following describes a process for transmitting multiple different clock signals over the C2C interface. As described in detail below, at least one clock signal is generated independently of the data signal and used as the clock signal for the IC chip's functional circuits. For example, a first portion of the wires of the C2C interface are driven based on a first clock signal, and a second portion of the wires are driven based on a second clock signal. The second clock signal is different from the first clock signal. The different clock signals are used to transmit the data signal and the control signal. The use of two clock signals allows the control signal to continue to be transmitted when an error occurs in the data signal, improving the reliability and performance of the C2C interface.

[0013] In one or more examples, multiple anchor IC chips (e.g., IC chips including programmable fabric logic) are interconnected via a C2C interface. The anchor chips may also be referred to as main IC chips. In such examples, instead of each anchor IC chip generating a different clock signal locally, the C2C interface is used to communicate clock signals between the IC chips. In such an operating mode, a fabric logic clock signal associated with one IC chip is communicated to another IC chip via the C2C interface. The fabric logic clock signal is communicated over a portion of the wires (e.g., sideband) of the C2C interface to synchronize the IC chips with each other, reduce data errors within the multiple IC chips, and improve the performance of the multiple IC chips.

[0014] 1 is a block diagram of a multi-chip (integrated circuit) device 100 including an IC chip 110 and an IC chip 120. The IC chips 110 and 120 may be mounted on an interposer (not shown) or other substrate.

[0015] In one example, IC chip 110 is a main IC chip or an anchor IC chip. IC chip 110 includes circuitry comprising one or more data processing blocks, such as a processing system or processing subsystem (PS), a memory system (including, for example, a memory controller), etc. Furthermore, IC chip 110 includes C2C interface circuit 112. IC chip 110 may be, among other things, an application specific integrated circuit (ASIC), a field programmable gate array (FPGA), a central processing unit (CPU), or a memory.

[0016] In one or more examples, IC chip 120 is a chiplet or an auxiliary IC chip. In such examples, IC chip 120 includes a dedicated logic device or device type configured to serve a specific purpose or provide a specific function, such as a data processing engine (DPE) or hardware accelerator IC chip configured to provide artificial intelligence (AI), machine learning (ML) functionality, Ethernet communications, memory functionality, etc. In one or more examples, employing a chiplet or an auxiliary IC chip as IC chip 120 decouples the development cycle of IC chip 110 from IC chip 120. For example, IC chip 110 is developed and manufactured independently of the development of IC chips 120, 110. In other examples, IC chip 120 is configured similarly to that of IC chip 110. For example, IC chip 110 and IC chip 120 are both main or anchor IC chips. In such examples, IC chip 120 is, among other things, an ASIC, an FPGA, a CPU, or memory.

[0017] In one example, IC chip 120 is a chiplet or auxiliary IC chip, which is part of an overall IC design framework that performs one or more specific functions, but requires an external entity (i.e., IC chip 110) to make the function useful. For example, IC chip 120 may perform acceleration of machine learning functions, but requires IC chip 110 to program registers, provide an interface to memory, etc.

[0018] The IC chip 120 includes a C2C interface circuit 122. The C2C interface circuit 122 of the IC chip 120 is connected to the C2C interface circuit 112 of the IC chip 110 via an interface 130. The interface 130 includes one or more wires. For example, the interface 130 may include N wires, where N is one or more. In one or more examples, the C2C interface circuit 112, the C2C interface circuit 122, and the interface 130 form a C2C interface system 140. In one example, each wire of the interface 130 is driven based on the same clock signal. In another example, at least two wires of the interface 130 are driven by a clock signal having a lower frequency than the frequency of the clock signal driven on the other wires of the interface 130. In one or more examples, the C2C interface system 140 operates at approximately 8 gigabits per second (Gbps) per wire.

[0019] In one example, C2C interface circuit 112 and C2C interface circuit 122 include one or more programmable elements (e.g., via a programming software model employing a programming interface for an end user). In some embodiments, C2C interface circuit 112 and C2C interface circuit 122 comprise digital and / or analog components that enable communication between IC chip 110 and IC chip 120.

[0020] In one or more examples, multi-IC chip device 100 includes three or more IC chips. For example, multi-IC chip device 100 includes IC chip 110 and two or more IC chips 120. In such examples, IC chips 120 may be configured to perform common functions and / or different functions.

[0021] C2C interface system 140 enables communication between IC chip 110 and IC chip 120. C2C interface system 140 provides flexibility in creating multiple IC chip device 100. In one or more examples, C2C interface system 140 allows different combinations of IC chips (e.g., IC chips 110 and 120) to be interconnected to form multiple IC chip device 100.

[0022] 2 illustrates a block diagram of the IC chip 110 and the IC chip 120. As illustrated in FIG. 2, the C2C interface circuit 112 of the IC chip 110 includes an application circuit 210, a protocol layer circuit 212, a link layer circuit 214, and a physical (PHY) layer circuit 216.

[0023] Application circuit 210 is circuitry that performs functions specified by a user and / or design. In one example, application circuit 210 includes non-programmable (hardened) circuitry such as a processor core, a DPE, a graphics processing unit, or transceiver circuitry (e.g., transmit and receive circuitry). In another example, application circuit 210 includes programmable circuitry (e.g., programmable fabric circuitry) such as a configurable logic block (CLB) or other type of programmable logic that can be customized on the fly. Application circuit 210 generates data that is transferred to IC chip 120 via interface 130 and processes data received from IC chip 120.

[0024] In one or more examples, the application circuit 210 transmits data to other hardware elements (e.g., protocol layer circuit 212) within the IC chip 110 using a particular protocol. The protocol is often different from the protocol used to transmit data over the interface 130. In such examples, the application circuit 210 outputs protocol words (or control signals) that are received by the protocol layer circuit 212. The protocol layer circuit 212 receives the protocol words and converts the protocol words into data signals (e.g., data words (DW)) that are compatible with the interface 130. The protocol words include both control data and data signals. Converting the protocol words includes separating the control data from the data signals. The control data is communicated over the interface 130 as a separate packet from the data signals.

[0025] In other examples, application circuit 210 outputs data signals that are compatible with interface 130. In such examples, protocol layer circuit 212 is bypassed and does not process the data signals output by application circuit 210. In the examples of Figures 3, 4, 6, and 7, the protocol layers are bypassed, as described below. Similar methods can be applied to examples in which the protocol layers are not bypassed.

[0026] In one example, link layer circuitry 214 generates a framing pattern from a data signal communicated along interface 130 with the data signal. The framing pattern indicates the start of data within the data signal. PHY layer circuitry 216 communicates the data signal and the framing pattern along interface 130. Additionally, PHY layer circuitry 216 receives the data signal and the framing pattern from interface 130. In such an example, the received data signal and framing pattern are provided to link layer circuitry 214. Link layer circuitry 214 detects the framing pattern and identifies the start of the data signal. The data signal is output to application circuit 210.

[0027] In one example, a data signal is transmitted with a framing signal that defines regions of valid data within the data signal, and in one example, the framing signal is used to mask invalid data within the data signal.

[0028] The C2C interface circuit 122 of the IC chip 120 includes an application circuit 220, a protocol layer circuit 222, a link layer circuit 224, a PHY layer circuit 226, and a reducer circuit 228. The application circuit 220, the protocol layer circuit 222, the link layer circuit 224, and the PHY layer circuit 226 are configured similarly to the application circuit 210, the protocol layer circuit 212, the link layer circuit 214, and the PHY layer circuit 216, respectively.

[0029] The C2C interface circuit 122 further includes a reducer circuit 228. The reducer circuit 228 receives the output (e.g., a protocol word or a data signal) from the application circuit 220 and adjusts the output by reducing the data rate (e.g., frequency) and increasing the bit size of the data signal. In one example, the reducer circuit 228 reduces the data signal from an 80-bit data signal having a frequency of 1.45 GHz to a 160-bit data signal having a frequency of 725 MHz. In one example, the frequency is reduced by the same factor as the number of bits in the data signal increases. Thus, after the output of the application circuit 220 is processed by the reducer circuit 228, the same amount of data is communicated in the same amount of time.

[0030] In one or more examples, protocol layer circuitry 222 converts the output of reducer circuitry 228 between protocols, as described above with respect to protocol layer circuitry 212. In other examples, protocol layer circuitry 222 is bypassed and the output of reducer circuitry 228 is communicated to link layer circuitry 224.

[0031] In one or more examples, C2C interface system 140 supports a variety of different communication modes. In one or more examples, application circuits 210 and / or 220 are transceiver circuits that may be configured as transmit and receive circuits, respectively. For example, application circuits 210 and / or 220 include serializer / deserializer (SERDES) circuits or other transceiver circuits.

[0032] In the low-latency streaming mode, the protocol layer circuits (e.g., protocol layer circuits 212 and 222) and / or link layer circuits (e.g., link layer circuits 214 and 224) are bypassed. In the low-latency streaming mode, all or a portion of the wires of interface 130 may be used.

[0033] In one or more examples, application circuit 210, link layer circuit 214, and PHY layer circuit 216 each include sideband circuits 230, 232, and 234, respectively. Additionally, application circuit 220, link layer circuit 224, and PHY layer circuit 226 each include sideband circuits 240, 242, and 244, respectively. Sideband circuits 230, 232, and 234 and sideband circuits 240, 242, and 244 communicate over a portion (e.g., a sideband) of interface 130. In such examples, interface 130 communicates data over its main band and sideband information over its sidebands. A sideband corresponds to M wires of the interface, and the main band corresponds to P wires of the interface. P and M are equal to or greater than 1. Additionally, P may be greater than M. In one or more examples, the frequency used to transmit data over the main band (e.g., the main band or datapath clock signal frequency) is greater than the frequency used to transmit data over the side band (e.g., the side band or control signal clock signal frequency). In one example, the side band may be used to communicate control data as sideband information between IC chips.

[0034] In one example, using all of the wires of interface 130 is referred to as full module mode, and using only a portion of the wires is referred to as half module mode. In full module mode, all of the wires of interface 130 are clocked with the same clock signal. The clock signal is generated by the PHY interface circuitry (e.g., PHY layer circuitry 216 and / or 226).

[0035] In one or more examples, IC chip 110 and IC chip 120 are connected via a data path and a sideband. In such examples, the data path is a synchronous, low-latency data path. As described in more detail below, the data path uses a data path clock signal generated from a clock generation circuit based on the data signal.

[0036] In one or more examples, the datapath clock signal may stop due to auto-negotiation and link training (ANLT), dynamic rate changes, or link data loss within IC chips 110 and / or 120, among other things. Stopping the datapath clock signal stops the transmission of data between IC chip 110 and IC chip 120. In such embodiments, to maintain communication of control data between IC chip 110 and IC chip 120, a sideband connection is used to communicate control data between IC chip 110 and IC chip 120. To ensure proper functioning of IC chips 110 and 120, the control data is communicated continuously even when the first clock signal is stopped. To support the continuous communication of control data, the sideband connection uses a sideband clock signal that is independent of the datapath clock signal.

[0037] In one example, sideband circuits 230-234 and sideband circuits 240-244 are used to transmit control data over the sideband of interface 130. In another example, in half module mode, one or more of the wires of interface 130 are used to communicate control data as a sideband connection, and the remaining wires of interface 130 are used to communicate data signals (e.g., a data path). In half module mode, sideband circuits 230-234 and sideband circuits 240-244 are used to transmit a clock signal or information defining characteristics of the clock signal (e.g., the frequency of the clock signal). In one or more examples, the sideband connection uses a clock signal that is different from the clock signal of the data bus (or main band).

[0038] In one or more examples, the interface 130 communicates an interface clock signal (e.g., a first clock signal or a mainband clock signal) between the IC chip 110 and the IC chip 120. The interface clock signal is synchronous with a data signal received by one of the IC chips 110 and 120. The interface 130 also communicates a logic clock signal (e.g., a second clock signal, a sideband clock signal, or a control clock signal) between the IC chip 110 and the IC chip 120. The logic clock signal is asynchronous with the data signal received by one of the IC chips 110 and 120. The logic clock signal is generated independently of the interface clock signal. Furthermore, the interface 130 communicates a data signal between the IC chip 110 and the IC chip 120. The frequency of the data signal is higher than the frequency of the interface clock signal. The interface 130 also communicates a control signal (e.g., a protocol signal) between the IC chip 110 and the IC chip 120. The control signal has the frequency of the data signal.

[0039] In one or more examples, interface 130 communicates an interface clock signal and a logic clock signal between IC chip 110 and IC chip 120. The frequency of the interface clock signal is a multiple of the frequency of the logic clock signal. In one example, the frequency of the interface clock signal is at least twice the frequency of the logic clock signal. In one or more examples, the interface communicates data signals between IC chip 110 and IC chip 120. The data signals are synchronized to the interface signal. A framing pattern is communicated with the data signals. In one example, the interface clock signal is generated on the rising edge of the logic clock signal. In one example, the framing signal is communicated with the data signals and is used to define valid data within the data signals.

[0040] Figure 3 is a block diagram of a multiple IC chip device 300. The multiple IC chip device 300 includes an IC chip 310 and an IC chip 350. The IC chip 310 is connected to the IC chip 350 via an interface 302. The IC chip 310 is configured similarly to that of the IC chip 110 in Figure 1, the IC chip 350 is configured similarly to that of the IC chip 120 in Figure 1, and the interface 302 is configured similarly to that of the interface 130 in Figure 1. In the example of Figure 3, the IC chip 310 is a main IC chip, and the IC chip 350 is an auxiliary IC chip or chiplet.

[0041] Multiple IC chip device 300 is configured such that both data path and sideband connections are used between IC chip 310 and IC chip 350 to communicate data and control data (or other sideband information).

[0042] IC chip 350 includes an application circuit 352 and a C2C interface circuit 360. C2C interface circuit 360 includes a PHY layer circuit 362, a link layer circuit 364, a protocol layer circuit 366, and a reducer circuit 368. C2C interface circuit 360 has a configuration similar to that of C2C interface circuit 122 of FIG. 1, PHY layer circuit 362 has a configuration similar to that of PHY layer circuit 216 of FIG. 2, C2C link layer circuit 364 has a configuration similar to that of C2C link layer circuit 214 of FIG. 2, protocol layer circuit 366 has a configuration similar to that of protocol layer circuit 212 of FIG. 2, and reducer circuit 368 has a configuration similar to that of reducer circuit 228 of FIG. 2. Application circuit 352 has a configuration similar to that of application circuit 220 of FIG. 2.

[0043] IC chip 350 further includes an application circuit 354 and a C2C interface circuit 370. C2C interface circuit 370 includes a PHY layer circuit 372, a link layer circuit 374, and a protocol layer circuit 376. C2C interface circuit 370 has a configuration similar to that of C2C interface circuit 122 of FIG. 1, PHY layer circuit 372 has a configuration similar to that of PHY layer circuit 216 of FIG. 2, C2C link layer circuit 374 has a configuration similar to that of C2C link layer circuit 214 of FIG. 2, and protocol layer circuit 376 has a configuration similar to that of protocol layer circuit 212 of FIG. 2. Application circuit 354 has a configuration similar to that of application circuit 220 of FIG. 2.

[0044] Additionally, IC chip 350 includes clock circuit 380 and clock circuit 390. Clock circuit 380 generates a datapath clock signal (e.g., clock signal 305), and clock circuit 390 generates a sideband clock signal (e.g., clock signal 307).

[0045] In one example, IC chip 350 is configured as a receiver circuit in a transceiver circuit. IC chip 350 receives data signal 351.

[0046] The clock circuit 380 includes a clock generation circuit 382, ​​a frequency divider circuit 384, a multiplying delay locked-loop (MDLL) circuit 386, and a frequency divider circuit 388. The clock circuit 390 is a frequency divider circuit.

[0047] The IC chip 310 includes an application circuit 312 and a C2C interface circuit 320. The C2C interface circuit 320 includes a PHY layer circuit 322, a link layer circuit 324, and a protocol layer circuit 326. The C2C interface circuit 320 has a configuration similar to that of the C2C interface circuit 112 in FIG. 1, the PHY layer circuit 322 has a configuration similar to that of the PHY layer circuit 216 in FIG. 2, the C2C link layer circuit 324 has a configuration similar to that of the C2C link layer circuit 214 in FIG. 2, and the protocol layer circuit 326 has a configuration similar to that of the protocol layer circuit 212 in FIG. 2. The application circuit 312 has a configuration similar to that of the application circuit 210 in FIG. 2.

[0048] The IC chip 310 further includes an application circuit 314 and a C2C interface circuit 330. The C2C interface circuit 330 includes a PHY layer circuit 332, a link layer circuit 334, and a protocol layer circuit 336. The C2C interface circuit 330 has a configuration similar to that of the C2C interface circuit 112 of FIG. 1, the PHY layer circuit 332 has a configuration similar to that of the PHY layer circuit 216 of FIG. 2, the C2C link layer circuit 334 has a configuration similar to that of the C2C link layer circuit 214 of FIG. 2, and the protocol layer circuit 336 has a configuration similar to that of the protocol layer circuit 212 of FIG. 2. The application circuit 314 has a configuration similar to that of the application circuit 210 of FIG. 2.

[0049] Additionally, IC chip 310 includes clock circuit 340 and clock circuit 346. Clock circuit 340 receives clock signal 305 (e.g., a datapath clock signal) from IC chip 350, and clock circuit 346 receives clock signal 307 (e.g., a sideband clock signal) from IC chip 350. Clock signal 307 is communicated as a differential signal.

[0050] Clock circuit 340 includes a frequency divider circuit 342 and an MDLL circuit 344. Clock circuit 346 includes a frequency divider circuit.

[0051] In one example, IC chip 350 communicates data signal 304, clock signal 305, control signal word 306, and clock signal 307 via interface 302. IC chip 350 generates data signal 304 and clock signal 305 based on data signal 351. For example, clock circuit 380 generates clock signal 305 based on data signal 351. Clock generation circuit 382 generates clock signal 383 from data signal 351. For example, clock generation circuit 382 generates clock signal 383 based on receiving data signal 351. Furthermore, the frequency of clock signal 383 corresponds to the frequency of data signal 353 generated by application circuit 352 from data signal 351. In one example, clock signal 383 has a frequency of 1.45 GHz, and data signal 353 has a frequency of 1.45 GHz. Clock signal 383 is received by application circuit 352 and divider circuit 384. Clock signal 383 serves as a clock signal for application circuit 352. Divider circuit 384 divides the frequency of clock signal 383 by two or more to determine divided clock signal 385a. Divider circuit 384 also receives divided clock signal 389a from divider circuit 388. Divider circuit 384 divides the frequency of clock signal 389a by two or more to determine divided clock signal 385b. In one example, clock signals 385a and 385b have a frequency of 725 MHz. Divided clock signal 385a and divided clock signal 385b are received by MDLL circuit 386.

[0052] MDLL circuit 386 reduces the delay of clock signals 385a and 385b. Furthermore, MDLL circuit 386 generates clock signal 387 from clock signals 385a and 385b. For example, MDLL circuit 386 multiplies the frequency of clock signals 385a and 385b by more than two. In one example, MDLL circuit 386 multiplies the frequency of clock signals 385a and 385b by five. In such an example, clock signal 387 has a frequency of 3.625 GHz. Clock signal 387 is output by driver circuit 356 through interface 302 as clock signal 305. In one example, clock signal 305 is communicated as a differential signal through two wires of interface 302.

[0053] Control signal 387 is further received by divider circuit 388. Divider circuit 388 outputs clock signals 389a, 389b, and 389c. Divider circuit 388 generates clock signal 389a by reversing the processing applied by divider circuit 384 and MDLL circuit 386. For example, divider circuit 388 divides the frequency of clock signal 387 by two or more, thereby multiplying the frequency of the clock signal by two or more. Divider circuit 388 further generates clock signal 389b by dividing the frequency of clock signal 387 by two or more. Clock signal 389c passes through divider circuit 388 without being processed or altered. The frequency of clock signal 389c is the same as the frequency of clock signal 387.

[0054] Clock signal 389a is received by reducer circuit 368, which processes data signal 353 using clock signal 389a. Reducer circuit 368 reduces the frequency of data signal 353 by two or more and increases the number of bits to generate data signal 363. In one example, data signal 353 has 80 bits and a frequency of 1.45 GHz. In this example, when the frequency is reduced by two and the number of bits is increased, data signal 363 has 160 bits and a frequency of 725 MHz. By reducing the frequency of data signal 353 to generate data signal 363, data signal 363 is placed within the operating range of link layer circuitry 364 and PHY layer circuitry 362.

[0055] Protocol layer circuitry 366 is bypassed because data signal 363 is compatible with link layer circuitry 364 and PHY layer circuitry 362. Link layer circuitry 364 receives clock signal 389b and generates a framing pattern to indicate the start of data signal 363. The framing pattern is communicated to PHY layer circuitry 362 along with data signal 363. In one example, data signal 363 is transmitted with a framing signal that defines regions of valid data within data signal 363. The framing signal masks invalid data within data signal 363.

[0056] PHY layer circuitry 362 receives clock signals 389b and 389c and generates data signal 304 from data signal 363. PHY layer circuitry 362 increases the frequency of data signal 363 and reduces its bit size by two or more to generate data signal 304. In one or more examples, PHY layer circuitry 362 increases the frequency and reduces the bit size of data signal 363 by five, ten, fifteen, or twenty times, or more. In one example, PHY layer circuitry 362 increases the frequency and reduces the bit size of data signal 363 by two or more times. If data signal 363 has a bit size of 160 bits and a frequency of 725 MHz, data signal 304 has a bit size of 16 bits and a frequency of 7.25 GHz. In one example, PHY layer circuitry 362 has a multiplication ratio of 16 to 1. In another example, PHY layer circuitry 362 has another multiplication ratio. In one example, the data signal 304 has a frequency of 7.25 GHz and 16 bits. In another example, the data signal 304 has a frequency higher or lower than 7.25 GHz.

[0057] In one or more examples, the link layer circuit 364 includes a buffer 365. The buffer 365 may be a first-in-first-out (FIFO) buffer. While FIG. 3 illustrates a single buffer 365, in other examples, the link layer circuit 364 may include multiple buffers 365. The buffer 365 receives a write clock signal and a read clock signal. The write clock signal and the read clock signal are in different clock domains (e.g., have different frequencies). The buffer 365 may include an array of memory elements that are addressed via a write pointer or a read pointer. During a write operation, data is written to the address of the write pointer. During a read operation, data is read from the address of the read pointer. In one example, the read pointer is offset from the write pointer to ensure that the data being read based on the read pointer does not change during the read.

[0058] A control signal 306 and a clock signal 308 are communicated from IC chip 350 to IC chip 310 via interface 302. Control signal 306 is generated based on a control signal 355 generated by application circuit 354. Control signal 306 may be a protocol word. Protocol layer circuit 376 is bypassed, and control signal 355 is received by link layer circuit 374. Link layer circuit 374 generates a framing pattern for control signal 355 and outputs the control signal and framing pattern to PHY layer circuit 372. In one example, control signal 355 is transmitted along with a framing signal. The framing signal defines a region of valid data within control signal 355. In one example, the framing signal is used to mask invalid data within control signal 355.

[0059] The PHY layer circuitry 372 increases the frequency of the control signal 355 by 2 or more and decreases the bit size of the control signal 355 to generate the control signal 306. In one particular example, the PHY layer circuitry 372 increases the frequency of the control signal 355 and decreases the bit size of the control signal 355 by 16. In such an example, the frequency of the control signal 355 is 200 MHz and the bit size of the control signal 355 is 320 bits. Thus, the control signal 306 has a bit size of 16 bits and a frequency of 8 GHz.

[0060] The sideband clock signal 308 is based on a clock signal generated by the IC chip 350 independently of the data signal 351. For example, the sideband clock signal 308 is generated by a clock generation circuit 392 of the IC chip 350. The IC chip 350 further includes a clock generation circuit 394 that generates a clock signal 395. The clock signal 395 is used internally by the application circuit 354, the link layer circuit 374, and the PHY layer circuit 372. The clock circuit 390 functions as a pass-through and outputs the clock signal 308 without modifying it. The clock signal 308 is output by the clock circuit 390 to a driver circuit 396, which drives the clock signal on the interface 302. The clock circuit 390 further outputs the clock signal 308 to the PHY layer circuit 372. The clock circuit 390 further divides the clock signal 308 by two or more. The clock signal 391 is output to the link layer circuit 374 and the PHY layer circuit 372 .

[0061] IC chip 310 receives data signal 304, clock signal 305, control signal 306, and sideband clock signal 308 from IC chip 350. Receive circuit 348 receives clock signal 305. Receive circuit 348 outputs the received clock signal 305 as clock signal 349 to divider circuit 342. Divider circuit 342 reduces the frequency of clock signal 349 by two or more. In one particular example, divider circuit 342 reduces the frequency of clock signal 349 by 10. In such an example, when clock signal 305 has a frequency of 3.625 GHz, divider circuit 342 divides the frequency of clock signal 349 by 10 to generate clock signal 343 having a frequency of 362.5 MHz. Divider circuit 342 also outputs clock signal 349 and functions as a pass-through so that clock signal 349 is not altered by divider circuit 342. The clock signal 349 is output to the PHY layer circuit 322 .

[0062] Clock signal 343 is output to PHY layer circuit 332 and link layer circuit 334. Clock signal 343 is further output to MDLL circuit 344. MDLL circuit 344 generates clock signal 345 based on clock signal 343 and a feedback signal (e.g., clock signal 315) received from application circuit 312. Clock signal 343 is output to application circuit 312. In one example, buffer 313 of application circuit 312 receives clock signal 343 and generates clock signal 315. In one example, clock signal 315 is a capture clock signal for flip-flop 317 of application circuit 312. Thus, clock signal 315, which is the clock signal for application circuit 312, is generated based on data signal 353.

[0063] In one or more examples, the feedback signal (eg, clock signal 315 ) is used by MDLL circuit 344 to deskew clock signal 343 and for phase alignment of clock signal 343 .

[0064] PHY layer circuitry 322 receives data signal 304 and generates data signal 323 from data signal 304 and clock signals 349 and 343. In one example, PHY layer circuitry 322 receives data signal 304 using clock signal 349 and generates data signal 353 using clock signal 343. Link layer circuitry 324 detects a framing pattern associated with data signal 323, identifies the start of data signal 323 based on the framing pattern, and generates data signal 325 based on clock signal 343. In one example, the framing signal is received and used to determine valid data in data signal 323.

[0065] The data signal 325 has a frequency corresponding to the operating frequency of the application circuit 312. For example, the frequency of the data signal 325 is the same as the frequency of the clock signal 315. Furthermore, the bit size of the data signal 325 is larger than the bit size of the data signal 304. The bit size of the data signal 325 is more than twice as large as the bit size of the data signal 304, and the frequency of the data signal 304 is more than twice as large as the frequency of the data signal 325. In one example, the PHY layer circuit 322 divides the frequency of the data signal 304 and multiplies the bit size of the data signal 304 by more than two to generate the data signal 323. In one example, the PHY layer circuit 322 has a multiplication ratio of 20 to 1. In another example, the PHY layer circuit 322 has another multiplication ratio.

[0066] In one or more examples, the link layer circuitry 324 includes a buffer 321. The buffer 321 may be a FIFO buffer. While FIG. 3 illustrates a single buffer 321, in other examples, the link layer circuitry 324 may include multiple buffers 365. The buffer 321 receives a write clock signal and a read clock signal. The write clock signal and the read clock signal are in different clock domains (e.g., have different frequencies). The buffer 321 may include an array of memory elements that are addressed via a write pointer or a read pointer. During a write operation, data is written to the address of the write pointer. During a read operation, data is read from the address of the read pointer. In one example, the read pointer is offset from the write pointer to ensure that the data being read based on the read pointer does not change during the read.

[0067] The data signal 325 is received by the application circuit 312 based on the clock signal 315. In one example, the flip-flop 317 captures the data signal 325 based on the clock signal 315.

[0068] Receiver circuit 337 receives sideband clock signal 308 from driver circuit 341 and outputs clock signal 338. Clock signal 338 is output to clock circuit 346. Clock circuit 346 shifts the phase of clock signal 338 by 90 degrees to generate clock signal 339. The phase of clock signal 339 differs from the phase of clock signal 338 by 90 degrees. Clock circuit 346 also generates clock signal 347 from clock signal 338. In one example, clock circuit 346 reduces (e.g., divides) the frequency of clock signal 338 by two or more. In one example, clock circuit 346 reduces (e.g., divides) the frequency of clock signal 338 by eight. Clock signal 347 is received by PHY layer circuit 332 and link layer circuit 334. PHY layer circuit 332 receives control signal 306 using clock signal 339 and generates control signal 333 using clock signal 347.

[0069] Application circuit 314 generates clock signal 323, which is used by link layer circuit 334 to generate control signal 335 and by application circuit 314 to capture the value of control signal 335. Flip-flop 319 captures the value of control signal 335 based on clock signal 323. Link layer circuit 334 receives control signal 333 based on clock signal 347 and generates control signal 335 based on clock signal 315 and a corresponding framing pattern. Link layer circuit 334 identifies the start of control signal 335 based on the framing pattern. In one example, the received framing signal is used to identify valid data in control signal 335.

[0070] The control signal 335 has a reduced frequency compared to the control signal 333 and is within the operating frequency parameters of the application circuit 314. In one example, the frequency of the control signal 335 is lower than the frequency of the control signal 333. However, the bit size of the control signal 335 is larger than the bit size of the control signal 333.

[0071] In the example described above with respect to FIG. 3 , IC chip 310 receives data signal 304 generated from data signal 351 using clock signal 305 generated from data signal 351. Therefore, any error in data signal 353 and / or IC chip 350 that causes clock signal 305 to stop will cause C2C interface circuit 320 and application circuit 312 to stop functioning (e.g., pause). Furthermore, because IC chip 310 receives control signal 306 using sideband clock signal 307 that is independent of clock signal 305, any error in data signal 351 and / or IC chip 350 will not affect the operation of C2C interface circuit 320 and application circuit 312. Therefore, if an error occurs in data signal 351 and / or IC chip 350, C2C interface circuit 320 and application circuit 312 can continue to receive and process protocol words.

[0072] In one example, the data paths associated with application circuit 352, C2C interface circuit 360, C2C interface circuit 320, and application circuit 312 may be referred to as synchronous data paths because the data paths transmit and receive data synchronously with the frequency of the data signal to be transmitted. The sideband paths associated with application circuit 354, C2C interface circuit 370, C2C interface circuit 330, and application circuit 314 may be referred to as asynchronous sideband paths because the sideband paths transmit and receive control data (e.g., protocol words) asynchronously with the frequency of the data signal. In an asynchronous sideband path, the application circuit (e.g., application circuit 314) receiving the control data captures the data using a locally generated clock signal. The locally generated clock signal is generated locally within IC chip 310, independent of any data signal. Furthermore, the clock signal used by C2C interface circuit 330 of IC chip 350 is generated by IC chip 310, independent of any data signal.

[0073] In the example of FIG. 4, data signal 425 is communicated from application circuit 312 of IC chip 310 to application circuit 352 of IC chip 350 for transmission. In such an example, application circuit 352 is a transmitter circuit (e.g., a transmitter circuit of a SERDES transceiver, among others) configured to transmit a data signal (e.g., data signal 416). Compared to the example of FIG. 3, in FIG. 4, clock signal 483 is output from clock generation circuit 382. Clock signal 483 is processed by divider circuit 384 to generate divided clock signal 485a, similar to what is described above with respect to clock signal 383 and divided clock signal 385a. Furthermore, divider circuit 384 receives clock signal 489a from divider circuit 388 and generates divided clock signal 485b, as described above with respect to clock signal 389a and divided clock signal 385b. MDLL circuit 386 generates clock signal 487 from divided clock signals 485a and 485b in a similar manner as described above with respect to divided clock signals 385a and 385b and clock signal 387.

[0074] Clock signal 487 is output by driver circuit 355 as clock signal 408 and received by receiver circuit 348 as clock signal 449. Clock signal 408 is communicated as a differential signal over a pair of wires in interface 302. Divider circuit 342 outputs clock signal 449 via a pass-through so that clock signal 449 is not modified by divider circuit 342. Clock signal 408 has a frequency of 3.625 GHz.

[0075] Clock signal 407 is communicated from IC chip 310 to IC chip 350 via interface 302. For example, driver circuit 448 of IC chip 310 outputs clock signal 489 as clock signal 407 to receiver circuit 455 of IC chip 350. Clock signal 407 is communicated as a differential signal via a pair of wires in interface 302. In one example, the clock signal has a frequency of 3.625 GHz. Receiver circuit 455 receives clock signal 407 and outputs clock signal 407 to divider circuit 388. Divider circuit 388 generates clock signals 489a, 489b, and 489c from clock signal 407. For example, divider circuit 388 divides the frequency of clock signal 407 by "Y" to generate clock signal 489a, divides by "Z" to generate clock signal 489b, and shifts the phase of clock signal 407 by 90 degrees to generate clock signal 489c. In one or more examples, "Y" and "Z" are greater than or equal to 1. In one example, "Y" is less than "Z." In one particular example, "Y" is 2.5 and "Z" is 5. In such an example, if clock signal 407 has a frequency of 3.625 GHz, clock signal 489a has a frequency of 1.45 GHz and clock signal 489b has a frequency of 725 MHz.

[0076] Divider circuit 342 generates clock signal 443 from clock signal 489 by dividing the frequency of clock signal 449 by 2 or more. In one example, divider circuit 342 divides the frequency of clock signal 449 by 10 to generate clock signal 443. In an example where clock signal 449 has a frequency of 3.625 GHz, dividing the frequency of clock signal 449 by 10 generates clock signal 443 having a frequency of 362.5 MHz. Clock signal 443 is output to PHY layer circuit 322, link layer circuit 324, and MDLL circuit 344.

[0077] MDLL circuit 344 additionally receives a feedback signal (e.g., clock signal 415) from application circuit 312. Application circuit 312 includes buffer 313 that receives clock signal 445 from MDLL circuit 344 and outputs clock signal 415 based on clock signal 445. MDLL circuit 344 deskews clock signal 443, adjusts for phase alignment mismatch between clock signal 443 and clock signal 415, and generates clock signal 445.

[0078] The clock signal 415 is used by the application circuit 312 to output the data signal 425. For example, the flip-flop 317 captures and outputs the value of the data signal 416 based on the clock signal 415.

[0079] Link layer circuitry 324 receives data signal 425 using clock signal 443 and outputs data signal 425 along with a framing pattern to PHY layer circuitry 322. Link layer circuitry 324 generates the framing pattern from data signal 425. PHY layer circuitry 322 receives data signal 425 and the framing pattern using clock signal 443 and outputs data signal 425 and the framing pattern as data signal 404 using clock signal 449. In one example, data signal 404 is transmitted at 7.25 GHz and has 16 bits. Furthermore, data signal 404 is transmitted using double data processing. In one example, a framing signal is received and used to determine valid data in data signal 425.

[0080] The PHY layer circuitry 322 increases the frequency of the data signal 425 and decreases the number of bits in the data signal 425 to generate the data signal 404. In one example, the frequency increases by the same amount as the number of bits decreases. For example, the frequency of the data signal 425 increases by one or more, and the number of bits in the data signal 425 decreases by one or more. In one particular example, the data signal 425 has 320 bits and a frequency of 362.5 MHz. In such an example, the PHY layer circuitry 322 increases the frequency of the data signal 425 to 7.25 GHz, the frequency of the interface 302. The frequency of the data signal 425 is increased by a factor of 20. Therefore, the number of bits in the data signal 425 decreases from 320 bits to 16 bits by dividing by 20.

[0081] The PHY layer circuitry 362 receives the data signal 404 and the framing pattern using a clock signal 489c. The PHY layer circuitry 362 outputs the data signal 463 and the framing pattern using a clock signal 489b. The link layer circuitry 364 uses the clock signal 489b to detect the framing pattern and identify the start of the data signal 463. In one example, the framing signal is received and used to determine valid data in the data signal 463.

[0082] Link layer circuitry 364 outputs data signal 467 having a frequency based on clock signal 489b. Because the frequency of clock signal 489b is lower than the frequency of data signal 404, link layer circuitry 364 increases the number of bits in data signal 467 based on the difference between the frequency of data signal 404 and clock signal 489b.

[0083] Data signal 467 is received by reducer circuit 368, which adjusts the frequency and bit size of data signal 467 to generate data signal 469. Reducer circuit 368 also receives clock signal 489a. Reducer circuit 368 adjusts the frequency of data signal 467 based on the frequency of clock signal 489a. Because the frequency of clock signal 489a is greater than the frequency of data signal 467, reducer circuit 368 increases the frequency of data signal 467 to generate data signal 469. The frequency of data signal 469 is the frequency of clock signal 489a. The number of bits of data signal 469 decreases by the amount that the frequency of data signal 469 increases. In an example where data signal 467 has a frequency of 725 MHz, the number of bits of data signal 467 is 160 bits, and the frequency of clock signal 489b is 1.45 GHz, data signal 469 has a frequency of 1.45 GHz and 80 bits.

[0084] The application circuit 352 receives the data signal 469 and transmits the data signal 469 from the IC chip 350. For example, the application circuit 352 includes a transceiver circuit that transmits the data signal 469 to another IC chip or device. In one example, the application circuit 352 transmits the data signal 469 to a system external to the multiple IC chip device 300.

[0085] The protocol word 406 is transmitted from the IC chip 310 to the IC chip 550 via a sideband path. The sideband path transmits the protocol word 406 using a clock signal that is different from the clock signal used by the data path to transmit the data signal 404, as described above. The protocol word 406 is transmitted at a frequency of 8 GHz and a bit size of 16 bits. In one example, the protocol word 406 is communicated using 4 GHz double data rate processing.

[0086] 4, the application circuit 314 includes a clock generation circuit 418 that generates a clock signal 417. In another example, the clock generation circuit 418 may be external to the application circuit 314 and output the clock signal 417 to the application circuit 314. The clock signal 417 is a clock signal for the application circuit 314. For example, a flip-flop 319 in the application circuit 314 outputs a protocol word 421 from the data signal 419 based on the clock signal 417. The protocol word 421 is output to the link layer circuit 334, bypassing the protocol layer circuit 336. The link layer circuit 334 further receives a clock signal 447. The clock signal 447 is generated by a clock circuit 346 from a clock signal 445 generated by the clock generation circuit 444. In one example, the clock circuit 346 reduces the frequency of the clock signal 445 by dividing the frequency of the clock signal by two or more. The clock signal 447 is output to the link layer circuit 334 and the PHY layer circuit 332 .

[0087] The link layer circuit 334 receives protocol words 421 from the application circuit 314 using a clock signal 447 and outputs protocol words (or control signals) 435 from the protocol words 421 based on the clock signal 417. Additionally, the link layer circuit 334 generates a framing pattern that is output along with the protocol words 435 to identify the start of the control signals 435. The frequency of the protocol words 435 corresponds to the frequency of the clock signal 447. In one example, the control signals 435 are transmitted along with a framing signal. The framing signal defines the region of valid data within the control signals 435. In one example, the framing signal is used to mask invalid data within the control signals 435.

[0088] The clock circuit 346 further outputs a clock signal 445 to the PHY layer circuit 332 and the divider circuit 437. The PHY layer circuit 332 receives the protocol words 435 and corresponding framing patterns using the clock signal 447 and generates and outputs the protocol words 406 from the protocol words 435 based on the clock signal 445. In one example, the PHY layer circuit increases the frequency of the protocol words 435 and decreases the bit size of the protocol words 435 based on the frequency of the clock signal 445. Thus, the bit size of the protocol words 406 is smaller than the bit size of the protocol words 435 and the frequency of the protocol words 406 is greater than the frequency of the protocol words 435. In one or more examples, the PHY layer circuit 332 increases the frequency of the protocol words 435 and decreases the bit size of the protocol words 435 by more than two times.

[0089] Clock signal 445 is transmitted by driver circuit 437 as clock signal 409 and received by receiver circuit 438 in IC chip 350. Clock signal 409 is communicated as a differential signal over two or more wires of interface 302. Receiver circuit 438 outputs clock signal 408 as clock signal 439. Control signal 439 is received by clock circuit 390. Clock circuit 390 generates clock signal 492 from clock signal 439 and outputs clock signal 492 to PHY layer circuit 372. Clock circuit 390 shifts the frequency of clock signal 439 to generate clock signal 492. Furthermore, clock circuit 390 generates clock signal 491 from clock signal 439. In one example, clock circuit 390 generates clock signal 491 by dividing the frequency of clock signal 439 by two or more. In one example, clock circuit 390 generates clock signal 439 by dividing the frequency of clock signal 491 by 8. Clock signal 491 is output to link layer circuitry 374 and PHY layer circuitry 372.

[0090] The clock generation circuit 394 generates a clock signal 495 and outputs the clock signal 495 to the application circuit 354 and the link layer circuit 374. The frequency of the clock signal 395 is lower than the frequency of the clock signal 491. In one example, the frequency of the clock signal 495 is 200 MHz.

[0091] PHY layer circuitry 372 receives the framing pattern and protocol words 406 using clock signal 492 and outputs protocol words 473 using clock signal 491. Thus, the frequency of protocol words 473 is the same as the frequency of clock signal 491 and is lower than the frequency of protocol words 406. Furthermore, the number of bits in protocol word 473 is greater than the number of bits in protocol word 406. The number of bits in protocol word 473 increases relative to protocol word 406 by the same factor that the frequency of protocol word 473 decreases relative to protocol word 406.

[0092] Link layer circuitry 374 receives protocol word 473 using clock signal 491. Link layer circuitry 374 identifies the framing pattern associated with protocol word 473 and identifies the start of protocol word 473. Link layer circuitry 374 outputs protocol word 475 using clock signal 495. Link layer circuitry 374 generates control signal 375 from protocol word 473 and clock signal 495 by reducing the clock signal of protocol word 473 to the frequency of clock signal 495. Additionally, link layer circuitry 374 increases the number of bits in protocol word 475 relative to protocol word 473 based on the factor by which the frequency of protocol word 475 is reduced relative to protocol word 473.

[0093] The application circuit 354 receives the protocol word 475 using the clock signal 495 and transmits the control signal 477 from the IC chip 350 via the transmit circuitry of the application circuit 354. The application circuit 354 may transmit the control signal 477 to another IC chip in the multiple IC chip device 300 or to a system external to the multiple IC chip device 300.

[0094] 4 , the sideband path including application circuit 314, C2C interface circuit 330, C2C interface circuit 370, and application circuit 354 employs a clock signal that is independent of the frequency of data signal 471 transmitted by application circuit 352. Thus, the sideband path including application circuit 314, C2C interface circuit 330, and C2C interface circuit 370 is asynchronous with data signal 471. In one or more examples, the data path including application circuit 312, C2C interface circuit 320, C2C interface circuit 360, and application circuit 352 uses a clock signal that is based on the frequency of data signal 471. Thus, the data path including application circuit 312, C2C interface circuit 320, C2C interface circuit 360, and application circuit 352 uses a clock signal that is based on the frequency of data signal 471 and is synchronous with data signal 471. In one example, the Sideband path continues to transmit protocol words (eg, control data) even when an error occurs in the data path and the data path stops transmitting data signals.

[0095] FIG. 5 is a block diagram of a multiple IC chip device 500. The multiple IC chip device 500 includes an IC chip 510 and an IC chip 550. The IC chip 510 is connected to the IC chip 550 via an interface 502. The IC chip 510 is configured similarly to the IC chip 110 of FIG. 1 and the IC chip 310 of FIG. 3, the IC chip 550 is configured similarly to the IC chip 120 of FIG. 1 and the IC chip 350 of FIG. 1, and the interface 502 is configured similarly to the interface 130 of FIG. 1 and the interface 302 of FIG. 2. In the example of FIG. 5, the IC chip 510 is a main IC chip, and the IC chip 550 is an auxiliary IC chip or chiplet.

[0096] As described above with respect to multiple IC chip device 300 of Figure 3, multiple IC chip device 500 is configured such that both data path and sideband connections are used between IC chip 510 and IC chip 550 to communicate data and control data (or other sideband information). However, compared to multiple IC chip device 300 of Figure 3, multiple IC chip device 500 includes sideband circuits 522, 524, 552, 562, and 564 that communicate with each other via sideband and control signals 506.

[0097] IC chip 550 includes application circuit 352 and C2C interface circuit 560. C2C interface circuit 560 includes PHY layer circuit 362, link layer circuit 364, protocol layer circuit 366, and reducer circuit 368. IC chip 550 also includes sideband circuits 552, 562, and 564. Sideband circuits 562 and 564 are included within C2C interface circuit 560. Furthermore, sideband circuit 562 may be included inside or outside PHY layer circuit 362. Sideband circuit 564 may be included inside or outside link layer circuit 364.

[0098] Additionally, IC chip 350 includes clock circuit 380. Clock circuit 380 generates a datapath clock signal (e.g., clock signal 505). A sideband clock signal is generated and transmitted through sideband circuits 552, 562, and 564. In one example, the sideband clock signal is transmitted as control signal 506. The sideband clock signal is generated independently of clock signal 505. The sideband clock signal may be referred to as a logic clock signal.

[0099] In one example, IC chip 550 is configured as a receiver circuit in a transceiver circuit. IC chip 550 receives data signal 551.

[0100] The clock circuit 380 includes a clock generation circuit 382, ​​a multiplying delay locked loop (MDLL) circuit 386, and a divider circuit 388. In one or more examples, the clock circuit 380 includes an optional divider circuit 38.

[0101] The IC chip 510 includes an application circuit 512 and a C2C interface circuit 320. The C2C interface circuit 320 includes a PHY layer circuit 322, a link layer circuit 324, and a protocol layer circuit 326. The C2C interface circuit 320 further includes sideband circuits 522 and 524. The sideband circuit 522 is included inside or outside the PHY layer circuit 322. The sideband circuit 524 is included inside or outside the link layer circuit 324.

[0102] Additionally, IC chip 510 includes clock circuit 340. Clock circuit 340 receives clock signal 505 (e.g., a data path or interface clock signal) from IC chip 550. Clock signal 505 is communicated as a differential signal. Sideband circuit 522 and sideband circuit 524 receive control signal 506 from IC chip 350. Control signal 506 may be a sideband clock signal.

[0103] The clock circuit 340 includes a frequency divider circuit 342 and an MDLL circuit 344. The clock circuit 346 is a frequency divider circuit.

[0104] In one example, IC chip 350 communicates data signal 504, clock signal 505, and control signal 506 via interface 302. IC chip 550 generates data signal 504 and clock signal 505 based on data signal 351. For example, clock circuit 380 generates clock signal 505 based on data signal 551. Clock generation circuit 382 generates clock signals 583 and 584 from data signal 351. Clock signals 583 and 584 may have the same or different frequencies. In one or more examples, clock generation circuit 382 generates clock signals 583 and 584 based on receiving data signal 351. Furthermore, the frequency of clock signals 583 and / or 584 corresponds to the frequency of data signal 553 generated by application circuit 352 from data signal 351. In one example, clock signals 583 and / or 584 have a frequency of 1.45 GHz, and data signal 553 has a frequency of 1.45 GHz. Clock signal 583 is received by application circuit 352, and clock signal 584 is received by MDLL circuit 386. In one example, clock signal 584 is received by divider circuit 384. Clock signal 583 serves as the clock signal for application circuit 352. In examples where divider circuitry is included, divider circuit 384 divides the frequency of clock signal 584 by two or more to determine divided clock signal 585. Divided clock signal 585 is received by MDLL circuit 386. In examples where divider circuit 384 is omitted, MDLL circuit 386 receives clock signal 584.

[0105] MDLL circuit 386 reduces the delay of clock signals 584 and 585. Furthermore, MDLL circuit 386 generates clock signal 587 from clock signal 584 or 585. For example, MDLL circuit 386 multiplies the frequency of clock signal 585 (or 584) by more than two to generate clock signal 587. In one or more examples, clock signal 587 has a frequency of 2.9 GHz. Clock signal 587 is output by driver circuit 356 through interface 502 as clock signal 505. In one example, clock signal 505 is communicated as a differential signal through two wires of interface 502.

[0106] Clock signal 587 is further received by divide-by circuit 388. Divide circuit 388 outputs clock signals 589a, 589b, and 589c. Divide circuit 388 generates clock signal 589a by reversing the processing applied by divide-by circuit 384 and MDLL circuit 386. For example, divide-by circuit 588 divides the frequency of clock signal 587 by two or more, thereby multiplying the frequency of the clock signal by two or more. Divide circuit 388 further generates clock signal 589b by dividing the frequency of clock signal 587 by two or more. Clock signal 589c passes through divide-by circuit 388 without being processed or altered. The frequency of clock signal 589c is the same as the frequency of clock signal 587.

[0107] Clock signal 589a is received by reducer circuit 368, which processes data signal 553 using clock signal 589a. Reducer circuit 368 reduces the frequency of data signal 553 by two or more and increases the number of bits to generate data signal 563. In one example, data signal 553 has 80 bits and a frequency of 1.45 GHz. In this example, when the frequency is reduced by two and the number of bits is increased, data signal 563 has a frequency of 725 MHz. By reducing the frequency of data signal 553 to generate data signal 563, data signal 563 is placed within the operating range of link layer circuitry 364 and PHY layer circuitry 362.

[0108] Because data signal 563 is compatible with link layer circuitry 364 and PHY layer circuitry 362, protocol layer circuitry 366 is bypassed. Link layer circuitry 364 receives clock signal 589b and generates a framing pattern to indicate the start of data signal 563. The framing pattern is communicated to PHY layer circuitry 362 along with data signal 563. In one example, data signal 563 is transmitted with the framing signal. The framing signal defines the region of valid data within data signal 563. In one example, the framing signal is used to mask invalid data within data signal 563. PHY layer circuitry 362 receives clock signals 589b and 589c and generates data signal 504 from data signal 563. PHY layer circuitry 362 increases the frequency of data signal 563 and reduces the bit size by two or more to generate data signal 504. In one or more examples, the PHY layer circuitry 362 increases the frequency and reduces the bit size of the data signal 563 by 5, 10, 15, or 20 times or more. In one example, the PHY layer circuitry 362 increases the frequency and reduces the bit size of the data signal 563 by 2 times or more. If the data signal 563 has a bit size of 160 bits and a frequency of 725 MHz, the data signal 504 has a bit size of 16 bits and a frequency of 7.25 GHz. In one example, the PHY layer circuitry 362 has a multiplication ratio of 16 to 1. In one or more examples, the PHY layer circuitry 362 has other multiplication ratios. In one example, the data signal 504 has a frequency of 7.25 GHz and 16 bits. In another example, the data signal 504 has a frequency higher or lower than 7.25 GHz.

[0109] A clock signal 506 is communicated from IC chip 550 to IC chip 510 via interface 502. Control signal 506 is generated based on a control signal generated by application circuit 352. Control signal 506 may be a sideband clock signal or may include an instruction for the frequency of a sideband clock signal. Control signal 506 is received by sideband circuit 522 and then by sideband circuit 524. The output of sideband circuit 524 is provided to flip-flop 517. In one example, the clock signal of control signal 506 is generated based on a clock signal generated by IC chip 550 independent of data signal 551.

[0110] The IC chip 510 receives a data signal 504, a clock signal 505, and a control signal 506. The receiver circuit 348 receives the clock signal 505. The receiver circuit 348 outputs the received clock signal 505 as a clock signal 549 to the divider circuit 342. The clock circuit 342 reduces the frequency of the clock signal 549 by two or more. In one specific example, the divider circuit 342 reduces the frequency of the clock signal 549 by ten. The divider circuit 342 further outputs the clock signal 549, which functions as a pass-through so that the clock signal 549 is not modified by the divider circuit 342. The clock signal 549 is output to the PHY layer circuit 322.

[0111] Clock signal 543 is output to PHY layer circuit 332 and link layer circuit 334. Clock signal 543 is further output to MDLL circuit 344. MDLL circuit 344 generates clock signal 545 based on clock signal 543 and a feedback signal (e.g., clock signal 515) received from application circuit 512. Clock signal 543 is output to application circuit 512. In one example, buffer 313 of application circuit 512 receives clock signal 545 and generates clock signal 515. In one example, clock signal 515 is a capture clock signal for flip-flop 517 of application circuit 512. Thus, clock signal 515, which is a clock signal for application circuit 512, is generated based on data signal 553.

[0112] In one or more examples, the feedback signal (eg, clock signal 515 ) is used by MDLL circuit 344 to deskew clock signal 543 and for phase alignment of clock signal 543 .

[0113] PHY layer circuitry 322 receives data signal 504 and generates data signal 523 from data signal 504 and clock signals 549 and 543. In one example, PHY layer circuitry 322 receives data signal 504 using clock signal 549 and generates data signal 553 using clock signal 543. Link layer circuitry 324 detects a framing pattern associated with data signal 523, identifies the start of data signal 523 based on the framing pattern, and generates data signal 525 based on clock signal 543. In one example, the framing signal is used to detect valid data in data signal 525.

[0114] The data signal 525 has a frequency corresponding to the operating frequency of the application circuit 512. For example, the frequency of the data signal 525 is the same as the frequency of the clock signal 505. Furthermore, the bit size of the data signal 525 is larger than the bit size of the data signal 504. The bit size of the data signal 525 is more than twice as large as the bit size of the data signal 504, and the frequency of the data signal 504 is more than twice as large as the frequency of the data signal 525. In one example, the PHY layer circuit 322 divides the frequency of the data signal 504 and multiplies the bit size of the data signal 504 by more than two to generate the data signal 523. In one example, the PHY layer circuit 322 has a multiplication ratio of 20 to 1. In another example, the PHY layer circuit 322 has another multiplication ratio.

[0115] The data signal 525 is received by the application circuit 512 based on the clock signal 515. In one example, the flip-flop 317 captures the data signal 525 based on the clock signal 315.

[0116] 5, IC chip 510 receives data signal 504 generated from data signal 351 using clock signal 505 generated from data signal 351. Thus, any error in data signal 553 and / or IC chip 550 that causes clock signal 505 to stop will cause C2C interface circuit 320 and application circuit 512 to stop functioning (e.g., pause). Furthermore, because IC chip 310 receives control signal 506 using a sideband clock signal of control signal 506 that is independent of clock signal 505, any error in data signal 351 and / or IC chip 550 will not affect the operation of C2C interface circuit 520 and application circuit 512. Thus, if an error occurs in data signal 351 and / or IC chip 550, C2C interface circuit 520 and application circuit 512 can continue to receive and process protocol words.

[0117] In one example, the data paths associated with application circuit 352, C2C interface circuit 560, C2C interface circuit 520, and application circuit 512 may be referred to as synchronous data paths because the data paths transmit and receive data synchronously with the frequency of the data signal to be transmitted. The sideband paths associated with sideband circuits 552, 564, 562 and sideband circuits 522 and 524 may be referred to as asynchronous sideband paths because the sideband paths transmit and receive control data (e.g., protocol words) asynchronously with the frequency of the data signal.

[0118] In the example of Figure 6, data signal 625 is communicated from application circuit 312 of IC chip 510 to application circuit 352 of IC chip 550 for transmission. In such an example, application circuit 352 is a transmitter circuit (e.g., a transmitter circuit of a SERDES transceiver, among others) configured to transmit a data signal (e.g., data signal 616). Compared to the example of Figure 5, in Figure 6, clock signals 681 and 683 are output from clock generation circuit 382. Control signal 683 is received by application circuit 352.

[0119] Clock signal 681 is processed by divider circuit 384 to generate divided clock signal 685, similar to that described above with respect to clock signal 683 and divided clock signal 685. In one or more examples, divider circuit 384 is omitted and clock signal 681 is received by MDLL circuit 386. MDLL circuit 386 generates clock signal 687 from divided clock signal 685 or clock signal 681, similar to that described above.

[0120] Clock signal 687 is output by driver circuit 355 as clock signal 608 and received by receiver circuit 348 as clock signal 649. Clock signal 608 is communicated as a differential signal over a pair of wires in interface 502. Divider circuit 342 outputs clock signal 649 via a pass-through such that clock signal 649 is not modified by divider circuit 342.

[0121] Clock signal 607 is communicated from IC chip 510 to IC chip 550 via interface 502. For example, driver circuit 448 of IC chip 310 outputs clock signal 649 as clock signal 607 to receiver circuit 455 of IC chip 550. Clock signal 607 is communicated as a differential signal via a pair of wires in interface 502. Receiver circuit 455 receives clock signal 607 and outputs clock signal 607 to divider circuit 388. Divider circuit 388 generates clock signals 689a, 689b, and 689c from clock signal 607. For example, divider circuit 388 divides the frequency of clock signal 607 by “Y” to generate clock signal 689a, divides by “Z” to generate clock signal 689b, and shifts the phase of clock signal 607 by 90 degrees to generate clock signal 689c. In one or more examples, “Y” and “Z” are equal to or greater than 1. In one example, "Y" is less than "Z." In one particular example, "Y" is 2.5 and "Z" is 5.

[0122] Divider circuit 342 generates clock signal 643 from clock signal 689 by dividing the frequency of clock signal 649 by 2 or more. In one example, divider circuit 342 divides the frequency of clock signal 649 by 10 to generate clock signal 643. Clock signal 643 is output to PHY layer circuit 322, link layer circuit 324, and MDLL circuit 344.

[0123] MDLL circuit 344 additionally receives a feedback signal (e.g., clock signal 615) from application circuit 312. Application circuit 312 includes buffer 313 that receives clock signal 645 from MDLL circuit 344 and outputs clock signal 615 based on clock signal 645. MDLL circuit 344 deskews clock signal 643, adjusts for phase alignment mismatch between clock signal 643 and clock signal 615, and generates clock signal 645.

[0124] The clock signal 615 is used by the application circuit 312 to output a data signal 625. For example, a flip-flop 317 captures and outputs the value of the data signal 616 based on the clock signal 615.

[0125] Link layer circuitry 324 receives data signal 625 using clock signal 643 and outputs data signal 627 along with a framing pattern to PHY layer circuitry 322. Link layer circuitry 324 generates the framing pattern from data signal 627. PHY layer circuitry 322 receives data signal 627 and the framing pattern using clock signal 643 and outputs data signal 627 and the framing pattern as data signal 604 using clock signal 649. In one example, data signal 627 is transmitted along with a framing signal. The framing signal defines a region of valid data within data signal 627. In one example, the framing signal is used to mask invalid data within data signal 627.

[0126] The PHY layer circuitry 322 increases the frequency of the data signal 627 and decreases the number of bits in the data signal 627 to generate the data signal 604. In one example, the frequency is increased by the same amount as the number of bits is decreased. For example, the frequency of the data signal 627 is increased by one or more, and the number of bits in the data signal 627 is decreased by one or more.

[0127] PHY layer circuit 362 receives data signal 604 and the framing pattern using clock signal 689c. PHY layer circuit 362 outputs data signal 663 and the framing pattern using clock signal 689b. Link layer circuit 364 uses clock signal 689b to detect the framing pattern and identify the start of data signal 663. Furthermore, the framing signal is used to define valid bits in data signal 604. Link layer circuit 364 outputs data signal 667 having a frequency based on clock signal 689b. Because the frequency of clock signal 689b is lower than the frequency of data signal 604, link layer circuit 364 increases the number of bits in data signal 667 based on the difference between the frequency of data signal 604 and clock signal 689b.

[0128] Data signal 667 is received by reducer circuit 368, which adjusts the frequency and bit size of data signal 667 to generate data signal 669. Reducer circuit 368 also receives clock signal 689a. Reducer circuit 368 adjusts the frequency of data signal 667 based on the frequency of clock signal 689a. Because the frequency of clock signal 689a is higher than the frequency of data signal 667, reducer circuit 368 increases the frequency of data signal 667 to generate data signal 669. The frequency of data signal 669 is the frequency of clock signal 689a.

[0129] The application circuit 352 receives the data signal 669 and transmits the data signal 669 from the IC chip 350 .

[0130] Control word 609 is transmitted from IC chip 510 to IC chip 550 via interface 502. Control signal 609 may be a sideband clock signal and / or may include an indication of the frequency of the sideband clock signal. In one example, sideband circuits 522 and 524 generate the sideband clock signal and / or data indicative of the frequency of the sideband clock signal and transmit control signal 609 including the sideband clock signal or information corresponding to the sideband clock signal. The sideband clock signal is generated independently of clock signals 608 and 607 and independently of data signal 616. In one or more examples, the frequency of the sideband clock signal is different from the frequency of clock signal 607 or 608. In one or more examples, the frequency of the sideband clock signal is lower than the frequency of clock signal 607 or 608.

[0131] The sideband clock signal transmitted as control signal 609 is asynchronous with data signal 671. Thus, the data path including application circuit 312, C2C interface circuit 320, C2C interface circuit 360, and application circuit 352 uses a clock signal that is based on the frequency of and synchronous with data signal 671. In one example, the control signal path continues to transmit control data and sideband clock signals even when an error occurs in the data path and when the data path stops transmitting data signals.

[0132] 5 and 6, interfaces 502 and 502 communicate control data over sideband paths. The sideband paths of interfaces 502 and 502 include one or more data lines. In one example, the sideband paths include one data line, a single port on IC chip 510, and a single port on IC chip 550. In another example, the sideband paths include two or more data lines, two or more ports on IC chip 510, and two or more ports on IC chip 550. Furthermore, interfaces 502 and 502 communicate data signal 504, clock signal 505, data signal 604, and clock signals 608 and 607, respectively, using two or more data lines. In one example, interfaces 502 and 502 include 40 or more data lines.

[0133] In one or more examples, when transmitting data from a first IC chip (e.g., IC chip 110) to a second IC chip (e.g., IC chip 120), the data is synchronized and transmitted as a continuous stream of data. During transmission, the data is serialized and deserialized. However, during transmission, the clock signal source may be constant. Therefore, errors may occur during transmission of the data. In one example, synchronization with a high-speed clock signal generated within the IC chip (e.g., IC chip 110 or 120) is used to ensure that a constant clock signal source is present.

[0134] FIG. 7 illustrates waveforms of various clock signals, control signals, and data signals. As illustrated in FIG. 7, clock signal 710 is a clock signal for an application circuit (e.g., application circuit 210 in FIG. 7). Clock signal 712 is a clock signal for a PHY layer circuit (e.g., PHY layer circuit 216 in FIG. 2), and clock signal 714 is a clock signal for a link layer circuit (e.g., link layer circuit 214 in FIG. 2). Signal 716 is a multiplexer select signal, and data signal 718 is a channel data signal. Furthermore, signal 720 is a link layer circuit clock signal for a receiver (e.g., link layer circuit 224 in FIG. 2), and signal 722 is a data output signal. Clock signal 714 is synchronized with clock signal 712. Furthermore, data in data signal 718 is transmitted on the rising edge of clock signal 714. Upon completion of the data in the transmitted data signal, a series of zeros is transmitted in data signal 718 until the next rising edge is detected. On the next rising edge, the framing pattern (e.g., a series of 1's) and the new data signal.

[0135] As illustrated by the timing diagram of FIG. 7, the four cycles of synchronization are reduced to 0.5 cycles. In one example, within 14.5 cycles of clock signal 712, there are 0.5 cycles available for setting up the transmit circuitry, 12 cycles of latency, 1 cycle of jitter, 1 cycle of misalignment, and 0 cycles for receive circuitry setup. In one example, one or more of MDLL circuits 840, 842, 881, and 886 of FIG. 8 (or MDLL circuits 386, 390, 344, and 346 of FIGS. 3-6) are configured in a primary-secondary configuration. The primary MDLL circuits are locked to their respective C2C interface clock signals. The primary MDLL circuits set the control voltages for the C2C interface circuits. Additionally, the primary MDLL circuits provide a continuous clock signal for regenerating the corresponding fabric (e.g., application) clock signals. The secondary MDLL circuits create a burst clock signal. The burst clock signal may be used by a PHY layer circuit (e.g., PHY layer circuits 322, 332, 822, 836, 892, 922, and / or 982 in FIGS. 3-6 and 8-9) and begins on the rising edge of the clock signal for the application circuit.

[0136] In one example, the clock synchronization technique is applied to the multiple-IC chip device of FIG. 8. FIG. 8 illustrates multiple-IC chip device 800. Multiple-IC chip device 800 includes IC chip 810 and IC chip 850. IC chips 810 and 850 are main IC chips configured similarly to IC chips 110 and 120 of FIG. 1. IC chip 810 includes application circuit 812, application circuit 814, C2C interface circuit 820, and C2C interface circuit 830. Furthermore, IC chip 810 includes clock circuit 840, clock circuit 842, driver circuit 844, driver circuit 846, and receiver circuit 848.

[0137] The C2C interface circuit 820 includes a PHY layer circuit 822, a link layer circuit 824, and a protocol layer circuit 826. The C2C interface circuit 820 has a similar configuration to the C2C interface circuit 112. The PHY layer circuit 822 has a similar configuration to the PHY layer circuit 216 in FIG. 2, the link layer circuit 824 has a similar configuration to the link layer circuit 214 in FIG. 2, and the protocol layer circuit 826 has a similar configuration to the protocol layer circuit 212 in FIG. 2.

[0138] The C2C interface circuit 830 includes a PHY layer circuit 832, a link layer circuit 834, and a protocol layer circuit 836. The C2C interface circuit 830 has a configuration similar to that of the C2C interface circuit 112. The PHY layer circuit 832 has a configuration similar to that of the PHY layer circuit 216 in FIG. 2, the link layer circuit 834 has a configuration similar to that of the link layer circuit 214 in FIG. 2, and the protocol layer circuit 836 has a configuration similar to that of the protocol layer circuit 212 in FIG. 2.

[0139] The IC chip 850 includes an application circuit 852, an application circuit 854, a C2C interface circuit 860, and a C2C interface circuit 870. The IC chip 850 further includes a clock circuit 880, a clock circuit 881, a receiving circuit 883, a receiving circuit 889, and a driver circuit 852.

[0140] C2C interface circuit 860 includes a PHY layer circuit 882, a link layer circuit 884, and a protocol layer circuit 866. C2C interface circuit 860 is configured similarly to C2C interface circuit 112. PHY layer circuit 882 is configured similarly to PHY layer circuit 216 in FIG. 2, link layer circuit 884 is configured similarly to link layer circuit 214 in FIG. 2, and protocol layer circuit 866 is configured similarly to protocol layer circuit 212 in FIG. 2.

[0141] C2C interface circuit 870 includes PHY layer circuit 872, link layer circuit 894, and protocol layer circuit 896. C2C interface circuit 870 is configured similarly to C2C interface circuit 112. PHY layer circuit 872 is configured similarly to PHY layer circuit 216 in FIG. 2, link layer circuit 874 is configured similarly to link layer circuit 214 in FIG. 2, and protocol layer circuit 876 is configured similarly to protocol layer circuit 212 in FIG. 2.

[0142] The application circuit 812 outputs a data signal 813 based on a clock signal 815. The clock signal 815 is a clock signal of the application circuit 812. The clock signal 815 is output to a clock circuit 840. The receiving circuit 840 also receives a clock signal 817. The clock signal 817 is generated and output from a clock generating circuit (not shown) inside or outside the IC chip 810. The clock circuit 840 divides the frequency of the clock signal 817 and synchronizes the clock signal 817 with the clock signal 815 to generate a clock signal 841. The clock circuit 840 divides the frequency of the clock signal 817 by two or more. In one example, the clock circuit 840 divides the frequency of the clock signal 817 by eight. Furthermore, the clock circuit 840 generates a clock signal 843. In one example, the clock signal 843 is the clock signal 817. In such an example, clock circuit 840 acts as a pass-through and outputs clock signal 843 such that clock signal 817 is the same as clock signal 843. In one example, the clock signal has a frequency of 4 GHz. In one or more examples, the clock signal has a frequency higher or lower than 4 GHz.

[0143] Link layer circuitry 824 receives clock signal 841 and data signal 813. Link layer circuitry 824 generates a framing pattern from data signal 813. Furthermore, link layer circuitry 824 generates data signal 825 based on clock signal 841. In one example, data signal 813 is transmitted along with a framing signal. The framing signal defines regions of valid data within data signal 813. In one example, the framing signal is used to mask invalid data within data signal 813.

[0144] The frequency of data signal 825 is higher than the frequency of data signal 813, and the number of bits in data signal 825 is fewer than the number of bits in data signal 813. In one example, the number of bits in data signal 825 is reduced by the same factor as the frequency of data signal 825 is increased relative to the number of bits and frequency of data signal 813. The frequency of data signal 825 is based on the frequency of clock signal 841. In one example, the frequency of data signal 825 is the same as the frequency of data signal 841.

[0145] The PHY layer circuit 822 receives a clock signal 841, a clock signal 843, and a data signal 825 (and a corresponding framing pattern). The PHY layer circuit 822 receives the data signal 825 using the clock signal 841. The PHY layer circuit 822 generates and outputs the data signal 827 and a corresponding framing pattern using the clock signal 841. Additionally, a framing signal is received and can be used to detect valid bits in the data signal 827. The frequency of the data signal 827 is higher than the frequency of the data signal 825, and the number of bits in the data signal 827 is fewer than the number of bits in the data signal 825. In one example, the number of bits in the data signal 827 is reduced by the same factor as the frequency of the data signal 827 is increased relative to the number of bits and frequency of the data signal 825. The frequency of the data signal 827 is based on the frequency of the clock signal 843. In one example, the frequency of the data signal 827 is the same as the frequency of the clock signal 843. In one example, the data signal 827 is transmitted at 4 GHz. Additionally, the data signal 827 is transmitted using double data rate processing.

[0146] The driver circuit 844 receives the clock signal 843 and outputs the clock signal 843 to the receiving circuit 883 of the IC chip 850. Additionally, the driver circuit 846 outputs the clock signal 845 to the receiving circuit 884 of the IC chip 850. In one example, the clock signal 845 is generated and transmitted via a sideband circuit as described above with respect to Figures 5 and 6. In one example, the clock signal 843 is generated at a transition (e.g., a rising edge or a falling edge) of the clock signal 845.

[0147] Clock circuit 880 receives clock signal 843 from receiving circuit 883 and generates and outputs clock signals 891 and 892. Clock circuit 880 shifts the phase of clock signal 843 by 90 degrees to generate clock signal 891. Clock circuit 880 divides the frequency of clock signal 843 by two or more to generate clock signal 892. In one example, clock circuit 880 divides the frequency of clock signal 843 by eight to generate clock signal 892.

[0148] PHY layer circuitry 882 receives clock signal 891, clock signal 892, data signal 827, and the corresponding framing pattern. PHY layer circuitry 882 uses clock signal 891 to receive data signal 827 and the corresponding framing pattern, and uses clock signal 892 to output data signal 863 to link layer circuitry 884. The framing signal is received and used to identify valid data in data signal 827. For example, PHY layer circuitry 882 reduces the frequency of data signal 827 by a common factor and increases the bit size of data signal 827 to generate data signal 863. The frequency of data signal 863 is the frequency of clock signal 892.

[0149] Data signal 863, the corresponding framing pattern, and clock signal 892 are received by link layer circuitry 884. Link layer circuitry 884 uses clock signal 892 to receive data signal 863 and the corresponding framing pattern. Because the data in data signal 863 is in a serial format, link layer circuitry 884 uses the framing pattern to identify the start of data signal 863. The framing signal is received and used to identify valid data in data signal 863.

[0150] Link layer circuitry 884 generates data signal 865 from data signal 863. Data signal 865 has a lower frequency than data signal 863 and a greater number of bits than data signal 863. In one example, link layer circuitry 884 increases the number of bits of data signal 865 and decreases the frequency of data signal 865 by the same factor to generate data signal 863. In one example, data signal 865 has a frequency of 200 MHz and a bit size of 892 bits.

[0151] Control signal 865 is received by application circuit 852. Application circuit 852 receives data signal 865 using clock signal 894. In one example, clock circuit 881 is an MDLL that receives clock signal 815 from receiving circuit 884. Clock circuit 881 also receives a feedback signal (e.g., clock signal 894). Based on the feedback signal, clock circuit 881 mitigates phase alignment error, deskews clock signal 815, and generates and outputs clock signal 893. Clock signal 893 is received by application circuit 852. In one example, application circuit 852 includes buffer 853 and flip-flop 855. Buffer 853 outputs clock signal 894 from clock signal 893. Clock signal 894 is received by flip-flop 855 and used to receive data signal 865.

[0152] Application circuit 854 also receives a clock signal 894 from application circuit 852. Application circuit 854 includes a flip-flop 855 that uses clock signal 894 to output a data signal 857.

[0153] Clock signal 894 is further received by clock circuit 886. Clock circuit 886 additionally receives clock signal 895 from a clock generation circuit (not shown) external or internal to IC chip 850. Clock circuit 886 synchronizes clock signal 895 using clock signal 894 to generate clock signals 887 and 897. Clock signal 887 is the same as clock signal 895. In one example, clock signal 895 is the same as clock signal 817. Clock signal 895 may have a frequency of 4 GHz. In other examples, clock signal 895 has a frequency higher or lower than 4 GHz.

[0154] Clock circuit 886 reduces the frequency of clock signal 895 to generate clock signal 897. For example, clock circuit 886 divides the frequency of clock signal 895 by two or more to generate clock signal 897. In one example, clock circuit 886 divides the frequency of clock signal 895 by eight to generate clock signal 897.

[0155] Link layer circuit 874 receives clock signal 897 from clock circuit 886. Link layer circuit 874 receives data signal 857 from application circuit 854 using clock signal 897. Link layer circuit 874 uses clock signal 897 to generate a framing pattern and data signal 875 from data signal 857. The frequency of data signal 875 is higher than the frequency of data signal 857, and the bit size of the data signal is smaller than the bit size of data signal 857. In one example, data signal 875 is transmitted with a framing signal. The framing signal defines a region of valid data in data signal 875. In one example, the framing signal is used to mask invalid data in data signal 875.

[0156] PHY layer circuitry 872 receives clock signals 896 and 897. PHY layer circuitry 872 uses clock signal 897 to receive data signal 875 and a corresponding framing pattern and uses clock signal 896 to generate data signal 873 from the data signal. In one example, a framing signal is received and used to identify valid data in data signal 873.

[0157] PHY layer circuitry 872 increases the frequency of data signal 875 and decreases the bit size of data signal 875 by the same factor to generate data signal 873. In one or more examples, PHY layer circuitry 872 increases the frequency of data signal 875 by two or more and decreases the bit size of data signal 875 by two or more to generate data signal 873. In one or more examples, PHY layer circuitry 872 increases the frequency of data signal 875 by two or more and decreases the bit size of data signal 875 by 16 to generate data signal 873. Data signal 873 has a bit size of 42 bits and a frequency of 4 GHz. Furthermore, data signal 873 is communicated via double data rate processing.

[0158] Driver circuit 885 receives clock signal 896 and outputs clock signal 896 as clock signal 887 to receiving circuit 848 of IC chip 810. Clock circuit 842 receives clock signal 887 and outputs clock signals 897 and 898. Clock circuit 842 shifts the phase of clock signal 887 by 90 degrees to generate clock signal 897. Clock circuit 842 divides the frequency of clock signal 887 by two or more to generate clock signal 898. In one example, clock circuit 842 divides the frequency of clock signal 887 by eight to generate clock signal 898.

[0159] PHY layer circuitry 832 receives clock signal 897 and clock signal 898. PHY layer circuitry 832 receives data signal 873 and a corresponding framing pattern using clock signal 897. In one example, PHY layer circuitry 832 reduces the frequency of data signal 873 by more than two times and increases the bit size of data signal 873 to generate data signal 837. In one particular example, PHY layer circuitry 832 reduces the frequency of data signal 873 by 16 and increases the bit size of data signal 873 to generate data signal 837. PHY layer circuitry 832 also generates and outputs data signal 837 and a corresponding framing pattern using clock signal 898.

[0160] Link layer circuitry 834 receives clock signal 898. Additionally, link layer circuitry 834 uses clock signal 898 to receive data signal 837 and a corresponding framing pattern. Link layer circuitry 834 uses the framing pattern to identify the start of data signal 837 and generate data signal 835. In one example, the framing signal is received and used to determine valid bits in data signal 837.

[0161] Additionally, link layer circuitry 834 reduces the frequency of data signal 837 by the same amount and increases the number of bits to generate data signal 835. In one example, link layer circuitry 834 reduces the frequency of data signal 837 by two or more and increases the number of bits to generate data signal 835. In one example, link layer circuitry 834 reduces the frequency of data signal 837 so that data signal 837 has the frequency of clock signal 898. In one example, data signal 835 has a bit size of 892 bits and a frequency of 200 MHz.

[0162] The application circuit 814 receives a clock signal 815 and uses the clock signal 815 to receive a data signal 835. In one example, the application circuit 814 includes a flip-flop 819. The flip-flop 819 receives the data signal 835 using the clock signal 815.

[0163] 8 , a clock signal, e.g., clock signal 815, used by application circuit 812 to transmit data signals is communicated and shared within IC chips 810 and 850 such that application circuits 812, 814, 852, and 854 are driven by the same clock signal, e.g., clock signal 815. Furthermore, C2C interface circuits 820 and 860 of IC chips 810 and 850, respectively, operate based on the same clock signal, e.g., clock signal 843. The clock signal is transmitted between IC chip 810 and IC chip 850 such that C2C interface circuits 820 and 860 operate based on the same clock signal. C2C interface circuits 830 and 890 of IC chips 810 and 850, respectively, operate based on the same clock signal, e.g., clock signal 887. The clock signal 887 is transmitted between IC chip 810 and IC chip 850 such that C2C interface circuits 860 and 890 operate based on the same clock signal.

[0164] 8 may be referred to as an oversampling process or scheme. As described above, the frequency of clock signal 843 is a multiple (e.g., N times) of the frequency of clock signal 845. N is 2 or greater. In one example, N is 4. N may be set such that the frequency of clock signal 843 is based on the minimum frequency required to accurately reproduce signal 827. Furthermore, in one or more examples, C2C interface circuits 820, 830, 860, and 870 operate at a higher frequency than the frequency of the input data signal.

[0165] FIG. 9 illustrates a multiple IC chip device 900 according to one or more examples. The multiple IC chip device 900 includes an IC chip 910 and an IC chip 950. The IC chip 910 includes an application circuit 912 and a C2C interface circuit 920. Additionally, the IC chip 810 includes a driver circuit 918. The C2C interface circuit 920 includes a PHY layer circuit 922, a link layer circuit 924, and a protocol layer circuit 926. The C2C interface circuit 920 is configured similarly to the C2C interface circuit 112 of FIG. 1. The PHY layer circuit 922 is configured similarly to the PHY layer circuit 216 of FIG. 2, the link layer circuit 924 is configured similarly to the link layer circuit 214 of FIG. 2, and the protocol layer circuit 926 is configured similarly to the protocol layer circuit 212 of FIG. 2.

[0166] The IC chip 950 includes an application circuit 952 and a C2C interface circuit 960. The IC chip 950 further includes a receiving circuit 958. The C2C interface circuit 960 includes a PHY layer circuit 962, a link layer circuit 964, and a protocol layer circuit 966. The C2C interface circuit 960 has a configuration similar to that of the C2C interface circuit 112 in FIG. 1. The PHY layer circuit 962 has a configuration similar to that of the PHY layer circuit 216 in FIG. 2, the link layer circuit 964 has a configuration similar to that of the link layer circuit 214 in FIG. 2, and the protocol layer circuit 966 has a configuration similar to that of the protocol layer circuit 212 in FIG. 2.

[0167] The example illustrated in FIG. 9 is used as part of a test interface for testing the functionality of IC chips 910 and 950. In such an example, protocol layer circuit 926, link layer circuit 924, link layer circuit 964, and protocol layer circuit 966 are bypassed. Therefore, a data signal 990 output from application circuit 912 is communicated to PHY layer circuit 922, bypassing the protocol layer circuit and link layer circuit. Application circuit 912 outputs a data signal based on a clock signal 992. In one example, application circuit 912 includes a buffer 916 and a flip-flop 914. Buffer 916 outputs clock signal 992. Clock signal 992 is generated by a clock generation circuit (not shown) connected to the input of buffer 916. Flip-flop 914 receives clock signal 992 and outputs data signal 990 based on clock signal 992. Additionally, clock signal 992 is received by driver circuit 918, which outputs clock signal 992 to receiver circuit 958. Clock signal 992 is output from receiver circuit 958 and received by an application circuit. For example, clock signal 992 is received and output by buffer 956 and then received by flip-flop 954.

[0168] The PHY layer circuitry 922 outputs a data signal 990 via the interface 902. The PHY layer circuitry 962 receives the data signal 990 via the interface 902 and outputs the data signal 990 to the application circuitry 952.

[0169] The application circuit 952 receives the data signal 990 using a clock signal 992. For example, the application circuit 952 includes a flip-flop 954 that receives the clock signal 992 from a buffer 956, and the flip-flop 954 receives the data signal 990 using the clock signal 992.

[0170] As illustrated in FIG. 9, a clock signal 992 is used by IC chips 910 and 950 to transmit and receive data signals 990 .

[0171] In one or more examples, the clock signal 992 is transmitted via sideband circuits of the C2C interface circuit 920 and the C2C interface circuit 960, as described above with respect to FIGS.

[0172] 10 illustrates a clock generation circuit 1000, according to one or more examples. The clock generation circuit 1000 may be used to deskew clock signals within an IC chip (e.g., IC chips 110 and / or 120 of FIG. 1). The clock generation circuit includes an MDLL circuit 1010, a phase interpolator circuit 1020, a phase reference circuit 1030, and a phase detector circuit 1040. In one example, the clock generation circuit 1000 may be used as part of clock circuit 344 of FIG. 3 and / or clock circuit 881 of FIG. 8.

[0173] Clock generation circuit 1000 generates clock signals 1062, 1064, and 1066 and drives and outputs clock signals 1062, 1064, and 1066 onto clock tree circuit 1050. Clock tree circuit 1050 includes PHY layer clock tree circuit 1052, link and protocol clock tree circuit 1054, and application clock tree circuit 1056. PHY layer clock tree circuit 1052 corresponds to PHY layer circuit 216 in Figure 2, link and protocol clock tree circuit 1054 corresponds to link layer circuit 214 and protocol layer circuit 212 in Figure 2, and application clock tree circuit 1056 corresponds to application circuit 210 in Figure 2.

[0174] MDLL circuit 1010 receives clock signal 1008 and generates clock signals 1012, 1014, and 1016 from clock signal 1008 and a feedback signal. The frequency of clock signal 1012 is greater than the frequency of clock signal 1014, which is greater than the frequency of clock signal 1016. Clock signals 1012, 1014, and 1016 are received by phase interpolator circuit 1020.

[0175] Phase interpolator circuit 1020 further receives phase signals 1041, 1043, and 1045 from phase detector circuit 1040. Phase detector circuit 1040 receives clock signals 1053, 1055, and 1057 from clock tree circuit 1050. Phase detector circuit 1040 includes phase detector segment circuit 1042, phase detector segment circuit 1044, and phase detector segment circuit 1046. Phase detector segment circuit 1042 determines the phase difference between clock signal 1053 and clock signal 1055, phase detector segment circuit 1044 determines the phase difference between clock signal 1055 and clock signal 1057, and phase detector segment circuit 1046 determines the phase difference between clock signal 1053 and clock signal 1062.

[0176] Phase detector segment circuit 1042 generates and outputs phase signal 1043 based on the phase difference between clock signal 1053 and clock signal 1055, phase detector segment circuit 1044 generates and outputs phase signal 1045 based on the phase difference between clock signal 1053 and clock signal 1057, and phase detector segment circuit 1046 generates and outputs phase signal 1047 based on the phase difference between clock signal 1053 and clock signal 1062.

[0177] Phase interpolator circuit 1020 includes phase interpolator circuit 1022, phase interpolator circuit 1024, and phase interpolator circuit 1026. Phase interpolator circuit 1022 receives clock signal 1012, reference clock signal 1031, and phase signal 1043, and generates clock signal 1062. Phase interpolator circuit 1022 adjusts the phase of clock signal 1012 based on phase signal 1043 and reference clock signal 1031 to generate clock signal 1062. Phase interpolator circuit 1024 receives clock signal 1014, reference clock signal 1031, and phase signal 1045, and generates clock signal 1064. Phase interpolator circuit 1024 adjusts the phase of clock signal 1014 based on phase signal 1045 and reference clock signal 1031 to generate clock signal 1064. Phase interpolator circuit 1026 receives clock signal 1016, reference clock signal 1031, and phase signal 1047 and generates clock signal 1066. Phase interpolator circuit 1026 adjusts the phase of clock signal 1016 based on phase signal 1047 and reference clock signal 1031 to generate clock signal 1066.

[0178] In one or more examples, an IC device includes a first IC chip, a second IC chip, and a chip-to-chip interface connected between the first IC chip and the second IC chip. The chip-to-chip interface is configured to communicate an interface clock signal and a logic clock signal between the first IC chip and the second IC chip. The interface clock signal is synchronous with a data signal received by one of the first IC chip and the second IC chip, and the logic clock signal is asynchronous with the data signal.

[0179] In one or more examples, the logic clock signal is generated independently of the interface clock signal. In one or more examples, the first IC chip is configured as a receiver and outputs the interface clock signal and the logic clock signal, and the second IC chip is configured as a transmitter and receives the interface clock signal and the logic clock signal from the first IC chip. In one or more examples, the first IC chip is configured as a receiver and outputs the logic clock signal and receives the interface clock signal, and the second IC chip is configured as a transmitter and outputs the interface clock signal and receives the logic clock signal. In one or more examples, the first IC chip is further configured to output the interface clock signal to the second IC chip based on receiving the interface clock signal from the second IC chip, and the second IC chip uses the interface clock signal to receive the second data signal. In one or more examples, one of the first IC chip and the second IC chip is configured to receive the interface clock signal, wherein one of the first IC chip and the second IC chip comprises a divider circuit configured to receive the interface clock signal and generate a first clock signal having a frequency lower than a frequency of the interface clock signal, and a clock circuit configured to receive the first clock signal and phase-align the first clock signal. In one or more examples, the chip-to-chip interface is configured to communicate a second data signal between the first IC chip and the second IC chip, wherein the frequency of the data signal is higher than a frequency of the interface clock signal. In one or more examples, the chip-to-chip interface is further configured to communicate a control signal between the first IC chip and the second IC chip, wherein the frequency of the control signal is higher than a frequency of the second data signal. In one or more examples, the interface clock signal and the control signal are differential signals. In one or more examples, the interface clock signal and the logic clock signal are communicated during at least partially overlapping time periods.

[0180] In one or more examples, the chip-to-chip interface is configured to communicate an interface clock signal between the IC chip and the second IC chip. The first IC chip and the second IC chip are connected to each other via the chip-to-chip interface. The interface clock signal is synchronous with a data signal. The data signal is received by one of the first IC chip and the second IC chip. The chip-to-chip interface is further configured to communicate a logic clock signal between the first IC chip and the second IC chip. The logic clock signal is asynchronous with the data signal. In one or more examples, the logic clock signal is generated independently of the interface clock signal. In one or more examples, the first IC chip is configured as a receiver and outputs the interface clock signal and the logic clock signal, and the second IC chip is configured as a transmitter and receives the interface clock signal and the logic clock signal from the first IC chip. In one or more examples, the first IC chip is configured as a receiver and outputs the logic clock signal and receives the interface clock signal, and the second IC chip is configured as a transmitter and outputs the interface clock signal and receives the logic clock signal. In one or more examples, the first IC chip is further configured to output an interface clock signal to the second IC chip based on receiving the interface clock signal from the second IC chip, and the second IC chip uses the interface clock signal to receive the second data signal. In one or more examples, the chip-to-chip interface is configured to communicate a second data signal between the first IC chip and the second IC chip, the data signal having a frequency higher than the frequency of the interface clock signal. In one or more examples, the chip-to-chip interface is further configured to communicate a control signal between the first IC chip and the second IC chip, the control signal having a frequency higher than the frequency of the second data signal.

[0181] In one or more examples, the IC chip includes a chip-to-chip interface connected to a second IC chip, and the chip-to-chip interface configured to communicate an interface clock signal to the second IC chip, the interface clock signal being synchronous with data signals received by the IC chip, and to communicate a logic clock signal to the second IC chip, the logic clock signal being asynchronous with the data signals. In one or more examples, the logic clock signal is generated independently of the interface clock signal. In one or more examples, the chip-to-chip interface is further configured to communicate a second data signal to the second IC chip, the data signal having a frequency higher than the frequency of the interface clock signal.

[0182] In one or more examples, an IC device includes a first IC chip, a second IC chip, and a chip-to-chip interface connected between the first IC chip and the second IC chip. The chip-to-chip interface is configured to communicate an interface clock signal and a logic clock signal between the first IC chip and the second IC chip. The frequency of the interface clock signal is a multiple of the frequency of the logic clock signal.

[0183] In one or more examples, the frequency of the interface clock signal is at least twice the frequency of the logic clock signal. In one or more examples, the chip-to-chip interface is further configured to communicate a data signal between the first IC chip and the second IC chip, the data signal being synchronized to the interface clock signal. In one or more examples, the chip-to-chip interface is further configured to communicate a data signal between the first IC chip and the second IC chip, the chip-to-chip interface being configured to communicate a framing pattern along with the data signal. In one or more examples, the chip-to-chip interface is configured to communicate the data signal using a framing signal, the framing signal defining a region of valid data within the data signal. In one or more examples, the interface clock signal is generated by one of the first IC chip and the second IC chip. In one or more examples, the interface clock signal is generated based on a rising edge of the logic clock signal. In one or more examples, the first IC chip comprises a first application circuit and a second application circuit, and the second IC chip comprises a third application circuit and a fourth application circuit, where the first application circuit, the second application circuit, the third application circuit, and the fourth application circuit are configured to function based on a logic clock signal. In one or more examples, the first IC chip comprises a first interface circuit and a second interface circuit, and the second IC chip comprises a third interface circuit and a fourth interface circuit, where the first interface circuit, the second interface circuit, the third interface circuit, and the fourth interface circuit are configured to function based on an interface clock signal.

[0184] In one or more examples, the chip-to-chip interface is configured to communicate an interface clock signal between the first IC chip and the second IC chip and to communicate a logic clock signal between the first IC chip and the second IC chip, wherein the frequency of the interface clock signal is a multiple of the frequency of the logic clock signal.

[0185] In one or more examples, the frequency of the interface clock signal is at least twice the frequency of the logic clock signal. In one or more examples, the chip-to-chip interface is further configured to communicate a data signal between the first IC chip and the second IC chip, the data signal being synchronized to the interface clock signal. In one or more examples, the chip-to-chip interface is further configured to communicate the data signal between the first IC chip and the second IC chip and to communicate a framing pattern along with the data signal. In one or more examples, the chip-to-chip interface is configured to communicate the data signal between the first IC chip and the second IC chip using a framing signal, the framing signal defining a region of valid data within the data signal. In one or more examples, the interface clock signal is generated by one of the first IC chip and the second IC chip. In one or more examples, the interface clock signal is generated based on a rising edge of the logic clock signal. In one or more examples, the first IC chip includes a first application circuit and a second application circuit, and the second IC chip includes a third application circuit and a fourth application circuit, wherein the first application circuit, the second application circuit, the third application circuit, and the fourth application circuit are configured to function based on a logic clock signal.

[0186] In one or more examples, the IC chip includes a chip-to-chip interface configured to communicate an interface clock signal to a second IC chip and to communicate a logic clock signal to the second IC chip. The frequency of the interface clock signal is a multiple of the frequency of the logic clock signal. In one or more examples, the chip-to-chip interface is further configured to communicate a data signal to the second IC chip, the data signal being synchronized to the interface clock signal. In one or more examples, the chip-to-chip interface is configured to at least one of communicate a framing pattern with the data signal and communicate the data signal using the framing signal, the framing signal defining a region of valid data within the data signal.

[0187] While the above is directed to particular examples, other and further examples may be devised without departing from the basic scope thereof, which scope is determined by the following claims.

Claims

1. 1. An integrated circuit (IC) device comprising: a first IC chip; a second IC chip; a chip-to-chip interface connected between the first IC chip and the second IC chip, the chip-to-chip interface configured to communicate an interface clock signal and a logic clock signal between the first IC chip and the second IC chip; An IC device comprising:

2. 2. The IC device of claim 1, wherein the interface clock signal is synchronous with a data signal received by one of the first IC chip and the second IC chip, and the logic clock signal is asynchronous with the data signal.

3. 3. The IC device of claim 2, wherein the logic clock signal is generated independently of the interface clock signal.

4. the first IC chip is configured as a receiver and outputs the interface clock signal and the logic clock signal; 3. The IC device of claim 2, wherein the second IC chip is configured as a transmitter and receives the interface clock signal and the logic clock signal from the first IC chip.

5. the first IC chip is configured as a receiver, and outputs the logic clock signal and receives the interface clock signal; 3. The IC device of claim 2, wherein the second IC chip is configured as a transmitter, outputs the interface clock signal, and receives the logic clock signal; the first IC chip is further configured to output the interface clock signal to the second IC chip based on receiving the interface clock signal from the second IC chip; and the second IC chip uses the interface clock signal to receive a second data signal.

6. One of the first IC chip and the second IC chip is configured to receive the interface clock signal, and the one of the first IC chip and the second IC chip: a divider circuit configured to receive the interface clock signal and generate a first clock signal having a frequency lower than a frequency of the interface clock signal; 3. The IC device of claim 2, comprising: a clock circuit configured to receive the first clock signal and to phase-align the first clock signal.

7. The chip-to-chip interface includes: communicating a second data signal between the first IC chip and the second IC chip, the second data signal having a frequency higher than a frequency of the interface clock signal; 3. The IC device of claim 2, further configured to communicate a control signal between the first IC chip and the second IC chip, the control signal having a frequency higher than a frequency of the second data signal, and the interface clock signal and the control signal being differential signals.

8. 2. The IC device of claim 1, wherein the frequency of the interface clock signal is a multiple of the frequency of the logic clock signal.

9. 9. The IC device of claim 8, wherein the frequency of the interface clock signal is at least twice the frequency of the logic clock signal.

10. 9. The IC device of claim 8, wherein the chip-to-chip interface is further configured to communicate data signals between the first IC chip and the second IC chip, the data signals being synchronized to the interface clock signal.

11. 9. The IC device of claim 8, wherein the chip-to-chip interface is further configured to communicate data signals between the first IC chip and the second IC chip, the chip-to-chip interface being configured to communicate a framing pattern along with the data signals.

12. 9. The IC device of claim 8, wherein the chip-to-chip interface is configured to communicate data signals using framing signals, the framing signals defining regions of valid data within the data signals.

13. the interface clock signal is generated based on one of the first IC chip and the second IC chip; or the interface clock signal is generated based on the rising edge of the logic clock signal; 9. The IC device of claim 8, wherein at least one of:

14. 9. The IC device of claim 8, wherein the first IC chip comprises a first application circuit and a second application circuit, and the second IC chip comprises a third application circuit and a fourth application circuit, and the first application circuit, the second application circuit, the third application circuit, and the fourth application circuit are configured to function based on the logic clock signal.

15. 15. The IC device of claim 14, wherein the first IC chip comprises a first interface circuit and a second interface circuit, and the second IC chip comprises a third interface circuit and a fourth interface circuit, and the first interface circuit, the second interface circuit, the third interface circuit, and the fourth interface circuit are configured to function based on the interface clock signal.

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