Self-aligned JFET devices

Abstract

The JFET transistor device (100) with reduced pitch provides a lower breakdown voltage and / or a lower R DSon As a result, the described devices have a high BV gs While maintaining the value of DSon provides a reduction in

Description

[Technical Field]

[0001] The present specification relates to semiconductor devices. [Background technology]

[0002] In many transistor-based devices, multiple transistor cells are connected within the active area of ​​the device. Each individual transistor cell can be considered a unit cell of the overall device, and the width of the unit cell can be referred to as the pitch of the device. The operating behavior of the entire device can be determined by the characteristics of the individual transistors contained within the device as well as the aggregate or combined characteristics of the multiple transistor cells within the active area.

[0003] For example, the source-drain on-resistance or R DSon The on-resistance of a transistor, also referred to as on-resistance, may indicate the amount of current (e.g., drain current or Id) present for a corresponding drain voltage (e.g., drain-source voltage or Vds). The gate-source breakdown voltage, or BVgs, may refer to the reverse voltage at which a transistor exhibits a surge in reverse current while in the off state.

[0004] Reducing the size of each unit cell of a transistor device within a given active area (i.e., reducing the pitch) provides more individual transistor cells within the active area, and therefore additional current channels, increased current, and R (for a given gate voltage). DSon However, reducing the device pitch to desired levels can be difficult or impossible using conventional techniques. Furthermore, attempts to reduce the pitch of conventional device structures can have undesirable consequences if any mismatch occurs. For example, such mismatch can result in performance degradation (e.g., a reduction in the BVgs or R across the device). DSon This can result in increased temperature, as well as reduced yield and reduced reliability. Summary of the Invention

[0005] According to one general aspect, a junction field effect transistor (JFET) semiconductor device may include a substrate including a drain region of the JFET, a drift region disposed in the substrate, and a lower gate disposed in the drift region. The JFET semiconductor device may include a source region having a lower source region disposed in the lower gate and extending laterally beyond the lower gate, and an upper source region disposed in the lower source region, and an upper gate formed in the lower source region and at least partially surrounding the upper source region, the upper gate extending laterally beyond the lower gate to define a gate offset between the upper gate and the lower gate.

[0006] According to another general aspect, a junction field effect transistor (JFET) semiconductor device may include a substrate including a drain region of the JFET semiconductor device, a drift region disposed in the substrate, and a plurality of unit cells arranged in a grid in the drift region, each unit cell may include a lower gate disposed in the drift region, a source region having a lower source region disposed in the lower gate and extending laterally beyond the lower gate, and an upper source region disposed in the lower source region, and an upper gate formed in the lower source region and at least partially surrounding the upper source region, the upper gate extending laterally beyond the lower gate to define a gate offset between the upper gate and the lower gate.

[0007] According to another general aspect, a method of fabricating a semiconductor device can include forming a lower source region implant and an upper gate implant through a first opening in a mask disposed on a substrate, forming first spacers on sidewalls of the mask to define a second opening smaller than the first opening, and forming a lower gate through the second opening. The method can also include forming second spacers on the first spacers to define a third opening smaller than the second opening, and forming an upper source region in the upper gate implant through the third opening, thereby defining a remainder of the upper gate implant as an upper gate of a junction field effect transistor (JFET), the substrate providing the drain of the JFET.

[0008] The details of one or more implementations are set forth in the accompanying drawings and the description below. Other features will be apparent from the description and drawings, and from the claims. [Brief explanation of the drawings]

[0009] [Figure 1] A top view of a self-aligned JFET device is shown. [Figure 2] FIG. 2 shows a cross-sectional view of the self-aligned JFET device of FIG. 1 along AA. [Figure 3] FIG. 2 shows a cross-sectional view of the self-aligned JFET device of FIG. 1 along BB. [Figure 4] FIG. 2 shows a cross-sectional view along BB of a first alternative implementation of the self-aligned JFET device of FIG. 1. [Figure 5] FIG. 2 shows a cross-sectional view along BB of a second alternative implementation of the self-aligned JFET device of FIG. 1. [Figure 6] 2 illustrates a first cross-sectional view of a fabrication process for producing the self-aligned JFET of FIG. 1. [Figure 7] 2 illustrates a second cross-sectional view of the fabrication process for producing the self-aligned JFET of FIG. 1. [Figure 8] 2 illustrates a third cross-sectional view of the fabrication process for producing the self-aligned JFET of FIG. 1. [Figure 9] 2 illustrates a fourth cross-sectional view of the fabrication process for producing the self-aligned JFET of FIG. 1. [Figure 10] 1. FIG. 4 illustrates a fifth cross-sectional view of the fabrication process for producing the self-aligned JFET of FIG. [Figure 11] 1. FIG. 4 illustrates a sixth cross-sectional view of the fabrication process for producing the self-aligned JFET of FIG. [Figure 12] 1. FIG. 4 illustrates a seventh cross-sectional view of the fabrication process for producing the self-aligned JFET of FIG. [Figure 13A] 12A-12C illustrate cross-sectional views of an exemplary manufacturing process for providing spacers used in the self-alignment of FIGS. 7, 9, and 11. [Figure 13B] 12A-12C illustrate cross-sectional views of an exemplary manufacturing process for providing spacers used in the self-alignment of FIGS. 7, 9, and 11. [Figure 13C] 12A-12C illustrate cross-sectional views of an exemplary manufacturing process for providing spacers used in the self-alignment of FIGS. 7, 9, and 11. [Figure 14] 13A-13C are first cross-sectional views of process modeling of the fabrication process of FIGS. 6-12 illustrating the top gate implant process. [Figure 15] FIG. 13 is a second cross-sectional view of the process modeling of the manufacturing process of FIGS. 6-12, illustrating the channel implantation process. [Figure 16] FIG. 13 is a third cross-sectional view of the process modeling of the fabrication process of FIGS. 6-12 illustrating the bottom gate implant process. [Figure 17] FIG. 13 is a fourth cross-sectional view of the process modeling of the manufacturing process of FIGS. 6-12 illustrating a lightly doped region implantation process. [Figure 18] FIG. 13 is a fifth cross-sectional view of the process modeling of the manufacturing process of FIGS. 6-12 illustrating a source region implant process. [Figure 19] FIG. 13 is a sixth cross-sectional view of the process modeling of the fabrication process of FIGS. 6-12 showing a partially completed JFET device cell. [Figure 20] 10 is a graph showing the relationship between device pitch and RDSon. [Figure 21] 2 is a graph illustrating the relationship between gate-source breakdown voltage and lightly doped regions of the JFET device of FIG. 1; [Figure 22A] 15A-15C are cross-sectional views of process modeling of the JFET device of FIGS. 1 and 14, illustrating current flow with and without gate alignment of the top and bottom gates. [Figure 22B] 15A-15C are cross-sectional views of process modeling of the JFET device of FIGS. 1 and 14, illustrating current flow with and without gate alignment of the top and bottom gates. [Figure 23] 1 is a graph showing the relationship between top / bottom gate matching and RDSon. [Figure 24] 24 is a flowchart illustrating an exemplary implementation for fabricating the JFET device described with respect to FIGS. 1-23. DETAILED DESCRIPTION OF THE INVENTION

[0010] The present disclosure relates to JFET transistor devices having reduced pitch, for example, pitches less than 5 microns, which can reduce BV and / or R DSon The devices can be fabricated using self-aligned techniques that allow for smaller device pitches than can be obtained using conventional mask-based photolithography techniques, while avoiding misalignments that can lead to increased R. As a result, the described devices provide additional current channels, increased current, and R (for a given active area and gate voltage) compared to conventional devices, while retaining acceptable BV values. DSon provides a reduction in

[0011] 1 illustrates a top view of a self-aligned JFET device including a plurality of individual JFET device cells, each of which is referred to herein as a JFET 100. In the example of FIG. 1, a plurality or grid of source regions 102 of a first conductivity type (e.g., n-type) are each shown as being at least partially surrounded by a lightly doped BVgs enhancement region 106 of the first conductivity type. That is, the BVgs enhancement regions 106 should be understood to have a lower doping than the doping of the source regions 102, as described in more detail below. For example, the BVgs enhancement regions 106 may have a doping level that is 20 percent or less, e.g., 10 percent or 15 percent, of the doping of the source regions 102.

[0012] Each BVgs enhancement region 106 is at least partially surrounded by an upper gate 104 of a second conductivity type (e.g., p-type). The lower gate (e.g., lower gate 204 in FIG. 2) is not visible in the top view of FIG. 1 but is shown and described in detail below with respect to, for example, FIGS. 2-5. In other words, in the top view of FIG. 1, the upper gate 104, BVgs enhancement region 106, and source region 102 are vertically above and obscure the lower gate (e.g., lower gate 204 in FIG. 2).

[0013] As used herein, the vertical direction V refers to the z-axis, which connects and is perpendicular to the planes of the upper gate 104 and lower gate 204 and the plane of the underlying substrate (e.g., substrate 206 in Figure 2), and so extends into the page in Figure 1. The lateral direction L refers to a direction perpendicular to the vertical direction V, along either the x-axis and / or the y-axis.

[0014] 1 forms a JFET 100 in which a current channel is formed between the top gate 104 and the bottom gate 204. Thus, current flows from the source region 102, first laterally between the top gate 104 and the bottom gate 204, and then vertically into the plane of the paper in FIG. 1 to the drain of the JFET device in FIG. 1 (e.g., drain 208 in FIG. 2, which is not visible in the top view of FIG. 1).

[0015] To control this current flow, a gate contact 108 of the second conductivity type is formed that connects to both the top gate 104 and the bottom gate 204. A single common gate voltage can therefore be applied to control all of the individual JFET cells 100 of the JFET device of FIG.

[0016] Further in FIG. 1 , a termination region 110 of a second conductivity type is defined adjacent to an active area 112 in which various JFET cells are formed. It will be understood that FIG. 1 is a partial view of the active area 112 and the termination region 110. In an exemplary implementation, the termination region 110 completely surrounds the active area 112. For example, the termination region 110 may define the periphery of the active area 112. In some implementations, the termination region 110 may include implants and / or trench structures to terminate electric fields associated with the operation of the various JFETs within the active area 112 of the semiconductor device of FIG. 1 . Thus, the termination region 110 may help maintain the breakdown voltage of the JFET of FIG. 1 near a maximum BV limited by material properties. For example, the termination region 110 may prevent breakdown below the rated voltage of the JFET 100 by, for example, terminating high electric fields during JFET operation.

[0017] 1, each JFET cell 100 defines a unit cell of a JFET device, with the lines of unit cells extending in the x-direction. As shown in FIG. 1, the pitch of the JFET device can be defined as the distance along the y-axis between adjacent lines of unit cells, or alternatively, as the width of a unit cell in the y-direction.

[0018] FIG. 1 shows cross-sectional lines AA and BB, FIG. 2 shows a first cross-sectional view of the JFET of FIG. 1 taken along line AA (i.e., a cross-section along the y-axis, looking in the x-direction), and FIG. 3 shows a second cross-sectional view of the JFET of FIG. 1 taken along line BB (i.e., a cross-section along the x-axis, looking in the y-direction).

[0019] 2, the source region 102 is shown as including an upper source region 102a and a lower source region 102b. As shown, the upper source region 102a is at least partially surrounded by a BVgs enhancement region 106, which is itself at least partially surrounded by an upper gate 104. The lower source region 102b extends along a lower gate 204, beneath the upper gate 104, the BVgs enhancement region 106, and the upper source region 102a, and forms a channel region L, as described in more detail below. ch Define the following.

[0020] 2, drain contact 208 has a drain region of a first conductivity type (e.g., n-type) formed in substrate 206. Voltage blocking drift region 202 is formed in substrate 206, for example, as an epitaxial layer, and may include relatively highly doped region 202a. Drift region 202 and substrate 206 may be formed using, for example, silicon carbide (SiC), Si, gallium nitride (GaN), aluminum nitride (AlN), or any other semiconductor material.

[0021] Also shown in Figure 2 is source metal 214, which was omitted from Figure 1 for clarity of the top view. As shown, source contact 212 facilitates electrical contact between source metal 214 and source region 102, while dielectric layer 216 provides insulation between source metal 214 and BVgs enhancement region 106, upper gate 104, and drift region 202.

[0022] In operation, application of a particular gate and drain voltage causes a current 211 (denoted as drain current Id) to flow through the upper source region 102a and into the channel region L ch 202 and vertically through the drift region 202 to the drain substrate 206. More specifically, as shown, the channel region L ch may be defined laterally between the inner edge of the top gate adjacent the BVgs enhancement region 106 and the outer edge of the bottom gate 204.

[0023] In addition, in Figure 2, the lateral distance L go refers to the gate offset between the edge of the top gate 104 and the edge of the bottom gate 204. That is, as shown, the outer edge of the top gate 104 is spaced from the outer edge of the bottom gate 204 by a distance L go For example, as described in more detail below with respect to FIGS. 22 and 23, the gate offset L go is channel L ch The depletion region in the channel L ch , which has the unintended and undesirable effect of turning JFET cell 100 off. For example, if JFET cell 100 is designed as a normally-on device, then the gate offset L go If is too small, excessive depletion will occur in the channel L ch 23, the L go Reducing R DSonIn some embodiments, the top gate 104 and the bottom gate 204 may not have a structural offset, but may be offset during the fabrication process (e.g., using a designated spacer) to allow for a wider spread of the bottom gate 204. That is, there may be a greater lateral extent of the buried bottom gate 204 (formed using a higher ion implantation energy compared to the energy used for the ion implantation of the top gate 104). In an exemplary implementation, the spacer width, and thus the resulting offset, may be as small as 0 μm (no offset) or as large as 0.7 μm.

[0024] 2 further illustrates the positioning of a BVgs enhancement region 106 between the upper gate 104 and the upper source region 102a. The BVgs enhancement region 106 thus prevents contact between the relatively highly doped upper source region and the relatively highly doped upper gate 104, thereby allowing for higher source doping, which allows for reduced source contact resistivity compared to what is possible in a device without a BVgs enhancement region. Contact between the two highly doped regions 102a, 104 could otherwise result in a reduction in the BVgs of the JFET 100. However, by including the BVgs enhancement region 106 as shown, contact between the two highly doped regions 102a, 104 is prevented, and the BVgs of the device is increased.

[0025] Figure 3 shows a cross-sectional view along line BB of the self-aligned JFET device of Figure 1. In the example of Figure 3, gate contact 312 and gate metal 314 (omitted from Figure 1 for clarity of the top view) are shown positioned to make electrical contact with both top gate 104 and bottom gate 204 using gate contact region 108a. An insulating dielectric layer 216 is further shown providing insulation between source metal 214 and gate metal 314.

[0026] 3, the gate contact region 108a includes an overlap region 302 that partially overlaps the top gate 104, the channel region, and the bottom gate 204. For example, the gate contact region 108a may extend over a distance (d <L ch ) may partially overlap the upper gate 104 and the channel region and therefore not contact the more highly doped portions of the source region.

[0027] 4, an alternative implementation of the gate contact region 108, shown as gate contact region 108b, is embedded within (i.e., within) the JFET cell 100 to define an overlap region 402. More specifically, as shown, the gate contact region 108b defines the overlap region 402 as extending through the upper gate 104, the lower source region 102b, and the BVgs enhancement region 106. Thus, the gate contact region 108b in FIG. ch 102a and into the upper source region 102a. In this embodiment, the doping in the gate contact region compensates for the doping in the source region. This simplifies the device fabrication process, but the source region doping may be limited to avoid lowering BVgs.

[0028] 5, the gate contact region 108c does not extend into the upper source region 102a, but extends into the upper gate 104, the lower gate 204, and the lower source region 102b to define an overlap region 502. In other words, the gate contact region 108c is embedded in the extended JFET cell without overlapping with the upper source region 102a. For example, the distance between the gate contact region 108c and the upper source region 102a can be 0.5 μm to 5 μm.

[0029] Therefore, the gate contact region 108c is connected to the channel L ch5, the BVgs enhancement region 106 is not included, and the gate contact region 108c may extend deeper into each JFET cell and closer to the upper source region 102a, as compared to the example of FIG. 4, for example. In the example of FIG. 5, gate-to-source leakage may be reduced by the structure shown, in which the upper source region 102a does not overlap the gate contact region 108c (i.e., the overlap region 502 does not extend into the upper source region 102a).

[0030] 6-12 illustrate cross-sectional views of exemplary stages in a fabrication process for fabricating the self-aligned JFET structure of FIG. 1. In the example of FIG. 6, the drift region 202 of FIG. 2 is processed using a first mask 606. As shown, the first mask 606 may be used to define openings through which the channel implant 602 and the top gate implant 604 may be formed. For example, the first mask 606 may be formed using SiO, polysilicon, silicon nitride (e.g., SiN), or a combination thereof. The openings defined by the mask 606 may be, for example, 4.5 microns or less.

[0031] The channel implant 602 and the top gate implant 604 may be formed using ion implantation or any suitable technique. As will become apparent from the following description, the channel implant 602 may be used to form the lower source region 102b of Figures 1-5, and the top gate implant 604 may be used to form the upper gate 104 of Figures 1-5.

[0032] 7, first spacers 702 are formed on the sidewalls of first mask 606. Techniques for forming first spacers 702 (and subsequent spacers) are described below, for example, with respect to FIGS. 13A-13C. The first spacers 702 thereby define a self-aligned mask (which may be referred to as a second mask) that enables the formation of bottom gate 804, as shown in FIG. 8. For example, localized ion implantation utilizing first spacers 702 as a second mask may be used to form bottom gate 804.

[0033] 2. Because the first spacers 702 effectively make the opening in the first mask 606 smaller than in the operation of FIG. 6, the bottom gate 804 can be optionally spaced apart from the top gate 604 by a gate offset L, as described above with respect to FIG. go Therefore, by controlling the thickness of the first spacer 702, the gate offset L go It will be appreciated that the extent to which the

[0034] More particularly, the formation of the bottom gate 804 may require or result in relatively high energy dopants below the channel implant 602. As a result, these high energy dopants may diffuse laterally following the formation (e.g., implantation) of the bottom gate 804. As mentioned above and described in detail below with respect to Figures 22A, 22B, and 23, such diffusion can result in the extension of the bottom gate 804 and the corresponding L go In such cases, the channel L ch The depletion of the L channel may extend beyond the bottom gate 804, preventing current flow through the channel. Therefore, the formation of the spacer 702 and bottom gate 804 is important to achieve the desired L go If the extension of the bottom gate 804 is comparable to the extension of the top gate 604, some embodiments may omit the first spacer formation (i.e., the bottom gate 804 may be formed using the same mask as the top gate 604).

[0035] 9, second spacers 902 are formed on the sidewalls of the first spacers (second mask) 702, thereby defining the third mask. As a result, the second spacers 902 can be used to implant (e.g., using local ion implantation) or otherwise form or define source region portions 1002 and lightly doped regions 1006, as shown in FIG.

[0036] 10, the top gate 604 of the second conductivity type has already been formed, as described above. Using the second spacers 902, when the first conductivity type implant is performed, the exposed portion of the top gate 604 may be compensated from the second conductivity type to the first conductivity type with a relatively light doping while maintaining the source region portion 1002 at a doping level consistent with the existing channel implant source region 602 of FIG. 6 (i.e., the lightly doped region is formed by compensating the second conductivity type with the doping of the first conductivity type).

[0037] In Figure 11, third spacers 1102 are formed on the sidewalls of second spacers (third mask) 902, thereby defining the fourth mask. As a result, as shown in Figure 12, third spacers 1102 can be used to implant or otherwise form or define upper source region 1202a, which, together with lower source region 1202b (formed from source region 602 in Figure 6 above and source region 1002 in Figure 10), define source region 1202. At the same time, the remaining portion of lightly doped region 1006 forms BVgs enhancement region 1206.

[0038] 6-12, the spacers 702, 902, and 1102 effectively form a self-aligned mask, thereby eliminating the need for a separate photolithography mask (such as first mask 606). Furthermore, by using the spacers from a prior fabrication step as a self-aligned mask in a subsequent fabrication step, it is possible to form the JFET devices of FIGS. 1-5 with greater precision than is possible using conventional techniques. For example, the described techniques do not require consideration of the misalignment margins of conventional masks (which may be, for example, 0.3 microns or more).

[0039] For example, the first spacers (second mask) 702 may have a width of up to 0.5 microns. The second spacers (third mask) 902 may have a width of up to 0.5 microns. The third spacers (fourth mask) 1102 may have a width of up to 0.2 microns. The foregoing widths are provided for illustrative purposes; different widths may similarly be used, and one or more of the spacers / masks 702, 902, 1102 may be omitted. The various spacers / masks 702, 902, 1102 may be formed using, for example, SiO2, poly-Si, Si3N4, or combinations thereof.

[0040] Thus, for example, using the techniques described herein, the pitch of the device of FIG. 1 can be made, for example, smaller than 5 microns, such as 3 microns, or 2 microns, or less. Accordingly, with reference to FIG. 1, the active area 112 can accommodate a larger number of JFET cells (i.e., more JFET device cells 100). As a result, as noted above, with reference to FIG. 2 and drain current 211, the techniques of FIGS. 6-12 can provide higher current and reduced R compared to conventional techniques. DSon Pitch and R DSon A simplified example of the relationship is shown and described below, for example, with respect to FIG.

[0041] Figures 13A-13C show cross-sectional views of an exemplary fabrication process for providing spacers used in the self-alignment in Figures 7, 9, and 11. In Figure 13A, a mask 1306 is formed on an epitaxial layer 1304, which is formed on a substrate 1302. Mask 1306 represents a photolithography mask, such as mask 606 in Figure 6.

[0042] In Figure 13B, deposition of conformal spacer material 1308 is performed over epitaxial layer 1304 and mask 1306. Then, as shown in Figure 13C, an anisotropic etching (etch-back) procedure is performed to leave spacers 1310 on the sidewalls of mask 1306. Spacers 1310 thus represent an example of any of spacers 702, 902, 1102 of Figures 7-12, as described above. The width of spacers 1310 can be controlled by controlling the process parameters of the etching process.

[0043] Figure 14 is a first cross-sectional view of process modeling of the fabrication process of Figures 6-12, illustrating the top gate implant process, i.e., Figure 14 shows a more detailed example of Figure 6, where a p-type dopant, such as aluminum (Al), may be used to form the top gate implant 604 using mask 606.

[0044] Figure 15 is a second cross-sectional view of the process modeling of the fabrication process of Figures 6-12, illustrating the channel implant process. Figure 15 shows a more detailed example of Figure 6, illustrating an exemplary implant of channel implant 602.

[0045] Figure 16 is a third cross-sectional view of the process modeling of the fabrication process of Figures 6-12, showing the bottom gate implant process. Figure 16 shows a more detailed example of Figures 7 and 8, where spacers 702 are used to form the bottom gate implant 804.

[0046] Figure 17 is a fourth cross-sectional view of the process modeling of the fabrication process of Figures 6-12, illustrating the lightly doped region implantation process. Figure 17 shows a more detailed example of Figures 9 and 10, where spacers 902 are used to form the lightly doped region 1006.

[0047] Figure 18 is a fifth cross-sectional view of the process modeling of the manufacturing process of Figures 6-12, illustrating the source region implant process. Figure 18 shows a more detailed example of Figures 11 and 12, where spacers 1102 are used to form source region implants 1202.

[0048] Figure 19 is a sixth cross-sectional view of the process modeling of the fabrication process of Figures 6-12, showing the completed JFET device. Figure 19 shows the JFET device with net active doping.

[0049] Figure 20 shows the relationship between device pitch and R DSon 20 is a graph showing the relationship between pitch and R. As shown by line 2002, the decrease in pitch DSon correlates with a decrease in

[0050] FIG. 21 is a graph illustrating the relationship between BVgs and lightly doped regions, e.g., BVgs enhancement region 106, of the JFET device of FIG. 1. As shown in FIG. 21, IV curves 2102, 2104, and 2106 indicate that as the width W_BVER of BV enhancement region 106 increases, the BVgs (e.g., maximum Vgs rating) also increases. As mentioned above, because the gate contact region 108 and the source region 102 are highly doped, direct contact of these regions can result in the formation of a pn junction with a low BV (e.g., due to tunneling). As a result, separating these regions by a lightly doped region results in the BVgs enhancement shown and described.

[0051] 22A and 22B are cross-sectional views of process modeling of the JFET device of FIGS. 1 and 14, showing current flow as a function of gate alignment of the top gate 104 and bottom gate 204. Specifically, FIG. 22A shows that with a sufficient positive gate offset L go (top gate 104 extends laterally beyond bottom gate 204), but current flow is limited to current channel L chAs shown, the depletion region 2202 does not extend beyond the channel.

[0052] On the other hand, in Figure 22B, L go When is very small or negative L go is present (i.e., the bottom gate 204 extends laterally beyond the top gate 104), the depletion region 2204 penetrates the channel region L ch The extension of the depletion region 2204 extends beyond the channel L ch impedes the flow of current through R DSon This increases the voltage, turning the JFET device off and preventing the normally-on operation of the JFET device.

[0053] As described herein, normally-on operation of a JFET device requires a desired gate offset, L go 7 and 8, the thickness of the spacer 702 and the energy level of the implant of the bottom gate implant 804 can be adjusted to maintain the gate offset L go For example, L go can be kept below 0.05 microns, for example 0.01 microns.

[0054] Figure 23 further shows that go and R DSon As shown by line 2302, L go The increase in R DSon and the corresponding reduction in channel L ch causing a corresponding increase in current through

[0055] FIG. 24 is a flowchart illustrating an exemplary implementation for fabricating the JFET device described with respect to FIGS. 1-23. In the example of FIG. 24, a lower source region implant (including a channel region) and an upper gate implant are formed (2402) through a first opening in a mask and disposed in a drift region disposed in a substrate, as described and illustrated above. First spacers are formed on the sidewalls of the mask to reduce the first opening (2404), i.e., to form a second opening having a reduced size compared to the first opening. A lower gate implant can then be formed (2406) through the second opening and disposed in the drift region, such that the lower source region is disposed in the lower gate implant. As described above, the formation (e.g., implantation) of the lower gate implant is performed to achieve a desired gate offset L between the upper gate implant and the lower gate implant. go The temperature may be calibrated to ensure that the temperature is maintained.

[0056] A second spacer may be formed on the first spacer to further reduce the size of the opening (2408), i.e., form a third opening. A lightly doped region may be formed through the third opening and disposed in the lower source region while maintaining the doping level of the lower source region implant (e.g., by doping compensation) (2410).

[0057] A third spacer may be formed on the second spacer to further reduce the size of the opening (2412), i.e., form a fourth opening. An upper source region implant may be formed through the fourth opening to define an upper source region, as well as a BVgs enhancement region and an upper gate disposed in the lower source region (2414). That is, the upper gate may be defined as the remaining portion of the upper gate implant formed through the first opening in operation 2402.

[0058] 1-24 thus illustrate example implementations of JFET devices including a plurality of unit cells of individual JFET cells, the unit cells arranged in a grid such that lines or segments of the unit cells have alternating gate-source contact layouts, and the pitch of the JFET devices can be 5 microns or less, e.g., 2 or 3 microns. Such JFET devices can be constructed in a self-aligned manner, where spacers formed in one operation can be used as a virtual mask during implantation steps in subsequent operations.

[0059] Many variations of the described embodiments may be provided as well. For example, the described embodiment includes a gate-source contact 108 that is connected to both the top gate 104 and the bottom gate 204, but not to the source region 102. However, other configurations are possible. For example, the bottom gate 204 may be connected to the source contact to form an integrated body diode, in which case channel conduction may be completely controlled by the top gate 104.

[0060] In a first exemplary implementation, referred to as Example 1, a junction field effect transistor (JFET) semiconductor device includes: a substrate including a drain region of a JFET; a drift region disposed on the substrate; a lower gate disposed in the drift region; a source region having a lower source region disposed on the lower gate and extending laterally beyond the lower gate, and an upper source region disposed on the lower source region; an upper gate formed on the lower source region and at least partially surrounding the upper source region, the upper gate extending laterally beyond the lower gate to define a gate offset between the upper gate and the lower gate.

[0061] Example 2 of the JFET semiconductor device described in Example 1 further includes a gate contact region in contact with the top gate and the bottom gate to provide a common gate contact for the JFET semiconductor device.

[0062] Example 3 includes the JFET semiconductor device of example 2, wherein a channel length of the JFET semiconductor device is defined as the overlap between an outer edge of the lower gate and an inner edge of the upper gate at the lower source region.

[0063] Example 4 includes the JFET semiconductor device of example 3, wherein the gate contact region overlaps the top gate by a distance that is less than the channel length.

[0064] Example 5 includes the JFET semiconductor device of example 2, wherein the gate contact region partially overlaps the lower source region.

[0065] Example 6 includes the JFET semiconductor device of example 1, wherein a gate-to-source breakdown voltage (BVgs) enhancement region is formed in the lower source region and disposed between the upper source region and the upper gate.

[0066] Example 7 includes the JFET semiconductor device of Example 6, wherein the BVgs enhancement region has a doping level that is less than or equal to 20 percent of the doping level of the upper source region.

[0067] Example 8 includes the JFET semiconductor device described in Example 1, wherein the substrate and the drift region comprise silicon carbide (SiC).

[0068] Example 9 includes the JFET semiconductor device described in Example 1, having a gate offset of 0.05 microns or less.

[0069] Example 10 includes the JFET semiconductor device of example 1, wherein the JFET semiconductor device is normally on.

[0070] In an eleventh exemplary implementation, referred to as Example 11, a junction field effect transistor (JFET) semiconductor device includes: a substrate including a drain region of a JFET semiconductor device; a drift region disposed on the substrate; A plurality of unit cells arranged in a lattice pattern in the drift region, each unit cell comprising: a lower gate disposed in the drift region; a source region having a lower source region disposed on the lower gate and extending laterally beyond the lower gate, and an upper source region disposed on the lower source region; an upper gate formed on the lower source region and at least partially surrounding the upper source region, the upper gate extending laterally beyond the lower gate to define a gate offset between the upper gate and the lower gate; and a plurality of unit cells including:

[0071] Example 12 includes the JFET semiconductor device of example 11, wherein a pitch of the JFET semiconductor devices defined between adjacent unit cells is 5 microns or less.

[0072] Example 13 includes the JFET semiconductor device of example 11, wherein each unit cell includes a gate-to-source breakdown voltage (BVgs) enhancement region formed on the lower source region and between the upper source region and the upper gate.

[0073] Example 14 includes the JFET semiconductor device of example 11, wherein the gate offset is less than or equal to 0.05 microns.

[0074] Example 15 includes the JFET semiconductor device of example 11, wherein each unit cell includes a gate contact region in contact with the top gate and the bottom gate to provide a common gate contact for the JFET semiconductor device.

[0075] In a sixteenth exemplary implementation, referred to as Example 16, a method for fabricating a semiconductor device includes: forming a lower source region implant and an upper gate implant through a first opening in a mask disposed over the substrate; forming first spacers on sidewalls of the mask to define second openings smaller than the first openings; forming a lower gate through the second opening; forming a second spacer on the first spacer to define a third opening smaller than the second opening; forming an upper source region in the upper gate implant through the third opening, thereby defining a remainder of the upper gate implant as an upper gate of a junction field effect transistor (JFET), the substrate providing a drain of the JFET.

[0076] Example 17 is directed to forming a lower source region implant and an upper gate implant. 17. The method of example 16, including forming a lower source region implant below the upper gate implant.

[0077] Example 18 includes forming a lower gate through the second opening; Example 17. The method of example 16, including forming a lower gate below the lower source region implant, the upper gate implant extending laterally beyond the lower gate to define a gate offset between the upper gate implant and the lower gate.

[0078] Example 19 is forming a third spacer in the first spacer to define a fourth opening having a size between the size of the second opening and the size of the third opening; Example 17. The method of example 16, further comprising forming a lightly doped region through the third opening before forming the second spacer.

[0079] Example 17 is a semiconductor device comprising: a first gate-source region; a second gate-source region; a second gate-source region; a third gate-source region; a fourth gate-source region; a fourth gate-source region; a fifth gate-source region; a fifth gate-source region; a sixth gate-source region; a sixth gate-source region; a sixth gate-source region; a sixth gate-source region; a sixth gate-source region; a seventh ... gs ) maintaining the area as an improved area, including the method described in Example 19.

[0080] In the foregoing description, when an element, such as a layer, region, substrate, or component, is referred to as being on, connected to, electrically connected to, coupled to, or electrically coupled with another element, it will be understood that it can be directly disposed on, connected to, or coupled with the other element, or that one or more intervening elements may be present. Conversely, when an element is referred to as being directly on, directly connected to, or directly coupled with another element or layer, no intervening elements or layers are present. Throughout the detailed description of the present invention, the terms direct, directly connected, or directly coupled may not be used, but elements shown as being directly on, directly connected, or directly coupled may be referred to as such. The claims of this application (if included) may be amended to describe the exemplary relationships described herein or shown in the drawings.

[0081] As used in this specification and claims, the singular can include the plural unless the context clearly dictates otherwise. Spatially relative terms (e.g., throughout, above, above, below, lower, underneath, below, etc.) are intended to encompass different orientations of the device during use or operation in addition to the orientation depicted in the drawings. In some implementations, the relative terms above and below can include vertically above and vertically below, respectively. In some implementations, the term adjacent can include laterally adjacent or horizontally adjacent.

[0082] Some implementations may be implemented using various semiconductor processing and / or packaging technologies, such as, but not limited to, silicon (Si), gallium arsenide (GaAs), gallium nitride (GaN), silicon carbide (SiC), and / or other types of semiconductor processing technologies associated with semiconductor substrates.

[0083] While certain features of the described implementations have been illustrated as described herein, many modifications, substitutions, changes, and equivalents will now occur to those skilled in the art. It will therefore be understood that the appended claims are intended to cover all such modifications and changes as fall within the scope of the implementations. These have been presented by way of example only, and not limitation, and it will be understood that various changes in form and detail may be made. Any portion of the apparatus and / or methods described herein may be combined in any combination except mutually exclusive combinations. The implementations described herein may include various combinations and / or subcombinations of functions, components, and / or features of the different implementations described.

[0084] While certain features of the described implementations have been illustrated as described herein, many modifications, substitutions, changes, and equivalents will now occur to those of ordinary skill in the art. It is therefore to be understood that the appended claims are intended to cover all such modifications and changes as fall within the scope of the embodiments.

Claims

1. A junction field effect transistor (JFET) semiconductor device (100), comprising: a substrate (206) including a drain region of the JFET (100); a drift region (202) disposed on the substrate (206); a lower gate (204) disposed in the drift region (202); a source region (102) having a lower source region (102b) disposed on the lower gate (204) and extending laterally beyond the lower gate (204), and an upper source region (102a) disposed on the lower source region (102b); An upper gate (104) formed on the lower source region (102b) and at least partially surrounding the upper source region (102a), the upper gate (104) extending laterally beyond the lower gate (204) to provide a gate offset (L) between the upper gate (104) and the lower gate (204). ｇｏ a top gate (104) defining a JFET semiconductor device.

2. 2. The JFET semiconductor device of claim 1, further comprising a gate contact region (108a) in contact with said top gate (104) and said bottom gate (204) to provide a common gate contact for said JFET semiconductor device.

3. 3. The JFET semiconductor device of claim 2, wherein a channel length of the JFET semiconductor device is defined as an overlap between an outer edge of the lower gate (204) and an inner edge of the upper gate (104) at the lower source region (102b).

4. 4. The JFET semiconductor device of claim 3, wherein the gate contact region (108a) overlaps the top gate (104) by a distance less than the channel length.

5. 3. The JFET semiconductor device of claim 2, wherein the gate contact region (108a) partially overlaps the lower source region (102b).

6. 2. The JFET semiconductor device of claim 1, further comprising a gate-to-source breakdown voltage (BVgs) enhancement region (106) formed in said lower source region (102b) and disposed between said upper source region (102a) and said upper gate (104).

7. 7. The JFET semiconductor device of claim 6, wherein said BVgs enhancement region (106) has a doping level that is less than or equal to 20 percent of the doping level of said upper source region (102a).

8. The JFET semiconductor device of claim 1 , wherein the substrate (206) and the drift region comprise silicon carbide (SiC).

9. The gate offset (L ｇｏ 2. The JFET semiconductor device of claim 1, wherein the thickness of the first and second gate electrodes is 0.05 microns or less.

10. 10. The JFET semiconductor device of claim 1, wherein said JFET semiconductor device is normally on.

11. A junction field effect transistor (JFET) semiconductor device (100), comprising: a substrate (206) including a drain region of the JFET semiconductor device (100); a drift region (202) disposed on the substrate (206); A plurality of unit cells arranged in a lattice pattern in the drift region, each unit cell comprising: a lower gate (204) disposed in the drift region (202); a source region (102) having a lower source region (102b) disposed on the lower gate (204) and extending laterally beyond the lower gate (204), and an upper source region (102a) disposed on the lower source region (102b); An upper gate (104) formed on the lower source region (102b) and at least partially surrounding the upper source region (102a), the upper gate (104) extending laterally beyond the lower gate (204) to provide a gate offset (L) between the upper gate (104) and the lower gate (204). ｇｏ a top gate (104) defining a JFET semiconductor device; and a plurality of unit cells including the top gate (104).

12. 12. The JFET semiconductor device of claim 11, wherein the pitch of the JFET semiconductor devices defined between adjacent unit cells is 5 microns or less.

13. 12. The JFET semiconductor device of claim 11, wherein each unit cell includes a gate-to-source breakdown voltage (BVgs) enhancement region (106) formed on the lower source region (102b) between the upper source region (102a) and the upper gate (104).

14. 12. The JFET semiconductor device of claim 11, wherein the gate offset is 0.05 microns or less.

15. 12. The JFET semiconductor device of claim 11, wherein each unit cell includes a gate contact region (108a) in contact with the top gate (104) and the bottom gate (204) to provide a common gate contact for the JFET semiconductor device.

16. 1. A method of fabricating a semiconductor device, comprising: forming (2402) a lower source region implant (1202b) and an upper gate implant (604) through a first opening in a mask (606) disposed on a substrate; forming (2404) first spacers (702) on sidewalls of the mask (606) to define second openings smaller than the first openings; forming (2406) a bottom gate (804) through the second opening; forming (2408) a second spacer (902) on the first spacer (702) to define a third opening smaller than the second opening; forming (2414) an upper source region (1202a) in the top gate implant through the third opening, thereby defining a remaining portion of the top gate implant (604) as an upper gate of a junction field effect transistor (JFET), wherein the substrate provides a drain of the JFET.

17. forming the lower source region implant and the upper gate implant; 17. The method of claim 16, comprising forming the lower source region implant (1202b) below the upper gate implant (604).

18. forming the lower gate through the second opening; 17. The method of claim 16, comprising forming the lower gate (804) below the lower source region implant (1202b), wherein the upper gate implant (604) extends laterally beyond the lower gate (804) to define a gate offset between the upper gate implant (604) and the lower gate (804).

19. forming (2412) a third spacer (1102) on the first spacer (702) to define a fourth opening having a size between the size of the second opening and the size of the third opening; 17. The method of claim 16, further comprising forming (2410) a lightly doped region through the third opening before forming the second spacer.

20. Forming the upper source region (1202a) may include disposing a portion of the lightly doped region at a gate-to-source breakdown voltage (BV ｇｓ 20. The method of claim 19, wherein the first region is maintained as an improvement region.

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