Triggered Producer Instructions and Triggered Consumer Instructions

Abstract

The execution circuit (14) performs processing operations in response to triggered instructions. The candidate instruction storage circuit (11) stores triggered instructions, each of which specifies condition information (40) indicating at least one condition. The issue circuit (12) issues a given triggered instruction for execution in response to determining / predicting that the condition indicated by the given triggered instruction is satisfied. The execution circuit updates the machine state (82) in response to state update information (48) specified by the given triggered instruction. When the given triggered instruction includes a triggered producer instruction, the execution circuit updates the dependency state (84) in response to completion of execution of the triggered producer instruction to indicate that the corresponding triggered consumer instruction may be issued. When the given instruction includes a triggered consumer instruction, the issue circuit evaluates whether the condition is determined / predicted to be satisfied depending on both the machine state and the dependency state.

Description

[Technical Field]

[0001] The present technology relates to the field of data processing.

[0002] A triggered instruction architecture (TIA) is an instruction set architecture (ISA) that does not have a program counter (PC); instead, instructions specify the conditions under which they are issued ("triggered"). The condition specified by each instruction may be referred to as a "trigger," "trigger condition," or "predicate," and an instruction that specifies a condition may be referred to as, for example, a triggered instruction, a condition-dependent instruction, or a condition-specifying instruction.

[0003] The condition specified by the triggered instruction is monitored, and if the system state (e.g., updates to the system state due to execution of previous instructions and updates due to hardware events) matches the state defined in the condition, the corresponding instruction is issued ("triggered").

[0004] A key advantage of using a TIA is that the instruction fetch, decode, and issue logic is much simpler than in a typical processor (e.g., a central processing unit, CPU, etc.), thus allowing more transistors (and therefore more circuit area and power budget) to be dedicated to the data path, increasing computational density.

[0005] Furthermore, by relying on system state rather than a program counter to control instruction execution, the number of control flow instructions (e.g., branch instructions) that must be executed can be reduced, and the PEs can react quickly to incoming data (which can "trigger" appropriate instructions) and events. For this reason, TIAs are sometimes referred to as event-driven architectures.

[0006] Looking at the first example of this technology, at least one triggered instruction processing element, a given triggered instruction processing element comprising execution circuitry for performing processing operations in response to a triggered instruction according to a triggered instruction architecture; a candidate instruction storage circuit for storing a plurality of triggered instructions, each triggered instruction specifying condition information indicative of at least one condition; an issue circuit for issuing the given triggered instruction for execution by the execution circuit in response to determining or predicting that at least one condition indicated by the condition information specified by the given triggered instruction is satisfied; an execution circuit responsive to the state update information specified by the given triggered instruction, for updating the machine state information in dependence on the state update information; causing the execution circuitry, when a given triggered instruction includes a triggered producer instruction, to update the dependency state information to indicate that the execution circuitry may issue at least one corresponding triggered consumer instruction for execution in response to completion of execution of the processing operation performed in response to the triggered producer instruction; An apparatus is provided, wherein the issue circuitry is configured to evaluate whether at least one condition is determined or predicted to be satisfied when a given instruction includes a triggered consumer instruction, depending on both machine state information and dependency state information.

[0007] In another example of this technology, performing processing operations in response to triggered instructions according to a triggered instruction architecture; storing a plurality of triggered instructions, each triggered instruction specifying condition information indicative of at least one condition; issuing a given triggered instruction in response to determining or predicting that at least one condition indicated by the condition information specified by the given triggered instruction is satisfied; In response to state update information specified by a given triggered instruction, updating machine state information in dependence on the state update information; responsive to completion of execution of a processing operation performed in response to a given triggered instruction, when the given triggered instruction includes a triggered producer instruction, updating dependency state information to indicate that at least one corresponding triggered consumer instruction may be issued for execution; and evaluating whether at least one condition is determined or predicted to be satisfied when a given instruction includes a triggered consumer instruction, depending on both the machine state information and the dependency state information.

[0008] In accordance with another example of the present technology, there is provided a computer program comprising instructions, which when executed on a computer: processing program logic for performing processing operations in response to triggered instructions according to a triggered instruction architecture; candidate instruction store program logic for maintaining a candidate instruction store data structure for storing a plurality of triggered instructions, each triggered instruction specifying condition information indicative of at least one condition; and issuing program logic for issuing the given triggered instruction for execution by the execution circuitry in response to determining or predicting that at least one condition indicated by the condition information specified by the given triggered instruction is satisfied; The processing program logic, in response to the state update information specified by the given triggered instruction, updates the machine state information depending on the state update information; when a given triggered instruction includes a triggered producer instruction, the processing program logic causes the dependency information to be updated to indicate that at least one corresponding triggered consumer instruction may be issued for execution in response to completion of execution of a processing operation performed in response to the triggered producer instruction; The issuing program logic is configured to evaluate whether at least one condition is determined or predicted to be satisfied when a given instruction includes a triggered consumer instruction, depending on both the machine state information and the dependency state information.

[0009] According to another embodiment of the present technology, there is provided a computer-readable storage medium storing the above-mentioned computer program. The computer-readable storage medium can be a transitory medium or a non-transitory medium. [Brief explanation of the drawings]

[0010] Further aspects, features, and advantages of the present technology will become apparent from the following description of examples, read in conjunction with the accompanying drawings. [Figure 1] 1 illustrates an apparatus comprising several triggered instruction processing elements (PEs) coupled by an on-chip communication interconnect. [Figure 2] 1 illustrates an example of a triggered command. [Figure 3] 1 illustrates an example of a tagged data item received on an input channel. [Figure 4] 1 illustrates an example of a triggered instruction processing element (PE). [Figure 5] 1 illustrates examples of triggered producer instructions and triggered consumer instructions. [Figure 6] 1 illustrates examples of triggered producer instructions and triggered consumer instructions. [Figure 7] 1 illustrates examples of triggered producer instructions and triggered consumer instructions. [Figure 8]1 illustrates another example of a triggered instruction processing element (PE). [Figure 9] FIG. 10 is a flow diagram illustrating a method for executing instructions in a TIA that supports triggered producer instructions and triggered consumer instructions. [Figure 10] Illustrates a virtual machine implementation.

[0011] Before discussing example implementations with reference to the accompanying drawings, the following description of example implementations and associated advantages is provided.

[0012] According to one exemplary configuration, an apparatus is provided, the apparatus comprising at least one triggered instruction processing element (PE), wherein a given triggered instruction processing element comprises execution circuitry for performing a processing operation in response to a triggered instruction according to a triggered instruction architecture (TIA).

[0013] For example, an apparatus may include a single triggered instruction PE (e.g., a given triggered instruction PE may be the only triggered instruction PE), while in other examples, an apparatus may include multiple triggered instruction PEs (e.g., a given triggered instruction PE may be one of multiple triggered instruction PEs in an array of triggered instruction PEs, e.g., providing an event-driven spatial fabric). In some examples, an apparatus may include a mix of triggered instruction PEs and PEs based on different types of instruction set architectures (ISAs), such as program counter (PC)-based architectures. A PE may also be referred to as, for example, a processor or a processing circuit.

[0014] The execution circuitry executes the triggered instruction by performing (e.g., executing) a processing operation. For example, the processing operation to be performed may be determined by information in the instruction encoding, such as an opcode, and may include, for example, arithmetic / logic operations, load / store operations, and floating point (FP) operations.

[0015] In a given triggered instruction PE, at least some of the instructions executed are triggered instructions executed in accordance with the TIA. However, it should be understood that a given triggered instruction PE may also be capable of processing some instructions that are not triggered instructions.

[0016] The apparatus also includes a candidate instruction storage circuit for storing a plurality of triggered instructions, each triggered instruction specifying condition information indicating at least one condition. The apparatus also includes an issue circuit for issuing a given triggered instruction for execution by the execution circuit in response to determining or predicting that the at least one condition indicated by the condition information specified by the given triggered instruction is satisfied.

[0017] The multiple triggered instructions stored in the candidate instruction storage circuit may also be referred to as a pool of triggered instructions and may include several triggered instructions whose condition information should be monitored to determine when the condition indicated by the condition information is determined or predicted to be met (and thus when the associated triggered instruction can be issued). For example, the condition indicated by the condition information of a particular triggered instruction may be determined or predicted to be met based on a machine state, which may depend on hardware events detected or generated by (for example) the triggered instruction PE and / or previously executed instructions. Note that there may be situations in which an instruction cannot be issued immediately after the condition is determined or predicted to be met. For example, if the conditions indicated by the condition information of multiple triggered instructions are determined or predicted to be met simultaneously, the multiple triggered instructions may be issued one after the other (e.g., this may be based on the order in which they are stored in memory). Alternatively, a particular triggered instruction whose condition is predicted or determined to be met may not be issued until any data it requires is available. It should also be noted that the issue circuitry of the present technology is configured to issue a given triggered instruction either when its condition is determined to be met or when it is predicted to be met (e.g., when the condition is met or predicted to be met soon), and thus the issue circuitry of the present technology may support inference of the condition of the triggered instruction.

[0018] In accordance with the techniques of the present invention, execution circuitry responds to state update information specified by a given triggered instruction by causing machine state information to be updated in accordance with the state update information.

[0019] Thus, a given triggered instruction specifies state update information as well as condition information, and therefore execution of a given triggered instruction can change machine state information, which may lead to the issuance of another triggered instruction. However, while a given triggered instruction specifies both condition information and state update information, some triggered instructions may specify only condition information.

[0020] According to the present technology, when a given triggered instruction includes a triggered producer instruction, the execution circuitry updates the dependency state information to indicate that at least one corresponding triggered consumer instruction can be issued for execution in response to completion of execution of a processing operation performed in response to the triggered producer instruction. The issue circuitry is configured to evaluate whether at least one condition is determined or predicted to be satisfied in dependence on both the machine state information and the dependency state information when a given instruction includes a triggered consumer instruction.

[0021] It should be noted that, in this application, completion of a processing operation performed in response to an instruction is sometimes referred to as completion of execution of the instruction or completion of the instruction, which completion is typically indicated by, for example, the availability of a result from the processing operation.

[0022] Thus, in accordance with the present technology, issuance of a triggered consumer instruction depends not only on machine state information (e.g., updated based on state update information of the executed triggered instruction, which may be updated based on other events, such as hardware events), but also on dependency state information (e.g., updated in response to completion of execution of a processing operation performed in response to the triggered producer instruction). This differs from the way instructions might be expected to be issued in a typical TIA, where the condition indicated by a triggered instruction may depend only on machine state information.

[0023] In an example of the present technology, the dependency information provides a mechanism for expressing fine-grained dependencies between small groups of two or more triggered instructions. Specifically, because the dependency information is updated in response to completion of a triggered producer instruction (e.g., completion of a processing operation performed in response to the triggered producer instruction), the present technology provides a mechanism for expressing a dependency in which a particular triggered instruction (triggered consumer instruction) cannot be issued until execution of another triggered instruction (triggered producer instruction) has completed. Specifically, the present technology can express such dependencies even if the machine state is updated before execution of the instructions completes. For example, the present technology may be particularly useful in scenarios in which execution of the triggered producer instruction involves one or more long-latency operations (e.g., operations that are performed over multiple clock cycles), in which case completion of execution of the triggered producer instruction may occur one or more cycles after the machine state is updated (e.g., because the long-latency operations may require more cycles to complete than the number of cycles required to update the machine state).

[0024] PC-based architectures may use barrier instructions to enforce dependencies between instructions. For example, some barrier instructions may prevent any instructions issued after the barrier from executing before the barrier instruction (and any instructions issued before the barrier instruction) have completed. However, barriers (also called fences) are typically quite restrictive (e.g., a full barrier blocks execution of all instructions after the barrier, which can have a significant performance impact). Furthermore, barriers typically rely on assuming sequential consistency of instructions (e.g., where program order implies execution order from the programmer's perspective, at least for a single thread). For example, in most PC-based architectures, even if a predefined program order exists and out-of-order execution is supported, the result of executing instructions is constrained to be equivalent to the result of executing instructions in program order. However, instruction issue in TIA is not sequential in nature, and there is generally no predefined program order for triggered instructions in TIA. Even if some instructions are issued sequentially, the sequence itself is frequently triggered by a machine state that meets a specified condition. Therefore, barrier instructions are not well-suited for TIA.

[0025] In TIA, triggered instruction dependencies are typically expressed in the instruction itself, e.g., in condition information. Therefore, it may be assumed that fine-grained instruction dependencies can be expressed using the condition information of the triggered consumer instruction. Therefore, it may be considered unnecessary to define dependency state information in addition to machine state information. However, the inventors have recognized (as described above) that this may be ineffective in situations where the execution of the triggered consumer instruction depends on the completion of the execution of the triggered producer instruction, especially when the execution of the triggered producer instruction involves at least one long-latency operation.

[0026] Therefore, the inventors of this technology have proposed making the condition indicated by the condition information of the triggered consumer instruction dependent on the dependency state information set in response to the completion of the execution of the triggered producer instruction in addition to the machine state information, thereby enabling fine-grained instruction dependency to be expressed in the TIA.

[0027] In some examples, the execution circuitry is permitted to cause the machine state information to be updated prior to completion of execution of the processing operation performed in response to the triggered producer instruction.

[0028] In such instances, the machine state information may not reliably indicate when execution of the triggered producer instruction has completed, and therefore some producer-consumer instruction dependencies may not be correctly expressed using conditions based solely on machine state information. Thus, the present technique may be particularly useful when machine state information is permitted to be updated before execution of the triggered producer instruction has completed, as the dependency state information set at completion provides an additional mechanism for expressing these dependencies.

[0029] In some examples, the apparatus comprises a set of predicate registers, the set of predicate registers including one or more predicate registers for storing machine state information.

[0030] While there are many ways in which machine state information may be stored, in these examples, the machine state is represented by one or more predicate registers. Note that these one or more predicate registers may be all of the registers in the set of predicate registers or a suitable subset (some but not all) of the registers in the set. In particular examples, each register is a one-bit register, although it is also possible for each register to hold more than one bit. Note that the number of predicate registers and the number of bits each predicate register can hold are implementation dependent, and the number of conditions that can be represented by the machine state depends on the number of bits available in the one or more predicate registers to hold the machine state.

[0031] In some examples, the set of predicate registers comprises at least one predicate register for storing dependency state information, and the issue circuitry is configured to determine that at least one condition indicated by the condition information of a given triggered instruction is satisfied when values ​​stored in at least a subset of the predicate registers match expected values ​​indicated by the condition information.

[0032] Thus, in these examples, at least one of the predicate registers in the set (e.g., other than one or more predicate registers used to represent machine state information) is used to represent dependency state information. This approach may be advantageous because it utilizes circuitry that may already be present in a TIA-based PE. Furthermore, this approach allows the condition specified by a triggered instruction to remain dependent on the same set of predicate registers regardless of whether the triggered instruction is a triggered consumer instruction. Note that the number of bits used to represent dependency state information (and therefore the number and size of predicate registers) is not particularly limited. Providing more bits to represent dependency state information increases the number of instruction dependencies that can be represented at any given time, but may also reduce the number of bits available to represent machine state information. Thus, for a given number of bits in the set of predicate registers, there is a trade-off between providing more bits to represent machine state and providing more bits to represent dependency information. However, the inventors of the present technology recognized that a typical TIA PE often has some unused predicate registers.

[0033] In some alternatives, the apparatus includes a dependency tag storage circuit for storing dependency state information, and the issue circuit is configured to determine whether at least one condition indicated by the condition information of a given triggered instruction is: the values ​​stored in at least a subset of the predicate registers match the expected values ​​indicated by the condition information, and The dependency tag storage circuit is configured to determine that a condition is satisfied when the dependency state information stored in the dependency tag storage circuit matches the expected dependency state information indicated by the condition information.

[0034] While the above example utilizes predicate registers to represent dependency state information, this example provides additional storage circuitry for storing dependency state information as one or more dependency tags, separate from the predicate registers, which can be advantageous because it leaves the entire set of predicate registers available to represent machine state.

[0035] In some examples, when a given instruction includes a triggered producer instruction, the execution circuitry issues a dependency update signal to cause the dependency information to be updated to indicate that at least one corresponding triggered consumer instruction can be issued for execution in response to completion of execution of a processing operation performed in response to the triggered producer instruction.

[0036] This is one example of a mechanism by which dependency state information can be updated.

[0037] In some particular examples, the device includes a delay circuit that is responsive to the dependency state update signal to introduce a delay between issuance of the dependency state update signal and updating of the dependency state information.

[0038] Introducing a delay in this manner (e.g., which may be a delay of a predetermined number of clock cycles between the issuance of the dependency state update signal and the update of the dependency state information) may be advantageous because it may allow other instructions (other than the triggered consumer instruction whose issuance depends on the dependency state information) to proceed before the triggered consumer instruction is issued. For example, these other instructions may be instructions whose issuance is triggered by updates applied to the machine state information. This may avoid a situation where, for example, the triggered producer instruction completes more quickly and / or more frequently than expected, resulting in intervening non-consumer instructions being unlikely to be issued before the issue of the triggered consumer instruction.

[0039] In some examples, the delay circuit introduces a delay in response to the dependency state update signal unless it is determined that the time between the issuance of the triggered producer instruction and the completion of the triggered producer instruction is greater than a predetermined threshold duration.

[0040] As described above, introducing a delay between the issuance of the dependency state update signal and the update of the dependency state information can be particularly useful when the triggered producer instruction completes quickly (e.g., without significant latency). However, the inventors recognized that if the triggered producer instruction does not complete quickly (e.g., when the triggered producer instruction requires the execution of one or more long-latency operations), the delay between the completion of the triggered producer instruction and the issuance of the triggered consumer instruction may be longer than required to issue all of the intervening non-consumer instructions. This can lead to downtime when the execution circuitry is available but not executing any instructions, which can adversely affect the performance of the device. Therefore, in this example, a delay is not introduced unless the time between the issuance and completion of the triggered producer instruction (e.g., which may be measured as a number of clock cycles) is less than or equal to a predetermined threshold duration (which may also be, for example, a threshold number of clock cycles). The delay circuit, in this example, may also be referred to as a dependency state update delay circuit.

[0041] In some examples, the predetermined threshold duration is based on the number of cycles required to issue one or more selected non-consumer instructions after issuing the triggered producer instruction.

[0042] In this manner, the predetermined threshold duration can be set such that there is expected to be sufficient time between the issuance of the triggered producer instruction and the issuance of the triggered consumer instruction for all of the selected non-consumer instructions to be issued. Note that in certain examples, the customary execution latency of the non-consumer instructions can also be taken into account.

[0043] In some examples, the predetermined threshold duration is configurable by software.

[0044] Thus, the threshold duration can be variable and set by a programmer.

[0045] In some examples, the execution circuitry is responsive to the state update information to issue a machine state update signal to cause the machine state information to be updated in dependence on the state update information.

[0046] This is one example of a mechanism by which machine state information can be updated.

[0047] In some particular examples, the apparatus includes a delay circuit that is responsive to the machine state update signal to introduce a delay between when the dependency state update signal is issued and when the dependency state information is updated.

[0048] Thus, while a delay circuit may be provided to introduce a delay between issuing a dependency state update signal and updating the dependency state information (as described above), a delay circuit may also (or instead) be provided to introduce a delay between issuing a machine state update signal and updating the machine state information, which in this example may also be referred to as a machine state update delay circuit.

[0049] Note that in examples where both a dependency state update delay circuit and a machine state update delay circuit are provided, these may be separate circuits (e.g., separate hardware), or the same delay circuit may perform both functions. In either case, the introduction of these delays may be particularly useful for instruction scheduling, for example, when multiple triggered instructions are triggered by the same condition of the machine state.

[0050] In some examples, the length of the delay is configurable by software.

[0051] Note that this can apply to delays introduced by dependency state update delay circuits and / or delays introduced by machine state update delay circuits.

[0052] In some examples, at least one corresponding triggered consumer instruction includes a triggered instruction, the execution of which depends on the completion of execution of a processing operation performed in response to the triggered producer instruction.

[0053] As used herein, the term "triggered producer instruction" generally refers to a triggered instruction that is expected to complete before one or more corresponding "triggered consumer" instructions can be issued.

[0054] The techniques discussed above can be implemented in a hardware device having circuit hardware that implements the triggered instruction processing elements, execution circuits, candidate instruction storage circuits, and issue circuits described above, which (the triggered instruction processing elements, execution circuits, candidate instruction storage circuits, and issue circuits) support triggered producer instructions and triggered consumer instructions as part of a native instruction set architecture supported by the decoding circuitry and processing circuitry.

[0055] However, in another embodiment, the same technique may be implemented in a computer program (e.g., an architecture simulator or model) that may be provided to control a host data processing apparatus to provide an instruction execution environment for executing instructions from the target code. The computer program may include instruction decoding program logic for decoding instructions of the target code to control the host data processing apparatus to perform data processing. The program may also include register maintenance program logic for maintaining (in the memory or architectural registers of the host apparatus) a data structure representing (emulating) the architectural registers (including any predicate registers) of the instruction set architecture being simulated by the program. The emulated registers may include any of the predicate registers described in the examples above. The program may also include issue program logic for emulating the issue circuitry described above, and candidate instruction storage program logic for maintaining a candidate instruction storage data structure to emulate the candidate instruction storage circuitry described above. The instruction decoding program logic includes support for the triggered instructions described above, including triggered producer instructions and triggered consumer instructions having the same functionality as described above for the hardware example. Thus, such a simulator computer program can present to target code executed on the simulator computer program an instruction execution environment similar to that which would be provided by an actual hardware device capable of directly executing a target instruction set, even if there is no actual hardware providing these capabilities in the host computer running the simulator program. This can be useful for executing code written for one instruction set architecture on a host platform that does not actually support that architecture.Simulators may also be useful during the development of software for new versions of instruction set architectures, while software development is performed in parallel with the development of hardware devices that support the new architecture. This may allow software to be developed and tested on the simulator so that software development can begin before hardware devices that support the new architecture are available. The computer program may be provided on a computer-readable storage medium, which may be transient or non-transitory.

[0056] Specific embodiments will now be described with reference to the drawings.

[0057] FIG. 1 illustrates an example of a data processing device 10 in which one or more TIA PEs may be implemented. Specifically, FIG. 1 schematically illustrates data processing device 10 arranged as a spatial architecture in accordance with various examples of the present technology. Spatial architectures can accelerate some applications by spreading the computations that form the most time-consuming portions of program execution in space rather than time. Computations are spread in "space" by using multiple hardware units capable of concurrent operation. In addition to taking advantage of the concurrency opportunities offered by isolated applications distributed across a chip, spatial architectures such as data processing device 10 also take advantage of distributed on-chip memory. In this way, each processing element is associated with one or more memory blocks in close proximity to it. As a result, spatial architectures can avoid the von Neumann bottleneck that hinders the performance of many conventional architectures.

[0058] The data processing device 10 comprises an array of processing elements (compute / memory access clusters) connected via an on-chip communication interconnect, such as a network-on-chip. The network is connected to a cache hierarchy or main memory through interface nodes, also referred to as interface tiles (ITs), which are connected to the network through multiplexers (X). Each processing element includes one or more compute tiles (CTs) and memory tiles (MTs). While FIG. 1 shows a 1:1 mapping between CTs and MTs, other examples may share an MT between two or more CTs. The CTs perform the majority of the data processing operations and arithmetic calculations performed by a given processing element (PE). The MTs function as memory access control circuits and are responsible for data access to locally attached memory (local storage circuitry), data transfers to / from more distant locations of memory, and inter-processing element memory transfers between processing elements and other processing elements.

[0059] In some exemplary configurations, each of the PEs includes a local storage circuit connected to a respective memory control circuit (MT), and each memory control circuit (MT) has a direct connection to one processing circuit (CT). Each PE is connected to a network-on-chip used to transfer data between the memory control circuits (MT) and between each memory control circuit (MT) and an interface node (IT).

[0060] In an alternative configuration, local storage circuits are provided between multiple processing elements and are accessible by multiple memory control circuits (MTs). Alternatively, a single MT can be shared among multiple CTs.

[0061] The processing circuitry formed by each compute / memory access cluster (CT / MT) shown in Figure 1 may be used as a hardware accelerator used to accelerate certain processing tasks, such as machine learning processing (e.g., neural network processing), encryption, etc. The IT may be used to communicate with other parts of the system-on-chip (not shown in Figure 1), such as memory storage and other types of processing units (e.g., a central processing unit (CPU) or a graphics processing unit (GPU)). Configuration of control data used to control the operation of the CT / MT may be performed by software running on the CPU or other processing units of the system.

[0062] The CT (or the entire cluster of CTs and MTs) can be viewed as a triggered instruction processing element that executes instructions according to a triggered instruction architecture rather than a program counter-based architecture.

[0063] In traditional program counter-based architectures, a program counter is used to track the sequential stepping of program flow through a program (except at branch points marked by branch instructions) according to a predefined order defined by the programmer or compiler. The exact sequence through the program is sequential except at branch points, where there are only two choices (taken or not taken) for the next step in the program flow. Processor implementations may use techniques such as out-of-order processing and speculation to execute instructions in an order other than program order, but the results produced must be consistent with the results that would have been produced if the instructions had been executed in program order.

[0064] In contrast, in a triggered instruction architecture (TIA), a programmer or compiler defines several triggered instructions (also called condition-dependent instructions) that do not have a predefined order in which they are assumed to be executed. Instead, each triggered instruction specifies a trigger condition that must be satisfied by the machine state of a processing element for that instruction to be validly issued for execution. In a given cycle in which it determines the next instruction to issue, the triggered instruction processing element may monitor multiple triggered instructions in the same cycle to see if their trigger conditions are satisfied (rather than examining the taken-or-not-taken condition of at most a single branch instruction to determine the next instruction to be executed after a branch, as in program counter-based architectures).

[0065] The processing elements of triggered instructions can use speculation to predict which instructions will satisfy their respective trigger conditions, resulting in the issuance of the instruction before the trigger conditions are actually satisfied. This helps to more fully utilize the processing pipeline (compared to a situation without speculation, in which the processing elements wait for a given instruction to update the machine state before evaluating whether the machine state satisfies another instruction's trigger condition). Such speculation can help improve performance. However, even when speculation is used to issue an instruction for execution before the instruction's trigger condition is actually satisfied, the final result should match the result that would have been achieved if one instruction's machine state update had occurred before evaluating the trigger condition to select the next instruction to be issued for execution. Thus, if the speculation is incorrect and an instruction was issued for execution but it is later determined that the instruction's trigger condition was not satisfied, a recovery action can be implemented to flush the potentially inaccurate results and resume execution from the exact point before the incorrect speculation.

[0066] Such event-driven (triggered) space architectures reduce control flow overhead in program execution, effectively mapping out applications in "space" rather than just time. In a typical event-driven space architecture, PEs are configured for each specific application, which involves loading instructions into each PE's instruction memory and loading configuration settings into control registers. Two key goals of this established event-driven approach are (1) reducing the complexity and physical area of ​​the hardware used to issue instructions, and (2) reducing the number of instructions required to manage program control flow through issuing instructions based on data availability. In these many-core systems, PE area becomes a major design constraint.

[0067] However, it should be noted that TIA is not limited to spatial architectures such as those shown in FIG. 1, although spatial architectures are examples of situations in which TIA may be particularly useful.

[0068] Figure 2 illustrates an example of a triggered instruction. The bottom part of Figure 2 illustrates example fields of the instruction encoding, and the top part of Figure 2 shows information specified (in high-level code representation) by the programmer / compiler for the example triggered instruction. The triggered instruction specifies the following: • Trigger condition information 40 (eg, a condition field indicating at least one condition) indicating one or more trigger conditions that must be satisfied by the machine state of the processing element for the instruction to be validly issued for execution. • An opcode 42 that identifies the type of processing operation to be performed in response to the instruction (eg, add in the high-level code example of FIG. 2). one or more operands 44 for a processing operation; a destination location 46 to which the results of the processing operation should be output, and • Trigger action information 48 (state update information) indicating one or more updates to the machine state of the processing element that are made in response to execution of the triggered instruction.

[0069] It will be appreciated that although the fields of the instruction are shown in a particular order in Figure 2, other implementations may order the fields differently. Also, information shown as a single field in the encoding of Figure 2 may be split between two or more non-contiguous sets of bits within the instruction encoding.

[0070] In this example, the trigger condition information includes predicate information and input channel availability information. The predicate information and the input channel availability information may be coded separately in the trigger condition information or may be represented by a common coding.

[0071] The predicate information specifies one or more events that must occur for the instruction to be validly issued. While other encodings of the predicate information are possible (e.g., each value of the predicate information represents a particular combination of events that must occur, not necessarily each event represented by a separate bit in the encoding), a relatively simple encoding may be one in which each bit of the predicate designation corresponds to a different event and indicates whether that event must occur for the instruction to be validly issued for execution. Thus, if multiple bits are set, the trigger condition requires that each of those events occur for the instruction to be issued. The "event" represented by the predicate information may be, for example, any of the following: - The occurrence of a hardware-signaled event (eg, a reset, an interrupt, a memory fault, or an error signal being asserted). A buffer full / empty event caused by one of the buffer structures described below becoming full or empty. Software-defined events that do not have a specific hardware-defined meaning. Software can use such predicate bits to impose ordering constraints on instructions. For example, if a first instruction should not be executed until a second instruction is executed, the second instruction can specify (in its trigger action information 48) that selected predicate bits should be set in response to the second instruction, and the first instruction can specify (in its trigger condition information 40) that selected predicate bits should be set in order for the first instruction to be validly issued for execution.

[0072] The meaning of a particular predicate bit may also depend on control states stored in a configuration register or other configuration storage that affect the interpretation of the predicate bit. For example, Figure 2 shows an 8-bit predicate field that allows 256 different combinations of events to be encoded (e.g., 8 different combinations of events with any independent combination of ON / OFF settings for each event if one bit is assigned per event, or any additional 256 combinations of events if the encoding does not assign a separate bit per event). The configuration register may store control over which set of events is represented by each encoding, with the events selected from a larger set of events supported by the hardware.

[0073] The trigger action information 48 may be defined using output predicates in a manner that corresponds to the input predicates defined for the trigger condition information 40 .

[0074] As noted above, the predicate bit (also referred to as condition information) may be set in response to execution of the instruction. Note that the timing of setting the predicate bit is not particularly limited and may occur at any time during the execution of the instruction; for example, the predicate bit may be set in parallel with performing any processing operation associated with the instruction. This may mean that the predicate bit is set before execution of the instruction is complete; for example, this may occur when the processing operation being performed in response to the instruction is a relatively long-latency operation (meaning it takes a significant number of clock cycles (e.g., more than one) to complete).

[0075] A given triggered instruction processing element (CT) may receive input data from several input channels, each of which may be a physical signal path that receives input data from a specific source. The source of the input data may be, for example, a memory tile MT associated with that CT, or a MT shared among a cluster of CTs that includes the given CT, or an on-chip network linking other sets of CTs, or a dedicated signal path between a specific pair of CTs or clusters of CTs (separate from the main on-chip network between CTs). As shown in FIG. 3, a given input channel n receives a tagged data item 50 that includes a tag value 52 and a data value 54. The tag value 52 is an identifier used to identify the purpose of the data and can be used by the triggered instruction processing element (CT) to control the triggering of the triggered instruction.

[0076] Thus, as shown in FIG. 2, trigger condition information 40 may also include an input data availability condition indicating that valid issuance of an instruction also depends on the availability of input data on a particular input data channel. For example, the high-level instruction shown at the top of FIG. 2 indicates the identifier “%i0.0” in its trigger condition, meaning that valid issuance requires that input data having a particular tag value “0” be available on a particular input channel (%i0). Of course, the designation “%i0.0” is merely an exemplary representation of this information at a high level, and it will be understood that in the instruction encoding itself, trigger condition information 40 may encode in other ways the fact that triggering of the instruction depends on the input data availability of data having a specified tag value on a specified input channel. It is not required to always specify a particular tag value that needs to be known in order for the trigger condition to be satisfied. The triggered instruction architecture may also support the ability for an instruction to be triggered based on the availability of input data (having any tag value) on a specified input channel.

[0077] Operands 44 for triggered instructions can be specified in different ways. While FIG. 2 shows an instruction with two operands, other instructions may have fewer or more operands. Operands can be identified as being stored in registers addressable using the local register address space of the triggered instruction processing element (CT). For example, see the operand identified in FIG. 2 using the identifier "%r3," which indicates that this operand is taken from register number 3. Operands can also be identified as being data values ​​taken from a particular input channel, such as input channel "%i0," as shown in FIG. 2. Again, FIG. 2 shows the general case where any data from input channel %i0 can be processed by the instruction, but it may also be possible to specify that data with a particular tag value should be used as the operand (e.g., an operand can be specified as %i0.0x5, indicating that the operand is a data value with tag 0x5 on input channel %i0).

[0078] Similarly, the destination location 46 for an instruction can be either a register in the CT's local register address space, or (as in the example of FIG. 2) an indication of an output data channel where the result of the instruction should be output. An output data channel can be a signal path that passes data to the same CT or another CT, or to an MT in the CT or an MT in another CT, or to a network-on-chip. The destination location 46 can identify a tag value specified in a tagged data item 50 that is output on an output channel. For example, the instruction in FIG. 2 specifies that a data value tagged with a tag value of 0xF should be output on output channel %o1.

[0079] 4 illustrates an example of circuitry included in a given triggered instruction processing element (specifically, the CT of the processing element) for processing triggered instructions. The triggered instruction storage circuit 11 includes several memory locations 60 for storing each triggered instruction. Trigger condition information 40 for these instructions is made available to the instruction issue circuit 12, which analyzes whether the trigger conditions 40 of the pool of triggered instructions are determined to be satisfied by the machine state and dependency states 22 (and, if applicable to the given instruction, also determines whether the trigger conditions are satisfied based on the input channel data availability status of input channel data received from the input channels and held in the input channel data holding storage 18). The machine state and dependency states 22 used to evaluate the trigger conditions may include hardware event signals indicating whether various hardware events have occurred, as well as predicate indications set based on trigger actions from previous triggered instructions, as discussed above. The interpretation of the predicate may depend on configuration information stored in the trigger condition / action configuration register 20.

[0080] Some examples may support speculative issuance of triggered instructions, in which case the instruction validation circuitry 12 includes a condition prediction circuitry 30 for predicting whether a trigger condition of a given triggered instruction will be satisfied. The prediction may be based on a prediction state maintained based on the results of previous attempts at executing the instruction (e.g., the prediction state may correlate an identification of a prior event or prior instruction with an identification of a later set of one or more instructions that are expected to execute at some point after the prior event or instruction). If the prediction is incorrect and the instruction is incorrectly issued despite the trigger condition not being known to be satisfied, the effect of the instruction may be reversed (e.g., by flushing the pipeline and resuming processing from the previous, correct point of execution).

[0081] If multiple ready-to-issue triggered instructions are available, each of which determines or predicts that the trigger condition will be satisfied in the same cycle that selects the next instruction to issue, the instruction issue circuitry 12 selects from among the ready-to-issue triggered instructions based on a predefined priority. For example, the priority may be a predetermined sequence of memory locations 60 in the triggered instruction storage circuitry 11 (instructions are assigned to those memory locations 60 in an order corresponding to the order in which they appear in the memory address space from which they are fetched; thus, a programmer or compiler may influence the priority by defining the order in which instructions appear in memory). Alternatively, an explicit priority designation may be assigned to each instruction to indicate their relative priority.

[0082] Once a triggered instruction is selected for issue, it is sent to the execution circuitry 14 of the processing element (CT), which comprises several execution units 15 for executing different types of classes of instructions. For example, the execution units 15 may include adders for performing addition / subtraction operations, multipliers for performing multiplication operations, etc. The operands for a given operation performed by the execution circuitry 14 may be derived from input channel data from input channel data holding storage 18 or from register data read from the processing element's local register storage 16 (or, as mentioned below, may be derived from further register storage in the input processing block accessible based on register addresses in the register address space used to access the local register storage 16). The results of a given operation performed by the execution circuitry may be output as output channel data 17 via a given output channel (to the same CT or other CTs, their associated MTs, or a network-on-chip), or may be written to a destination register in the local register storage 16 (or to register storage in the input processing block). In addition to outputting the computational results of the executed instruction, the execution circuitry 14 may also update the machine state based on any trigger actions specified by the trigger action information 48 of the executed instruction (e.g., one or more predicate bits may be set or cleared as specified by the trigger action information 48), and may also update dependency state, as discussed in more detail below.

[0083] Thus, because the triggered instruction specifies the conditions required for its own effective processing and sets a predicate for controlling subsequent program flow, it can also perform a computational operation, eliminating the need for dedicated branch instructions that only control program flow but do not perform a corresponding computational operation. This can help increase computational density (the amount of computational workload accomplished per instruction) and therefore improve performance.

[0084] A triggered spatial processing element (PE) typically has several input (and output) channels to which (and from which) packets of data are fed. An input packet contains a tagged data value 50, having a tag 52 and data 54, as shown in FIG. 3. The tag modifies a system condition, represented as a predicate bit, and can therefore cause a particular instruction to be triggered based on the value of the tag. An advantage of the triggered instruction paradigm is how it efficiently reacts to an incoming data stream based on data availability.

[0085] As explained above, machine state is permitted to be set based on state update information (trigger action information) specified by an instruction before the instruction's execution completes. As a result, this can mean that predicate bits within triggered instructions cannot always correctly represent dependencies between instructions, particularly in the case of producer-consumer instruction dependencies (where one or more triggered consumer instructions are not permitted to issue until the corresponding triggered producer instructions have completed execution). Figure 5 illustrates this problem.

[0086] FIG. 5 shows an example of a pair of instructions: a bulk data movement instruction (bstw.w) and a remote store instruction (rstw.w), where a programmer may want the execution of the second instruction (rstw.w) to be dependent on the completion of the first instruction (bstw.w). FIG. 5 illustrates how this dependency might be represented in a typical TIA. Specifically, the first (bstw.w) instruction specifies a value 48 to which a predicate (part of machine state 22) is set when the instruction is executed, and the second (rstw.w) instruction specifies a value (40) to which the predicate is expected to be set in order for the instruction to be issued. In this case, the first instruction sets the predicate to the same value (0000_1011, i.e., predicate bits p0, p1, and p3 are set, with p0 being the rightmost bit in this representation) required by the second instruction's condition information 40, meaning that the issuance of the second instruction is dependent on the execution of the first instruction.

[0087] However, the inventors recognized that because the predicate is permitted to be set before the execution of the first instruction is completed, the predicate does not provide a mechanism for expressing a dependency where the issuance of a second instruction is dependent on the completion of execution of the first instruction. For example, processing operations associated with a bstw.w instruction may be associated with a relatively long latency, which may mean that execution of these operations has not completed by the time the predicate is updated, which may mean that an rstw.w instruction is issued while execution of the bstw.w instruction is in progress. In some examples, this may be problematic if, for example, execution of the rstw.w instruction stalls or fails after execution of the bstw.w instruction has begun. Thus, bstw.w and rstw.w are examples of instructions for which implementation of the present technique may be useful. However, it should be noted that these are merely examples of instructions for which the present technique may be implemented, and in fact the present technique may be applied to any producer / consumer group of instructions in a triggered architecture, especially when the producer instruction has a long latency.

[0088] 6 and 7 illustrate examples of how the bstw.w and rstw.w instructions may be implemented as triggered producer and consumer instructions in accordance with the present techniques.

[0089] 6, the bstw.w instruction is modified to require a specified one of the predicates (p7) to be set upon completion of execution of the instruction. This update is in addition to setting the results of the other predicate registers (p0-p6) in response to state update information 48. The condition information specified by the rstw.w instruction is then modified to require predicate bit p7 to be set in addition to predicate bits p0, p1, and p3 (i.e., the condition information for the rstw.w instruction requires the predicate registers to be set to 1000_1011).

[0090] In the example of Figure 6, predicate bit p7 represents dependency information that (set in response to completion of execution of a triggered producer instruction—in this case, bstw.w—) indicates that the corresponding triggered consumer instruction (in this case, rstw.w) may be issued. This dependency information thus provides a mechanism for expressing producer-consumer instruction dependencies.

[0091] Note that additional non-consumer instructions may be triggered between the setting of predicate registers p0-p6 (in response to state update information 48) and the setting of predicate register p7 (in response to the completion of the bstw.w instruction). These instructions (which may, for example, specify condition information that requires the predicate register to be set to 0000_1011) may then be executed concurrently with the bstw.w instruction.

[0092] 6 uses a single predicate bit to represent dependency information. However, it should be understood that the number of different instruction dependencies that can be expressed at any given time can be increased by increasing the number of predicate bits made available to represent dependency information.

[0093] Using some of the predicate bits to represent dependency state information may seem counterintuitive because it may reduce the number of predicate bits available to represent machine state. While an extra predicate register could be provided, this may increase the circuit area required for the PE and may also increase the number of bits that need to be provided in the encoding of each instruction to represent the predicate information. This is not ideal because it may put significant pressure on the encoding space within the instruction. However, the inventors have recognized that in typical TIAs, there are often spare predicate bits. Therefore, the example shown in FIG. 6 utilizes these extra predicate bits (in both the predicate register and the encoding of the triggered producer instruction and the triggered consumer instruction) to represent dependency state information.

[0094] Figure 7 illustrates an alternative representation of a triggered producer instruction and a triggered consumer instruction. In this example, it is assumed that one or more tag bits (e.g., a completion flag) are provided alongside (or in addition to) the predicate registers, and that these tag bits are used to represent dependency state information. Thus, in Figure 7, the bstw.w instruction is modified to set tag bit p.1 when the instruction completes execution, and the condition information of the rstw.w instruction is modified to require the tag bit to be set in addition to predicate registers p0, p1, and p3 being set. In this example, more predicate bits are available to represent machine state than in the example of Figure 6, but additional circuitry may be required to represent the tag bits.

[0095] Referring now to FIG. 8, this is another illustrative diagram of a triggered instruction processing element CT. As shown in this figure, several candidate triggered instructions are stored in a set of memory locations 60, each with corresponding condition information 40. A trigger resolution circuit 80 monitors the conditions 40, a set of predicate registers 82 (comprising, in this example, eight 1-bit predicate registers), and one or more dependency tags 84. Note that in some examples, dependency tags are not provided, and the dependency information is instead represented by a subset of the predicate registers 82 (as discussed above). The trigger resolution circuit 80 also monitors data tags and channel conditions, as discussed above. When a condition associated with one of the candidate instructions is determined or predicted to be satisfied, a priority encoder 86 issues a signal that serves as a control signal for a multiplexer 88, causing the triggered instruction to be issued for execution. Thus, the trigger resolution circuit 80, priority encoder 86, and multiplexer 88 may collectively be considered an issue circuit.

[0096] As shown in the figure, once a triggered instruction is issued, it is executed. If the triggered instruction is part of a block of triggered instructions (other than the last instruction in the block) that are all associated with the same condition information, the issue circuitry advances to the next instruction in the block once the preceding instruction is issued. Note, for example, that the instructions in I-memory (60) are of different lengths, illustrating the possibility that a sequence of triggered instructions can share the same I-trigger (40). This represents a hybrid dataflow design; not every single instruction needs to be triggered; a block of instructions may only be triggered once.

[0097] On the other hand, if the triggered instruction is not part of a block of instructions or is the last instruction in a block of instructions, execution of the triggered instruction also involves updating predicate register 82 based on state update information specified by the instruction. In addition, if the triggered instruction is a triggered producer instruction, tag bits 84 are also updated when execution of the instruction is complete.

[0098] As shown in the figure, a delay circuit 90 may also be provided. The delay circuit may intercept an update signal issued by the execution circuit to update the predicate register or dependency tag, creating a delay between when the signal is issued and when the corresponding update is performed. This delay may be selective (e.g., not always applied), and the length of the delay may be variable. Two instances of delay circuit 90 are shown in FIG. 8 to illustrate the multiple locations where delay circuit 90 may be provided. For example, delay circuit 90a may be provided on the path updating the tag bits to delay updates to the tag bits without affecting updates to the predicates. In another example, delay circuit 90b may be provided on both the path for updating the tag bits and the path for updating the predicate register, thereby introducing a delay when updating the predicate register. In yet another example (not shown), a delay may be introduced with respect to updating the predicate register but not with respect to the tag bits.

[0099] 9 is a flow diagram illustrating the processing of a triggered instruction. In step 100, the instruction issue circuitry 12 of the processing element determines whether the machine and dependency state 22 (and input channel data availability, if associated with any particular instruction) satisfies or is predicted to satisfy the trigger condition of any of the pool of triggered instructions stored in the triggered instruction storage circuitry 11. If not, the instruction issue circuitry 12 waits until an instruction is determined or predicted to satisfy its trigger condition. If multiple triggered instructions are ready to issue (step 102), the issue circuitry issues one of the ready-to-issue instructions, selected based on a predetermined priority (e.g., the storage order of the instructions in memory), in step 104. Otherwise, if only one instruction is ready to issue, that instruction is issued in step 106. In step 108, the execution circuitry 14 executes the issued instruction on one or more operands to produce a result value. The operands may be read from local registers 16, or from input channel data stored in input channel data holding area 18, or may be dequeued data dequeued from one of the input data buffers managed by input channel processing circuit 70. The result value may be written to local register 16, output as output channel data, or enqueued in one of the buffers managed by input channel processing circuit 70. In step 110, execution circuit 16 also triggers updates to machine state 22 based on trigger action information 48 specified by the executed instruction. In step 112, dependency states are updated, although this step is not performed until execution of the instruction is complete.

[0100] FIG. 10 illustrates a simulator implementation that may be used. While the above embodiments implement the present invention in terms of apparatus and methods for operating specific processing hardware supporting the technology, it is also possible to provide an instruction execution environment according to the embodiments described herein implemented through the use of a computer program. Such computer programs are often referred to as simulators, insofar as they provide a software-based implementation of a hardware architecture. Various simulator computer programs include emulators, virtual machines, models, and binary translators, including dynamic binary translators. Typically, a simulator implementation may run on a host processor 210, optionally running a host operating system 208 and supporting a simulator program 202. In some arrangements, there may be multiple layers of simulation between the hardware and the provided instruction execution environment, and / or there may be multiple different instruction execution environments provided on the same host processor. Historically, powerful processors have been required to provide simulator implementations that run at reasonable speeds, but such an approach may be justified in certain situations, such as when it is desirable to execute code native to another processor for compatibility or reuse reasons. For example, a simulator implementation may provide an instruction execution environment that has additional functionality not supported by the host processor hardware, or that is typically associated with a different hardware architecture. An overview of simulation is given in "Some Efficient Architecture Simulation Techniques," Robert Bedichek, Winter 1990 USENIX Conference, pp. 53-63.

[0101] While embodiments have been described above with reference to specific hardware components or features, equivalent functionality may be provided in simulated embodiments by suitable software components or features. For example, certain circuits may be implemented as computer program logic in simulated embodiments. Similarly, memory hardware such as registers or caches may be implemented as software data structures in simulated embodiments. For example, as shown in FIG. 10 , simulator code may include processing program logic 204 for emulating the execution circuitry described above and issuing program logic 206 for emulating the issuing circuitry described above. In arrangements where one or more of the hardware elements referenced in the foregoing embodiments reside on host hardware (e.g., host processor 210), some simulated embodiments may use the host hardware where appropriate.

[0102] Simulator program 202 may be stored on a computer-readable storage medium (which may be a non-transitory medium) and provides a program interface (an instruction execution environment) to target code 200 (which may include an application, an operating system, and a hypervisor) that is the same as the interface of the hardware architecture being modeled by simulator program 202. Thus, program instructions of target code 200, which may include triggered instructions such as the triggered producer instructions and triggered consumer instructions described above, may be executed from within the instruction execution environment using simulator program 202, thereby enabling host computer 210, which does not actually have the hardware capabilities of device CT discussed above, to emulate these capabilities.

[0103] In this application, the term "configured to" is used to mean that elements of a device have a configuration that allows them to perform a defined operation. In this context, "configuration" refers to the arrangement or interconnection of hardware or software. For example, a device may have dedicated hardware that provides the defined operation, or a processor or other processing device may be programmed to perform the function. "Configured to" does not imply that the device elements need to be modified in any way to provide the defined operation.

[0104] Furthermore, the phrase "comprising at least one of" is used herein to mean including any one of the following options or any combination of the following options. For example, "at least one of A, B, and C" is intended to mean A or B or C or any combination of A, B, and C (e.g., A and B or A and C or B and C).

[0105] Although illustrative embodiments of the present invention have been described in detail herein with reference to the accompanying drawings, it will be understood that the invention is not limited to those precise embodiments, and that various changes and modifications can be made to the embodiments by those skilled in the art without departing from the scope of the invention as defined by the appended claims.

Claims

1. 1. An apparatus comprising: at least one triggered instruction processing element, a given triggered instruction processing element comprising execution circuitry for performing processing operations in response to a triggered instruction according to a triggered instruction architecture; a candidate instruction storage circuit for storing a plurality of triggered instructions, each triggered instruction specifying condition information indicative of at least one condition; an issue circuit for issuing the given triggered instruction for execution by the execution circuit in response to determining or predicting that the at least one condition indicated by the condition information specified by the given triggered instruction is satisfied; the execution circuitry responds to state update information specified by the given triggered instruction and causes machine state information to be updated in dependence on the state update information; when the given triggered instruction includes a triggered producer instruction, updating dependency state information to indicate that the execution circuitry may issue at least one corresponding triggered consumer instruction for execution in response to completion of execution of a processing operation performed in response to the triggered producer instruction; the issuing circuitry is configured to evaluate whether the at least one condition is determined or predicted to be satisfied when the given instruction includes a triggered consumer instruction, dependent on both the machine state information and the dependency state information.

2. the execution circuitry is permitted to update the machine state information prior to completion of execution of the processing operation performed in response to the triggered producer instruction; 10. The apparatus of claim 1.

3. a set of predicate registers, the set of predicate registers including one or more predicate registers for storing said machine state information; 3. The device according to claim 1 or 2.

4. the set of predicate registers comprises at least one predicate register for storing said dependency state information; the issue circuitry is configured to determine that the at least one condition indicated by the condition information of the given triggered instruction is satisfied when values ​​stored in at least a subset of predicate word registers match expected values ​​indicated by the condition information.

4. The apparatus of claim 3.

5. a dependency tag storage unit for storing the dependency state information; The issuing circuitry the values ​​stored in at least a subset of the predicate registers match expected values ​​indicated by the condition information; and configured to determine that the at least one condition indicated by the condition information of the given triggered instruction is satisfied when the dependency state information stored in the dependency tag storage circuit matches expected dependency state information indicated by the condition information.

4. The apparatus of claim 3.

6. when the given instruction includes the triggered producer instruction, issuing a dependency update signal to cause the execution circuitry to update the dependency information to indicate that the at least one corresponding triggered consumer instruction can be issued for execution in response to completing the execution of the processing operation performed in response to the triggered producer instruction; the apparatus includes a delay circuit, the delay circuit being responsive to the dependency state update signal to introduce a delay between issuance of the dependency state update signal and updating of the dependency state information; An apparatus according to any one of claims 1 to 5.

7. the delay circuit is responsive to the dependency state update signal to introduce the delay unless it is determined that the time between issuance of the triggered producer instruction and completion of the triggered producer instruction is greater than a predetermined threshold duration.

7. The apparatus of claim 6.

8. the predetermined threshold duration is based on a number of cycles required to issue one or more selected non-consumer instructions after issuing the triggered producer instruction; 8. The apparatus of claim 7.

9. the predetermined threshold duration is configurable by software; 9. Apparatus according to claim 7 or 8.

10. the execution circuitry is responsive to the state update information to issue a machine state update signal for causing the machine state information to be updated in dependence on the state update information; the apparatus further comprising a delay circuit responsive to the machine state update signal for introducing a delay between issuance of the dependency state update signal and updating of the dependency state information; An apparatus according to any one of claims 1 to 9.

11. the length of the delay is software configurable; An apparatus according to any one of claims 6 to 10.

12. the at least one corresponding triggered consumer instruction comprises a triggered instruction, execution of which is dependent on completion of execution of the processing operation performed in response to the triggered producer instruction; An apparatus according to any one of claims 1 to 11.

13. 1. A method comprising: performing processing operations in response to triggered instructions according to a triggered instruction architecture; storing a plurality of triggered instructions, each triggered instruction specifying condition information indicative of at least one condition; issuing a given triggered instruction in response to determining or predicting that the at least one condition indicated by the condition information specified by the given triggered instruction is satisfied; In response to state update information specified by said given triggered instruction, causing machine state information to be updated in dependence on said state update information; responsive to completion of execution of a processing operation performed in response to the given triggered instruction, when the given triggered instruction includes a triggered producer instruction, updating dependency state information to indicate that at least one corresponding triggered consumer instruction may be issued for execution; and evaluating whether the at least one condition is determined or predicted to be satisfied when the given instruction includes a triggered consumer instruction, depending on both the machine state information and the dependency state information.

14. A computer program comprising instructions which, when executed on a computer: processing program logic for performing processing operations in response to triggered instructions according to a triggered instruction architecture; candidate instruction store program logic for maintaining a candidate instruction store data structure for storing a plurality of triggered instructions, each triggered instruction specifying condition information indicative of at least one condition; issuing program logic for issuing the given triggered instruction for execution by the execution circuitry in response to determining or predicting that the at least one condition indicated by the condition information specified by the given triggered instruction is satisfied; the processing program logic, in response to state update information specified by the given triggered instruction, causes machine state information to be updated in dependence on the state update information; when the given triggered instruction includes a triggered producer instruction, causing the processing program logic to update dependency state information to indicate that, in response to completion of execution of a processing operation performed in response to the triggered producer instruction, at least one corresponding triggered consumer instruction may be issued for execution; 10. A computer program product, comprising: the issuing program logic configured to evaluate whether the at least one condition is determined or predicted to be satisfied when the given instruction includes a triggered consumer instruction, depending on both the machine state information and the dependency state information.

15. A computer-readable storage medium storing the computer program of claim 14.

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