Method for depositing conductive materials

Abstract

1. A method for processing a substrate, the method comprising: depositing a fill material over a substrate having a first recess and a second recess, wherein the fill material fills the first recess and the second recess; patterning the fill material to reopen the first recess while leaving the second recess filled with the fill material; filling the first recess with a conductive material to a first height; etching the fill material selectively to the conductive material to reopen the second recess; filling a remainder of the first recess and a remainder of the second recess with the conductive material; and performing an etch-back process to etch the conductive material so that the first recess and the second recess are filled with the conductive material to a second height.

Description

[Technical Field]

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS This application claims the benefit of priority and the filing date of U.S. Non-Provisional Patent Application No. 18 / 070,030, filed November 28, 2022, which is incorporated herein by reference in its entirety.

[0002] The present invention relates generally to methods of processing substrates and, in particular embodiments, to the deposition of conductive materials. [Background technology]

[0003] Typically, semiconductor devices used in electronic devices such as cell phones, digital cameras, and computers are fabricated by using photolithography and etching to sequentially deposit and pattern layers of dielectric, conductive, and semiconducting materials on a semiconductor substrate to form structures that function as circuit components (e.g., transistors, resistors, and capacitors) and interconnect elements (e.g., conductive lines, contacts, and vias). Driven by the demand for low-cost electronics, the semiconductor industry has reduced the cost of integrated circuits (ICs) by repeatedly shrinking the minimum feature size in semiconductor devices to a few nanometers through innovations in lithography (e.g., immersion lithography and multiple patterning), thereby increasing the packing density of components. Further increases in density and cost reductions are realized using three-dimensional (3D) structures (e.g., fin field effect transistors (FinFETs)) and, in some instances, by stacking electronic components such as memory storage elements (e.g., ferroelectric capacitors, magnetic tunnel junctions (MTJs), etc.) and precision passive components (e.g., thin film resistors (TFRs) and metal-insulator-metal (MIM) capacitors) in layers between successive interconnect levels. Summary of the Invention [Problem to be solved by the invention]

[0004] The diversity of materials used in IC fabrication, such as semiconductors, insulators (including SiO2, Si3N4, high-k gate dielectrics, and low-k dielectrics), magnetic and ferroelectric films, and metals for interconnects and electrodes, poses the challenge of continually developing processing techniques for these diverse materials. The scaling down to several nanometers exacerbates this challenge. Plasma processes are expected to deliver precise dimensions (e.g., linewidth, etch depth, and film thickness) in the nanometer range, along with precisely controlled features, such as conformality, anisotropy, selectivity, surface and line edge roughness, and edge profile, often at atomic-scale dimensions, uniformly across large-diameter (e.g., 300 mm) wafers. Furthermore, the introduction of unconventional materials (e.g., Co and Ru) at feature sizes below 20 nm may pose new challenges in developing plasma etch and deposition processes compatible with conventional Si IC fabrication.

[0005] Overcoming the hurdles in adapting plasma processing techniques for scaled semiconductor device manufacturing is a challenge that requires further innovation. [Means for solving the problem]

[0006] According to one embodiment of the present invention, a method for processing a substrate includes depositing a fill material over a substrate having a first recess and a second recess, wherein the fill material fills the first recess and the second recess; patterning the fill material to reopen the first recess while leaving the second recess filled with the fill material; filling the first recess with a conductive material to a first height; etching the fill material selectively with respect to the conductive material to reopen the second recess; filling a remainder of the first recess and the second recess with the conductive material; and performing an etch-back process to etch the conductive material so that the first recess and the second recess are filled with the conductive material to a second height.

[0007] According to one embodiment of the present invention, a method for processing a substrate includes depositing a fill material over a substrate having line recesses, wherein the fill material fills the line recesses, and patterning the fill material so that every other line of the line recesses is reopened while remaining portions of the line recesses remain filled with the fill material; depositing a conductive material over the substrate, wherein the conductive material fills the reopened line recesses to a first height; performing an etch-back process to etch the conductive material so that every other line of the line recesses is filled with the conductive material to a second height that is lower than the first height; etching the fill material to reopen the remaining portions of the line recesses; and filling all of the line recesses with the conductive material to a third height.

[0008] According to one embodiment of the present invention, a method for processing a substrate includes depositing a first fill material over a substrate having a first recess and a second recess, the first fill material filling the first recess and the second recess, patterning the first fill material such that the first recess is reopened while the second recess remains filled with the fill material, depositing a conductive material over the substrate, the conductive material filling the first recess to a first height, and patterning the conductive material such that the first recess is filled with the conductive material to a second height that is less than the first height. 1. A method comprising: performing a first etch-back process to etch; depositing a second fill material such that the first recess is filled with a conductive material and a second fill material; selectively etching the first fill material relative to the conductive material and the second fill material to reopen the second recess; redepositing a conductive material over the substrate, the conductive material filling the second recess; and performing a second etch-back process to etch the conductive material such that the first recess and the second recess are filled with the conductive material to a second height.

[0009] For a more complete understanding of the present invention, and the advantages thereof, reference is now made to the following descriptions which should be read in conjunction with the accompanying drawings. [Brief explanation of the drawings]

[0010] [Figure 1A] 1A-1C illustrate cross-sectional views of an exemplary substrate during an exemplary process of semiconductor fabrication including metal deposition at various stages, according to various embodiments, with FIG. 1A showing an incoming substrate with a recess that is filled with metal. [Figure 1B] 1A-1C illustrate cross-sectional views of an exemplary substrate during an exemplary process of semiconductor fabrication including metal deposition at various stages, according to various embodiments, with FIG. 1B showing the substrate after depositing a fill material. [Figure 1C] 1A-1C show cross-sectional views of an exemplary substrate during an exemplary process of semiconductor fabrication including metal deposition at various stages, according to various embodiments, with FIG. 1C showing the substrate after forming a layer stack for lithography. [Figure 1D] 1A-1D show cross-sectional views of an exemplary substrate during an exemplary process of semiconductor fabrication including metal deposition at various stages, according to various embodiments, with FIG. 1D showing the substrate after lithography processing. [Figure 1E] 1A-1E show cross-sectional views of an exemplary substrate during an exemplary process of semiconductor fabrication including metal deposition at various stages, according to various embodiments, with FIG. 1E showing the substrate after patterning a fill material. [Figure 1F] 1A-1F illustrate cross-sectional views of an exemplary substrate during an exemplary process of semiconductor fabrication including metal deposition at various stages according to various embodiments, with FIG. 1F illustrating the substrate after forming a first liner layer. [Figure 1G] 1A-1G show cross-sectional views of an exemplary substrate during an exemplary process of semiconductor fabrication including metal deposition at various stages according to various embodiments, with FIG. 1G showing the substrate after a first metal deposition. [Figure 1H] 1A-1H illustrate cross-sectional views of an exemplary substrate during an exemplary process of semiconductor fabrication including metal deposition at various stages according to various embodiments, with FIG. 1H showing the substrate after a first etch-back. [Figure 1I]1A-1I illustrate cross-sectional views of an exemplary substrate during an exemplary process of semiconductor fabrication including metal deposition at various stages according to various embodiments, with FIG. 1I illustrating the substrate after removal of fill material. [Figure 1J] 1A-1J show cross-sectional views of an exemplary substrate during an exemplary process of semiconductor fabrication including metal deposition at various stages according to various embodiments, with FIG. 1J showing the substrate after forming a second liner layer. [Figure 1K] 1A-1K show cross-sectional views of an exemplary substrate during an exemplary process of semiconductor fabrication including metal deposition at various stages according to various embodiments, with FIG. 1K showing the substrate after a second metal deposition. [Figure 1L] 1A-1L show cross-sectional views of an exemplary substrate during an exemplary process of semiconductor fabrication including metal deposition at various stages according to various embodiments, with FIG. 1L showing the substrate after a second etch-back. [Figure 2A] 2A and 2B show scanning electron microscopy (SEM) cross-sectional images of an exemplary Si substrate during an exemplary process of semiconductor fabrication including ruthenium (Ru) deposition, according to various embodiments, with FIG. 2A showing an incoming Si substrate with line recesses that are filled with Ru. [Figure 2B] 2A and 2B show scanning electron microscopy (SEM) cross-sectional images of an exemplary Si substrate during an exemplary process of semiconductor fabrication including ruthenium (Ru) deposition, according to various embodiments; FIG. 2B shows the Si substrate after amorphous silicon (a-Si) deposition. [Figure 2C] 2A-2C show scanning electron microscopy (SEM) cross-sectional images of an exemplary Si substrate during an exemplary process of semiconductor fabrication including ruthenium (Ru) deposition, according to various embodiments, with FIG. 2C showing the Si substrate after a-Si patterning. [Figure 2D] 2A-2D show cross-sectional scanning electron microscopy (SEM) images of an exemplary Si substrate during an exemplary process of semiconductor fabrication including ruthenium (Ru) deposition, according to various embodiments, with FIG. 2D showing the Si substrate after forming a tantalum nitride (TaN) liner layer and depositing Ru. [Figure 2E]2A-2C show cross-sectional scanning electron microscopy (SEM) images of an exemplary Si substrate during an exemplary process of semiconductor fabrication including ruthenium (Ru) deposition, according to various embodiments, with FIG. 2E showing the Si substrate after etch-back. [Figure 3A] 3A shows cross-sectional views of an exemplary substrate during another exemplary process of semiconductor fabrication including metal deposition with two fill materials at various stages according to an alternative embodiment, with FIG. 3A showing the substrate after first metal deposition followed by capping with a second fill material. [Figure 3B] 3A and 3B show cross-sectional views of an exemplary substrate during another exemplary process of semiconductor fabrication including metal deposition with two fill materials at various stages according to an alternative embodiment, with FIG. 3B showing the substrate after removal of the first fill material, second metal deposition, and second etchback. [Figure 4] 1 illustrates an exemplary substrate with wiring bending problems as a result of metal deposition in the absence of filler material. [Figure 5A] 5A-5C illustrate process flow diagrams for methods of metal deposition according to various embodiments, with FIG. 5A illustrating a process flow embodiment. [Figure 5B] 5A-5C illustrate process flow diagrams for methods of metal deposition according to various embodiments, with FIG. 5B illustrating an alternative process flow embodiment. [Figure 5C] 5A-5C illustrate process flow diagrams for methods of metal deposition according to various embodiments, with FIG. 5C illustrating another alternative process flow embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0011] This application relates to the fabrication of semiconductor devices, e.g., integrated circuits including semiconductor devices, and more specifically, to the fabrication of high-capacity three-dimensional (3D) memory devices such as 3D-NAND (or vertical NAND), 3D-NOR, or dynamic random access memory (DRAM) devices. The generation of ICs, commonly referred to as the 10-nm node, uses pitches of less than 40 nm for densely packed metal wiring at lower interconnect levels and approximately 50 nm for contacts to transistors. At these and smaller dimensions, the interconnect-RC delay of traditional copper (Cu) wiring and tungsten (W) contacts can limit the speed of digital circuits. New materials are being introduced below the 10-nm node to replace dense Cu wiring and W contacts. Ruthenium (Ru) metal is a leading candidate for replacing copper and tungsten in these and other applications. For example, Ru can be used for buried word lines (bWL) in DRAM devices. However, applying Ru to fine-pitch line / space (L / S) structures is currently difficult because the high stress of Ru at such small scales (e.g., line widths < 20 nm) often causes wiring bending problems. Therefore, it is desirable to develop an effective method for depositing metal (e.g., Ru) within fine-pitch L / S structures without wiring bending problems.

[0012] Embodiments of the present application disclose a method for multi-step metal deposition using a fill material. The method includes selectively pre-filling some of the recesses on a substrate with a fill material for structural reinforcement. The fill material provides structural support during a first metal deposition, thereby preventing wiring flexing. After the first metal deposition, the fill material may be removed to reopen the pre-filled portions of the recesses, which can then be filled with metal by a second metal deposition. Various embodiments of the method further include a lithography process that provides a pattern of fill material for the selective pre-filling of the recesses. The method may advantageously enable the application of high-stress metals, such as Ru, to fine-pitch L / S structures (e.g., bWL) by preventing wiring flexing during deposition. The method may also be applied to use Ru in back-end-of-line (BEOL) processes. While the present disclosure primarily describes the method as a metal deposition process, it should be noted that the method is not limited to pure metals and may be applied to any conductive materials and mixtures thereof that may be useful in various semiconductor device applications.

[0013] Metal deposition steps for filling recesses without line bending according to various embodiments are described below with reference to FIGS. 1A-1L, 2A-2E, and 3A-3B. Representative SEM images (FIGS. 2A-2E) are described along with the corresponding structures in FIGS. 1A-1H. The issue of line bending in the case of metal deposition without fill material is described with reference to FIG. 4. Then, the process flow of several embodiments of metal deposition is described with reference to FIGS. 5A-5C. All figures in this disclosure, including aspect ratios of features, are not to scale and are for illustrative purposes only.

[0014] FIG. 1A shows a cross-sectional view of an incoming substrate 100 with a recess 105 that will be filled with metal.

[0015] FIG. 2A shows a scanning electron microscopy (SEM) cross-sectional image of an incoming Si substrate with line recesses that are filled with ruthenium (Ru).

[0016] In one or more embodiments, the substrate 100 may be a silicon wafer or a silicon-on-insulator (SOI) wafer. In certain embodiments, the substrate may include silicon germanium wafers, silicon carbide wafers, gallium arsenide wafers, gallium nitride wafers, and other compound semiconductors. In other embodiments, the substrate includes heterogeneous layers, such as layers of silicon germanium on silicon, gallium nitride on silicon, silicon carbon on silicon, and silicon on silicon or SOI substrates.

[0017] In various embodiments, substrate 100 may be part of or include a semiconductor device and may have undergone several steps of processing, such as following conventional processing. For example, a semiconductor structure may include substrate 100 in which various device regions have been formed. At this stage, substrate 100 may include isolation regions, such as shallow trench isolation (STI) regions, and other regions formed therein.

[0018] 1A, substrate 100 may be patterned to have recesses 105. In various embodiments, recesses 105 may comprise a series of line recesses as part of a line / space (L / S) structure useful for fabricating semiconductor devices such as logic and DRAM devices. In particular embodiments, the surface of substrate 100 may be covered by oxide layer 110, and substrate 100 may include a hard mask 120 that is used to form recesses 105. In particular embodiments, oxide layer 110 may include silicon oxide, and hard mask 120 may include silicon nitride.

[0019] In various embodiments, the recesses 105 may comprise a series of parallel line recesses (i.e., a line / space (L / S) structure) separating the lines. In certain embodiments, the recesses 105 may comprise thin lines and / or L / S structures having a high aspect ratio (HAR, height-to-width ratio), in which case the methods of the present disclosure may be particularly useful. One of the recesses 105 may have a height of 20 nm to 300 nm in one embodiment, and 100 nm to 200 nm in another embodiment. The width of one of the recesses 105 may be 5 nm to 50 nm in one embodiment, and 10 nm to 30 nm in another embodiment. The aspect ratio of one of the recesses 105 may be 4:1 to 20:1. In one example shown in the SEM image of FIG. 2A, the substrate may be a Si substrate, and the recesses may have a pitch size of about 50 nm and a height of about 180 nm. L / S structures with fine lines and HAR tend to experience wiring bending and other problems of pattern distortion / collapse during metal deposition, especially when using metals with high stress, such as Ru. These L / S structure features tend to be too fragile to withstand the high metal stresses imposed during deposition without some structural support. The methods described in this disclosure can advantageously strengthen the L / S structure by selectively pre-filling some of the recesses 105 prior to metal deposition, as further described below with reference to FIGS. 1B-1L.

[0020] In certain embodiments, the L / S structures defined by the recesses 105 may include lines having different widths and / or heights. In other embodiments, the features defined by the recesses 105 may not be limited to parallel lines and spaces. Although not specifically shown, the recesses 105 filled by the present method may have any structure that may benefit from structural reinforcement during metal deposition.

[0021] FIG. 1B shows a cross-sectional view of the substrate 100 after depositing a first fill material 130 .

[0022] FIG. 2B shows an SEM cross-sectional image of the substrate after amorphous silicon (a-Si) deposition.

[0023] In various embodiments, selective pre-filling can be performed by blanket deposition of a first fill material 130 ( FIG. 1B ), followed by patterning of the first fill material 130 to reopen some of the pre-filled recesses ( FIGS. 1C-1E ). In FIG. 1B , the first fill material 130 can be deposited using a suitable technique, such as vapor deposition, including chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), and other plasma processes, such as plasma-enhanced CVD (PECVD), as well as other processes. As shown in FIG. 1B , the first fill material 130 can overfill and cover the entire recess 105. In various embodiments, the first fill material 130 can include a dielectric material, such as amorphous silicon (a-Si). In certain embodiments, the first fill material 130 can include spin-on carbon, spin-on glass, or silicon oxide. In one embodiment, silicon oxide can be prepared by plasma-enhanced CVD or flowable CVD using tetraethyl orthosilicate (TEOS) as a precursor. The material used for first fill material 130 can be selected for its mechanical strength and chemical stability in the subsequent metal etch-back step. In one embodiment, shown in the SEM image of FIG. 2B, the recess in the Si substrate shown in FIG. 2A can be completely filled with a-Si.

[0024] FIG. 1C shows a cross-sectional view of substrate 100 after forming a layer stack for lithography.

[0025] Next, selected portions of the pre-filled recesses may be reopened. In various embodiments, a lithography process may be used to enable this selective reopening of the pre-filled recesses. First, the top surface of the first fill material 130 may be planarized, for example, by chemical mechanical planarization (CMP). On the planarized surface of the first fill material 130, a layer stack 140 may be formed for a lithography process. In various embodiments, the layer stack may include, from bottom to top as shown in FIG. 1C , a hard mask layer 142, an organic dielectric layer (ODL) 144, a silicon-containing antireflective coating (SiARC) layer 146, and a photoresist layer 148. In certain embodiments, the hard mask layer 142 may include silicon nitride, silicon carbide (SiCN), or other suitable organic materials, such as silicon oxycarbide (SiOC), silicon oxynitride, silicon carbide, titanium nitride, or a spin-on carbon hard mask (SOH) material. In various embodiments, the ODL 144 may include spin-on carbon or other carbon-based materials. The illustrated structure of layer stack 140 in FIG. 1C is merely an example and may have different layer structures with different materials.

[0026] FIG. 1D shows a cross-sectional view of the substrate 100 after the lithographic process.

[0027] Lithographic exposure of photoresist layer 148 with a patterned photomask creates a pattern in photoresist layer 148, and a development step results in patterned photoresist layer 149, as shown in FIG. 1D. In various embodiments, the lithographic process can be performed using any suitable technique with sufficient resolution for patterning, such as deep ultraviolet (DUV) lithography (e.g., dry ArF lithography and immersion ArF lithography at 193 nm) or extreme ultraviolet (EUV) lithography at about 13.5 nm. As further described below in FIG. 1E, the photoresist patterning should be designed to define areas for reopening of pre-filled recesses. In certain embodiments, as shown in FIG. 1D, every other line recess in a series of line recesses is selected to be reopened first, while the remaining portions of the line recesses remain filled with first fill material 130 during the initial metal deposition for structural reinforcement.

[0028] FIG. 1E shows a cross-sectional view of the substrate 100 after the first fill material 130 has been patterned.

[0029] FIG. 2C shows an SEM cross-sectional image of the Si substrate after patterning the a-Si.

[0030] In FIG. 1E, the pattern of the patterned photoresist layer 149 defined by the lithography process (FIG. 1D) can be transferred to the first fill material 130 by one or more pattern-transfer etching processes. In various embodiments, one or more of the pattern-transfer etching processes can be performed using a plasma etching process, a reactive ion etching (RIE) process, and / or other etching process, or a combination of etching processes, to form the selectively reopened recesses 106. As a result, the first fill material 130 after the pattern-transfer etching fills only the selected recesses. As shown in FIG. 1E, in various embodiments, the selectively reopened recesses 106 can include every other recess of the recess 105 in FIG. 1A. In one embodiment, shown in the SEM image of FIG. 2C, every other line recess in the a-Si-filled Si substrate shown in FIG. 2B can be reopened.

[0031] In various embodiments, this step of patterning the first fill material 130 may include a first pattern-transfer etch to pattern the hard mask layer 142 (hard mask release), a second pattern-transfer etch to pattern the first fill material 130, and subsequent hard mask removal. In particular embodiments, hard mask removal may be performed using hot phosphoric acid in a wet process that selectively etches nitride. Other remaining layers and residues from the lithography process may also be removed by dry and / or wet processes before subsequent processes.

[0032] In FIGS. 1D-1E, every other recess is selected to be reopened before the first metal deposition. However, in alternative embodiments, any configuration for selective filling or reopening of recesses can be applied. For example, only one out of every three recesses may be reopened. The pattern for reopening can be selected taking into account the critical dimension (CD) of the feature to be fabricated and the resulting structural strength. For very delicate structures, fewer recesses may be selected to be reopened. By introducing a lithography step, the method advantageously enables any pattern for selective reopening of pre-filled recesses. Filling some of the recesses in the substrate 100 with the first fill material 130 can improve the mechanical strength of the features in the substrate 100, thereby enabling a subsequent metal deposition step with reduced risk of wiring buckling.

[0033] FIG. 1F shows a cross-sectional view of the substrate 100 after forming the first liner layer 150.

[0034] In various embodiments, prior to metal deposition, the first liner layer 150 can be formed as a thin film that conformally covers the exposed surfaces. Deposition of the first liner layer can be performed using vapor deposition, such as atomic layer deposition (ALD) techniques. In certain embodiments, the thickness of the first liner layer 150 can be less than 1.5 nm and greater than or equal to 1 nm, and in other embodiments, less than 5 nm and greater than or equal to 0.5 nm. In various embodiments, the first liner layer 150 can include a titanium (Ti)-based or tantalum (Ta)-based material, such as titanium nitride or tantalum nitride. In other embodiments, Ru, Co, or silicon nitride (SiN)-based materials can be used.

[0035] FIG. 1G shows a cross-sectional view of the substrate 100 after the first metal deposition.

[0036] FIG. 2D shows an SEM cross-sectional image of the Si substrate after forming a tantalum nitride (TaN) liner layer and depositing Ru.

[0037] In FIG. 1G, metal 160 is deposited, for example, using chemical vapor deposition (CVD), ALD, or magnetron sputtering, to completely fill the selectively reopened recess 106. In various embodiments, metal 160 can be deposited to overfill the selectively reopened recess 106, such that only metal 160 is exposed at the top surface. As shown in FIG. 1G, the ratio of the thickness of metal 160 filling the recess feature to the thickness of metal 160 above the recess feature can be greater than 1. This ratio can be from about 5:1 to about 20:1, depending on the width and aspect ratio of the recess feature. In various embodiments, metal 160 comprises a high-stress metal such as ruthenium (Ru). In another embodiment, metal 160 can comprise osmium (Os). In further alternative embodiments, metal 160 can comprise any conductive material or mixture thereof that can be useful in various semiconductor device applications. In one embodiment, shown in the SEM image of Figure 2D, the remaining line recesses in the Si substrate of Figure 2C can be completely filled with Ru, with a thin TaN liner layer underneath the Ru. Additionally, in yet another embodiment, the metal deposition can be performed as a series of deposition processes to form a conductive layer stack of two or more materials.

[0038] In various embodiments, the first fill material 130 advantageously provides structural support during the first metal deposition, thereby preventing any line bending or other undesired deformation of features of the substrate 100. This structural support enabled by the present method can be particularly beneficial when depositing highly stressed metals such as Ru.

[0039] In one or more embodiments, after the first metal deposition, the top surface of metal 160 may be planarized using, for example, chemical mechanical planarization (CMP). In other embodiments, the method may advantageously avoid the planarization process and proceed directly to the first etchback described below. Because CMP processes generally require significant consumable materials, such as pads, slurries, or cleaning chemicals, these embodiments that do not include CMP may be advantageous in terms of process cost and efficiency.

[0040] FIG. 1H shows a cross-sectional view of the substrate 100 after the first etch-back.

[0041] FIG. 2E shows an SEM cross-sectional image of the Si substrate after etch-back.

[0042] 1H, the first etch-back may be performed using a plasma etching process, a reactive ion etching (RIE) process, and / or other etching process, or a combination of etching processes. The metal 160 may be etched back to fill only a portion of the recess 106, with the remaining portion of the metal 160 selectively reopened. Thus, the first etch-back may be timed and terminated when a target etching amount is achieved. In one embodiment, the first etch-back may be selective to the fill material 130, as shown in FIG. 1H. In another embodiment, the first fill material 130 may also be partially or completely removed.

[0043] In various embodiments, the first etch-back process can be a plasma etching process using a mixture of argon (Ar), dioxygen (O), and dinitrogen (N) gases in various proportions as the plasma source gas. The direct plasma in contact with the substrate 100 can be generated and maintained within the plasma processing chamber using power from an external RF power source. Without wishing to be limited by any theory, it is believed that oxygen (e.g., oxygen radicals (O * )) can react with metal atoms (e.g., Ru) on portions of the surface exposed to the plasma to form volatile oxides. In certain embodiments, the first etch-back can be performed at room temperature. In other embodiments, the process temperature can be between 10°C and 300°C, and in one embodiment, between 10°C and 50°C. In one embodiment, shown in the SEM image of FIG. 2E, after the first etch-back, Ru partially fills every other recess in the Si substrate, while the other line recesses remain completely filled with a-Si.

[0044] FIG. 1I shows a cross-sectional view of the substrate 100 after the first fill material 130 has been removed.

[0045] 1I, removal of first fill material 130 may be performed selectively to metal 160 using a dry or wet etching process, resulting in reopened recess 107. For example, this removal step may be performed by a plasma etching process using a fluorine-containing gas as an etchant or a wet etching process using an alkaline solution such as aqueous KOH. The reopened recess 107 may then be filled with metal 160 in a subsequent step described below.

[0046] FIG. 1J shows a cross-sectional view of the substrate 100 after forming a second liner layer 170.

[0047] In various embodiments, the second liner layer 170 may comprise the same material as the first liner layer 150 and may similarly be formed, for example, using ALD, as a thin film that conformally covers the exposed surfaces. In certain embodiments, the second liner layer 170 may be less than 1.5 nm and greater than or equal to 1 nm, and in other embodiments, less than 5 nm and greater than or equal to 0.5 nm.

[0048] FIG. 1K shows a cross-sectional view of substrate 100 after the second metal deposition.

[0049] In various embodiments, the second metal deposition may use the same material as metal 160 shown in FIG. 1K. In alternative embodiments, a different conductive material may be used instead of or in addition to metal 160. Similar to the first metal deposition, the second metal deposition may be performed using, for example, CVD, ALD, or magnetron sputtering to completely fill the reopened recess 107 and the remaining portions of the selectively reopened recess 106 of FIG. 1J. In various embodiments, as described above for the first metal deposition, metal 160 may be deposited to overfill the reopened recess 107 and the selectively reopened recess 106 such that only metal 160 is exposed at the top surface.

[0050] FIG. 1L shows a cross-sectional view of the substrate after the second etch-back.

[0051] In various embodiments, the second etch-back may be performed in a manner similar to the first etch-back, for example, using a plasma etch process, an RIE process, and / or other etch process, or a combination of etch processes. Metal 160 may be etched back so that remaining portions of metal 160 partially fill each recess (i.e., both selectively reopened recess 106 and reopened recess 107). Therefore, the second etch-back may be timed and terminated when a target etch amount is achieved. The extent of filling with metal 160 may be adjusted by repeating the first and second etch-back processes. In various embodiments, as shown in FIG. 1L, a portion of each recess may need to be left open so that an insulating cap layer can be formed in a subsequent step to complete the fabrication of buried interconnects in logic devices and buried word lines (bWL) in DRAM devices. In certain embodiments, 10-90% (height) of the recess 105 in FIG. 1A may be filled with metal 160 at the end of the metal deposition process (e.g., FIG. 1L), while in other embodiments, 50-70% (height) of the recess 105 in FIG. 1A may be filled with metal 160.

[0052] In various embodiments, it may be desirable to fill each recess with metal 160 to the same height. To minimize variations in metal fill between recesses, the second metal deposition and second etch-back process may be repeated as a cyclic process (e.g., FIGS. 1K and 1L). In an alternative embodiment, the top surface of metal 160 may be planarized, for example by CMP, before the second etch-back.

[0053] Following metal deposition, the process may proceed further with various subsequent steps. For example, one or more conductive or insulating cap layers (e.g., silicon nitride) may be formed over and bury the metal 160.

[0054] 3A-3B show cross-sectional views of an exemplary substrate 100 during another exemplary process of semiconductor fabrication including metal deposition with two fill materials at various stages according to an alternative embodiment. Figure 3A shows the substrate 100 after a first metal deposition followed by capping with a second fill material 310.

[0055] The previous embodiments described above describe the use of a fill material for structural reinforcement. In alternative embodiments, two or more fill materials may be used to further improve structural stability during second metal deposition. In FIG. 3A, substrate 100 may have a structure similar to that shown in FIG. 1A and has been processed for deposition of first fill material 130, patterning of first fill material 130, and first metal deposition with metal 160 as described in previous embodiments (FIGS. 1B-1H). At this stage (e.g., FIG. 1H), after the first etchback, metal 160 only partially fills the selectively reopened recesses 106; therefore, the feature may still be susceptible to wiring bending during second metal deposition (e.g., FIG. 1K). Therefore, the remaining portions of the selectively reopened recesses 106 may be further filled with second fill material 310 to provide additional structural support. In various embodiments, second fill material 310 may comprise a different dielectric material than first fill material 130. In certain embodiments, the second fill material 310 may include an oxide (e.g., silicon oxide, aluminum oxide, or titanium oxide) or a nitride (e.g., silicon nitride or titanium nitride). In alternative embodiments, any suitable material may be used for the second fill material 310 (e.g., an oxynitride). Deposition of the second fill material may be performed using, for example, vapor deposition, including chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), and other plasma processes, such as plasma-enhanced CVD (PECVD), as well as other processes. In one example, trimethylaluminum (TMA) may be used in CVD to selectively form aluminum oxide in the recessed features. In one or more embodiments, deposition may be performed using a wet process.

[0056] FIG. 3B shows the substrate 100 after removal of the first fill material 130, a second metal deposition, and a second etchback.

[0057] Following the deposition of the second fill material 310, a series of steps (i.e., removal of the first fill material 130, formation of the second liner layer 170, second metal deposition, and second etch-back) may be performed as described in the previous embodiment with reference to FIGS. 1I-1L. The removal of the first fill material 130 and the second etch-back may be performed selectively with respect to the second fill material 310. In certain embodiments, the second fill material 310 may advantageously be used as an insulating layer and remain during subsequent steps following the second etch-back.

[0058] FIG. 4 shows an exemplary substrate 100 with a wiring bending problem as a result of metal deposition in the absence of a fill material.

[0059] Conventional methods of simply depositing metal 160 to fill recesses can result in structural deformations, such as wiring bends, as shown in FIG. 4. In FIG. 4, each line may bend in one direction or another due to stress exerted by the metal 160 during the deposition process. These problems can arise particularly when depositing a high-stress metal (e.g., Ru) to fill high-aspect-ratio (HAR) recesses. In some cases, another problem of forming voids 410 in the metal 160 can also occur due to non-uniformity in the deposition process. Various embodiments of methods for metal deposition described in this disclosure can advantageously overcome some of these deformation problems by providing structural support using one or more fill materials. The method generally follows the steps of pre-filling some of the recesses with a fill material, first metal deposition, removal of the fill material, and second metal deposition to complete the filling of each recess. An etch-back process can be performed after each metal deposition step to achieve a flat metal surface with the same height in each recess. This method may enable various applications of Ru as conductive wiring, such as for buried word lines (bWL) in DRAM devices.

[0060] 5A-5C show process flow diagrams for metal deposition methods according to various embodiments. These process flows can be followed using the figures described above (FIGS. 1A-1L and 3A-3B) and will not be repeated.

[0061] In FIG. 5A, process 50 begins with depositing a fill material over a substrate to fill a first recess and a second recess in the substrate (block 510, FIG. 1B). The fill material may then be patterned to reopen the first recess while leaving the second recess filled with the fill material (block 520, FIGS. 1C-1E). In certain embodiments, this patterning step (block 520) may include a lithography process. Optionally, in certain embodiments, a liner may be formed by vapor deposition (block 525, FIG. 1F). The first recess may then be filled with a conductive material to a first height (block 530, FIGS. 1G-1H). In certain embodiments, this step may include a first conductive material deposition to overfill the first recess (FIG. 1G), followed by a first etch-back process to the first height (FIG. 1H). After the first metal deposition and the first etch-back process, the fill material may be etched selectively to the conductive material to reopen the second recess (block 540, FIG. 1I). In certain embodiments, another optional liner may be formed by vapor deposition (block 545, FIG. 1J). A second conductive material deposition may then be performed to fill the remaining portions of the first and second recesses with conductive material (block 550, FIG. 1K). A second etch-back process may then be performed to etch the conductive material so that the first and second recesses are filled with conductive material to a second height (block 560, FIG. 1L).

[0062] In FIG. 5B, another process 52 begins by depositing a fill material on a substrate with line recesses to completely fill the line recesses with the fill material (block 512, FIG. 1B), followed by patterning the fill material to reopen every other line of the line recesses while leaving the remaining portions of the line recesses filled with the fill material (block 522, FIGS. 1C-1E). A conductive material may then be deposited on the substrate to fill the reopened line recesses to a first height (block 532, FIG. 1G), followed by an etch-back process to fill every other line of the line recesses with the conductive material to a second height that is lower than the first height (block 533, FIG. 1H). The fill material may then be etched to reopen the remaining portions of the line recesses (block 542, FIG. 1I), followed by filling all of the line recesses with the conductive material to a third height (block 552, FIGS. 1K-1L).

[0063] In FIG. 5C, yet another process 54 begins with depositing a first fill material on the substrate to fill the first recess and the second recess (block 514, FIG. 1B), followed by patterning the first fill material to reopen the first recess while leaving the second recess filled with the fill material (block 524, FIGS. 1C-1E). Next, a conductive material may be deposited on the substrate to fill the first recess to a first height (block 534, FIG. 1G). Thereafter, a first etch-back process may be performed to etch the conductive material so that the first recess is filled with the conductive material to a second height that is lower than the first height (block 535, FIG. 1H). Then, a second fill material may be deposited on the substrate to fill the first recess with the conductive material and the second fill material (block 536, FIG. 3A). The first fill material may then be etched selectively to the conductive material and the second fill material to reopen the second recess (block 544), and the conductive material may be redeposited on the substrate to fill the second recess. A second etch-back process may then be performed to etch the conductive material so that the first recess and the second recess are filled to a second height with the conductive material (block 555, FIG. 3B).

[0064] Illustrative embodiments of the present invention are summarized here, with other embodiments being apparent from the specification as a whole and from the claims filed herewith. [Example]

[0065] Example 1. 1. A method for processing a substrate, the method comprising: depositing a fill material over a substrate having a first recess and a second recess, wherein the fill material fills the first recess and the second recess; patterning the fill material to reopen the first recess while leaving the second recess filled with the fill material; filling the first recess with a conductive material to a first height; etching the fill material selectively to the conductive material to reopen the second recess; filling a remainder of the first recess and the second recess with the conductive material; and performing an etch-back process to etch the conductive material so that the first recess and the second recess are filled with the conductive material to a second height.

[0066] Example 2. The method of Example 1, wherein filling the first recess with a conductive material to a first height includes depositing a conductive material over the substrate, wherein the conductive material overfills the first recess to a height greater than the first height, and performing a first etch-back process to etch the conductive material such that the first recess is filled with the conductive material to the first height.

[0067] Example 3. 3. The method of example 1 or 2, wherein patterning the fill material comprises a lithographic process.

[0068] Example 4. The method of any one of Examples 1-3, wherein patterning the fill material includes planarizing a surface of the fill material; depositing a layer stack over the fill material, the layer stack including a hard mask and a photoresist; performing lithographic exposure to pattern the photoresist, the pattern in the photoresist corresponding to the locations of the first recess and the second recess; and transferring the pattern to the fill material.

[0069] Example 5. 5. The method of any one of Examples 1-4, further comprising forming a liner by vapor deposition before filling the first recess with the conductive material to the first height, and forming another liner by vapor deposition before filling the remainder of the first recess and the second recess with the conductive material.

[0070] Example 6. 6. The method of any one of Examples 1 to 5, further comprising repeating the steps of depositing a conductive material on the substrate and etching the conductive material to planarize a top surface of the conductive material.

[0071] Example 7. The method of any one of Examples 1 to 6, wherein the first height and the second height are essentially the same height.

[0072] Example 8. The method of any one of Examples 1 to 7, wherein the conductive material comprises ruthenium (Ru).

[0073] Example 9. The method of any one of Examples 1 to 8, wherein the fill material comprises amorphous silicon (a-Si).

[0074] Example 10. The method according to any one of Examples 1 to 9, wherein the second height is 20 nm to 300 nm, and the widths of the first recess and the second recess are 5 nm to 50 nm.

[0075] Example 11. 1. A method for processing a substrate, the method comprising: depositing a fill material over a substrate having line recesses, the fill material filling the line recesses; patterning the fill material so that every other line of the line recesses is reopened while remaining portions of the line recesses remain filled with the fill material; depositing a conductive material over the substrate, the conductive material filling the reopened line recesses to a first height; performing an etch-back process to etch the conductive material so that every other line of the line recesses is filled with the conductive material to a second height that is less than the first height; etching the fill material to reopen the remaining portions of the line recesses; and filling all of the line recesses with the conductive material to a third height.

[0076] Example 12. Example 12. The method of Example 11, wherein filling all of the line recesses with the conductive material to the third height includes redepositing a conductive material on the substrate, the conductive material filling every other line of the line recesses and the remaining portions of the line recesses, and performing another etch-back process to etch the conductive material so that all of the line recesses are filled with the conductive material to the third height.

[0077] Example 13. 13. The method of Example 11 or 12, further comprising repeating the steps of depositing a conductive material over the substrate and etching the conductive material to planarize a top surface of the conductive material.

[0078] Example 14. The method of any one of Examples 11 to 13, wherein the conductive material comprises ruthenium (Ru) and the fill material comprises amorphous silicon (a-Si).

[0079] Example 15. The method according to any one of Examples 11 to 14, wherein the line recess has a height of 20 nm to 300 nm and a width of 5 nm to 50 nm.

[0080] Example 16. 16. The method of any one of Examples 11 to 15, wherein the line recess has an aspect ratio (height to width) of 4:1 to 20:1.

[0081] Example 17. A method of processing a substrate includes depositing a first fill material over a substrate having a first recess and a second recess, the first fill material filling the first recess and the second recess, patterning the first fill material to reopen the first recess while the second recess remains filled with the fill material, depositing a conductive material over the substrate, the conductive material filling the first recess to a first height, and etching the conductive material so that the first recess is filled with the conductive material to a second height that is less than the first height. performing a first etch-back process to deposit a conductive material over the substrate, the conductive material filling the second recess; depositing a second fill material such that the first recess is filled with a conductive material and a second fill material; selectively etching the first fill material relative to the conductive material and the second fill material to reopen the second recess; redepositing a conductive material over the substrate, the conductive material filling the second recess; and performing a second etch-back process to etch the conductive material such that the first recess and the second recess are filled with the conductive material to a second height.

[0082] Example 18. 18. The method of example 17, wherein the first fill material comprises amorphous silicon (a-Si), the second fill material comprises silicon oxide, and the conductive material comprises ruthenium (Ru).

[0083] Example 19. 19. The method of Example 17 or 18, wherein patterning the first fill material includes planarizing a surface of the first fill material; depositing a layer stack over the first fill material, the layer stack including a hard mask and a photoresist; performing lithographic exposure to pattern the photoresist, the pattern in the photoresist corresponding to the locations of the first recess and the second recess; and transferring the pattern to the first fill material.

[0084] Example 20. The method of any one of Examples 17 to 19, wherein the depositing and redepositing of the conductive material is performed by chemical vapor deposition (CVD).

[0085] While the present invention has been described with reference to exemplary embodiments, this specification is not intended to be construed in a limiting sense. Various modifications and combinations of the exemplary embodiments, as well as other embodiments of the invention, will become apparent to those skilled in the art upon reading this specification. It is therefore intended that the appended claims cover any and all such modifications or embodiments.

Claims

1. 1. A method for processing a substrate, the method comprising: depositing a fill material over the substrate having a first recess and a second recess, the fill material filling the first recess and the second recess; patterning the fill material to reopen the first recess while leaving the second recess filled with the fill material; filling the first recess with a conductive material to a first height; selectively etching the fill material relative to the conductive material to reopen the second recess; filling the remaining portions of the first recess and the second recess with the conductive material; performing an etch-back process to etch the conductive material such that the first recess and the second recess are filled with the conductive material to a second height; A method comprising:

2. filling the first recess with the conductive material to the first height; depositing the conductive material over the substrate, the conductive material overfilling the first recess to a height greater than the first height; performing a first etch-back process to etch the conductive material such that the first recess is filled with the conductive material to the first height; The method of claim 1 , comprising:

3. The method of claim 1 , wherein patterning the fill material comprises a lithographic process.

4. patterning the fill material planarizing the surface of the fill material; depositing a layer stack over the fill material, the layer stack including a hard mask and a photoresist; performing a lithographic exposure to pattern the photoresist, the pattern in the photoresist corresponding to the locations of the first recess and the second recess; transferring the pattern to the fill material; The method of claim 3, comprising:

5. forming a liner by vapor deposition before filling the first recess with the conductive material to the first height; forming another liner by vapor deposition before filling the remaining portions of the first recess and the second recess with the conductive material; The method of claim 1 further comprising:

6. The method of claim 1 , further comprising repeating depositing the conductive material on the substrate and etching the conductive material to planarize a top surface of the conductive material.

7. The method of claim 1 , wherein the first height and the second height are essentially the same height.

8. The method of claim 1 , wherein the conductive material comprises ruthenium (Ru).

9. The method of claim 1 , wherein the fill material comprises amorphous silicon (a-Si).

10. 2. The method of claim 1, wherein the second height is between 20 nm and 300 nm, and the widths of the first recess and the second recess are between 5 nm and 50 nm.

11. 1. A method for processing a substrate, the method comprising: depositing a fill material over the substrate having a line recess, the fill material filling the line recess; patterning the fill material to reopen every other line of the line recesses while remaining portions of the line recesses remain filled with the fill material; depositing a conductive material over the substrate, the conductive material filling the reopened line recesses to a first height; performing an etch-back process to etch the conductive material such that every other line of the line recess is filled with the conductive material to a second height that is lower than the first height; etching the fill material to reopen the remaining portion of the line recess; filling all of the line recesses to a third height with the conductive material; A method comprising:

12. filling all of the line recesses with the conductive material to the third height; redepositing the conductive material on the substrate, the conductive material filling every other line of the line recess and the remaining portion of the line recess; performing another etch-back process to etch the conductive material so that all of the line recesses are filled with the conductive material to a third height; The method of claim 11 , comprising:

13. The method of claim 11 , further comprising repeating depositing the conductive material on the substrate and etching the conductive material to planarize a top surface of the conductive material.

14. The method of claim 11, wherein the conductive material comprises ruthenium (Ru) and the fill material comprises amorphous silicon (a-Si).

15. The method of claim 11, wherein the line recess has a height of 20 nm to 300 nm and a width of 5 nm to 50 nm.

16. The method of claim 11, wherein the line recess has an aspect ratio (height to width) of 4:1 to 20:

1.

17. 1. A method for processing a substrate, the method comprising: depositing a first fill material over the substrate having a first recess and a second recess, the first fill material filling the first recess and the second recess; patterning the first fill material to reopen the first recess while the second recess remains filled with the fill material; depositing a conductive material over the substrate, the conductive material filling the first recess to a first height; performing a first etch-back process to etch the conductive material such that the first recess is filled with the conductive material to a second height that is less than the first height; depositing the second fill material such that the first recess is filled with the conductive material and the second fill material; selectively etching the first fill material relative to the conductive material and the second fill material to reopen the second recess; redepositing the conductive material over the substrate, the conductive material filling the second recess; performing a second etch-back process to etch the conductive material such that the first recess and the second recess are filled with the conductive material to the second height; A method comprising:

18. 18. The method of claim 17, wherein the first fill material comprises amorphous silicon (a-Si), the second fill material comprises silicon oxide, and the conductive material comprises ruthenium (Ru).

19. patterning the first fill material; planarizing a surface of the first fill material; depositing a layer stack over the first fill material, the layer stack including a hard mask and a photoresist; performing a lithographic exposure to pattern the photoresist, the pattern in the photoresist corresponding to the locations of the first recess and the second recess; transferring the pattern to the first fill material; 18. The method of claim 17, comprising:

20. 20. The method of claim 17, wherein the depositing and redepositing of the conductive material is performed by chemical vapor deposition (CVD).

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