Enhanced Area Getter Architecture for Wafer-Level Vacuum Packaged Uncooled Focal Plane Arrays

Abstract

A method and system utilizing an enhanced area getter architecture for wafer-level vacuum-packaged uncooled focal plane array (FPA) assemblies is disclosed. The FPA assembly includes a device die having a first device surface, an infrared detector array disposed on the first device surface, infrared reference pixels disposed on the first device surface, and a window die bonded to the device die. The window die includes a recess, the first die surface overlying the infrared detector array, a second die surface overlying the infrared reference pixels, and a die wall surface connecting the first die surface and the second die surface. The die wall surface forms a perimeter of the recess, and a getter material is disposed on at least one of the die wall surface or the first die surface.

Description

[Technical Field]

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0001] This application claims priority to U.S. Provisional Patent Application No. 63 / 430,953, filed December 7, 2022, entitled "Enhanced Area Getter Architecture for Wafer-Level Vacuum Packaged Uncooled Focal Plane Arrays," the disclosure of which is incorporated herein by reference in its entirety for all purposes. [Background technology]

[0002]

[0002] As photodetector technology has advanced, new designs have become capable of achieving significantly improved resolution compared to past technologies. The resolution of a photodetector is determined, at least in part, by the number of pixels in the detector array. Typically, the more pixels there are in a detector array, the greater the level of detail that can be provided during image processing operations. Improvements in technology have made it possible to incorporate more pixels to improve resolution, while still producing pixels of much smaller size in the manufacturing process in order to maintain the overall form factor of the detector array.

[0003] Despite advances in detector arrays, there remains a need in the art for improved methods and systems related to detector arrays. Summary of the Invention

[0004] In accordance with various aspects of the present disclosure, embodiments of the present disclosure relate to methods and systems with enhanced area getter architectures for wafer-level vacuum packaged uncooled focal plane arrays.

[0005] According to one embodiment of the present invention, a focal plane array (FPA) assembly is provided. The FPA assembly includes a device die having a first device surface, an infrared detector array disposed on the first device surface, an infrared reference pixel array disposed on the first device surface, and a window die coupled to the device die. The window die includes a recess and has the first die surface overlying the infrared detector array, a second die surface overlying the infrared reference pixel array, and a die wall surface coupling the first die surface and the second die surface. The die wall surface forms a perimeter of the recess. The FPA assembly further includes a getter material disposed on at least one of the die wall surface or the first die surface.

[0006] In some embodiments, the recess extends within the window die along a first direction, and the first die surface overlaps the infrared detector array in a plane perpendicular to the first direction. In various embodiments, a getter material is disposed on a portion of the second die surface. In some embodiments, the second die surface overlaps the infrared reference pixel array in a plane perpendicular to the first direction. In various embodiments, a perimeter of the recess is defined by four die wall surfaces, and the getter material is disposed on the four die wall surfaces. In some embodiments, the FPA assembly further includes a seal ring disposed between the device die and the window die and surrounding the recess. In various embodiments, the window die, the device die, and the seal ring form a hermetic cavity overlapping the infrared detector array. In some embodiments, the seal ring includes solder ring metallization and solder joints. In various embodiments, the infrared reference pixel array is disposed outside the perimeter of the recess. In some embodiments, the getter material includes titanium. In some embodiments, the getter material is optically non-transparent. In various embodiments, the getter material forms a light-blocking structure for the infrared reference pixel array. In some embodiments, the pixel elements of the infrared reference pixel array are identical in configuration to the pixel elements of the infrared detector array. In various embodiments, the pixel elements of the infrared detector array comprise microbolometer detector pixel elements.

[0007] According to another embodiment of the present invention, there is provided a method for manufacturing a focal plane array (FPA) assembly. The method includes providing a handle wafer having a bonding side and a planar side opposite the bonding side, providing a silicon-on-insulator wafer having a first side and a second side opposite the first side, and providing a device wafer having a plurality of solder joints. The method also includes bonding the first side of the silicon-on-insulator wafer to the bonding side of the handle wafer, forming a plurality of seal-ring metallizations on the second side of the silicon-on-insulator wafer, and etching a recess in the second side of the silicon-on-insulator wafer to expose a portion of the bonding side of the handle wafer and forming a plurality of recess walls. The method further includes forming a first antireflective coating on a first portion of the planar side of the handle wafer, forming a second antireflective coating on a second portion of the bond side of the handle wafer, depositing a getter material on a third portion of the bond side of the handle wafer, on the plurality of recess walls, and on a fourth portion of the second side of the silicon-on-insulator wafer, and bonding a device wafer to the second side of the silicon-on-insulator wafer.

[0008] In some embodiments, etching recesses into the second side of the silicon-on-insulator wafer is performed by dry etching followed by wet etching. In various embodiments, the device wafer comprises an infrared detector pixel array and an infrared reference pixel. In some embodiments, the infrared reference pixel is identical in configuration to the pixel elements of the infrared detector pixel array. In some embodiments, depositing a getter material is performed using a shadow mask. In various embodiments, a first portion of the bond side of the handle wafer is disposed inside the plurality of recess walls. In some embodiments, a fourth portion of the second side of the silicon-on-insulator wafer is disposed outside the plurality of recess walls. In various embodiments, bonding the device wafer to the silicon-on-insulator wafer is performed by attaching a plurality of solder joints to a plurality of seal ring metallizations on the second surface of the silicon-on-insulator wafer. In some embodiments, depositing a getter material is performed after forming a first antireflective coating.

[0009] The present invention provides numerous advantages over the prior art. For example, embodiments of the present disclosure provide methods and systems for an enhanced area getter architecture suitable for use in wafer-level vacuum-packaged uncooled focal plane arrays (FPAs). To increase the surface area available for getter material application, embodiments enable the use of cavities formed in the window die within the FPA assembly, thereby increasing the getter adsorption capacity within the cavity. In some embodiments, getter material is formed on the surface of the window die where the recess is not etched, on the surface of the handle die in the recessed region, and on the sidewall surfaces of the recess. Increasing the sidewall surface area for getter deposition material increases the getter material area, improving the getter adsorption capacity within the cavity. In various embodiments, the recess can be made deeper or shallower by adjusting the thickness of the window die. The depth of the recess can be increased as far as the optical aperture allows, thereby increasing the available getter area. Furthermore, embodiments of the present invention enable the use of an enhanced area getter architecture that acts as a blocking structure for optically blind reference pixels. These and other embodiments of the present disclosure, along with its many advantages and features, are described in further detail in the following text and in conjunction with the accompanying figures. [Brief explanation of the drawings]

[0010] Aspects of the present disclosure are described in more detail below with reference to the accompanying drawings, but are intended to be read in conjunction with both this summary, the detailed description, and the preferred and / or specific embodiments specifically discussed or disclosed. However, various aspects may be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided for illustrative purposes only, so that this disclosure will be thorough and complete, and will fully convey its full scope to those skilled in the art. [Figure 1A]1 illustrates a wafer-level vacuum packaging process for an uncooled bolometer-based focal plane array according to an embodiment of the present disclosure. [Figure 1B] 1 illustrates a wafer-level vacuum packaging process for an uncooled bolometer-based focal plane array according to an embodiment of the present disclosure. [Figure 1C] 1 illustrates a wafer-level vacuum packaging process for an uncooled bolometer-based focal plane array according to an embodiment of the present disclosure. [Figure 2] FIG. 1 is a cross-sectional view of a focal plane array assembly according to an embodiment of the present disclosure. [Figure 3A] FIG. 1 illustrates a plan view of a device die including an infrared detector array and an infrared reference pixel array according to an embodiment of the present disclosure. [Figure 3B] 1 illustrates a plan view of a window die according to an embodiment of the present disclosure. [Figure 3C] FIG. 4 shows a plan view of the bonded device die and window die of FIGS. 3A and 3B according to one embodiment of the present disclosure. [Figure 4A] 3 shows a top view of a shadow mask used to deposit getter material onto the focal plane array assembly of FIG. 2 in accordance with one embodiment of the present invention. [Figure 4B] 3 shows a top view of a shadow mask used to deposit getter material onto the focal plane array assembly of FIG. 2 in accordance with one embodiment of the present invention. [Figure 5A] 1A-1D are cross-sectional views illustrating a method for manufacturing a focal plane array assembly according to one embodiment of the present invention. [Figure 5B] 1A-1D are cross-sectional views illustrating a method for manufacturing a focal plane array assembly according to one embodiment of the present invention. [Figure 5C] 1A-1D are cross-sectional views illustrating a method for manufacturing a focal plane array assembly according to one embodiment of the present invention. [Figure 5D] 1A-1D are cross-sectional views illustrating a method for manufacturing a focal plane array assembly according to one embodiment of the present invention. [Figure 5E] 1A-1D are cross-sectional views illustrating a method for manufacturing a focal plane array assembly according to one embodiment of the present invention. [Figure 5F] 1A-1D are cross-sectional views illustrating a method for manufacturing a focal plane array assembly according to one embodiment of the present invention. [Figure 5G] 1A-1D are cross-sectional views illustrating a method for manufacturing a focal plane array assembly according to one embodiment of the present invention. [Figure 6] 1 shows a simplified flowchart illustrating a method for manufacturing a focal plane array assembly according to one embodiment of the present invention. DETAILED DESCRIPTION OF THE INVENTION

[0011]

[0019] The described embodiments relate generally to focal plane array (FPA) devices. More specifically, embodiments of the present disclosure provide methods and systems that utilize an enhanced area getter architecture for wafer-level vacuum packaged uncooled FPA structures.

[0012]

[0020] 1A-1C illustrate a wafer-level vacuum packaged (WLVP) process for uncooled bolometer-based focal plane arrays (FPAs) according to an embodiment of the present disclosure. In the illustrated embodiment, a solder ring is placed around each die on the FPA wafer, and a corresponding seal ring is placed on the corresponding window wafer. The FPA wafer and window wafer can be aligned and bonded in a vacuum environment. After wafer bonding, slots are cut in the window wafer to provide access to the probe pads on the FPA wafer. This enables radiometric testing of the vacuum-packaged FPA at the wafer scale after bonding. Wafer-level vacuum packaging can provide a relatively small, lightweight, and low-cooling solution for packaging uncooled FPAs.

[0013]

[0021] Modern bolometer-based uncooled infrared (IR) imaging FPAs can thermally isolate bolometer pixels from the environment to maximize the temperature change of the bolometer pixel caused by the infrared scene flux incident on the pixel. A temperature-dependent resistive transducer can detect temperature changes caused by the scene through changes in resistance. Temperature-dependent resistive transducers can be made from, but are not limited to, vanadium oxide (VOx) or amorphous silicon (a-Si). The array of bolometer pixels is addressed by a readout integrated circuit (ROIC) chip, enabling the bolometer-based uncooled infrared imaging FPA to image the scene. Thermal isolation of the bolometer pixels can be achieved by using relatively long, low-thermal-conductivity legs that electrically connect the bolometer transducer to the underlying ROIC. To achieve relatively high sensitivity, the array of bolometer pixels can be vacuum-packaged to reduce or eliminate heat conduction by gas molecules within the package. A package vacuum of less than 10 mTorr is maintained to reduce or eliminate the effects of gas heat conduction within the package.

[0014]

[0022] To maintain a package vacuum of less than 10 mTorr in wafer-level vacuum packaging, an uncooled FPA getter material may be deposited on the inner surface of the window wafer within the vacuum package area. However, the area of ​​the silicon window wafer open to the scene opening must be transparent to incident scene radiation, so the area of ​​the inner surface available for getter deposition may be limited. In some embodiments of the present disclosure, an enhanced getter region architecture is provided. The enhanced getter region architecture utilizes the presence of a cavity etched within the window to enlarge the getter area, thereby increasing the getter adsorption capacity.

[0015]

[0023] FIG. 2 is a cross-sectional view of a focal plane array (FPA) assembly according to one embodiment of the present disclosure. The FPA assembly 200 includes a window die 220 and a device die 208. The window die 220 can be bonded to the device die 208 by solder joints 215. The device die 208 can include an infrared detector pixel array 218 disposed on a first surface 207 of the device die 208 and an optically blind infrared pixel array 216 disposed on the first surface 207. The device die 208 can further include solder ring metallization 214. Solder joints 215 can be formed on the solder ring metallization 214. The device die 208 can include bond pads 206 disposed on the first surface 207 of the device die 208. The bond pads 206 can be used to form connections to a semiconductor package. The bond pads 206 can be used to form connections to a semiconductor package that interfaces with external camera electronics that drive the operation of the FPA assembly 200 and collect electrical output from the pixels in the FPA used for infrared imaging of a scene.

[0016]

[0024] The window die 220 may include a handle die 224 and a silicon-on-insulator die 226. In some embodiments, the handle die 224 may have a thickness of, for example, 600 μm, and the silicon-on-insulator die 226 may have a thickness of, for example, 200 μm. The silicon-on-insulator die 226 may include a monocrystalline silicon layer 225 disposed on a buried oxide layer 222. In some embodiments, the buried oxide layer 222 may have a thickness of, for example, 1 to 2 μm. The buried oxide layer 222 may be bonded to the bonding side of the handle die 224. The window die 220 may include a recess 202. The recess 202 may be formed by etching the silicon-on-insulator die 226, which also removes the buried oxide layer 222. The silicon-on-insulator die 226 may include a solder ring metallization 212. A solder joint 215 may be connected to the solder ring metallization 212.

[0017]

[0025] A cavity 209 can be formed adjacent to the recess 202 and disposed between the device die 208 and the window die 220. The cavity 209 and recess 202 can be in a vacuum environment. Getter material can be formed on the mating side of the handle die 224 in region 210a, the die wall surface in region 210b, and the second side of the silicon-on-insulator die 226 in region 210c. In this manner, the die wall surface is used to form the getter material, thereby increasing or maximizing the surface area of ​​the getter material within the cavity 209 and recess 202. The recess 202 can be made deeper or shallower by adjusting the thickness of the silicon-on-insulator die 226. If optical aperture permits, the recess depth can be increased, thereby increasing the available getter area on the die wall surface in region 210b. In some embodiments, the perimeter of the recess 202, and therefore the size of the recess 202, is reduced to allow getter to be formed on all sides of the recess 202. In this manner, additional getter material can be disposed within the volume defined by recess 202 while reducing the volume of recess 202. Accordingly, embodiments of the present invention not only utilize getter material to form a light blocking structure over infrared pixel array 216, but also increase the amount of getter material and increase the amount of getter area in a vacuum environment by depositing getter material on both the die wall surface in region 210b and / or the mating side of handle die 224 in region 210a. It should be noted that embodiments of the present invention reduce the perimeter of recess 202, thereby reducing the volume associated with recess 202, which is typically undesirable because this reduction in volume reduces the volume-to-getter surface area ratio. However, because getter material is formed on the die wall surface in region 210b, the volume-to-getter surface area ratio can be maintained or increased despite the reduced volume. As will be apparent to those skilled in the art, the amount of getter material that can be formed on the mating side of handle die 224 in region 210a is limited by the optical aperture required to receive infrared light passing through handle die 224 and reaching infrared detector pixel array 218.Obviously, many variations, modifications, and alternatives will be apparent to those of ordinary skill in the art.

[0018]

[0026] As shown in FIG. 2 , the height of cavity 209, measured along the Z direction, can be much smaller than the height of recess 202, also measured along the Z direction. As described above, the height of recess 202 is related to the thickness (e.g., 200 μm) of silicon-on-insulator die 226, while the height of cavity 209 is related to the thickness (on the order of 10 μm) of solder ring metallization 212, solder joint 215, and solder ring metallization 214. Therefore, blocking light from reaching infrared pixel array 216 is facilitated by embodiments of the present invention because disposing getter material in region 210 c closer to infrared pixel array 216 provides more effective light blocking performance. At the same time, the height of recess 202 is independent of the height of cavity 209, allowing for a larger volume for a given surface area, which is desirable for achieving low-pressure (e.g., 10 mTorr) environments.

[0019]

[0027] A first anti-reflection (AR) coating 204 may be formed on the flat side of the handle die 224. A second AR coating 211 may be formed on the mating side of the handle die 224. The handle die 224 may be transparent to infrared light so that infrared light can pass through the handle die 224 and impinge on the infrared detector pixel array 218. The AR coating may be formed on both the flat side and the mating side of the handle die 224 in areas open to the collection aperture of the scene flux incident on the infrared detector pixel array 218. In some embodiments, the anti-reflection layer may be a deposited AR coating, such as a multilayer dielectric stack. In various embodiments, the AR layer may be formed from a high spatial frequency anti-reflection grating etched into the surface of the handle die.

[0020]

[0028] 3A shows a plan view of a device die including an infrared detector array and an infrared reference pixel array according to one embodiment of the present disclosure. Device die 302 includes bond pads 304, solder ring metallization 306, infrared pixel array 308, and infrared detector pixel array 310, also referred to as a blind reference bolometer pixel array. As will be appreciated by those skilled in the art, infrared pixel array 308, which includes detectors identical to those in infrared detector pixel array 310, is not exposed to incident radiation and provides a reference output (e.g., resistance value) that can be used during calibration of infrared detector pixel array 310 and during operation of infrared detector pixel array 310.

[0021]

[0029] 3B shows a top view of a window die according to one embodiment of the present disclosure. The window die 322 includes a solder ring metallization 324, a cavity edge 320, an AR layer region 328, and a deposited getter region 326.

[0022]

[0030] Figure 3C shows a plan view of the bonded device die and window die of Figures 3A and 3B, respectively, according to one embodiment of the present disclosure. Figure 3C is a view from the top side of the handle die. The bonded device die 302, window die 322, bond pads 304, solder ring metallization 306, solder ring metallization 324, infrared pixel array 308, infrared detector pixel array 310, AR layer region 328, and getter region 326 are shown. In Figure 3C, the solder ring metallization on the device die 302 is aligned with the corresponding solder ring metallization on the window die 322, thereby forming a hermetically sealed FPA package. Figure 3C also shows a plan view of the getter region 326, in which getter material is formed on the surface of the silicon-on-insulator die 226 where no recesses are formed, on the surface of the handle die in the recessed region, and on the surface of the die wall in the recess. 3C further illustrates the presence of an optically blind infrared pixel array 308, also referred to as reference pixels, formed on the device die 302. As previously discussed, the present disclosure discloses the use of an enhanced area getter architecture that acts as an optically upstream blocking structure for the optically blind infrared pixel array 216. Although not shown in FIG. 3C due to the plan view shown, getter material is formed on the die wall surfaces extending into the plane of the figure in region 210b of cavity edge 320.

[0023]

[0031] 4A-4B show plan views of a shadow mask used to deposit getter material on the focal plane array assembly of FIG. 2, in accordance with one embodiment of the present invention. FIG. 4A shows a plan view of a wafer shadow mask 402. FIG. 4B shows a detailed depiction of a die-level shadow mask having open areas 404 where no mask material, such as metal, is present, and shadowed areas 406 where mask material, such as metal, is present. While some embodiments of the present invention are described in connection with the use of a shadow mask during getter deposition, other getter deposition processes, including the use of photolithography and lift-off processes, are within the scope of the present invention. Many variations, modifications, and alternatives will be apparent to those skilled in the art.

[0024]

[0032] 5A-5G are cross-sectional views illustrating a method for fabricating a focal plane array assembly according to one embodiment of the present invention. As shown in FIG. 5A, a handle wafer 504 and a silicon-on-insulator wafer 506 can be bonded to form a window wafer 502. The handle wafer can include a planar side 503 and a bonding side 505. The silicon-on-insulator wafer 506 can include a first surface 507 and a second surface 509, and can have a buried oxide layer 508 adjacent to the first surface 507. As shown in FIG. 5A, the first surface 507 of the silicon-on-insulator wafer 506 is bonded to the bonding side 505 of the handle wafer 504.

[0025]

[0033] 5B shows the formation of a solder ring metallization 510 on the second side 509 of the silicon-on-insulator wafer 506. FIG. 5C shows the formation of a recess 512 in the silicon-on-insulator wafer 506. The recess is formed by etching the recess 512 into the second side 509 of the silicon-on-insulator wafer 506. In some embodiments, the etching process is performed by dry etching followed by wet etching to remove the buried oxide layer 508 to expose a portion of the bond side 505 of the handle wafer 504.

[0026]

[0034] 5D shows the configuration of an antireflection (AR) layer 514 on the planar side 503 of the handle wafer 504. Figure 5E shows the configuration of an AR layer 516 on the bonded side 505 of the handle wafer 504. The AR layer is formed in the open areas of both the planar side 503 and the bonded side 505 and serves as a collection aperture for the scene flux incident on the infrared detector pixel array 218 shown in Figure 2. In some embodiments, the AR layer can be a coating, while in other embodiments, the AR layer can be a high spatial frequency antireflection grating etched into the planar side 503 and / or bonded side 505 of the handle wafer 504.

[0027]

[0035] 5F shows getter regions formed on the bond side 505 of the handle die wafer 504 in region 518a, on the die wall surface in region 518b, and on the second side 509 of the silicon-on-insulator wafer 506 in region 518c. As previously described, the getters are formed by evaporating a getter material using a shadow mask. In some embodiments, the getter material includes, for example, but is not limited to, titanium, or alloys of aluminum, zirconium, titanium, vanadium, and / or iron.

[0028]

[0036] 5G illustrates the formation of an FPA assembly by bonding a device wafer 522 to a window wafer 502 and singulating the FPA assembly 500. The device wafer 522 can include an infrared detector pixel array 528, an optically blind infrared pixel array 526, and a solder ring metallization 534. Bonding of the device wafer 522 and the window wafer 502 can be achieved by forming solder joints 520.

[0029]

[0037]

[0023] Figure 6 shows a simplified flowchart illustrating a method of fabricating a focal plane array (FPA) assembly according to one embodiment of the present invention. As shown in Figure 6, the method of fabricating the FPA assembly includes providing a handle wafer (610) having a bonding side and a planar side opposite the bonding side. The method also includes providing a silicon-on-insulator wafer (612) having a first side and a second side opposite the second side. The method further includes bonding the first side of the silicon-on-insulator wafer to the bonding side of the handle wafer (614).

[0030]

[0038] The method also includes forming a plurality of seal ring metallizations on the second side of the silicon-on-insulator wafer (616). The method further includes etching a recess on the second side of the silicon-on-insulator wafer to expose a portion of the bond side of the handle wafer and form a plurality of recess walls (618). Furthermore, the method includes forming a first anti-reflective (AR) coating on a first portion of the planar side of the handle wafer (620). Moreover, the method includes forming a second AR coating on a second portion of the bond side of the handle wafer (622). In some embodiments, the second AR coating is optional, for example, in low-cost implementations where the cavity-side AR coating is eliminated, and in even lower-cost implementations where both the planar and cavity-side AR coatings are eliminated. Further, the method includes depositing (624) a getter material on a third portion of the bonding side of the handle wafer, on the plurality of recess walls, and on a fourth portion of the second side of the silicon-on-insulator wafer, and bonding (626) the device wafer to the silicon-on-insulator wafer, e.g., the second side of the silicon-on-insulator wafer.

[0031]

[0039] It should be understood that the specific steps illustrated in FIG. 6 provide a particular method for fabricating an FPA assembly according to one embodiment of the present invention. Other sequences of steps may be performed according to alternative embodiments. For example, alternative embodiments of the present disclosure may perform the steps outlined above in a different order. Furthermore, individual steps illustrated in FIG. 6 may include multiple sub-steps that may be performed in various sequences depending on the individual step. Furthermore, additional steps may be added or removed depending on the particular application. Many variations, modifications, and alternatives will be apparent to those skilled in the art.

[0032]

[0040] Various examples of the present disclosure are provided below. As used below, references to a series of examples shall be understood as referring to each example separately (e.g., "Examples 1-4" shall be understood as "Example 1, 2, 3, or 4").

[0033]

[0041] Example 1 is a focal plane array (FPA) assembly comprising: a device die having a first device surface, an infrared detector array disposed on the first device surface, and an infrared reference pixel array disposed on the first device surface; a window die bonded to the device die, the window die including a recess, the window die comprising: a first die surface positioned over the infrared detector array; a second die surface overlying the infrared reference pixel array; and a die wall surface bonding the first die surface and the second die surface, the die wall surface forming a perimeter of the recess; and a getter material disposed on at least one of the die wall surface or the first die surface.

[0034]

[0042] Example 2 is the FPA assembly of Example 1, wherein the recess extends into the window die along a first direction, and the first die surface overlaps the infrared detector array in a plane perpendicular to the first direction.

[0035]

[0043] Example 3 is the FPA assembly of Examples 1-2, where the getter material is disposed on a portion of the second die surface.

[0036]

[0044] Example 4 is the FPA assembly of Examples 1-3, wherein the second die surface overlaps the infrared reference pixel array in a plane perpendicular to the first direction.

[0037]

[0045] Example 5 is the FPA assembly of Example 1, where the perimeter of the recess is defined by four die wall surfaces and a getter material is disposed on the four die wall surfaces.

[0038]

[0046] Example 6 is the FPA assembly of Example 1, further comprising a seal ring disposed between the device die and the window die and surrounding the recess.

[0039]

[0047] Example 7 is the FPA assembly of Examples 1 and 6, in which the window die, device die, and seal ring form an airtight cavity that overlaps the infrared detector array.

[0040]

[0048] Example 8 is the FPA assembly of Examples 1 and 6, where the seal ring includes a solder ring metallization and a solder joint.

[0041]

[0049] Example 9 is the FPA assembly of Example 1, where the infrared reference pixel array is located outside the perimeter of the recess.

[0042]

[0050] Example 10 is the FPA assembly of Example 1, where the getter material comprises titanium.

[0043]

[0051] Example 11 is the FPA assembly of Example 1, where the getter material is non-light transmissive.

[0044]

[0052] Example 12 is the FPA assembly of Example 1, where the getter material forms a light blocking structure for the infrared reference pixel array.

[0045]

[0053] Example 13 is the FPA assembly of Example 1, in which the pixel elements of the infrared reference pixel array have the same configuration as the pixel elements of the infrared detector array.

[0046]

[0054] Example 14 is the FPA assembly of Example 1, wherein the pixel elements of the infrared detector array comprise microbolometer detector pixel elements.

[0047]

[0055] Example 15 is a method of manufacturing a focal plane array (FPA) assembly, the method comprising: providing a handle wafer having a bond side and a planar side opposite the bond side; providing a silicon-on-insulator wafer having a first side and a second side opposite the first side; providing a device wafer having a plurality of solder joints; bonding the first side of the silicon-on-insulator wafer to the bond side of the handle wafer; forming a plurality of seal-ring metallizations on the second side of the silicon-on-insulator wafer; etching a recess in the second side of the silicon-on-insulator wafer to expose a portion of the bond side of the handle wafer and forming a plurality of recess walls; forming a first antireflective coating on a first portion of the planar side of the handle wafer; forming a second antireflective coating on a second portion of the bond side of the handle wafer; depositing a getter material on a third portion of the bond side of the handle wafer, on the plurality of recess walls, and on a fourth portion of the second side of the silicon-on-insulator wafer; and bonding the device wafer to the second side of the silicon-on-insulator wafer.

[0048]

[0056] Example 16 is the method of manufacturing the FPA assembly of Example 15, in which the step of etching a recess on the second side of the silicon-on-insulator wafer is performed by dry etching followed by wet etching.

[0049]

[0057] Example 17 is a method of manufacturing the FPA assembly of Example 15, wherein the device wafer comprises an infrared detector pixel array and an infrared reference pixel.

[0050]

[0058] Example 18 is a method of manufacturing the FPA assembly of Examples 15 and 17, wherein the infrared reference pixel is identical in configuration to the pixel element of the infrared detector pixel array.

[0051]

[0059] Example 19 is a method of manufacturing the FPA assembly of Example 15, in which deposition of the getter material is performed using a shadow mask.

[0052]

[0060] Example 20 is a method of manufacturing the FPA assembly of Example 15, wherein the first portion of the bonding side of the handle wafer is disposed inside the plurality of recess walls.

[0053]

[0061] Example 21 is a method of manufacturing the FPA assembly of Example 15, wherein a fourth portion of the second side of the silicon-on-insulator wafer is disposed outside the plurality of recess walls.

[0054]

[0062] Example 22 is a method of manufacturing the FPA assembly of Example 15, wherein bonding the device wafer to the silicon-on-insulator wafer is performed by attaching a plurality of solder joints to a plurality of seal ring metallizations on the second surface of the silicon-on-insulator wafer.

[0055]

[0063] Example 23 is a method of manufacturing the FPA assembly of Example 15, in which deposition of a getter material is performed after forming the first antireflective coating.

[0056]

[0064] Those skilled in the art will appreciate that other modifications may be made to the disclosed apparatus and methods to implement various applications of the method and system for enhanced area getter architecture for wafer-level vacuum packaged uncooled focal plane arrays without departing from the scope of the present disclosure.

[0057]

[0065] The examples and embodiments described herein are for illustrative purposes only. Various modifications and variations will be apparent to those skilled in the art in light of these examples and embodiments, which are intended to be included within the spirit and scope of this application and the appended claims.

Claims

1. a device die having a first device surface, an infrared detector array disposed on the first device surface, and an infrared reference pixel array disposed on the first device surface; a window die bonded to the device die, the window die including a recess; a first die surface overlying the infrared detector array; a second die surface overlying the infrared reference pixel array; a window die comprising a die wall surface joining the first die surface and the second die surface, the die wall surface forming a perimeter of the recess; a getter material disposed on at least one of the die wall surface or the first die surface.

2. The FPA assembly of claim 1 , wherein the recess extends into the window die along a first direction, and the first die surface overlaps the infrared detector array in a plane perpendicular to the first direction.

3. The FPA assembly of claim 2 , wherein the getter material is disposed on a portion of the second die surface.

4. The FPA assembly of claim 3 , wherein the second die surface overlaps the infrared reference pixel array in the plane perpendicular to the first direction.

5. 2. The FPA assembly of claim 1, wherein the perimeter of the recess is defined by four die wall surfaces, and the getter material is disposed on the four die wall surfaces.

6. The FPA assembly of claim 1 , further comprising a seal ring disposed between the device die and the window die and surrounding the recess.

7. The FPA assembly of claim 6 , wherein the window die, the device die, and the seal ring form a sealed cavity that overlaps the infrared detector array.

8. The FPA assembly of claim 6 , wherein the seal ring comprises a solder ring metallization and a solder joint.

9. The FPA assembly of claim 1 , wherein the infrared reference pixel array is disposed outside the perimeter of the recess.

10. The FPA assembly of claim 1 , wherein the getter material comprises titanium.

11. The FPA assembly of claim 1 , wherein the getter material is non-light-transmitting.

12. The FPA assembly of claim 1 , wherein the getter material forms a light blocking structure for the infrared reference pixel array.

13. The FPA assembly of claim 1 , wherein pixel elements of the infrared reference pixel array are of the same configuration as pixel elements of the infrared detector array.

14. The FPA assembly of claim 1 , wherein the pixel elements of the infrared detector array comprise microbolometer detector pixel elements.

15. 1. A method of manufacturing a focal plane array (FPA) assembly, comprising: providing a handle wafer having a bond side and a planar side opposite the bond side; providing a silicon-on-insulator wafer having a first side and a second side opposite the first side; providing a device wafer having a plurality of solder joints; bonding the first surface of the silicon-on-insulator wafer to the bonding side of the handle wafer; forming a plurality of seal ring metallizations on the second side of the silicon-on-insulator wafer; etching a recess in the second side of the silicon-on-insulator wafer to expose a portion of the bond side of the handle wafer and form a plurality of recess walls; forming a first anti-reflective coating on a first portion of the planar side of the handle wafer; forming a second anti-reflective coating on a second portion of the bond side of the handle wafer; depositing a getter material on a third portion of the bond side of the handle wafer, on the plurality of recess walls, and on a fourth portion of the second surface of the silicon-on-insulator wafer; and bonding the device wafer to the second side of the silicon-on-insulator wafer.

16. 16. The method of claim 15, wherein the step of etching the recess into the second side of the silicon-on-insulator wafer is performed by dry etching followed by wet etching.

17. The method of claim 15 , wherein the device wafer comprises an infrared detector pixel array and an infrared reference pixel.

18. 20. The method of claim 17, wherein the infrared reference pixels are identical in configuration to pixel elements of the infrared detector pixel array.

19. The method of claim 15, wherein the deposition of the getter material is performed using a shadow mask.

20. The method of claim 15 , wherein the first portion of the bond side of the handle wafer is disposed inside the plurality of recess walls.

21. 16. The method of claim 15, wherein the fourth portion of the second side of the silicon-on-insulator wafer is disposed outside the plurality of recess walls.

22. 16. The method of claim 15, wherein bonding the device wafer to the silicon-on-insulator wafer is performed by attaching the plurality of solder joints to the plurality of seal ring metallizations on the second side of the silicon-on-insulator wafer.

23. 16. The method of claim 15, wherein deposition of a getter material is performed after forming the first anti-reflective coating.

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