Data transmission method and apparatus, system and computer-readable storage medium

Abstract

The present application discloses a data transmission method, an apparatus, a system, and a computer-readable storage medium, which relate to the field of communication technology. The method includes: a first module performs convolutional interleaving on symbols included in a plurality of obtained first codewords to obtain an interleaving result, where the first codeword is a codeword obtained by encoding the first data using a first FEC code; the first module obtains second data including identification information based on the interleaving result and transmits the second data to a second module; the convolutional interleaving is performed on the symbols included in the plurality of first codewords, so that when a burst error subsequently occurs in the second data, the burst error is distributed across multiple symbols, reducing the BER of the second data after error correction; when the second data includes a second codeword, the identification information includes codeword boundary information of the second codeword, eliminating the need to insert additional data as the identification information, thereby reducing data transmission costs.

Description

[Technical Field]

[0001] This application claims priority to Chinese Patent Application No. 202310037983.5, entitled "Data Transmission Method and Apparatus, System and Computer-Readable Storage Medium," filed on January 10, 2023, the entire contents of which are incorporated herein by reference.

[0002] Technical Field The present application relates to the field of communication technologies, and in particular to a data transmission method and apparatus, system, and computer-readable storage medium. [Background technology]

[0003] With the development of communication technology, data is encoded at the data transmitting end based on a forward error correction (FEC) code, and the received data is decoded at the data receiving end by using the same FEC code. This has become a widely used data transmission method. During the decoding process, the data receiving end performs error correction on the received data to correct bit errors in the data. Since the distribution of bit errors in the data changes, when the bit error rate (BER) before error correction is the same, the BER after error correction may be different.

[0004] For example, based on the distribution, bit errors include random errors and non-random errors, and non-random errors are the occurrence of multiple bit errors concentrated in a short data sequence. Typically, based on the same BER before error correction, non-random errors result in a higher BER after error correction than random errors. Therefore, a data transmission method is needed that is based on FEC, in which the data position is adjusted in an interleaved manner at the data sending end and the data position is restored in a deinterleaved manner at the data receiving end, so that the distribution of non-random errors is closer to the distribution of random errors after deinterleaving, thereby reducing the BER after error correction. Summary of the Invention [Problem to be solved by the invention]

[0005] The present application provides a data transmission method and apparatus, a system, and a computer-readable storage medium for implementing FEC-based data transmission in combination with convolutional interleaving. [Means for solving the problem]

[0006] According to a first aspect, there is provided a data transmission method. The method includes: a first module performing convolutional interleaving on symbols included in a plurality of obtained first codewords to obtain interleaving results, where the first codewords are codewords obtained by encoding the first data using a first FEC code; and the first module then obtains second data including identification information based on the interleaving results, and transmits the second data to a second module. When the second data includes the second codeword, the identification information includes codeword boundary information of the second codeword.

[0007] In this method, convolutional interleaving is performed on symbols included in a plurality of first code words, so that if a burst error subsequently occurs in the second data, the burst error is distributed across a plurality of symbols, and the BER of the second data after error correction is reduced. In addition, if the second data includes a second code word, the identification information is code word boundary information of the second code word, and there is no need to insert additional identification information indicating a start interleaving position where convolutional interleaving is performed on symbols included in a plurality of first code words, thereby reducing data transmission costs, increasing applicability to data transmission scenarios where the bandwidth or frequency of a phase-locked loop is limited, and reducing the implementation complexity of a data transmission system used to implement this method.

[0008] In one possible implementation, the step of performing convolutional interleaving on symbols included in the multiple obtained first codewords to obtain an interleaved result includes the steps of inputting the symbols included in the multiple first codewords into multiple first delay units of a convolutional interleaver, performing convolutional interleaving on the symbols included in the multiple first codewords and obtained through round robin through the multiple first delay units to obtain multiple first bit groups output by the multiple first delay units through round robin, and using the multiple first bit groups output by the multiple first delay units through round robin as an interleaved result, wherein one first bit group includes symbols output by the multiple first delay units once through round robin. In this method, in the process of obtaining an interleaved result through convolutional interleaving, convolutional interleaving is performed on symbols included in the multiple first codewords, and no additional data is introduced. Therefore, the amount of data required for performing convolutional interleaving is small, and the efficiency of convolutional interleaving is high.

[0009] In one possible implementation, the interleaving result includes n first bit groups output by the multiple first delay units through n-time round robin, and the step of obtaining second data including identification information based on the interleaving result includes encoding the n first bit groups output by the multiple first delay units through n-time round robin based on a second FEC code to obtain m second codewords, and obtaining the second data based on the m second codewords, wherein the number of bits corresponding to the n first bit groups is equal to the number of bits included in the information bits of the m codewords of the second FEC code, and m and n are both positive integers and m is less than or equal to n.

[0010] In this implementation, n first bit groups are encoded based on a second FEC code to obtain m second codewords. The receiving end then obtains the codeword boundary information of the second codeword to obtain the starting interleaving position for performing convolutional interleaving on the symbols included in the first codewords, and then performs convolutional deinterleaving based on the starting interleaving position. Because no additional identification information needs to be inserted, this implementation has low data transmission costs and is highly applicable to data transmission scenarios where the bandwidth or frequency of the phase-locked loop is limited.

[0011] In one possible implementation, the second data does not include a second codeword, the interleaving result includes n first bit groups output by the multiple first delay units through n-time round robin, and the step of obtaining the second data including the identification information based on the interleaving result includes: obtaining k target data frames based on a format of the reference data frame and the n first bit groups output by the multiple first delay units through n-time round robin; and obtaining the second data based on the k target data frames, where the target data frames include frame synchronization information, which is used as the identification information, and the number of bits corresponding to the n first bit groups is less than or equal to the number of bits included in the k target data frames, where k and n are both positive integers and less than or equal to n. If the second data does not include a second codeword, this means that the method is applicable to non-cascaded coding scenarios, and the application scenarios of this method are flexible.

[0012] In one possible implementation, the second data does not include a second code word, and the step of performing convolutional interleaving on symbols included in the plurality of obtained first code words to obtain an interleaving result includes the steps of inputting at least one piece of identification information and symbols included in the plurality of first code words to a plurality of first delay units of a convolutional interleaver, and performing convolutional interleaving on the at least one piece of identification information obtained through round robin and the symbols included in the plurality of first code words obtained through round robin via a plurality of first delay units. and using the plurality of second bit groups output by the plurality of first delay units through a round robin as an interleaving result, wherein at least one second bit group includes a symbol output by the plurality of first delay units through a round robin, or at least one second bit group includes a symbol output by the plurality of first delay units through a round robin and identification information, the identification information indicating a starting interleaving position where convolutional interleaving is performed on symbols included in the plurality of first codewords. When an interleaving result is obtained in this implementation, the specific form of the identification information can be set based on experience or practical requirements, as long as the identification information can indicate a starting interleaving position where convolutional interleaving is performed on symbols included in the plurality of first codewords. The type of the identification information is flexible.

[0013] In one possible implementation, the starting interleaving position at which convolutional interleaving is performed on symbols included in the plurality of first codewords is within any one of the plurality of first delay units, and the starting interleaving position is flexible.

[0014] In one possible implementation, symbols included in the plurality of first codewords are input to the plurality of first delay units of the convolutional interleaver in the manner of a first data stream, where the transmission rate of the first data stream is 100 gigabits per second (Gbps) or greater, and the symbols included in the plurality of first codewords are input to the plurality of first delay units of the convolutional interleaver at a high speed.

[0015] In one possible implementation, the first data stream is transmitted to multiple first delay units of the convolutional interleaver through at least one lane of an attachment unit interface (AUI), and the transmission scheme of the first data stream is flexible.

[0016] According to a second aspect, a data transmission method is provided. The method includes: a second module receiving second data, including identification information, transmitted by a first module. The second data is obtained based on an interleaving result obtained by performing convolutional interleaving on symbols included in a plurality of first codewords, where the first codewords are codewords obtained by encoding the first data using a first FEC code. If the second data includes a second codeword, the identification information includes codeword boundary information of the second codeword. The second module further obtains, based on the identification information, data to be deinterleaved within the second data and a starting interleaving position at which convolutional interleaving will be performed on the symbols included in the plurality of first codewords; and, based on the starting interleaving position, performs convolutional deinterleaving on the deinterleaved data to obtain a plurality of first codewords.

[0017] In this method, the second data is obtained based on an interleaving result obtained by performing convolutional interleaving on symbols included in a plurality of first code words, so that when a burst error occurs in the second data, the burst error is distributed over a plurality of symbols, thereby reducing the BER of the second data after error correction. In addition, when the second data includes a second code word, the identification information is code word boundary information of the second code word, and additional identification information indicating a start interleaving position where convolutional interleaving is performed on symbols included in the plurality of first code words does not need to be inserted into the second data, thereby reducing data transmission costs, improving applicability to data transmission scenarios where the bandwidth or frequency of a phase-locked loop is limited, and reducing the implementation complexity of a data transmission system used to implement the method.

[0018] In one possible implementation, the step of obtaining data to be deinterleaved in the second data and a starting interleaving position at which convolutional interleaving is performed on symbols included in the plurality of first codewords based on the identification information includes the steps of: obtaining at least one second codeword included in the second data based on codeword boundary information of the second codeword; obtaining a starting position of the at least one second codeword; using the starting position as the starting interleaving position at which convolutional interleaving is performed on symbols included in the plurality of first codewords; and decoding the at least one second codeword to obtain the data to be deinterleaved. This implementation is applicable to cascade encoding scenarios.

[0019] In one possible implementation, if the second data does not include a second codeword, the identification information is frame synchronization information, and the step of obtaining data to be deinterleaved in the second data and a starting interleaving position at which convolutional interleaving is performed on symbols included in the multiple first codewords based on the identification information includes the steps of obtaining at least one target data frame included in the second data based on the frame synchronization information, obtaining a starting position of frame data of the at least one target data frame, using the starting position as a starting interleaving position at which convolutional interleaving is performed on symbols included in the multiple first codewords, and using the frame data included in the at least one target data frame as data to be deinterleaved. This implementation is applicable to a non-cascaded coding scenario in which the second data includes a target data frame.

[0020] In one possible implementation, the data to be deinterleaved includes a plurality of third bit groups, each of which includes symbols of a first codeword output by a plurality of first delay units of a convolutional interleaver through a round robin process, and the step of performing convolutional deinterleaving on the data to be deinterleaved based on a start interleave position to obtain a plurality of first codewords includes the steps of: obtaining a start deinterleave position corresponding to the start interleave position and within a plurality of second delay units of the convolutional deinterleaver; inputting the plurality of third bit groups into a plurality of second delay units at the start deinterleave position; performing convolutional deinterleaving on symbols included in the plurality of third bit groups and obtained through the round robin process through the plurality of second delay units; obtaining symbols included in the plurality of first codewords output by the plurality of second delay units through the round robin process; and obtaining the plurality of first codewords based on the symbols included in the plurality of first codewords. In this implementation, the third bit group does not contain any identifying information, and convolutional deinterleaving is performed efficiently.

[0021] In one possible implementation, if the second data does not include a second codeword, the identification information indicates a starting interleaving position at which convolutional interleaving is performed on symbols included in the plurality of first codewords, and the step of obtaining data to be deinterleaved in the second data and a starting interleaving position at which convolutional interleaving is performed on symbols included in the plurality of first codewords based on the identification information includes obtaining a starting interleaving position at which convolutional interleaving is performed on symbols included in the plurality of first codewords indicated by the identification information, and using data at and after the starting interleaving position in the second data as data to be deinterleaved. This implementation is applicable to non-cascaded encoding scenarios in which the second data does not include a target data frame.

[0022] In one possible implementation, the data to be deinterleaved includes a plurality of fourth bit groups, and at least one fourth bit group includes a symbol of a first codeword output by a plurality of first delay units of a convolutional interleaver through a round robin once, or at least one fourth bit group includes a symbol and identification information output by a plurality of first delay units through a round robin once; and the step of performing convolutional deinterleaving on the data to be deinterleaved based on a start interleave position to obtain a plurality of first codewords includes performing convolutional deinterleaving on a start interleave position that corresponds to the start interleave position and is within a plurality of second delay units of the convolutional deinterleaver. The method includes obtaining a deinterleaving position, inputting the plurality of fourth bit groups into a plurality of second delay units at the start deinterleaving position, performing convolutional deinterleaving on symbols included in the plurality of fourth bit groups and obtained through round robin processing, or on symbols included in the plurality of fourth bit groups and obtained through round robin processing and identification information, via the plurality of second delay units, obtaining symbols included in the plurality of first codewords and the identification information output by the plurality of second delay units through round robin processing, and obtaining a plurality of first codewords based on the symbols included in the plurality of first codewords. This implementation is applicable to performing convolutional deinterleaving on the fourth bit group including the identification information.

[0023] In one possible implementation, the starting deinterleaving position is within any one of a plurality of second delay units, and the starting deinterleaving position is flexible.

[0024] In one possible implementation, the plurality of second delay units of the convolutional deinterleaver output symbols included in the plurality of first codewords in the manner of a second data stream, where the transmission rate of the second data stream is 100 Gbps or more, and the plurality of second delay units output symbols included in the plurality of first codewords at a high rate.

[0025] In one possible implementation, the plurality of second delay units of the convolutional deinterleaver output a second data stream through at least one lane of the AUI, and the transmission scheme of the second data stream is flexible.

[0026] According to a third aspect, there is provided a data transmission device, the device being used in a first module, the device comprising: an interleaving unit configured to perform convolutional interleaving on symbols included in a plurality of obtained first codewords to obtain interleaved results, wherein the first codewords are codewords obtained by encoding first data by using a first FEC code; an acquiring unit configured to acquire second data including identification information based on the interleaving result, where, when the second data includes a second code word, the identification information includes code word boundary information of the second code word; a transmitting unit configured to transmit the second data to a second module.

[0027] In one possible implementation, the interleaving unit is configured to input symbols included in the multiple first codewords into multiple first delay units of a convolutional interleaver; perform convolutional interleaving on the symbols included in the multiple first codewords and obtained through round robin through the multiple first delay units to obtain multiple first bit groups output by the multiple first delay units through round robin, where one first bit group includes symbols output by the multiple first delay units through round robin once; and use the multiple first bit groups output by the multiple first delay units through round robin as the interleaving result.

[0028] In one possible implementation, the interleaving result includes n first bit groups output by the multiple first delay units through n-time round robin, and the obtaining unit is configured to encode the n first bit groups output by the multiple first delay units through n-time round robin based on a second FEC code to obtain m second codewords, where the number of bits corresponding to the n first bit groups is equal to the number of bits included in the information bits of the m codewords of the second FEC code, where m and n are both positive integers and m is less than or equal to n; and obtain second data based on the m second codewords.

[0029] In one possible implementation, the second data does not include a second code word, the interleaving result includes n first bit groups output by the multiple first delay units through n-time round robin, and the acquisition unit is configured to acquire k target data frames based on a format of the reference data frame and the n first bit groups output by the multiple first delay units through n-time round robin, where the target data frames include frame synchronization information, which is used as identification information, and the number of bits corresponding to the n first bit groups is less than or equal to the number of bits included in the k target data frames, where k and n are both positive integers and k is less than or equal to n; and acquire the second data based on the k target data frames.

[0030] In one possible implementation, the second data does not include a second codeword, and the interleaving unit is configured to input at least one piece of identification information and symbols included in the multiple first codewords to multiple first delay units of a convolutional interleaver; to perform convolutional interleaving on the at least one piece of identification information obtained through round robin and the symbols included in the multiple first codewords obtained through round robin via the multiple first delay units to obtain multiple second bit groups output by the multiple first delay units through round robin, where at least one second bit group includes symbols output by the multiple first delay units through round robin once, or at least one second bit group includes symbols and identification information output by the multiple first delay units through round robin once, where the identification information indicates a starting interleaving position at which convolutional interleaving is performed on the symbols included in the multiple first codewords; and to use the multiple second bit groups output by the multiple first delay units through round robin as interleaving results.

[0031] In one possible implementation, the starting interleaving position at which convolutional interleaving is performed on the symbols contained in the plurality of first codewords is within any one of the plurality of first delay units.

[0032] In one possible implementation, symbols included in a plurality of first codewords are input to a plurality of first delay units of a convolutional interleaver in the form of a first data stream, and the transmission rate of the first data stream is 100 Gbps or more.

[0033] In one possible implementation, the first data stream is transmitted to a plurality of first delay units of the convolutional interleaver through at least one lane of an AUI.

[0034] According to a fourth aspect, there is provided a data transmission device, the device being used in a second module, the device comprising: an acquiring unit including identification information and configured to receive second data transmitted by the first module, the second data being acquired based on an interleaving result acquired by performing convolutional interleaving on symbols included in a plurality of first codewords, the first codewords being codewords acquired by encoding the first data by using a first FEC code, and when the second data includes a second codeword, the identification information includes codeword boundary information of the second codeword; an acquiring unit, the acquiring unit being further configured to acquire, based on the identification information, data to be deinterleaved in the second data and a start interleaving position at which convolutional interleaving is performed on the symbols included in the plurality of first codewords; and a deinterleaving unit configured to perform convolutional deinterleaving on the deinterleaving target data based on the starting interleaving position to obtain the plurality of first codewords.

[0035] In one possible implementation, the obtaining unit is configured to obtain at least one second codeword included in the second data based on the codeword boundary information of the second codeword, obtain a starting position of the at least one second codeword, use the starting position as a starting interleaving position at which convolutional interleaving is performed on symbols included in a plurality of first codewords, and decode the at least one second codeword to obtain data to be deinterleaved.

[0036] In one possible implementation, when the second data does not include a second code word, the identification information is frame synchronization information, and the acquisition unit is configured to acquire at least one target data frame included in the second data based on the frame synchronization information, acquire a starting position of frame data of the at least one target data frame, use the starting position as a starting interleaving position, and use the frame data included in the at least one target data frame as data to be deinterleaved.

[0037] In one possible implementation, the data to be deinterleaved includes a plurality of third bit groups, each of which includes symbols of a first codeword output by a plurality of first delay units of a convolutional interleaver through a round robin process; the deinterleaving unit is configured to obtain a start deinterleaving position corresponding to the start interleaving position and located within a plurality of second delay units of the convolutional deinterleaver; input the plurality of third bit groups into the plurality of second delay units at the start deinterleaving position; perform convolutional deinterleaving on the symbols included in the plurality of third bit groups and obtained through the round robin process through the plurality of second delay units; obtain symbols included in the plurality of first codewords and output by the plurality of second delay units through the round robin process; and obtain a plurality of first codewords based on the symbols included in the plurality of first codewords.

[0038] In one possible implementation, when the second data does not include a second code word, the identification information indicates a starting interleaving position at which convolutional interleaving is performed on symbols included in the plurality of first code words, and the obtaining unit is configured to obtain the starting interleaving position indicated by the identification information at which convolutional interleaving is performed on symbols included in the plurality of first code words, and use the data at the starting interleaving position and the data after the starting interleaving position in the second data as data to be deinterleaved.

[0039] In one possible implementation, the data to be deinterleaved includes a plurality of fourth bit groups, at least one of which includes a symbol of a first codeword output by a plurality of first delay units of a convolutional interleaver through a round robin once, or at least one of which includes a symbol and identification information output by a plurality of first delay units through a round robin once; the deinterleave unit obtains a start deinterleave position that corresponds to the start interleave position and is within a plurality of second delay units of the convolutional deinterleaver, and The multi-bit decoder is configured to input the plurality of fourth bit groups to a plurality of second delay units at the leave position, perform convolutional deinterleaving on the symbols included in the plurality of fourth bit groups and obtained through the round robin, or on the symbols included in the plurality of fourth bit groups and obtained through the round robin and the identification information, via the plurality of second delay units, obtain the symbols included in the plurality of first codewords and the identification information output by the plurality of second delay units through the round robin, and obtain the plurality of first codewords based on the symbols included in the plurality of first codewords.

[0040] In one possible implementation, the starting deinterleaving position is within any one of a plurality of second delay units.

[0041] In one possible implementation, the plurality of second delay units of the convolutional deinterleaver output symbols included in the plurality of first codewords in the manner of a second data stream, and the transmission rate of the second data stream is 100 Gbps or more.

[0042] In one possible implementation, the plurality of second delay units of the convolutional deinterleaver output the second data stream through at least one lane of the AUI.

[0043] According to a fifth aspect, there is provided a data transmission system. The system includes a first module and a second module. The first module is configured to perform the data transmission method of any implementation of the first aspect. The second module is configured to perform the data transmission method of any implementation of the second aspect.

[0044] According to a sixth aspect, there is provided a computer system. The computer system includes a processor, the processor including a first module or a second module. When the processor includes the first module, the computer system performs the data transmission method of any implementation of the first aspect when the processor executes program instructions or code. When the processor includes the second module, the computer system performs the data transmission method of any implementation of the second aspect when the processor executes program instructions or code. For example, the computer system further includes a memory, the memory configured to store the program instructions or code.

[0045] According to a seventh aspect, there is provided a computer-readable storage medium. The computer-readable storage medium stores at least one program instruction or code, the program instruction or code being executable by a computer, the computer including a first module or a second module. When the computer includes the first module, the program instruction or code, when executed by the computer, enables the computer to perform the data transmission method in any implementation of the first aspect. When the computer includes the second module, the program instruction or code, when executed by the computer, enables the computer to perform the data transmission method in any implementation of the second aspect.

[0046] According to an eighth aspect, there is provided a communications device. The device includes a transceiver, a memory, and a processor. The transceiver, the memory, and the processor communicate with each other through an internal connection path. The memory is configured to store instructions. The processor is configured to execute the instructions stored in the memory to control the transceiver to receive and transmit signals. The processor includes a first module or a second module. If the processor includes the first module, the processor executes the instructions stored in the memory to enable the processor to perform the data transmission method in any implementation of the first aspect. If the processor includes the second module, the processor executes the instructions stored in the memory to enable the processor to perform the data transmission method in any implementation of the second aspect.

[0047] For example, there may be one or more processors and there may be one or more memories.

[0048] For example, the memory and processor may be integrated together, or the memory and processor are located separately.

[0049] In a particular implementation, the memory may be a non-transitory memory, such as a read-only memory (ROM). The memory and the processor may be integrated on the same chip or may be separately located on different chips. The type of memory and the manner in which the memory and the processor are located are not limited by this application.

[0050] According to a ninth aspect, there is provided a computer program or computer program product. The computer program or computer program product includes computer program instructions or code that are executed by a computer, the computer including a first module and a second module. When the computer includes the first module, the computer program instructions or code, when executed by the computer, enable the computer to perform the data transmission method in any implementation of the first aspect. When the computer includes the second module, the computer program instructions or code, when executed by the computer, enable the computer to perform the data transmission method in any implementation of the second aspect.

[0051] According to a tenth aspect, there is provided a chip. The chip includes a processor, the processor including a first module or a second module, and the processor is configured to execute program instructions or code. When the processor includes the first module, a device including the chip performs the data transmission method of any implementation of the first aspect. When the processor includes the second module, a device including the chip performs the data transmission method of any implementation of the second aspect.

[0052] For example, the chip further includes an input interface, an output interface, and a memory. The input interface, the output interface, the processor, and the memory are connected through an internal connection path. The memory is configured to store program instructions or codes.

[0053] It should be understood that the beneficial effects achieved by the technical solutions of the third to tenth aspects of the present application and corresponding possible implementations of the technical solutions of the third to tenth aspects of the present application refer to the technical effects of the first and second aspects and corresponding possible implementations of the first and second aspects, and the details will not be described again in this specification. [Brief explanation of the drawings]

[0054] [Figure 1] FIG. 2 is a diagram of random errors and burst errors according to an embodiment of the present application.

[0055] [Figure 2] FIG. 2 is a diagram of a process for using an interleaver and a deinterleaver according to an embodiment of the present application.

[0056] [Figure 3] FIG. 1 is a diagram of an interleaving process according to an embodiment of the present application.

[0057] [Figure 4] FIG. 10 is a diagram of a starting interleave position according to an embodiment of the present application.

[0058] [Figure 5] 1 is a diagram of an implementation scenario according to an embodiment of the present application;

[0059] [Figure 6] FIG. 2 is a diagram of another implementation scenario according to an embodiment of the present application.

[0060] [Figure 7]FIG. 10 is a diagram of yet another implementation scenario according to an embodiment of the present application.

[0061] [Figure 8] 1 is a flowchart of a data transmission method according to an embodiment of the present application;

[0062] [Figure 9] FIG. 10 is a diagram of a process for obtaining second data according to an embodiment of the present application.

[0063] [Figure 10] FIG. 10 is a diagram of another process for obtaining second data according to an embodiment of the present application.

[0064] [Figure 11] FIG. 10 is a diagram of yet another process for obtaining second data according to an embodiment of the present application.

[0065] [Figure 12] FIG. 10 is a diagram of yet another process for obtaining second data according to an embodiment of the present application.

[0066] [Figure 13] 1 is a structural diagram of a data transmission device according to an embodiment of the present application;

[0067] [Figure 14] FIG. 10 is a structural diagram of another data transmission device according to an embodiment of the present application;

[0068] [Figure 15] 1 is a diagram of a computer system architecture according to an embodiment of the present application;

[0069] [Figure 16] FIG. 10 is a diagram of another computer system architecture according to an embodiment of the present application. DETAILED DESCRIPTION OF THE INVENTION

[0070] The terms used in the implementation of the present application are only used to describe the embodiments of the present application and are not intended to limit the present application. The following describes the embodiments of the present application with reference to the accompanying drawings.

[0071] In the data transmission process, bit errors remain an unavoidable problem due to the existence of environmental interference and system errors. A bit error is a bit in the data received by the data receiving end that does not match a bit in the data transmitted by the data transmitting end. Bit errors in data can cause data transmission system failure and data loss. Furthermore, bit errors can affect communication delays and user experience in video, games, calls, etc. Therefore, the amount of bit errors in received data, i.e., the bit error rate (BER) of data, has long been an index for measuring the performance of a communication system.

[0072] The smaller the BER of data, the higher the reliability of data transmission. Therefore, by limiting the BER of received data, the reliability of the data transmission system can be guaranteed. For example, the Institute of Electrical and Electronics Engineers (IEEE) 802.3 400 Gigabit Ethernet (GE) standard requires that the BER of data at the receiving end be lower than 1e-13 when the data enters the media access control (MAC) layer. 1e-13 is 1×10 -13 The BER of the data when it reaches the receiving end through the link transmission is approximately 2e-4. 2e-4 is 2×10 -4In this case, the data transmitting end encodes the data using an FEC code, and the data receiving end decodes the received data using the same FEC code to correct bit errors in the received data. This is a method for eliminating bit errors that occur in the data transmission process. After error correction is performed on the bit errors in the data based on the FEC code, the BER of the received data is low.

[0073] Based on the distribution, bit errors include random errors and non-random errors, and non-random errors are sometimes called burst errors. Figure 1 is a diagram of random error and burst error scenarios according to an embodiment of the present application. In Figure 1, b represents correct data and y represents bit errors. (1) in Figure 1 represents the distribution of random errors, and (2) in Figure 1 represents the distribution of burst errors, and the BER of the data shown in (1) and (2) in Figure 1 is the same.

[0074] Because the distribution of bit errors in data varies, the BER after error correction may differ even if the BER before error correction is the same. Under most data transmission conditions, based on the same BER before error correction, burst errors will result in a higher BER after error correction than random errors. Therefore, by interleaving the data through an interleaver, the BER after error correction for burst errors can be further reduced.

[0075] FIG. 2 is a diagram illustrating a process using an interleaver and a deinterleaver according to an embodiment of the present application. At the data transmitting end, data positions are adjusted through interleaving, and at the data receiving end, data positions are restored through deinterleaving, thereby dispersing burst errors that occur during data transmission through a transmission channel. In this way, the distribution of burst errors after deinterleaving is close to the distribution of random errors, thereby reducing the BER after error correction. As shown in FIG. 2, the data transmitting end can perform FEC encoding on the data through an FEC encoder before interleaving, and then interleave the FEC-encoded data through an interleaver. The interleaved data is transmitted to the receiving end through a channel. The receiving end can deinterleave the received data through a deinterleaver, and then perform FEC decoding on the data after deinterleaving through an FEC decoder. The FEC code used by the FEC encoder at the transmitting end is the same as the FEC code used by the FEC decoder at the receiving end. For example, the FEC code may be a Reed-Solomon (RS) code, a Bose-Chaudhuri-Hocquenghem (BCH) code, an extended BCH code, a Hamming code, an extended Hamming code, a staircase code, a low-density parity-check (LDPC) code, a turbo code, or a turbo product code (TPC). The FEC codes referred to elsewhere in this application may be a Reed-Solomon (RS) code, a Bose-Chaudhuri-Hocquenghem (BCH) code, an extended BCH code, a Hamming code, an extended Hamming code, a staircase code, a low-density parity-check (LDPC) code, a turbo code, or a turbo product code (TPC).

[0076] In some embodiments, the interleaver may include a block interleaver and a convolutional interleaver. Figure 3 is a diagram of an interleaving process according to an embodiment of the present application. (1) of Figure 3 illustrates data interleaving by a block interleaver, and (2) of Figure 3 illustrates data interleaving by a convolutional interleaver. (1) of Figure 3 is used as an example. At the data transmitting end (transmitter, Tx), codewords (cw) A to D encoded based on a first FEC code are arranged into four rows, and then the symbols of the FEC codewords are used as the granularity for outputting column by column to form interleaved data. In (1) of Figure 3, a represents a symbol included in cw A, b represents a symbol included in cw B, c represents a symbol included in cw C, and d represents a symbol included in cw D.

[0077] 3(2) is used as an example. The convolutional interleaver includes multiple delay units. The delay units may correspond to the delay lines shown in FIG. 3(2). The delay length corresponding to each delay line is determined based on the delay block length and the delay block number of each delay line. As shown in FIG. 3(2), the number of delay lines is four, and the four delay lines may be delay line 0, delay line 1, delay line 2, and delay line 3 in order from top to bottom. The delay blocks may be implemented by linear-feedback shift registers (LFSRs), and the delay blocks may store data. For example, if the delay blocks in each delay line have the same size, each delay line has a different number of delay blocks; or, if the delay blocks in each delay line have different sizes, each delay line has the same number of delay blocks. The input side and output side of the convolutional interleaver each have a switchable connection switch, and both of the two connection switches are configured to connect to the delay lines. As shown in Figure 3(2), the symbols of the FEC codeword can enter the convolutional interleaver column by column. For each symbol input from the input side, one symbol is output from the output side, after which the connection switches on both sides switch to the next delay line. A round robin may be performed for multiple delay lines in the sequence 0, 1, 2, 3, 0, 1, 2, 3, 0, 1, ... In Figure 3(2), the delay block is represented by D, and the data stored in the delay block before cw A to cw D is represented by x.

[0078] Because a convolutional interleaver includes multiple delay units, each with a different delay length, when performing deinterleaving, the receiving end of the data needs to determine a starting interleaving position for interleaving symbols to obtain correct data. In an embodiment of the present application, the starting interleaving position may also be referred to as a synchronization position. Because the multiple delay units input and output symbols in a round-robin manner, the starting interleaving position appears periodically in the data stream obtained through convolutional interleaving. FIG. 4 is a diagram of a starting interleaving position according to an embodiment of the present application. The data stream shown in FIG. 4 may be the data stream obtained through convolutional interleaving shown in (2) of FIG. 3. In the data stream, the starting interleaving position is the circled position in FIG. 4. FIG. 4 further illustrates a process of performing convolutional deinterleaving on the data stream obtained through interleaving. Please refer to FIG. 4. A plurality of symbols received through a channel are input to a plurality of delay units of a convolutional deinterleaver through a round robin, and convolutional deinterleaving is performed on the plurality of symbols through the plurality of delay units of the convolutional deinterleaver, and cw A to cw D are obtained based on the symbols output by the plurality of delay units of the convolutional deinterleaver through a round robin.

[0079] An embodiment of the present application provides a data transmission method for implementing data transmission based on FEC in combination with convolutional interleaving. The method may be applied to an implementation scenario shown in FIG. 5. This implementation scenario includes a first module 101 and a second module 102, where the first module 101 is communicatively connected to the second module 102. For example, the first module 101 may be included in a first device, and the second module 102 may be included in a second device. Alternatively, the first module 101 and the second module 102 may be included in the same device. The device where the first module 101 and the second module 102 are located may be a network device or another device based on an Ethernet interface.

[0080] The implementation scenario shown in FIG. 5 may be combined with a cascade encoding scenario. In other words, the implementation environment of this method may be that shown in FIG. 6. See FIG. 6. The first module 101 may perform encoding based on a first FEC code, convolutional interleaving, and encoding based on a second FEC code, and then transmit the data obtained through the encoding based on the second FEC code to the second module 102 through a channel. The second module 102 may perform decoding based on the second FEC code, convolutional deinterleaving, and decoding based on the first FEC code. In one possible implementation, after obtaining the data through encoding based on the second FEC code, the first module 101 may further interleave the data and transmit the interleaved data obtained through the encoding based on the second FEC code to the second module 102 through a channel. Correspondingly, the second module 102 may further deinterleave the interleaved data obtained through encoding based on the second FEC code to obtain the data obtained through encoding based on the second FEC code, and then perform decoding and other subsequent operations based on the second FEC code. The manner of interleaving the data obtained through encoding based on the second FEC code includes, but is not limited to, block interleaving and convolutional interleaving. If the interleaving manner is block interleaving, the manner of deinterleaving the interleaved data obtained through encoding based on the second FEC code by the second module 102 is block deinterleaving. If the interleaving manner is convolutional interleaving, the manner of deinterleaving the interleaved data obtained through encoding based on the second FEC code by the second module 102 is convolutional deinterleaving.

[0081] In addition, for the purpose of explanation, the above uses an example in which the first module 101 in FIG. 6 uses two interleavings, where the first interleaving is convolutional interleaving and the second interleaving is convolutional interleaving or block interleaving. In one possible implementation, the method provided in this embodiment of the present application may further support a scheme in which the first module 101 uses block interleaving for the first interleaving and convolutional interleaving for the second interleaving. Correspondingly, the second module 102 performs two deinterleavings. The first deinterleaving is block deinterleaving, and the second deinterleaving is convolutional deinterleaving. Regardless of the sequence in which the convolutional interleaving or convolutional deinterleaving is performed, the convolutional interleaving and convolutional deinterleaving methods provided in this embodiment of the present application may be referred to.

[0082] The implementation scenario shown in FIG. 5 may alternatively be combined with a non-cascaded encoding scenario. In other words, the implementation environment of this method may be that shown in FIG. 7. See FIG. 7. The first module 101 may perform encoding based on a first FEC code, perform convolutional interleaving, obtain a data frame, and then transmit the obtained data frame to the second module 102 through a channel. The second module 102 may receive the data frame, perform convolutional deinterleaving, and perform decoding based on the first FEC code. The implementation scenarios shown in FIGS. 5 to 7 may further include another module. This is not limited to the embodiments of the present application.

[0083] The data transmission method provided in this embodiment of the present application may be shown in Fig. 8. The following describes the data transmission method provided in this embodiment of the present application with reference to the implementation scenario shown in Fig. 5. As shown in Fig. 8, the method includes S801 to S803.

[0084] S801: A first module performs convolutional interleaving on symbols included in a plurality of obtained first code words to obtain interleaved results, where the first code words are code words obtained by encoding first data by using a first FEC code.

[0085] The manner in which the first module obtains the first codeword is not limited in the embodiments of the present application. For example, the first module may receive a plurality of first codewords transmitted by another module, or the first module may encode first data based on a first FEC code to obtain a plurality of first codewords. The first data may be data received by the first module and transmitted by another module, or data generated by the first module.

[0086] For example, symbols of multiple first codewords used for convolutional interleaving may be distributed. For example, the first module distributes symbols included in the first codewords to obtain multiple data channels, where any data channel includes symbols from multiple first codewords, and then the symbols included in each data channel are used as symbols for convolutional interleaving. Of course, the first module may alternatively not distribute the symbols included in the multiple first codewords and directly use the symbols included in the multiple first codewords as symbols for convolutional interleaving.

[0087] In the embodiment of the present application, the number of bits included in the symbol used for convolutional interleaving may or may not be related to the first FEC code. For example, the number of bits included in the symbol used for convolutional interleaving may be equal to the number of bits included in the symbol of the codeword of the first FEC code, or the number of bits included in the symbol used for convolutional interleaving may be determined based on experience or practical requirements. The number of bits included in the symbol used for convolutional interleaving is not limited in the embodiment of the present application.

[0088] In one possible implementation, performing convolutional interleaving on symbols included in the multiple obtained first codewords to obtain an interleaved result includes the following Scheme 1 and Scheme 2.

[0089] Scheme 1: Symbols included in a plurality of first codewords are input to a plurality of first delay units of a convolutional interleaver. Convolutional interleaving is performed on the symbols included in the plurality of first codewords and obtained through round robin through the plurality of first delay units to obtain a plurality of first bit groups output by the plurality of first delay units through round robin, where one first bit group includes symbols output by the plurality of first delay units through round robin once. The plurality of first bit groups output by the plurality of first delay units through round robin are used as interleaving results.

[0090] When convolutional interleaving is performed through multiple first delay units of a convolutional interleaver, the starting interleaving position at which convolutional interleaving is performed on symbols included in multiple first codewords is the round-robin starting position at which the symbols of the first codeword are input through the round-robin. For example, the convolutional interleaver includes four first delay units, and the four first delay units are numbered from the first delay unit 0 to the first delay unit 3. When the input of the symbols of the first codeword starts from the first delay unit 0 through the round-robin, the starting interleaving position is in the first delay unit 0. When the input of the symbols of the first codeword starts from the first delay unit 1 through the round-robin, the starting interleaving position is in the first delay unit 1. When the input of the symbols of the first codeword starts from the first delay unit 2 or the first delay unit 3 through the round-robin, the principle of the starting interleaving position is the same as that described above. Details will not be described again in this specification. Referring to the above, it can be seen that in this embodiment of the present application, the starting interleaving position at which convolutional interleaving is performed on the symbols contained in the plurality of first codewords can be within any one of the plurality of first delay units.

[0091] For example, if the symbols output by the first delay units through one round robin are used as one first bit group, the symbols output by the first delay units through n round robin are used as n first bit groups, and the n first bit groups are used as interleaving results, where n is a positive integer. When the delay units are delay lines, the multiple delay lines may output symbols by column. Therefore, if the starting interleaving position is in the first delay line of the multiple delay lines, the symbols output by the multiple delay lines through one round robin are located in the same column. If the starting interleaving position is in a delay line other than the first delay line of the multiple delay lines, the symbols output by the multiple delay lines through one round robin are located in different columns.

[0092] In Scheme 1, in the process of obtaining an interleaving result through convolutional interleaving, convolutional interleaving is performed only on symbols included in the multiple first codewords, and no additional data is introduced. Therefore, the amount of data required to perform convolutional interleaving is small, and the efficiency of convolutional interleaving is high. In an embodiment of the present application, in a non-cascaded coding scenario, the first module may further obtain identification information, where the identification information indicates a starting interleaving position at which convolutional interleaving is performed on symbols included in the multiple first codewords; and may perform convolutional interleaving on both the identification information and the symbols included in the multiple first codewords. In this case, the obtained interleaving result includes the identification information indicating the interleaving starting position. For the process of performing convolutional interleaving on both the identification information and the symbols included in the multiple first codewords, please refer to Scheme 2 below.

[0093] Method 2: At least one piece of identification information and symbols included in a plurality of first codewords are input to a plurality of first delay units of a convolutional interleaver. Convolutional interleaving is performed on the at least one piece of identification information obtained through round robin and the symbols included in the plurality of first codewords obtained through round robin via a plurality of first delay units to obtain a plurality of second bit groups output by the plurality of first delay units through round robin. Here, at least one second bit group includes a symbol output by the plurality of first delay units through a single round robin, or at least one second bit group includes a symbol and identification information output by the plurality of first delay units through a single round robin. The plurality of second bit groups output by the plurality of first delay units through round robin are used as interleaving results.

[0094] The number of bits included in the identification information may be equal to the number of bits included in the symbol. When the interleaving result is obtained by Scheme 2, as long as the identification information can indicate the starting interleaving position, the specific format of the identification information can be set based on experience or practical requirements. This is not limited in the embodiments of the present application.

[0095] In Scheme 2, the starting interleaving position may alternatively be located at any one of the first delay units. This is not limited to this embodiment of the present application. In Scheme 2, convolutional interleaving is performed on both the identification information and the symbols of the first codeword. Therefore, one second bit group output by the first delay units through one round robin may include only symbols, or may include both symbols and identification information. For example, the first delay units output one second bit group through one round robin. If the first delay units perform the round robin output t times, the first delay units output t second bit groups, and the t second bit groups are used as interleaving results. Here, t is a positive integer.

[0096] For example, symbols included in multiple first codewords may be input to multiple first delay units of a convolutional interleaver in the form of a first data stream, where the transmission rate of the first data stream is 100 Gbps or more. Of course, the transmission rate of the first data stream may alternatively be higher. For example, the transmission rate of the first data stream may be 200 Gbps or more. In one possible implementation, the first data stream is transmitted to multiple first delay units of the convolutional interleaver through at least one lane of an AUI. In this embodiment of the present application, convolutional interleaving may be performed on both the at least one piece of identification information and the symbols included in the multiple first codewords. In this case, the at least one piece of identification information and the symbols included in the multiple first codewords may alternatively be input to multiple first delay units of the convolutional interleaver in the form of a data stream, i.e., the first data stream may include the at least one piece of identification information and the symbols included in the multiple first codewords. In this embodiment of the present application, symbols or identification information in the first data stream are input to a plurality of first delay units in a round robin fashion.

[0097] S802: The first module obtains, based on the interleaving result, second data including identification information.

[0098] Referring to S801, the identification information may indicate a starting interleaving position where convolutional interleaving is performed on symbols included in the plurality of first codewords. Because the interleaving result obtained by Scheme 1 does not include identification information, the first module may introduce identification information when obtaining second data based on the interleaving result. For example, if the second data includes a second codeword, the identification information may include codeword boundary information of the second codeword. In other words, the codeword boundary information of the second codeword may indicate a starting interleaving position where convolutional interleaving is performed on symbols included in the plurality of first codewords. Because the interleaving result obtained by Scheme 2 includes identification information, the first module may directly use the obtained interleaving result as the second data to improve the efficiency of obtaining the second data. When the interleaving result is directly used as the second data, the second data does not include the second codeword. In this embodiment of the present application, the second codeword may be a codeword obtained by performing FEC encoding on the interleaving result based on a second FEC code. For the content of obtaining the second codeword, please refer to the content of the following method A1. The details are not described here. If the second data does not include the second codeword, it means that the method is applicable to non-cascade coding scenarios.

[0099] For example, when the interleaving result is obtained by Scheme 1, the interleaving result includes n first bit groups output by multiple first delay units through n round robin. When the method is applied to a cascade coding scenario, the second data can be obtained by Scheme A1 below.

[0100] Scheme A1: n first bit groups output by multiple first delay units through n round-robin coding are coded based on a second FEC code to obtain m second codewords, where the number of bits corresponding to the n first bit groups is equal to the number of bits included in the information bits of the m codewords of the second FEC code, where m and n are both positive integers and m is less than or equal to n. Second data is obtained based on the m second codewords.

[0101] When the second data includes a second codeword, the identification information may include codeword boundary information of the second codeword, the second codeword including information bits and parity bits, and the codeword boundary information of the second codeword may include a partition position between the parity bits of a first second codeword and the information bits of a subsequent second codeword in two adjacent second codewords.

[0102] The second FEC code is not limited in the embodiments of the present application, and may be determined based on experience or practical requirements. For example, when an FEC code is used as the second FEC code, the number of bits corresponding to one first bit group is equal to the number of bits included in the information bits of one codeword of the second FEC code, that is, n second codewords are obtained by encoding n first bit groups, where m is equal to n. In another example, when an FEC code is used as the second FEC code, No. and When m is used, the number of bits corresponding to the first bit groups is equal to the number of bits included in the information bits of one codeword of the second FEC code, i.e., m second codewords are obtained by encoding n first bit groups, where m is less than n.

[0103] The number of bits included in the n first bit groups depends on the number of delay units included in the convolutional interleaver and the number of bits included in a symbol, and the number of bits included in the symbol may be determined based on the delay length corresponding to the delay blocks of the delay units. In other words, the number of bits included in the n first bit groups may be determined based on the structure of the convolutional interleaver. When the number of bits corresponding to the n first bit groups is equal to the number of bits included in the m information bits of the second FEC code, the value relationship between m and n is flexible, which means that the adaptive relationship between the convolutional interleaver and the second FEC code is flexible. When both m and n are greater than 2 and are not equal, the codeword boundary information of at least two of the second codewords is different. In the method provided in this embodiment of the present application, when second data including identification information is obtained based on the interleaving result, additional data may be inserted into the interleaving result to function as identification information, and the identification information indicates the starting interleaving position.

[0104] The diagram in Figure 4 is still used as an example. When n=3 and m=2, that is, when two second codewords are obtained by encoding three first bit groups, there are two types of codeword boundary information for the second codeword. In this case, additional data can be inserted into the obtained interleaving result to serve as identification information indicating the starting interleaving position. During deinterleaving, the starting interleaving position can be determined based on the inserted identification information, avoiding incorrect deinterleaving due to different codeword boundary information and ensuring the accuracy of deinterleaving.

[0105] 9 is a diagram of a process for obtaining second data according to an embodiment of the present application. In the process for obtaining second data shown in FIG. 9, m is equal to n, that is, n bit groups are encoded based on a second FEC code to obtain n second codewords, where the number of bits corresponding to one first bit group is equal to the number of bits included in the information bits of one codeword of the second FEC code. The principle of the process for performing convolutional interleaving on cw A to cw D shown in FIG. 9 is the same as the convolutional interleaving process shown in (2) of FIG. 3. The details will not be described again in this specification.

[0106] 10 is a diagram of another process for obtaining second data according to an embodiment of the present application. In the process for obtaining second data shown in FIG. 10, m is smaller than n, and the number of bits corresponding to the two first bit groups is equal to the number of bits included in the information bits of one codeword of the second FEC code. The principle of the process for performing convolutional interleaving on cw A to cw D shown in FIG. 10 is the same as the convolutional interleaving process shown in (2) of FIG. 3. The details will not be described again in this specification.

[0107] 9 and 10 are explained by using an example in which symbols included in cw A to cw D appear consecutively within one delay unit. This method is further applicable to a scenario in which multiple symbols from one codeword appear consecutively within one delay unit. FIG. 11 is a diagram of yet another process for obtaining second data according to an embodiment of the present application. Please refer to FIG. 11. The first codeword includes 320 bits, i.e., cw A to cw D each include 320 bits, and the information bits of the codeword of the second FEC code include 160 bits. In FIG. 11, convolutional interleaving is performed on the symbols included in cw A to cw D, and the number of delay lines of the convolutional interleaver is equal to the number of the first codeword, i.e., the convolutional interleaver includes four delay lines. In FIG. 11, a represents the symbols included in cw A, b represents the symbols included in cw B, c represents the symbols included in cw C, and d represents the symbols included in cw D. When the symbols output by the convolutional interleaver for each column are used to obtain one second codeword obtained through encoding based on a second FEC code, each symbol included in cw A to cw D contains 40 bits, and the number of bits corresponding to the delay blocks included in each delay line is also 40 bits. Because one first codeword contains 320 bits, the difference between the number of delay blocks included in each delay line is equal to (320 / 40) / 4=2. Therefore, as shown in FIG. 11, D represents the delay block, and delay line 0 may contain 6 delay blocks, delay line 1 may contain 4 delay blocks, delay line 2 may contain 2 delay blocks, and delay line 3 may contain 0 delay blocks.

[0108] Continuing to refer to FIG. 11 , after convolutional interleaving is performed on the symbols included in the multiple first codewords via the delay lines, four adjacent output symbols are from different first codewords. Therefore, if a 160-bit burst error occurs in the second data, the bits included in the burst error are distributed across four symbols, and since the four symbols are from different first codewords, the burst error is distributed. In addition, as shown in FIG. 11 , four symbols output in one sequence are used to obtain one codeword obtained through encoding based on the second FEC codeword. In other words, in FIG. 11 , four symbols output by four delay lines through one round robin are encoded based on the second FEC code to obtain one second codeword.

[0109] The n first bit groups are encoded based on a second FEC code to obtain m second codewords, whereby the receiving end obtains the starting interleaving position by obtaining the codeword boundary information of the second codeword and then performs convolutional deinterleaving based on the starting interleaving position without inserting identification information indicating the starting interleaving position. Inserting additional identification information increases the link transmission rate, increasing the transmission bandwidth required for data transmission and resulting in higher data transmission costs. In addition, because inserting additional identification information increases the link transmission rate, the method is not applicable to data transmission scenarios where the bandwidth or frequency of the phase-locked loop is limited. In contrast, method A1 does not require inserting additional identification information and can directly use the codeword boundary information of the second codeword as identification information, thereby reducing the data transmission cost and improving its applicability to data transmission scenarios where the bandwidth or frequency of the phase-locked loop is limited.

[0110] When the method provided in this embodiment of the present application is applied to a non-cascade encoding scenario, the second data may be obtained in the following manner A2.

[0111] Method A2: k target data frames are obtained based on the format of the reference data frame and n first bit groups output by multiple first delay units through n round-robin round-robin, where the target data frames include frame synchronization information, which is used as identification information, and the number of bits corresponding to the n first bit groups is less than or equal to the number of bits included in the k target data frames, where k and n are both positive integers and k is less than or equal to n. Second data is obtained based on the k target data frames.

[0112] In other words, in a non-cascaded coding scenario, the second data may be obtained by obtaining k target data frames based on the n first bit groups. In this case, the second data does not include a second codeword. For example, the frame synchronization information may include, but is not limited to, a frame alignment word in coherent transmission or other data used for frame synchronization. The format of the reference data frame may be determined based on the frame format to be used for data transmission. This is not limited in the embodiment of the present application. For example, the k target data frames may be used as the second data.

[0113] 12 is a diagram of yet another process for acquiring second data according to an embodiment of the present application. In the process for acquiring second data shown in FIG. 12, k is smaller than n, and four first bit groups are used to acquire one target data frame. The principle of the process for performing convolutional interleaving on cw A to cw D shown in FIG. 12 is the same as the convolutional interleaving process shown in (2) of FIG. 3. The details will not be described again in this specification.

[0114] S803: The first module sends the second data to the second module.

[0115] The first module transfers the second data to the second Module The manner of transmitting the second data to the first module is not limited in this embodiment of the present application. For example, the first module transmits the second data to the second module through a channel.

[0116] In the method provided in this embodiment of the present application, convolutional interleaving is performed on symbols included in multiple first code words, so that when a burst error occurs in the second data later, the burst error is distributed to multiple symbols, thereby reducing the BER of the second data after error correction.In addition, when the second data includes a second code word, the identification information is the code word boundary information of the second code word, and there is no need to insert additional identification information indicating the starting interleaving position, thereby reducing the data transmission cost, being highly applicable to data transmission scenarios where the bandwidth or frequency of the phase-locked loop is limited, and the implementation complexity of the data transmission system used to implement the method is low.

[0117] The above uses the first module side as an example to describe the data transmission method provided in this embodiment of the present application. The following uses the second module side as an example to describe the data transmission method. As shown in Figure 8, the data transmission method includes S804 to S806.

[0118] S804: A second module receives second data including the identification information and sent by the first module.

[0119] The manner in which the second module receives the second data is not limited in this embodiment of the present application, as long as it is compatible with the manner in which the first module transmits the second data to the second module. Referring to the content of S802, it can be seen that the second data is obtained based on an interleaving result obtained by performing convolutional interleaving on symbols included in a plurality of first codewords, and the first codewords are codewords obtained by encoding the first data using a first FEC code. If the second data includes a second codeword, the identification information includes codeword boundary information of the second codeword.

[0120] S805: A second module obtains, based on the identification information, data to be deinterleaved in the second data and a starting interleaving position at which convolutional interleaving is performed on symbols included in the plurality of first codewords.

[0121] Based on different cases of the second data, the second module may perform operations in different manners to obtain, based on the identification information, data to be deinterleaved in the second data and a starting interleaving position at which convolutional interleaving is performed on symbols included in the plurality of first codewords.

[0122] Case B1: The second data includes a second codeword.

[0123] If the second data includes a second code word, the second module obtains at least one second code word included in the second data based on code word boundary information of the second code word, obtains a starting position of the at least one second code word, uses the starting position as a starting interleaving position at which convolutional interleaving is performed on symbols included in a plurality of first code words, and decodes the at least one second code word to obtain data to be deinterleaved.

[0124] For example, the codeword boundary information of the second codeword may be obtained in a codeword self-synchronizing manner, so that the second module can obtain the at least one second codeword included in the second data based on the boundary information of the second codeword. For example, the process of the second module obtaining the codeword boundary information of the second codeword in a codeword self-synchronizing manner includes: obtaining a local codeword of a second FEC code; and identifying the codeword boundary information of the second codeword based on the local codeword of the second FEC code. If the second data includes an alignment marker (AM), the position of the AM is associated with the position of the second codeword, so that the second module can obtain the codeword boundary information of the second codeword by determining the position of the AM in the second data.

[0125] The second codeword is obtained by encoding the n first bit groups based on the second FEC code, and the n first bit groups are obtained from a starting interleaving position at which convolutional interleaving is performed on symbols included in the plurality of first codewords. Thus, the starting position of the second codeword can be used as a starting interleaving position at which convolutional interleaving is performed on symbols included in the plurality of first codewords. The manner in which the second module decodes the second codeword only needs to correspond to the manner in which the second codeword is obtained through encoding. In other words, the second module may decode the at least one second codeword based on the second FEC code to obtain data to be deinterleaved.

[0126] Case B2: The second data does not include the second codeword.

[0127] If the second data does not include a second code word but includes at least one target data frame, the identification information is frame synchronization information, and the second module may perform an operation of obtaining, based on the identification information, data to be deinterleaved in the second data and a starting interleaving position at which convolutional interleaving is performed on symbols included in the plurality of first code words, in the following manner C1.

[0128] Method C1: The at least one target data frame included in the second data is obtained based on frame synchronization information. A start position of frame data of the at least one target data frame is obtained. The start position is used as a start interleaving position at which convolutional interleaving is performed on symbols included in a plurality of first codewords. The frame data included in the at least one target data frame is used as data to be deinterleaved.

[0129] For example, the second module divides the second data based on the frame synchronization information to obtain the at least one target data frame included in the second data. The number of target data frames may be k. Additionally, after the at least one target data frame is obtained, a start position of frame data for each target data frame may be obtained. The k target data frames may be obtained based on the n first bit groups, and the n first bit groups are obtained from a start interleaving position at which convolutional interleaving is performed on symbols included in the multiple first codewords. Therefore, the start position of frame data for the target data frame may be used as a start interleaving position at which convolutional interleaving is performed on symbols included in the multiple first codewords.

[0130] When the second data does not include a second codeword or a target data frame, the identification information indicates a starting interleaving position where convolutional interleaving is performed on symbols included in the plurality of first codewords. The second module may perform an operation of obtaining, based on the identification information, data to be deinterleaved in the second data and a starting interleaving position where convolutional interleaving is performed on symbols included in the plurality of first codewords, in accordance with the following scheme C2.

[0131] Method C2: A start interleaving position indicated by the identification information is obtained, where convolutional interleaving is performed on symbols included in multiple first codewords. Data at the start interleaving position and data after the start interleaving position in the second data are used as data to be deinterleaved.

[0132] In other words, the identification information may directly indicate a starting interleaving position at which convolutional interleaving is performed on symbols contained in the plurality of first code words, so that the second module uses the data at the starting interleaving position and the data after the starting interleaving position in the second data as data to be deinterleaved.

[0133] S806: A second module performs convolutional deinterleaving on the deinterleaving target data based on the starting interleaving position to obtain a plurality of first codewords.

[0134] For example, when the data to be deinterleaved is obtained by the method in case B1 or the method C1 in case B2, the data to be deinterleaved includes a plurality of third bit groups, and each third bit group includes symbols of a first codeword output by a plurality of first delay units of a convolutional interleaver through one round-robin process. Since bit errors may occur in the data transmission process, bit errors may exist in the third bit groups.

[0135] When the data to be deinterleaved includes a plurality of third bit groups, performing convolutional deinterleaving on the data to be deinterleaved based on a start interleave position to obtain a plurality of first codewords may include the steps of: obtaining a start deinterleave position corresponding to the start interleave position and within a plurality of second delay units of a convolutional deinterleaver; inputting the plurality of third bit groups into a plurality of second delay units at the start deinterleave position; performing convolutional deinterleaving on symbols included in the plurality of third bit groups and obtained through round robin via the plurality of second delay units; obtaining symbols included in the plurality of first codewords and output by the plurality of second delay units through round robin; and obtaining a plurality of first codewords based on the symbols included in the plurality of first codewords.

[0136] The starting interleaving position may be the same as the starting deinterleaving position. After obtaining the starting interleaving position, the second module may use the starting interleaving position as the starting deinterleaving position. First Similarly to the case where the interleaving position can be in any one of the plurality of first delay units, the starting deinterleaving position can be in any one of the plurality of second delay units. After the symbols included in the plurality of first codewords are obtained, the first codeword can be obtained based on the symbols included in the first codeword.

[0137] For example, when the data to be deinterleaved is obtained by the method C2 in the case B2, the data to be deinterleaved includes a plurality of fourth bit groups, and at least one fourth bit group includes symbols of a first codeword output by a plurality of first delay units of a convolutional interleaver through one round-robin process, or at least one fourth bit group includes symbols and identification information output by a plurality of first delay units through one round-robin process. Because bit errors may occur in the data transmission process, bit errors may exist in the fourth bit group.

[0138] When the data to be deinterleaved includes a plurality of fourth bit groups, the step of performing convolutional deinterleaving on the data to be deinterleaved based on a start interleaving position to obtain a plurality of first codewords may include the steps of: obtaining a start deinterleaving position corresponding to the start interleaving position and within a plurality of second delay units of a convolutional deinterleaver; inputting the plurality of fourth bit groups into a plurality of second delay units at the start deinterleaving position; performing convolutional deinterleaving on symbols included in the plurality of fourth bit groups and obtained through round robin, or on symbols included in the plurality of fourth bit groups and obtained through round robin and identification information, via the plurality of second delay units; obtaining the identification information and symbols included in the plurality of first codewords output by the plurality of second delay units through round robin; and obtaining a plurality of first codewords based on the symbols included in the plurality of first codewords.

[0139] In this case, the principle of how the second module obtains the starting deinterleaving position and the method of performing convolutional deinterleaving to obtain multiple first codewords are the same as those in the above case where the data to be deinterleaved includes multiple third bit groups, and the details will not be described again in this specification.

[0140] For example, the second delay units of the convolutional deinterleaver output symbols included in the first codewords in the form of a second data stream, where the transmission rate of the second data stream is 100 Gbps or more. Alternatively, the transmission rate of the second data stream may be higher. For example, the transmission rate of the second data stream may be 200 Gbps or more. When the second data is obtained through convolutional interleaving performed on both the identification information and the symbols of the first codewords, the second data stream may further include the identification information. In this case, the second delay units of the convolutional deinterleaver output the identification information and the symbols included in the first codewords in the form of a second data stream. For example, the second delay units of the convolutional deinterleaver output the second data stream through at least one lane of the AUI. The plurality of second delay units may input the second data stream to at least one lane of the AUI in a round-robin manner and output the second data stream through the at least one lane of the AUI.

[0141] In the method provided in this embodiment of the present application, the second data is obtained by performing convolutional interleaving on symbols included in multiple first code words, so that when a burst error occurs in the second data, the burst error is distributed over multiple symbols, thereby reducing the BER of the second data after error correction.In addition, when the second data includes a second code word, the identification information is code word boundary information of the second code word, and there is no need to insert additional identification information indicating the starting interleaving position into the second data, thereby reducing the data transmission cost, improving applicability to data transmission scenarios where the bandwidth or frequency of a phase-locked loop is limited, and reducing the implementation complexity of a data transmission system used to implement the method.

[0142] An embodiment of the present application further provides a data transmission device. Figure 13 is a diagram of the structure of a data transmission device according to an embodiment of the present application. Based on the multiple units shown in Figure 13, the data transmission device shown in Figure 13 can perform all or part of the operations performed by the first module. It should be understood that the device may include more additional units than the units shown, or may omit some of the units shown. This is not limited in this embodiment of the present application. As shown in Figure 13, the device an interleaving unit 1301 configured to perform convolutional interleaving on symbols included in a plurality of obtained first codewords to obtain interleaved results, the first codewords being codewords obtained by encoding first data by using a first FEC code; and an acquiring unit 1302 configured to acquire second data including identification information based on the interleaving result, where if the second data includes a second code word, the identification information includes code word boundary information of the second code word; and and a sending unit 1303 configured to send the second data to the second module.

[0143] In one possible implementation, the interleaving unit 1301 is configured to input symbols included in a plurality of first codewords into a plurality of first delay units of a convolutional interleaver, perform convolutional interleaving on the symbols included in the plurality of first codewords and obtained through round robin through the plurality of first delay units, to obtain a plurality of first bit groups output by the plurality of first delay units through round robin, one first bit group including symbols output by the plurality of first delay units through round robin once, and use the plurality of first bit groups output by the plurality of first delay units through round robin as the interleaving result.

[0144] In one possible implementation, the interleaving result includes n first bit groups output by the multiple first delay units through n-time round robin, and the obtaining unit 1302 is configured to encode the n first bit groups output by the multiple first delay units through n-time round robin based on a second FEC code to obtain m second codewords, where the number of bits corresponding to the n first bit groups is equal to the number of bits included in the information bits of the m codewords of the second FEC code, where m and n are both positive integers and m is less than or equal to n; and obtain second data based on the m second codewords.

[0145] In one possible implementation, the second data does not include a second code word, the interleaving result includes n first bit groups output by the multiple first delay units through n-time round robin, and the acquiring unit 1302 is configured to acquire k target data frames based on the format of the reference data frame and the n first bit groups output by the multiple first delay units through n-time round robin, where the target data frames include frame synchronization information, which is used as identification information, and the number of bits corresponding to the n first bit groups is less than or equal to the number of bits included in the k target data frames, where k and n are both positive integers and k is less than or equal to n; and to acquire the second data based on the k target data frames.

[0146] In one possible implementation, the second data does not include a second codeword, and the interleaving unit 1301 is configured to input at least one piece of identification information and symbols included in the multiple first codewords into multiple first delay units of a convolutional interleaver; to perform convolutional interleaving on the at least one piece of identification information obtained through round robin and the symbols included in the multiple first codewords obtained through round robin through the multiple first delay units to obtain multiple second bit groups output by the multiple first delay units through round robin, where at least one second bit group includes symbols output by the multiple first delay units through round robin once, or at least one second bit group includes identification information and symbols output by the multiple first delay units through round robin once, where the identification information indicates a starting interleaving position at which convolutional interleaving is performed on the symbols included in the multiple first codewords; and to use the multiple second bit groups output by the multiple first delay units through round robin as interleaving results.

[0147] In one possible implementation, the starting interleaving position at which convolutional interleaving is performed on the symbols contained in the plurality of first codewords is within any one of the plurality of first delay units.

[0148] In one possible implementation, symbols included in a plurality of first codewords are input to a plurality of first delay units of a convolutional interleaver in the form of a first data stream, and the transmission rate of the first data stream is 100 Gbps or more.

[0149] In one possible implementation, the first data stream is transmitted to a plurality of first delay units of a convolutional interleaver through at least one lane of the AUI.

[0150] In the device provided in this embodiment of the present application, convolutional interleaving is performed on symbols included in multiple first code words, so that when a burst error occurs in the second data thereafter, the burst error is distributed to multiple symbols, and the BER of the second data after error correction is reduced.In addition, when the second data includes a second code word, the identification information is the code word boundary information of the second code word, and there is no need to insert additional identification information indicating the starting interleaving position, thereby reducing the data transmission cost, being highly applicable to data transmission scenarios where the bandwidth or frequency of the phase-locked loop is limited, and reducing the implementation complexity of a data transmission system including the device.

[0151] 14 is a diagram of the structure of another data transmission device according to an embodiment of the present application. Based on the multiple units shown in FIG. 14, the data transmission device shown in FIG. 14 can perform all or part of the operations performed by the second module. It should be understood that the device may include more additional units than the units shown, or may omit some of the units shown. This is not limited to this embodiment of the present application. As shown in FIG. 14, the device an obtaining unit 1401 including identification information and configured to receive second data transmitted by a first module, wherein the second data is obtained based on an interleaving result obtained by performing convolutional interleaving on symbols included in a plurality of first codewords, the first codewords being codewords obtained by encoding the first data by using a first FEC code; and when the second data includes a second codeword, the identification information includes codeword boundary information of the second codeword, an acquiring unit, the acquiring unit 1401 being further configured to acquire, based on the identification information, data to be deinterleaved in the second data and a starting interleaving position at which convolutional interleaving is performed on symbols included in the plurality of first codewords; and a deinterleaving unit 1402 configured to perform convolutional deinterleaving on the data to be deinterleaved based on the starting interleave position to obtain a plurality of first codewords.

[0152] In one possible implementation, the obtaining unit 1401 is configured to obtain at least one second codeword included in the second data based on the codeword boundary information of the second codeword, obtain a starting position of the at least one second codeword, use the starting position as a starting interleaving position at which convolutional interleaving is performed on symbols included in a plurality of first codewords, and decode the at least one second codeword to obtain data to be deinterleaved.

[0153] In one possible implementation, when the second data does not include a second code word, the identification information is frame synchronization information, and the acquisition unit 1401 is configured to acquire at least one target data frame included in the second data based on the frame synchronization information, acquire a starting position of frame data of the at least one target data frame, use the starting position as a starting interleaving position at which convolutional interleaving is performed on symbols included in a plurality of first code words, and use the frame data included in the at least one target data frame as data to be deinterleaved.

[0154] In one possible implementation, the data to be deinterleaved includes a plurality of third bit groups, each of which includes symbols of a first codeword output by a plurality of first delay units of a convolutional interleaver through a round robin process; the deinterleaving unit 1402 is configured to obtain a start deinterleaving position corresponding to the start deinterleaving position and located within a plurality of second delay units of the convolutional deinterleaver; input the plurality of third bit groups into the plurality of second delay units at the start deinterleaving position; perform convolutional deinterleaving on the symbols included in the plurality of third bit groups and obtained through the round robin process through the plurality of second delay units; obtain symbols included in the plurality of first codewords and output by the plurality of second delay units through the round robin process; and obtain a plurality of first codewords based on the symbols included in the plurality of first codewords.

[0155] In one possible implementation, when the second data does not include a second code word, the identification information indicates a starting interleaving position at which convolutional interleaving is performed on symbols included in the plurality of first code words, and the obtaining unit 1401 is configured to obtain the starting interleaving position indicated by the identification information at which convolutional interleaving is performed on symbols included in the plurality of first code words, and use the data at the starting interleaving position and the data after the starting interleaving position in the second data as data to be deinterleaved.

[0156] In one possible implementation, the data to be deinterleaved includes a plurality of fourth bit groups; at least one fourth bit group includes a symbol of a first codeword output by a plurality of first delay units of a convolutional interleaver through a round robin once, or at least one fourth bit group includes a symbol and identification information output by a plurality of first delay units through a round robin once; the deinterleaving unit 1402 obtains a start deinterleaving position that corresponds to the start deinterleaving position and is within a plurality of second delay units of the convolutional deinterleaver, and selects the start deinterleaving position. The method is configured to input the plurality of fourth bit groups to a plurality of second delay units at the terleaving positions, perform convolutional deinterleaving on the symbols included in the plurality of fourth bit groups and obtained through round robin, or on the identification information and symbols included in the plurality of fourth bit groups and obtained through round robin, via the plurality of second delay units, obtain the symbols and identification information included in the plurality of first codewords output by the plurality of second delay units through round robin, and obtain the plurality of first codewords based on the symbols included in the plurality of first codewords.

[0157] In one possible implementation, the starting deinterleaving position is within any one of a plurality of second delay units.

[0158] In one possible implementation, the plurality of second delay units of the convolutional deinterleaver output symbols included in the plurality of first codewords in the form of a second data stream, and the transmission rate of the second data stream is 100 Gbps or more.

[0159] In one possible implementation, the plurality of second delay units of the convolutional deinterleaver output the second data stream through at least one lane of the AUI.

[0160] In the device provided in this embodiment of the present application, the second data is obtained by performing convolutional interleaving on symbols included in multiple first code words, so that when a burst error occurs in the second data, the burst error is distributed to multiple symbols, thereby reducing the BER of the second data after error correction.In addition, when the second data includes a second code word, the identification information is code word boundary information of the second code word, and there is no need to insert additional identification information indicating the starting interleaving position into the second data, thereby reducing the data transmission cost, increasing the applicability to data transmission scenarios where the bandwidth or frequency of the phase-locked loop is limited, and reducing the implementation complexity of a data transmission system including the device.

[0161] It should be understood that when the apparatuses provided in Figures 13 and 14 implement the functions of the apparatus, the division of the above-mentioned functional units is only used as an example for explanation. In actual application, the above-mentioned functions may be allocated to different functional units for implementation as needed. That is, the internal structure of the device is divided into different functional units for implementing all or part of the above-mentioned functions. In addition, the apparatuses provided in the above-mentioned embodiments belong to the same concept as the method embodiments. For the specific implementation process thereof, please refer to the method embodiments. The details will not be described again in this specification.

[0162] 15 is a diagram of a computer system according to an embodiment of the present application. For example, as shown in FIG. 15, the computer system is computer system 2000. Computer system 2000 may be a network device, a routing device, or a switching device. Computer system 2000 shown in FIG. 15 is configured to perform operations associated with the first module or the second module in the data transmission method shown in FIG. 8. Computer system 2000 may be, for example, a server, and computer system 2000 may be implemented using a general-purpose bus architecture.

[0163] As shown in FIG. 15, the computer system 2000 includes at least one processor 2001, a memory 2003, and at least one communication interface 2004.

[0164] The processor 2001 may be, for example, a central processing unit (CPU), a digital signal processor (DSP), a network processor (NP), a graphics processing unit (GPU), a neural-network processing unit (NPU), a data processing unit (DPU), a microprocessor, or one or more integrated circuits configured to implement the solutions of the present application. For example, the processor 2001 may include an application-specific integrated circuit (ASIC), a programmable logic device (PLD) or another programmable logic device, a transistor logic device, a hardware component, or any combination thereof. The PLD may be, for example, a complex programmable logic device (CPLD), a field-programmable gate array (FPGA), a generic array logic (GAL), or any combination thereof. The processor may implement or execute various logic blocks, modules, and circuits described with reference to the disclosed content in the embodiments of the present application. Alternatively, the processor may be a combination for implementing computing functions, such as a combination of one or more microprocessors, or a combination of a DSP and a microprocessor.

[0165] Optionally, the computer system 2000 further includes a bus. The bus is used for transmitting information between components of the computer system 2000. The bus may be a peripheral component interconnect (PCI) bus, an extended industry standard architecture (EISA) bus, or the like. The bus may be classified into an address bus, a data bus, a control bus, or the like. For ease of representation, only one thick line is used in FIG. 15 for representation, but this does not mean that only one bus or only one type of bus is present.

[0166] Memory 2003 may be, for example, but is not limited to, read-only memory (ROM) or another type of static storage device capable of storing static information and instructions, random access memory (RAM) or another type of dynamic storage device capable of storing information and instructions, electrically erasable programmable read-only memory (EEPROM), compact disc read-only memory (CD-ROM) or other optical disc storage, optical disc storage (including compact discs, laser discs, optical discs, digital versatile discs, Blu-ray discs, etc.), disc storage media or other magnetic storage devices, or any other medium that can be used to carry or store expected program code in the form of instructions or data structures and that can be accessed by a computer. For example, memory 2003 exists independently and is connected to processor 2001 through a bus. Alternatively, memory 2003 may be integrated with processor 2001.

[0167] The communication interface 2004 is any device, such as a transceiver, configured to communicate with another device or a communication network. The communication network may be an Ethernet, a radio access network (RAN), a wireless local area network (WLAN), or the like. The communication interface 2004 may include a wired communication interface or may further include a wireless communication interface. Specifically, the communication interface 2004 may be an Ethernet interface, a fast Ethernet (FE) interface, a gigabit Ethernet (GE) interface, an asynchronous transfer mode (ATM) interface, a WLAN interface, a cellular network communication interface, or a combination thereof. The Ethernet interface may be an optical interface, an electrical interface, or a combination thereof. In this embodiment of the present application, the communication interface 2004 may be used by the computer system 2000 to communicate with another device.

[0168] During specific implementation, in one embodiment, the processor 2001 may include one or more CPUs, such as CPU0 and CPU1 shown in FIG. 15. Each of the processors may be a single-core (single-CPU) processor or a multi-core (multi-CPU) processor. A processor herein may be one or more devices, circuits, and / or processing cores configured to process data (e.g., computer program instructions).

[0169] Among specific implementations, in one embodiment, computer system 2000 may include multiple processors, such as processor 2001 and processor 2005 shown in FIG. 15. Each of the processors may be a single-core (single-CPU) processor or a multi-core (multi-CPU) processor. A processor herein may be one or more devices, circuits, and / or processing cores configured to process data (e.g., computer program instructions).

[0170] During specific implementation, in one embodiment, the computer system 2000 may further include an output device and an input device. The output device communicates with the processor 2001 and may display information in multiple ways. For example, the output device may be a liquid crystal display (LCD), a light emitting diode (LED) display device, a cathode ray tube (CRT) display device, or a projector. The input device communicates with the processor 2001 and may receive user input in multiple ways. For example, the input device may be a mouse, a keyboard, a touchscreen device, or a sensor device.

[0171] In some embodiments, the memory 2003 is configured to store program code 2010 for performing the solutions of the present application, and the processor 2001 may execute the program code 2010 stored in the memory 2003. The program code 2010 may include one or more software modules. Optionally, the processor 2001 may also store program code or instructions for performing the solutions of the present application.

[0172] In a specific embodiment, the computer system 2000 in this embodiment of the present application may include the first module in the method embodiment described above. The processor 2001 in the computer system 2000 reads the program code 2010 in the memory 2003 or the program code or instructions stored in the processor 2001 to enable the computer system 2000 shown in FIG. 15 to perform all or a portion of the operations performed by the first module.

[0173] In a specific embodiment, the computer system 2000 in this embodiment of the present application may include the second module in the method embodiment described above. The processor 2001 in the computer system 2000 reads the program code 2010 in the memory 2003 or the program code or instructions stored in the processor 2001 to enable the computer system 2000 shown in FIG. 15 to perform all or a portion of the operations performed by the second module.

[0174] The computer system 2000 may further correspond to the devices shown in Figures 13 and 14. Each functional unit in the devices shown in Figures 13 and 14 is implemented by using software in the computer system 2000. In other words, the functional units included in the devices shown in Figures 13 and 14 are generated after the processor 2001 of the computer system 2000 reads the program code 2010 stored in the memory 2003.

[0175] The steps of the data transmission method shown in FIG. 8 are completed by hardware integrated logic circuits in the processor of the computer system 2000 or by instructions in the form of software. The steps of the methods disclosed with reference to the embodiments of the present application may be performed directly by the hardware processor or by a combination of hardware and software modules in the processor. The software modules may be located in a storage medium established in the art, such as random access memory, flash memory, read-only memory, programmable read-only memory, electrically erasable programmable memory, or registers. The storage medium is located in the memory, and the processor reads information in the memory and completes the steps of the aforementioned method in combination with the hardware in the processor. To avoid repetition, the details will not be described again here.

[0176] FIG. 16 is a diagram of another computer system structure according to an embodiment of the present application. The computer system is configured to perform operations associated with the first module or the second module in the data transmission method shown in FIG. 8. For example, the computer system may be a server, which may vary greatly due to different configurations or performance. The computer system may include one or more processors 1601 and one or more memories 1602. The one or more memories 1602 store at least one computer program, which is loaded and executed by the one or more processors 1601. For example, the processor 1601 may be a CPU. Of course, the computer system may further include components such as a wired or wireless network interface, a keyboard, and an input / output interface for input / output. The computer system may further include other components configured to implement device functions. Details will not be described herein.

[0177] An embodiment of the present application further provides a computer system. The computer system includes a processor. The processor includes a first module or a second module. The processor is configured to retrieve instructions stored in the memory from a memory and execute the instructions. If the processor includes the first module, the computer system performs a data transmission method performed by the first module. If the processor includes the second module, the computer system performs a data transmission method performed by the second module.

[0178] In one possible implementation, the computer system further includes an input interface, an output interface, and a memory, wherein the input interface, the output interface, the processor, and the memory are connected through an interconnection path.

[0179] An embodiment of the present application further provides a data transmission system. The data transmission system includes a first module and a second module. The first module is configured to perform the method performed by the first module shown in Figure 8, and the second module is configured to perform the method performed by the second module shown in Figure 8. For functions of the first module and the second module in the data transmission system, please refer to the related description shown in Figure 8. Details will not be described again in this specification.

[0180] An embodiment of the present application further provides a communications device. The device includes a transceiver, a memory, and a processor. The transceiver, the memory, and the processor communicate with each other through an internal connection path. The memory is configured to store instructions. The processor is configured to execute the instructions stored in the memory to control the transceiver to receive and transmit signals. The processor includes a first module or a second module. When the processor includes the first module, executing the instructions stored in the memory enables the processor to perform a data transmission method performed by the first module. When the processor includes the second module, executing the instructions stored in the memory enables the processor to perform a data transmission method performed by the second module.

[0181] It is to be understood that the processor may be a CPU, or may be another general-purpose processor, a DSP, an ASIC, an FPGA or other programmable logic device, a discrete gate or transistor logic device, a discrete hardware component, etc. The general-purpose processor may be a microprocessor, any conventional processor, etc. It is noted that the processor may also be a processor supporting an advanced reduced instruction set computing machine (advanced RISC machine, ARM) architecture.

[0182] Additionally, in some optional embodiments, the memory may include read-only memory and random access memory to provide instructions and data for the processor. The memory may further include non-volatile random access memory. For example, the memory may further store information regarding the device type.

[0183] The memory may be volatile or nonvolatile, or may include both volatile and nonvolatile memory. Nonvolatile memory may be ROM, programmable read-only memory (PROM), erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), or flash memory. Volatile memory may be RAM, acting as an external cache. By way of example and not limitation, many forms of RAM are available, such as static random access memory (SRAM), dynamic random access memory (DRAM), synchronous dynamic random access memory (SDRAM), double data rate synchronous dynamic random access memory (DDR SDRAM), enhanced synchronous dynamic random access memory (ESDRAM), synchlink dynamic random access memory (SLDRAM), and direct Rambus random access memory (DR RAM).

[0184] An embodiment of the present application further provides a computer-readable storage medium. The computer-readable storage medium stores at least one program instruction or code, and the program instruction or code is executed by a computer, the computer including a first module or a second module. When the computer includes the first module, the program instruction or code, when executed by the computer, enables the computer to perform the data transmission method performed by the first module. When the computer includes the second module, the program instruction or code, when executed by the computer, enables the computer to perform the data transmission method performed by the second module.

[0185] An embodiment of the present application further provides a computer program or computer program product. The computer program or computer program product includes computer program instructions or code that are executed by a computer, the computer including a first module and a second module. When the computer includes the first module, the computer program instructions or code, when executed by the computer, enable the computer to perform a data transmission method performed by the first module. When the computer includes the second module, the computer program instructions or code, when executed by the computer, enable the computer to perform a data transmission method performed by the second module.

[0186] An embodiment of the present application further provides a chip including a processor. The processor includes a first module or a second module, and the processor is configured to execute program instructions or codes. When the processor includes the first module, a device including the chip executes the data transmission method executed by the first module. When the processor includes the second module, a device including the chip executes the data transmission method executed by the second module.

[0187] For example, the chip further includes an input interface, an output interface, and a memory. The input interface, the output interface, the processor, and the memory are connected through interconnect paths. The memory includes program instructions or codes.

[0188] All or part of the above-described embodiments may be implemented by software, hardware, firmware, or any combination thereof. When software is used for implementation, all or part of the embodiments may be implemented in the form of a computer program or computer program product. A computer program or computer program product includes one or more computer instructions. When the computer program instructions are loaded and executed on a computer, all or part of the procedures or functions described herein are generated. The computer may be a general-purpose computer, a special-purpose computer, a computer network, or another programmable device. The computer instructions may be stored in a computer-readable storage medium or transmitted from a computer-readable storage medium to another computer-readable storage medium. For example, the computer instructions may be transmitted from a website, computer, server, or data center to another website, computer, server, or data center via wired (e.g., coaxial cable, fiber optic, or digital subscriber line) or wireless (e.g., infrared, radio, or microwave) transmission. A computer-readable storage medium may be any available medium that can be accessed by a computer, or a data storage device such as a server or data center that consolidates one or more available media. The available medium may be magnetic media (e.g., floppy disks, hard disks, or magnetic tapes), optical media (e.g., digital versatile disks (DVDs)), semiconductor media (e.g., solid-state drives (SSDs)), etc.

[0189] In the above embodiment, the unit of transmission rate is Gb / s, which may be abbreviated as G. For example, a rate of 400 Gb / s may be abbreviated as 400 G.

[0190] In order to clearly explain the compatibility of hardware and software, the steps and configurations of the embodiments are generally described in the preceding description based on functions. Whether a function is performed by hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art may use different methods to implement the described functions for each specific application, but such implementation should not be considered as going beyond the scope of the present application.

[0191] The computer program code used to implement the methods of the embodiments of the present application may be written in one or more programming languages. The computer program code may be provided to a processor of a general-purpose computer, a special-purpose computer, or another programmable data transmission device, so that when the program code is executed by the computer or another programmable data transmission device, the functions / acts specified in the flowcharts and / or block diagrams are implemented. The program code may run entirely on the computer, partially on the computer, as a stand-alone software package, partially on the computer and partially on a remote computer, or entirely on a remote computer or server.

[0192] In the context of the embodiments of the present application, computer program code or associated data may be carried on any suitable carrier that enables a device, apparatus, or processor to perform the various processes and operations described above. Examples of carriers include signals, computer-readable media, etc. Examples of signals may include electrical signals, optical signals, radio signals, audio signals, or other forms of propagated signals such as carrier waves and infrared signals.

[0193] For the sake of convenience, those skilled in the art can clearly understand that the detailed operation processes of the aforementioned systems, devices and modules may refer to the corresponding processes in the aforementioned method embodiments, and the details will not be described again in this specification.

[0194] In some embodiments provided herein, it should be understood that the disclosed systems, devices, and methods may be implemented in other manners. For example, the device embodiments described above are merely examples. For example, the division into modules is merely a logical division of function, and other divisions may be used in actual implementation. For example, multiple modules or components may be combined or integrated into another system, or some features may be ignored or not implemented. In addition, the shown or described mutual couplings or direct couplings or communication connections may be implemented through some interfaces. Indirect couplings or communication connections between devices or modules may be implemented electrically, mechanically, or in other ways.

[0195] Modules described as separate parts may or may not be physically separate, and parts denoted as modules may or may not be physical modules, i.e., they may be located in one location or distributed over multiple network modules. Some or all of the modules may be selected based on the actual needs to achieve the objectives of the solutions of the embodiments of the present application.

[0196] In addition, the functional modules in the embodiments of the present application may be integrated into one processing module, and each module may exist physically alone, or two or more modules may be integrated into one module. The integrated module may be implemented in the form of hardware or in the form of a software functional module.

[0197] In this application, terms such as "first" and "second" are used to distinguish between the same item or similar items having essentially the same function. It should be understood that there is no logical or time sequence dependency between "first," "second," and "nth," and that the quantities and execution order are not limited. While the following description uses terms such as "first" and "second" to describe various elements, it should be further understood that these elements should not be limited by these terms. These terms are used merely to distinguish one element from another. For example, a first module may be referred to as a second module, and similarly, a second module may be referred to as a first module, without departing from the scope of various examples.

[0198] It should be further understood that the sequence numbers of the processes do not mean the execution sequence in the embodiments of the present application, and the execution sequence of the processes should be determined based on the functions and internal logic of those processes, and should not constitute any limitation on the implementation process of the embodiments of the present application.

[0199] As used herein, the term "at least one" means one or more, and the term "plurality" as used herein means two or more. For example, a plurality of code blocks means two or more code blocks. The terms "system" and "network" are often used interchangeably herein.

[0200] It should be understood that the terminology used in the description of the various examples herein is intended to describe particular examples only and is not intended to constitute limitations. For example, the singular forms "a" and "an" and "the," as used in the descriptions of the various examples and the appended claims, are intended to include the plural forms unless the context clearly dictates otherwise.

[0201] It will be further understood that the term "include" (also referred to as "includes," "including," "comprises," and / or "comprising") as used herein specifies the presence of stated features, integers, steps, operations, elements, and / or components, and does not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or combinations thereof.

[0202] Furthermore, it should be understood that, depending on the context, the phrases "when it is determined that" or "when [the described condition or event] is detected" may be interpreted to mean "when it is determined that," "in response to determining that," "when [the described condition or event] is detected," or "in response to detecting [the described condition or event]."

[0203] It should be understood that determining B based on A does not mean that B is determined based only on A. B may alternatively be determined based on A and / or other information.

[0204] It should be further understood that references throughout this specification to "one embodiment," "an embodiment," and "possible implementations" mean that a particular feature, structure, or characteristic associated with an embodiment or implementation is included in at least one embodiment of the present application. Thus, the appearances of "one embodiment," "an embodiment," or "possible implementations" throughout this specification do not necessarily refer to the same embodiment. In addition, these particular features, structures, or characteristics may be combined in any suitable manner in one or more embodiments.

Claims

1. 1. A data transmission method, the method comprising: performing, by a first module, convolutional interleaving on symbols included in a plurality of obtained first code words to obtain interleaved results, wherein the first code words are obtained by encoding first data by using a first forward error correction (FEC) code; obtaining second data including identification information based on the interleaving result, where, when the second data includes a second code word, the identification information includes code word boundary information of the second code word; transmitting the second data to a second module; A method comprising:

2. The step of performing convolutional interleaving on symbols included in the plurality of obtained first code words to obtain an interleaved result includes: inputting symbols included in the plurality of first codewords into a plurality of first delay units of a convolutional interleaver, and performing convolutional interleaving on the symbols included in the plurality of first codewords and obtained through round robin through the plurality of first delay units to obtain a plurality of first bit groups output by the plurality of first delay units through round robin, wherein one first bit group includes symbols output by the plurality of first delay units through one round robin; using the plurality of first bit groups output by the plurality of first delay units through a round robin as the interleaving result; The method of claim 1 , comprising:

3. The interleaving result includes n first bit groups output by the plurality of first delay units through n round robin rounds, and the step of obtaining second data including identification information based on the interleaving result includes: encoding the n first bit groups output by the plurality of first delay units through n-time round-robin based on a second FEC code to obtain m second codewords, where the number of bits corresponding to the n first bit groups is equal to the number of bits included in information bits of the m codewords of the second FEC code, and m and n are both positive integers, and m is less than or equal to n; obtaining the second data based on the m second code words; The method of claim 2 , comprising:

4. The second data does not include the second code word, and the interleaving result includes n first bit groups output by the plurality of first delay units through n-time round robin, and the step of obtaining second data including identification information based on the interleaving result includes: obtaining k target data frames based on a format of a reference data frame and the n first bit groups output by the plurality of first delay units through n-time round robin, wherein the target data frames include frame synchronization information, the frame synchronization information is used as the identification information, the number of bits corresponding to the n first bit groups is less than or equal to the number of bits included in the k target data frames, k and n are both positive integers, and k is less than or equal to n; acquiring the second data based on the k target data frames; The method of claim 2 , comprising:

5. The step of performing convolutional interleaving on symbols included in the second data and the plurality of obtained first code words to obtain an interleaving result, wherein the second data does not include the second code word, includes: inputting at least one piece of identification information and symbols included in the plurality of first codewords into a plurality of first delay units of a convolutional interleaver, and performing convolutional interleaving on the at least one piece of identification information obtained through round robin and the symbols included in the plurality of first codewords obtained through round robin via the plurality of first delay units to obtain a plurality of second bit groups output by the plurality of first delay units through round robin, wherein at least one second bit group includes symbols output by the plurality of first delay units through one round robin, or at least one second bit group includes symbols and identification information output by the plurality of first delay units through one round robin, and the identification information indicates a starting interleaving position at which convolutional interleaving is performed on symbols included in the plurality of first codewords; using the second bit groups output by the first delay units through a round robin as the interleaving result; The method of claim 1 , comprising:

6. 6. The method according to claim 2, wherein a starting interleaving position at which the convolutional interleaving is performed on symbols included in the plurality of first codewords is within any one of the plurality of first delay units.

7. 7. The method according to claim 2, wherein symbols included in the plurality of first codewords are input to the plurality of first delay units of the convolutional interleaver in the form of a first data stream, and a transmission rate of the first data stream is equal to or greater than 100 gigabits per second.

8. 8. The method of claim 7, wherein the first data stream is transmitted to the plurality of first delay units of the convolutional interleaver through at least one lane of an attachment unit interface (AUI).

9. 1. A data transmission method, the method comprising: receiving, by a second module, second data transmitted by the first module, the second data including identification information, the second data being obtained based on an interleaving result obtained by performing convolutional interleaving on symbols included in a plurality of first code words, the first code words being obtained by encoding the first data by using a first forward error correction (FEC) code, and when the second data includes a second code word, the identification information includes code word boundary information of the second code word; obtaining, based on the identification information, data to be deinterleaved in the second data and a start interleaving position at which the convolutional interleaving is performed on symbols included in the plurality of first codewords; performing convolutional deinterleaving on the data to be deinterleaved based on the start interleaving position to obtain the plurality of first codewords; A method comprising:

10. The step of obtaining, based on the identification information, data to be deinterleaved in the second data and a start interleaving position at which the convolutional interleaving is performed on symbols included in the plurality of first codewords includes: obtaining at least one second code word included in the second data based on the code word boundary information of the second code word; obtaining a starting position of the at least one second codeword and using the starting position as a starting interleaving position at which the convolutional interleaving is performed on symbols included in the plurality of first codewords; decoding the at least one second codeword to obtain the data to be deinterleaved; 10. The method of claim 9, comprising:

11. When the second data does not include the second codeword, the identification information is frame synchronization information, and the step of obtaining, based on the identification information, data to be deinterleaved in the second data and a start interleaving position at which the convolutional interleaving is performed on symbols included in the plurality of first codewords, includes: obtaining at least one target data frame included in the second data based on the frame synchronization information; obtaining a starting position of frame data of the at least one target frame of data and using the starting position as the starting interleaving position at which the convolutional interleaving is performed on symbols included in the plurality of first codewords; and using the frame data included in the at least one target data frame as the data to be deinterleaved.

10. The method of claim 9.

12. The deinterleaving target data includes a plurality of third bit groups, and one third bit group includes symbols of the first codeword output by a plurality of first delay units of a convolutional interleaver through one round robin, and the step of performing convolutional deinterleaving on the deinterleaving target data based on the start interleaving position to obtain the plurality of first codewords includes: obtaining a starting deinterleave position corresponding to the starting interleave position and located within a plurality of second delay units of a convolutional deinterleaver; inputting the third bit groups into the second delay units at the start deinterleaving position, and performing convolutional deinterleaving on symbols included in the third bit groups and obtained through round robin via the second delay units; obtaining the symbols included in the plurality of first codewords output by the plurality of second delay units through a round robin process, and obtaining the plurality of first codewords based on the symbols included in the plurality of first codewords; 12. The method of claim 10 or 11, comprising:

13. When the second data does not include the second codeword, the identification information indicates the start interleaving position at which the convolutional interleaving is performed on symbols included in the plurality of first codewords; The step of obtaining, based on the identification information, data to be deinterleaved in the second data and a start interleaving position at which the convolutional interleaving is performed on symbols included in the plurality of first codewords includes: obtaining the starting interleaving position at which the convolutional interleaving is performed on symbols included in the plurality of first codewords indicated by the identification information; using the data at the start interleaving position and the data after the start interleaving position in the second data as the data to be deinterleaved.

10. The method of claim 9.

14. the deinterleaved data includes a plurality of fourth bit groups, at least one fourth bit group including symbols of the first codeword output by a plurality of first delay units of a convolutional interleaver through a round robin once, or at least one fourth bit group including symbols and identification information output by a plurality of first delay units through a round robin once; The step of performing convolutional deinterleaving on the deinterleaving target data based on the start interleaving position to obtain the plurality of first codewords includes: obtaining start deinterleaving positions in a plurality of second delay units of a convolutional deinterleaver corresponding to the start interleaving positions; inputting the plurality of fourth bit groups to the plurality of second delay units at the start deinterleaving position, and performing convolutional deinterleaving on the symbols included in the plurality of fourth bit groups and obtained through round robin, or on the symbols included in the plurality of fourth bit groups and obtained through round robin and identification information, via the plurality of second delay units; obtaining symbols included in the plurality of first code words output by the plurality of second delay units through a round robin process and the identification information, and obtaining the plurality of first code words based on the symbols included in the plurality of first code words; 14. The method of claim 13, comprising:

15. The method of claim 12 or 14, wherein the starting deinterleaving position is within any one of the plurality of second delay units.

16. 16. The method of claim 12, wherein the plurality of second delay units of the convolutional deinterleaver output the symbols included in the plurality of first codewords in the form of a second data stream, and a transmission rate of the second data stream is equal to or greater than 100 gigabits per second.

17. 17. The method of claim 16, wherein the plurality of second delay units of the convolutional deinterleaver output the second data stream through at least one lane of an attachment unit interface (AUI).

18. 1. A data transmission device for use in a first module, the device comprising: an interleaving unit configured to perform convolutional interleaving on symbols included in a plurality of obtained first code words to obtain interleaved results, wherein the first code words are obtained by encoding first data by using a first forward error correction (FEC) code; an acquiring unit configured to acquire second data including identification information based on the interleaving result, where, when the second data includes a second code word, the identification information includes code word boundary information of the second code word; a transmitting unit configured to transmit the second data to a second module; An apparatus having:

19. 19. The apparatus of claim 18, wherein the interleaving unit is configured to: input symbols included in the plurality of first codewords to a plurality of first delay units of a convolutional interleaver; perform convolutional interleaving on symbols included in the plurality of first codewords and obtained through round robin through the plurality of first delay units to obtain a plurality of first bit groups output by the plurality of first delay units through round robin, wherein one first bit group includes symbols output by the plurality of first delay units through round robin once; and use the plurality of first bit groups output by the plurality of first delay units through round robin as the interleaving result.

20. 20. The apparatus of claim 19, wherein the interleaving result includes n first bit groups output by the plurality of first delay units through n-time round robin, and the obtaining unit is configured to perform the steps of: encoding the n first bit groups output by the plurality of first delay units through n-time round robin based on a second FEC code to obtain m second codewords, wherein a number of bits corresponding to the n first bit groups is equal to a number of bits included in information bits of the m codewords of the second FEC code, where m and n are both positive integers and m is less than or equal to n; and obtaining the second data based on the m second codewords.

21. 20. The apparatus of claim 19, wherein the second data does not include the second code word, and the interleaving result includes n first bit groups output by the plurality of first delay units through n-time round robin, and the acquisition unit is configured to perform the steps of: acquiring k target data frames based on a format of a reference data frame and the n first bit groups output by the plurality of first delay units through n-time round robin, wherein the target data frames include frame synchronization information, the frame synchronization information is used as the identification information, a number of bits corresponding to the n first bit groups is less than or equal to a number of bits included in the k target data frames, k and n are both positive integers and less than or equal to n; and acquiring the second data based on the k target data frames.

22. The second data does not include the second codeword, and the interleaving unit: inputs at least one piece of identification information and symbols included in the plurality of first codewords to a plurality of first delay units of a convolutional interleaver; and performs convolutional interleaving on the at least one piece of identification information obtained through round robin and the symbols included in the plurality of first codewords obtained through round robin via the plurality of first delay units to obtain a plurality of second bit groups output by the plurality of first delay units through round robin, 19. The apparatus of claim 18, wherein a group includes symbols output by the plurality of first delay units through one round robin, or at least one second bit group includes symbols output by the plurality of first delay units through one round robin and identification information, the identification information indicating a starting interleaving position at which convolutional interleaving is performed on symbols included in the plurality of first codewords; and a step of using the plurality of second bit groups output by the plurality of first delay units through round robin as the interleaving result.

23. 23. The apparatus of claim 19, wherein a starting interleaving position at which the convolutional interleaving is performed on symbols included in the plurality of first codewords is within any one of the plurality of first delay units.

24. 24. The apparatus according to claim 19, wherein symbols included in the plurality of first codewords are input to the plurality of first delay units of the convolutional interleaver in the form of a first data stream, and a transmission rate of the first data stream is equal to or greater than 100 gigabits per second.

25. 25. The apparatus of claim 24, wherein the first data stream is transmitted to the plurality of first delay units of the convolutional interleaver through at least one lane of an attachment unit interface (AUI).

26. A data transmission device for use in a second module, the device comprising: an acquiring unit configured to receive second data transmitted by a first module, the second data including identification information, the second data being acquired based on an interleaving result acquired by performing convolutional interleaving on symbols included in a plurality of first code words, the first code words being acquired by encoding the first data by using a first forward error correction (FEC) code, and when the second data includes a second code word, the identification information includes code word boundary information of the second code word; an obtaining unit further configured to obtain, based on the identification information, data to be deinterleaved in the second data and a start interleaving position at which the convolutional interleaving is performed on symbols included in the plurality of first codewords; a deinterleaving unit configured to perform convolutional deinterleaving on the deinterleaved data based on the starting interleaving position to obtain the plurality of first codewords; An apparatus having:

27. 27. The apparatus of claim 26, wherein the obtaining unit is configured to: obtain at least one second codeword included in the second data based on the codeword boundary information of the second codeword; obtain a starting position of the at least one second codeword and use the starting position as a starting interleaving position at which the convolutional interleaving is performed on symbols included in the plurality of first codewords; and decode the at least one second codeword to obtain the data to be deinterleaved.

28. 27. The apparatus of claim 26, wherein, when the second data does not include the second code word, the identification information is frame synchronization information, and the acquisition unit is configured to: acquire at least one target data frame included in the second data based on the frame synchronization information; acquire a starting position of frame data of the at least one target data frame and use the starting position as the starting interleaving position at which the convolutional interleaving is performed on symbols included in the plurality of first code words; and use the frame data included in the at least one target data frame as the data to be deinterleaved.

29. 29. The apparatus of claim 27, wherein the data to be deinterleaved includes a plurality of third bit groups, each of which includes symbols of the first codeword output by a plurality of first delay units of a convolutional interleaver through a round robin once, and the deinterleaving unit is configured to perform the following steps: obtain a start deinterleaving position corresponding to the start interleaving position and located among a plurality of second delay units of the convolutional deinterleaver; input the plurality of third bit groups into the plurality of second delay units at the start deinterleaving position and perform convolutional deinterleaving on symbols included in the plurality of third bit groups and obtained through round robin via the plurality of second delay units; and obtain the symbols included in the plurality of first codewords output by the plurality of second delay units through round robin, and obtain the plurality of first codewords based on the symbols included in the plurality of first codewords.

30. 27. The apparatus of claim 26, wherein, when the second data does not include the second code word, the identification information indicates the starting interleaving position at which the convolutional interleaving is performed on symbols included in the plurality of first code words, and the obtaining unit is configured to: obtain the starting interleaving position at which the convolutional interleaving is performed on symbols included in the plurality of first code words indicated by the identification information; and use data at the starting interleaving position and data after the starting interleaving position in the second data as the data to be deinterleaved.

31. The deinterleaving target data includes a plurality of fourth bit groups; at least one fourth bit group includes symbols of the first codeword output by a plurality of first delay units of a convolutional interleaver through one round robin, or at least one fourth bit group includes symbols and identification information output by a plurality of first delay units through one round robin; the deinterleaving unit: obtains a start deinterleaving position in a plurality of second delay units of a convolutional deinterleaver corresponding to the start deinterleaving position; and 31. The apparatus of claim 30, configured to: input bit groups into the plurality of second delay units, and perform convolutional deinterleaving on symbols included in the plurality of fourth bit groups and obtained through round robin, or on symbols included in the plurality of fourth bit groups and obtained through round robin and identification information, via the plurality of second delay units; and obtain symbols included in the plurality of first codewords and the identification information output by the plurality of second delay units through round robin, and obtain the plurality of first codewords based on the symbols included in the plurality of first codewords.

32. 32. The apparatus of claim 29 or 31, wherein the starting deinterleaving position is within any one of the plurality of second delay units.

33. 33. The apparatus of claim 29, 31, or 32, wherein the plurality of second delay units of the convolutional deinterleaver output the symbols included in the plurality of first codewords in the form of a second data stream, and a transmission rate of the second data stream is equal to or greater than 100 gigabits per second.

34. 34. The apparatus of claim 33, wherein the plurality of second delay units of the convolutional deinterleaver output the second data stream through at least one lane of an attachment unit interface (AUI).

35. 18. A data transmission system comprising a first module and a second module, the first module being configured to perform the method of any one of claims 1 to 8, and the second module being configured to perform the method of any one of claims 9 to 17.

36. A computer system, the computer system having a processor, the processor having a first module or a second module, wherein if the processor has the first module, the computer system performs the method of any one of claims 1 to 8 when the processor executes program instructions or code, or if the processor has the second module, the computer system performs the method of any one of claims 9 to 17 when the processor executes program instructions or code.

37. 37. The computer system of claim 36, further comprising a memory, said memory configured to store said program instructions or said code.

38. 19. A computer-readable storage medium storing at least one program instruction or code, the program instruction or code being executable by a computer, the computer having a first module or a second module, wherein if the computer has the first module, the program instruction or code, when executed by the computer, enables the computer to perform the method of any one of claims 1 to 8, or if the computer has the second module, the program instruction or code, when executed by the computer, enables the computer to perform the method of any one of claims 9 to 17.

39. 19. A computer program product comprising computer program instructions or code, the computer program instructions or code being executed by a computer, the computer having a first module or a second module, the computer having the first module, the computer program instructions or code being executed by the computer to enable the computer to perform the method of any one of claims 1 to 8, or the computer having the second module, the computer program instructions or code being executed by the computer to enable the computer to perform the method of any one of claims 9 to 17.

40. A chip having a processor, the processor having a first module or a second module, the processor configured to execute program instructions or code, and wherein if the processor has the first module, a device having the chip performs a method according to any one of claims 1 to 8, or if the processor has the second module, a device having the chip performs a method according to any one of claims 9 to 17.

41. 41. The chip of claim 40, further comprising an input interface, an output interface, and a memory, wherein the input interface, the output interface, the processor, and the memory are connected through interconnect paths, and the memory contains the program instructions or the code.

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