Backside Interface for Chiplet Architecture Mixing

Abstract

The disclosed semiconductor package includes a first chiplet region for receiving a first chiplet, a second chiplet region for receiving a second chiplet, and a host die coupled to the first chiplet region and the second chiplet region. The semiconductor package also includes an interconnect directly coupling the first chiplet region to the second chiplet region. Various other methods, systems, and computer-readable media are also disclosed.

Description

[Background technology]

[0001] Silicon chip manufacturing often becomes nonlinearly expensive as chip size increases. For example, manufacturing larger chips has lower yields because manufacturing defects require the scrapping of larger chips. Therefore, to improve yield and manufacturing costs, larger chips may be redesigned into multiple smaller chips (e.g., chiplets). Chiplets often interface with a host die to coordinate communication between the chiplets and with other components off-die.

[0002] The accompanying drawings illustrate several exemplary embodiments and are a part of this specification and, together with the following description, demonstrate and explain various principles of the present disclosure. [Brief explanation of the drawings]

[0003] [Figure 1] FIG. 1 is a block diagram of an example system of backside interfaces for chiplet architecture mixing. [Figure 2] FIG. 1 is a simplified diagram of a layout of chiplet areas around a host die. [Figure 3A] FIG. 1 is a simplified diagram of an exemplary chiplet architecture using a backside interface. [Figure 3B] FIG. 1 is a simplified diagram of an exemplary chiplet architecture using a backside interface. [Figure 3C] FIG. 1 is a simplified diagram of an exemplary chiplet architecture using a backside interface. [Figure 3D] FIG. 1 is a simplified diagram of an exemplary chiplet architecture using a backside interface. [Figure 3E] FIG. 1 is a simplified diagram of an exemplary chiplet architecture using a backside interface. [Figure 3F]FIG. 1 is a simplified diagram of an exemplary chiplet architecture using a backside interface. [Figure 3G] FIG. 1 is a simplified diagram of an exemplary chiplet architecture using a backside interface. [Figure 3H] FIG. 1 is a simplified diagram of an exemplary chiplet architecture using a backside interface. [Figure 3I] FIG. 1 is a simplified diagram of an exemplary chiplet architecture using a backside interface. [Figure 3J] FIG. 1 is a simplified diagram of an exemplary chiplet architecture using a backside interface. [Figure 4] FIG. 1 is a simplified side view of a backside interface for chiplet architecture mixing. DETAILED DESCRIPTION OF THE INVENTION

[0004] Throughout the drawings, like reference numerals and descriptions indicate similar, but not necessarily identical, elements. While the exemplary embodiments described herein are susceptible to various modifications and alternative forms, specific embodiments have been shown by way of example in the drawings and are described in detail herein. However, the exemplary embodiments described herein are not intended to be limited to the particular forms disclosed. Rather, the present disclosure covers all modifications, equivalents, and alternatives falling within the scope of the appended claims.

[0005] The present disclosure is generally directed to backside interfaces for chiplet architecture mixing. As described in more detail below, embodiments of the present disclosure include at least first and second chiplet regions for receiving chiplets and a host die having interfaces with each of the first and second chiplet regions to enable connection to the chiplets received in the first and second chiplet regions. Embodiments of the present disclosure further include interconnects directly coupling the first chiplet region to the second chiplet region to enable direct connection between the chiplets received in the first and second chiplet regions.

[0006] As described in more detail below, this disclosure describes various systems and methods for chiplet architecture mixing that use backside interfaces, which allow for direct connections between chiplets by bypassing the host die.

[0007] In one embodiment, a semiconductor package for chiplet architecture mixing includes a first chiplet region for receiving a first chiplet, a second chiplet region for receiving a second chiplet, a host die coupled to the first chiplet region and the second chiplet region, and an interconnect directly coupling the first chiplet region to the second chiplet region.

[0008] In some examples, the semiconductor package further includes a first chiplet in the first chiplet region and a second chiplet in the second chiplet region. In some examples, the first chiplet communicates with the host die using a first communication protocol, and the first chiplet communicates with the second chiplet using a second communication protocol via the interconnect. In some examples, the first protocol and the second communication protocol operate at different clock speeds. In some examples, the second chiplet includes circuitry for disabling the interconnect. In some examples, the circuitry includes a ground.

[0009] In one embodiment, a device for chiplet architecture mixing includes a host die, a plurality of chiplets positioned around the host die and each coupled to the host die, and an interconnect directly coupling a first chiplet of the plurality of chiplets to a second chiplet of the plurality of chiplets.

[0010] In some examples, the multiple chiplets communicate with the host die using a first communication protocol, and the first chiplet communicates with a second chiplet via the interconnect using a second communication protocol, and in some examples, the first communication protocol and the second communication protocol operate at different clock speeds.

[0011] In some examples, the second chiplet comprises circuitry for disabling the interconnect. In some examples, the device further includes a passive device and a second interconnect directly coupling the passive device to any of the plurality of chiplets. In some examples, the passive device is not coupled to the host die.

[0012] In some examples, the first chiplet is adjacent to the second chiplet. In some examples, the first chiplet is not adjacent to the second chiplet.

[0013] In one embodiment, a system for chiplet architecture mixing includes a host die and a plurality of chiplets positioned around the host die and each coupled to the host die through an interconnect interface. Each of the plurality of chiplets communicates with the host die using a first communication protocol via the interconnect interface. The system also includes an interconnect directly coupling a first chiplet of the plurality of chiplets to a second chiplet of the plurality of chiplets. The first chiplet communicates with the second chiplet using a second communication protocol via the interconnect.

[0014] In some examples, the first communication protocol and the second communication protocol operate at different clock speeds. In some examples, the second chiplet includes circuitry for disabling the interconnect. In some examples, the circuitry includes a ground. In some examples, the system further includes a passive device and a second interconnect directly coupling the passive device to any of the plurality of chiplets. In some examples, the passive device is not coupled to a host die.

[0015] In some examples, the first chiplet is adjacent to the second chiplet. In some examples, the first chiplet is not adjacent to the second chiplet.

[0016] Features from any of the embodiments described herein may be used in combination with each other in accordance with the general principles described herein. These and other embodiments, features, and advantages will be more fully understood from the following detailed description read in conjunction with the accompanying drawings and claims.

[0017] Below, a detailed description of interfaces and layouts for chiplet architecture mixing is provided with reference to Figures 1-4. A detailed description of an exemplary system for chiplet architecture mixing is provided with reference to Figures 1 and 2. A detailed description of an exemplary layout and corresponding interfaces is provided with reference to Figures 3A-3J. A detailed description of an exemplary backside interface is provided with reference to Figure 4.

[0018] 1 is a block diagram of an example system 100 for a chiplet architecture. System 100 corresponds to a computing device, such as a desktop computer, a laptop computer, a server, a tablet device, a mobile device, a smartphone, a wearable device, an augmented reality device, a virtual reality device, a network device, and / or an electronic device. As shown in FIG. 1 , system 100 includes one or more memory devices, such as memory 120. Memory 120 generally represents any type or form of volatile or non-volatile storage device or medium capable of storing data and / or computer-readable instructions. Examples of memory 120 include, but are not limited to, random access memory (RAM), read-only memory (ROM), flash memory, hard disk drive (HDD), solid-state drive (SSD), optical disk drive, cache, any variation or combination of one or more of these, and / or any other suitable storage memory.

[0019] 1, exemplary system 100 includes one or more physical processors, such as processor 110. Processor 110 generally represents any type or form of hardware-implemented processing unit capable of interpreting and / or executing computer-readable instructions. In some examples, processor 110 accesses and / or modifies data and / or instructions stored in memory 120. Examples of processor 110 include, but are not limited to, a microprocessor, a microcontroller, a central processing unit (CPU), a graphics processing unit (GPU), a field-programmable gate array (FPGA) implementing a soft-core processor, an application-specific integrated circuit (ASIC), a system on a chip (SoC), a digital signal processor (DSP), a neural network engine (NNE), an accelerator, a graphics processing unit (GPU), one or more portions thereof, one or more variations or combinations thereof, and / or any other suitable physical processor.

[0020] As further shown in FIG. 1 , processor 110 includes host die 130, chiplets 142, 144, and interconnects 152. Host die 130 corresponds to a host die, such as an input / output die (IOD) or other central die, for coordinating the inputs and outputs of various chiplets, such as chiplet 142 and chiplet 144. For example, host die 130 has separate connections to each of chiplet 142 and chiplet 144. Chiplet 142 and chiplet 144 are each chiplets (e.g., small integrated circuits designed for a specific function or a subset of functions that can cooperate as a single, larger integrated circuit). Chiplet 142 and chiplet 144 can be identical or similarly designed chiplets, although in other examples, chiplet 142 and chiplet 144 may be differently designed. Chiplet 142 and chiplet 144 can cooperate to improve performance, for example, by communicating through host die 130. Thus, host die 130 utilizes a standard interface and a standard communication protocol to be compatible with various chiplets, and chiplet 142 and chiplet 144 can communicate with each other using the standard communication protocol as relayed through host die 130.

[0021] 2 illustrates a simplified exemplary layout of a semiconductor package 200 corresponding to system 100 and / or processor 110. Semiconductor package 200 includes host die 230 corresponding to host die 130, chiplet region 232, chiplet region 234, and interface 262. Chiplet region 232 and chiplet region 234 are chiplet areas or mounting locations for receiving chiplets, such as chiplet 142 and chiplet 144. For example, chiplet 142 may be located in chiplet region 232, and chiplet 144 may be located in chiplet region 234. Each chiplet region further includes an interface 262 coupled to host die 230. Interface 262, which in some examples is a die-to-die (D2D) interface or other interconnect interface, includes connection points for coupling to host die 230, such as via metal wires, contacts, etc.

[0022] As described herein, the host die 230 interfaces with and coordinates communication for the various chiplets. Accordingly, chiplet regions, such as chiplet region 232 and chiplet region 234, are disposed or positioned around the host die 230. Additionally, while FIG. 2 illustrates chiplet regions around two sides of the host die 230, in other examples, the chiplet regions can be around additional or fewer sides. In some examples, the chiplet regions are disposed adjacent to the host die 230 to reduce the length of the interface 262 and improve latency. However, as shown in FIG. 2, the chiplet regions only include an interface to the host die 230, and as a result, communication between chiplets must be routed through the host die 230. In some examples, inter-chiplet communication does not require off-chip communication, as the host die 230 may be a bottleneck in terms of power, latency, etc., for inter-chiplet communication. Furthermore, inter-chiplet communication through the host die 230 requires sending / receiving signals using a standard communication protocol compatible with the host die 230. For example, a first chiplet in chiplet area 232 and a second chiplet in chiplet area 234 must convert data and / or signals to a standard communication protocol for transmission through host die 230.

[0023] 3A-3J illustrate various exemplary chiplet architectures. FIG. 3A illustrates a semiconductor package 300 corresponding to system 100 and / or processor 110. Semiconductor package 300 includes a host die 330 corresponding to host die 130 and / or host die 230, a chiplet region 332 corresponding to chiplet region 232, a chiplet region 334 corresponding to chiplet region 234, an interface 362 corresponding to interface 162 and / or interface 262, and an interconnect 352 corresponding to interconnect 152. Interconnect 352 enables direct communication between the connected chiplets. For example, in FIG. 3A , interconnect 352 directly couples chiplet region 332 to chiplet region 334, enabling direct inter-chiplet communication between a first chiplet in chiplet region 332 and a second chiplet in chiplet region 334, as indicated by the arrows.

[0024] Additionally, the interconnect 352 allows the first and second chiplets to communicate with each other using a communication protocol that differs from the standard communication protocol used with the host die 330. The first and second chiplets can communicate directly using the standard communication protocol, but a custom communication protocol can reduce latency. For example, the first and second chiplets can communicate data, addresses, and / or other signals directly without having to first convert to the standard communication protocol. The first and second chiplets can use a communication protocol that operates at a clock speed that differs from the clock speed of the standard communication protocol. The first and second chiplets can customize how the interconnect 352 is used, as described further below.

[0025] 4 shows a side view of semiconductor package 400 corresponding to semiconductor package 300. Semiconductor package 400 includes a package substrate 412, a chiplet 442 corresponding to chiplet 142, a chiplet 444 corresponding to chiplet 144, an interface 462 corresponding to interface 162, interface 262, and / or interface 362, and an interconnect 452 corresponding to interconnect 152 and / or interconnect 352. As shown in FIG. 4 , interconnect 452 is a backside interconnect or backside link, for example, provided as one or more pre-mounted metal paths / wires on package substrate 412. In some examples, interconnect 452 includes multiple metal paths between chiplet 442 and chiplet 444.

[0026] Chiplet 442 includes control circuitry 482, and chiplet 444 includes control circuitry 484. Control circuitry 482 and control circuitry 484 allow each of chiplets 442 and 444 to customize how they use interconnect 452, such as by establishing a custom communication protocol between chiplets 442 and 444. For example, some metal paths in interconnect 452 can be used to transmit data signals, other paths can be used to transmit address signals, etc. Control circuitry 482 and / or control circuitry 484 can establish a clock speed for transmitting / receiving signals. In some examples, control circuitry 482 and control circuitry 484 can work in conjunction to utilize interconnect 452.

[0027] In some examples, control circuitry 482 and / or control circuitry 44 can disable one or more of the paths. For example, control circuitry 482 can include a ground connection, and control circuitry 484 can include switches to disable one or more paths. In some examples, control circuitry 482 and / or control circuitry 484 can disable all paths in interconnect 452, effectively disabling interconnect 452. For example, if chiplet 442 does not require direct coupling to chiplet 444, interconnect 452 can be disabled.

[0028] In yet other examples, chiplet 442 and / or chiplet 444 may include additional control circuitry for controlling additional interconnects. For example, as described further herein, chiplet 442 may be directly coupled to multiple chiplets via interconnects. Based on the chiplet architecture (e.g., which chiplets communicate with each other), the control circuitry can enable / disable corresponding interconnects as needed.

[0029] 3B, which illustrate various exemplary alternative layouts for semiconductor package 300. FIG. 3B illustrates semiconductor package 301 corresponding to system 100, processor 110, and / or semiconductor package 300. In FIG. 3B, chiplet 342 (corresponding to chiplet 142) is attached to chiplet region 332. Chiplet 342 is therefore connected to both interface 362 and interconnect 352. Interconnect 352 does not modify or alter interface 362 to enable chiplet 342 to communicate with host die 330 (e.g., via a standard communication protocol).

[0030] FIG. 3C illustrates a semiconductor package 302 corresponding to system 100, processor 110, and / or semiconductor package 300. FIG. 3C illustrates interconnects 352 between adjacent chiplets. In FIG. 3C, chiplet 344 (corresponding to chiplet 144) is attached to chiplet region 334. Chiplet 342 communicates directly with chiplet 344 via interconnect 352 (e.g., via a custom communication protocol), as indicated by the arrows. Additionally, each of chiplets 342 and 344 can communicate with host die 330 (e.g., via a standard communication protocol) as needed.

[0031] FIG. 3D illustrates a semiconductor package 303 corresponding to system 100, processor 110, and / or semiconductor package 300. FIG. 3D illustrates interconnections between multiple adjacent chiplets. Chiplet 346 and chiplet 348 are also attached in FIG. 3D. Interconnect 354 directly couples chiplet 344 to chiplet 346. Interconnect 356 directly couples chiplet 346 to chiplet 348. Chiplet 342, chiplet 344, chiplet 346, and chiplet 348 can communicate directly with each other (e.g., via a custom communication protocol) via interconnect 352, interconnect 354, and interconnect 356, as indicated by arrows. Additionally, each of chiplet 342, chiplet 344, chiplet 346, and chiplet 348 can communicate with host die 330 (e.g., via a standard communication protocol) as needed. Furthermore, in some examples, chiplet 342, chiplet 344, chiplet 346, and chiplet 348 may all communicate using the same communication protocol, or may use different communication protocols (e.g., between adjacent chiplets).

[0032] FIG. 3E illustrates a semiconductor package 304 corresponding to system 100, processor 110, and / or semiconductor package 300. FIG. 3E illustrates how chiplet communication can be customized, for example, by disabling interconnects to establish separate chiplet groups (e.g., pairs). In FIG. 3E, interconnect 354 is disabled so that chiplet 342 and chiplet 344 can communicate directly with each other, and chiplet 346 and chiplet 348 can communicate directly with each other, as indicated by the respective arrows. In some examples, chiplet 342 and chiplet 344 communicate using a communication protocol that is different from the communication protocol of chiplet 346 and chiplet 348. In some examples, unlike FIG. 3D, the pair of chiplets cannot communicate directly but can communicate through host die 330 if necessary. Alternatively, interconnect 354 is enabled to allow the pair to communicate (e.g., via a third communication protocol).

[0033] 3F illustrates semiconductor package 305, which corresponds to system 100, processor 110, and / or semiconductor package 300. FIGURE 3F illustrates interconnections between non-adjacent chiplets. For example, interconnect 353 directly couples chiplet 342 to chiplet 346, and interconnect 355 directly couples chiplet 344 to chiplet 348. Other interconnects can be enabled / disabled as needed.

[0034] FIG. 3G illustrates a semiconductor package 306 corresponding to system 100, processor 110, and / or semiconductor package 300. FIG. 3G illustrates another example of directly coupling non-adjacent chiplets. For example, chiplet 341 is positioned on an adjacent side of host die 330, as is chiplet 342. Interconnect 358 directly couples chiplet 342 and chiplet 344, and other interconnects can be enabled / disabled as needed. Additionally, FIG. 3G illustrates an exemplary routing for interconnect 358. In other examples, interconnect 358 can be positioned differently, for example, underneath host die 330.

[0035] FIG. 3H illustrates a semiconductor package 307 corresponding to system 100, processor 110, and / or semiconductor package 300. FIG. 3H illustrates yet another example of directly coupling non-adjacent chiplets. For example, chiplet 343 is positioned on a side of host die 330 opposite the side of chiplet 342, which further includes at least chiplet area 335. Interconnect 350 directly couples chiplet 342 and chiplet 343, while other interconnects can be enabled / disabled as needed. Additionally, FIG. 3H illustrates an exemplary routing for interconnect 350. In other examples, interconnect 350 can be positioned differently, for example, underneath host die 330.

[0036] FIG. 3I illustrates a semiconductor package 308 corresponding to the system 100, processor 110, and / or semiconductor package 300. FIG. 3I illustrates how additional components can be coupled via interconnects. Component area 374 can be adjacent to chiplet area 334 and, in some examples, can have a reversed arrangement with respect to interconnects (e.g., interconnect 357) from chiplet area 334, as shown in FIG. 3I. Component area 374 is a component area or mounting location for a component. Component 372 is attached to a corresponding component area adjacent to chiplet 342. Component 372 corresponds to a component, such as a chiplet, or, in some examples, a passive device not coupled to host die 330. Interconnect 351 directly couples chiplet 342 and component 372, and other interconnects can be enabled / disabled as needed.

[0037] FIG. 3J illustrates a semiconductor package 309 corresponding to system 100, processor 110, and / or semiconductor package 300. FIG. 3J illustrates how non-adjacent components can be coupled via interconnects. Component area 376 can be adjacent to chiplet 342, and component 378 is mounted adjacent to chiplet area 334. Component 378 corresponds to a component, such as a chiplet, or, in some examples, a passive device not coupled to host die 330. Interconnect 359 directly couples chiplet 342 and component 378, and other interconnects can be enabled / disabled as needed. Additionally, FIG. 3J illustrates an example routing for interconnect 359. In other examples, interconnect 359 can be positioned differently, for example, underneath the chiplet and / or component.

[0038] As described herein, the systems and methods provided in this disclosure are directed to chiplet architecture mixing via interconnects. Current chiplet interface efforts involve standardizing the definition of how chiplets communicate with each other. A common topology includes a host die (e.g., IOD) with separate connections to each of the chiplets. However, multiple chiplets (especially from third parties) may have additional point-to-point communication needs between them that do not require support from the host die and / or may be more efficient if an interface other than a standardized interface is utilized. The present disclosure provides a multi-chiplet accelerator and generic packaging support that can support the assembly of both cooperatively operating chiplets and individually operating chiplets.

[0039] Different products require different levels of accelerator computing power that can be provided by a chiplet. However, achieving different levels requires either building multiple chiplet types (e.g., low-, medium-, and high-level accelerator performance), requiring higher design costs, or designing a single "lowest common denominator" chiplet and varying how many such chiplets are implemented in a given system. However, with this multi-chiplet accelerator approach, the host-centric chiplet interconnect model funnels all inter-chiplet communication through the host die, creating a bottleneck with the host die.

[0040] In examples where the number of chiplets is varied to effectively achieve different levels of performance or acceleration, different numbers of third-party accelerator chiplets can provide different levels of performance in the same overall processor package. When more than one chiplet is present, the interconnect described herein allows the chiplets to communicate directly with each other without passing data back through the host die. For example, the interconnect allows data to be passed between machine learning accelerators during the all-reduce phase of neural network training. In some embodiments, the chiplets are identical, but other embodiments can use a mix of different chiplets that need not be identical.

[0041] In examples of chiplets that do not use interconnects, the chiplets can set the interconnects to ground or disconnect / high-impedance (high-Z). In some examples, some coordination between adjacent chiplets can prevent the interconnect electrical traces from floating. For example, one chiplet can connect its end of the interconnect path to ground, while the other chiplet sets its interconnect output to high-impedance (e.g., a disabled tri-state buffer).

[0042] The processor package provides electrical connections but, in some instances, does not specify the particular protocol or signaling used over the interconnect interface. Multiple chiplets can choose to use one appropriate for their use case. For example, some chiplets can use a standardized protocol, while others can use a proprietary protocol. Within the same package, different sets of chiplets can utilize different protocols.

[0043] In some examples, interconnects can connect adjacent chiplet locations (see, e.g., FIGS. 3A-3E). In other examples, interconnects can connect non-adjacent locations, with potential trade-offs in bandwidth / power, etc. (see, e.g., FIGS. 3F-3H). For example, longer interconnects may result in larger transmitter / receiver capacitance / impedance issues on either side of the link, which can lead to more challenging signal integrity and / or lower data rates.

[0044] In some examples, chiplets are not limited to a single "column" of placement locations (as in FIG. 3A). For example, FIG. 3I shows two columns of chiplet placement locations with interconnects running between both the rows and columns. In this example, the components on the right side are rotated 180 degrees so that all of the interconnect interfaces are aligned. If die-to-die interfaces (e.g., on the right side, not shown in FIG. 3I) are not used, they can be powered down and / or disconnected. Other embodiments can extend to more columns and / or more rows.

[0045] While interconnects can couple identical chiplets together, they can also be applied to a heterogeneous mix of chiplets that benefit from a direct point-to-point interface without having to route traffic back through the host die. For example (e.g., FIG. 3I), rather than disabling the unused D2D interface on the right, another approach (though perhaps more expensive) involves using a different chiplet design on the right column that did not implement the D2D interface (thus potentially freeing up more silicon area for computation or other functionality).

[0046] Although the above description is presented in the context of a processor package (e.g., an organic substrate), the systems and methods described herein can be applied to other technologies for integrating multiple chiplets, including silicon interposers, silicon bridges, integrated fan-out (InFO), etc.

[0047] As noted above, the computing devices and systems described and / or illustrated herein broadly represent any type or form of computing device or system capable of executing computer-readable instructions, such as those contained within the modules described herein. In their most basic configurations, these computing devices each include at least one memory device and at least one physical processor.

[0048] In some examples, the term "memory device" generally refers to any type or form of volatile or non-volatile storage device or medium capable of storing data and / or computer-readable instructions. In one example, a memory device stores, loads, and / or maintains one or more of the modules and / or circuits described herein. Examples of memory devices include, but are not limited to, random access memory (RAM), read-only memory (ROM), flash memory, hard disk drives (HDDs), solid-state drives (SSDs), optical disk drives, caches, variations or combinations of one or more of these, or any other suitable storage memory.

[0049] In some examples, the term "physical processor" generally refers to any type or form of hardware-implemented processing unit capable of interpreting and / or executing computer-readable instructions. In one example, a physical processor accesses and / or modifies one or more modules stored in the memory devices described above. Examples of physical processors include, but are not limited to, a microprocessor, a microcontroller, a central processing unit (CPU), a field programmable gate array (FPGA) implementing a soft-core processor, an application-specific integrated circuit (ASIC), a system-on-chip (SoC), a digital signal processor (DSP), a neural network engine (NNE), an accelerator, a graphics processing unit (GPU), one or more portions thereof, one or more variations or combinations thereof, or any other suitable physical processor.

[0050] In some embodiments, the term "computer-readable medium" generally refers to any form of device, carrier, or medium capable of storing or carrying computer-readable instructions. Examples of computer-readable media include, but are not limited to, transmission-type media such as carrier waves, and non-transitory-type media such as magnetic storage media (e.g., hard disk drives, tape drives, and floppy disks), optical storage media (e.g., compact disks (CDs), digital video disks (DVDs), and BLU-RAY disks), electronic storage media (e.g., solid-state drives and flash media), and other distribution systems.

[0051] The process parameters and order of steps described and / or illustrated herein are given by way of example only and can be changed as desired. For example, although the steps illustrated and / or described herein are illustrated or described in a particular order, these steps do not necessarily have to be performed in the order illustrated or described. The various exemplary methods described and / or illustrated herein may omit one or more of the steps described or illustrated herein or may include additional steps in addition to those disclosed.

[0052] The foregoing description is provided to enable those skilled in the art to best utilize various aspects of the exemplary embodiments disclosed herein. This exemplary description is not intended to be exhaustive or to be limited to any precise form disclosed. Many changes and modifications are possible without departing from the spirit and scope of the present disclosure. The embodiments disclosed herein are to be considered in all respects as illustrative and not restrictive. In determining the scope of the present disclosure, reference should be made to the appended claims and their equivalents.

[0053] Unless otherwise specified, the terms "connected to" and "coupled to" (and their derivatives) as used in this specification and claims should be interpreted as allowing both direct and indirect connections (i.e., via other elements or components). Additionally, the terms "a" or "an" as used in this specification and claims should be interpreted as meaning "at least one of." Finally, for ease of use, the terms "including" and "having" (and their derivatives) as used in this specification and claims are interchangeable with the term "comprising," and have the same meaning.

Claims

1. A semiconductor package comprising: a first chiplet area for receiving a first chiplet; a second chiplet area for receiving a second chiplet; a host die coupled to the first chiplet area and the second chiplet area; an interconnect directly coupling the first chiplet region to the second chiplet region. Semiconductor package.

2. a first chiplet in the first chiplet region and a second chiplet in the second chiplet region; 2. The semiconductor package of claim 1.

3. the first chiplet communicates with the host die using a first communication protocol, and the first chiplet communicates with the second chiplet via the interconnect using a second communication protocol.

3. The semiconductor package of claim 2.

4. the first communication protocol and the second communication protocol operate at different clock speeds; 4. The semiconductor package of claim 3.

5. the second chiplet comprising circuitry for disabling the interconnect; 3. The semiconductor package of claim 2.

6. the circuit comprises a ground; 6. The semiconductor package of claim 5.

7. A device, a host die; a plurality of chiplets arranged around and coupled to the host die; an interconnect directly coupling a first chiplet of the plurality of chiplets to a second chiplet of the plurality of chiplets. device.

8. the plurality of chiplets communicate with the host die using a first communication protocol, and the first chiplet communicates with the second chiplet via the interconnect using a second communication protocol; The device of claim 7.

9. the first communication protocol and the second communication protocol operate at different clock speeds; The device of claim 8.

10. the second chiplet comprising circuitry for disabling the interconnect; The device of claim 7.

11. a passive device; and a second interconnect directly coupling the passive device to any of the plurality of chiplets; the passive device is not coupled to the host die; The device of claim 7.

12. the first chiplet is adjacent to the second chiplet; The device of claim 7.

13. the first chiplet is not adjacent to the second chiplet; The device of claim 7.

14. 1. A system comprising: a host die; a plurality of chiplets arranged around the host die and coupled to the host die via an interconnection interface, each of the plurality of chiplets communicating with the host die via the interconnection interface using a first communication protocol; an interconnect directly coupling a first chiplet of the plurality of chiplets to a second chiplet of the plurality of chiplets, the first chiplet communicating with the second chiplet via the interconnect using a second communications protocol; system.

15. the first communication protocol and the second communication protocol operate at different clock speeds; 15. The system of claim 14.

16. the second chiplet comprising circuitry for disabling the interconnect; 15. The system of claim 14.

17. the circuit comprises a ground; 17. The system of claim 16.

18. a passive device; and a second interconnect directly coupling the passive device to any of the plurality of chiplets; the passive device is not coupled to the host die; 15. The system of claim 14.

19. the first chiplet is adjacent to the second chiplet; 15. The system of claim 14.

20. the first chiplet is not adjacent to the second chiplet; 15. The system of claim 14.

Images