memory device

Abstract

1. A memory device for storing data, comprising: a voltage divider circuit comprising at least one memory element, the at least one memory element operable or selected to be in a resistance and / or impedance state representative of at least a portion of the data, the voltage divider circuit configured to divide a voltage in response to the resistance and / or impedance state of the at least one memory element as part of a data read and / or data write operation, the at least one memory element being capacitive and connected to one or more further capacitive elements such that the voltage divider circuit comprises a capacitor divider configuration.

Description

[Technical Field]

[0001] Field The present invention relates to a memory device or system, for example a memory device or system for performing content addressable read operations. [Background technology]

[0002] background Memory structures such as SRAM and DRAM are address-addressable only. With the development of more intelligent systems, address-addressable-only memory can limit computational efficiency in data processing and transfer. Advanced intelligent systems require not only memory storage but also the ability to locate memory addresses by their specific contents. Such memories are called content-addressable memories (CAMs) or associative memories.

[0003] Known CAMs using CMOS technology typically use SRAM as their memory element for storing data, with data comparisons performed using NAND- or NOR-based topologies. CAM memory is desirable for its high operating speed and search capabilities, but its density can increase implementation costs in CMOS compared to other standard memories.

[0004] Alternatives to CMOS technology include, for example, resistive random access memory (RRAM), phase change memory (PCM), ferroelectric RAM (FeRAM), and magnetic RAM (MRAM). Summary of the Invention [Means for solving the problem]

[0005] overview According to a first aspect, there is provided a memory device for storing data, the memory device comprising: a voltage divider circuit comprising at least one memory element operable or selected to be in a resistance and / or impedance state representative of at least a portion of data, the voltage divider circuit configured to divide a voltage in response to the resistance and / or impedance state of the at least one memory element, the voltage may be divided as part of a data read and / or data write operation.

[0006] At least one memory element may be capacitive. At least one memory element may be connected to one or more additional capacitive elements such that the voltage divider circuit comprises a capacitor divider configuration. The capacitor divider configuration may be referred to as a capacitive voltage divider configuration or may comprise a capacitive voltage divider. At least one memory element may comprise a capacitive component. At least one memory element may comprise a parasitic capacitance.

[0007] The voltage divider circuit may be configured to avoid and / or at least reduce a resistance path during a data read and / or data write operation of the at least one variable resistance memory element.

[0008] The voltage divider circuit may comprise a voltage divider. The at least one memory element may be operable to be in a high or low resistance and / or impedance state, and the voltage divider circuit may be configured to at least reduce a voltage shared with the at least one memory element of the voltage divider circuit when the at least one memory element is in a low resistance and / or impedance state.

[0009] 10. A memory device according to any preceding claim, wherein the voltage divider circuit is configured to share a voltage between the at least one memory element and the one or more further elements when the at least one memory element is in a high resistance and / or impedance state.

[0010] The one or more impedance states may include a combination of at least resistance and / or reactance. The one or more impedance states may include one or more resistance states. The one or more impedance states may include one or more reactance states. The one or more impedance states may include a combination of resistance and reactance states.

[0011] The voltage sharing may further depend on the input voltage and capacitance and reactance values ​​of the at least one memory element and the one or more further elements. The voltage divider circuit may comprise at least one memory element connected to one or more further elements in a voltage dividing arrangement such that the voltage is divided between the at least one memory element and the one or more further elements. The at least one memory element and / or the one or more further elements provide capacitance and / or inductance and / or reactance.

[0012] The voltage divider circuit may be configured to operate as a capacitance divider when at least one memory element is in a high resistance and / or high impedance state.

[0013] The parasitic capacitance of the memory element may provide part of the capacitance of the capacitance divider circuit, and the parasitic capacitance of one further element may provide part of the capacitance of the capacitance divider.

[0014] The at least one memory element may be configured to substantially block and / or allow current flow through the at least one memory element depending on the resistance and / or impedance of the memory element.

[0015] The voltage divider circuit may comprise at least one memory element connected to one or more further elements, the voltage divider circuit being connected between the first data line and the second data line. The voltage divider circuit may further comprise one or more output transistors connected between the at least one memory element and the one or more further elements, optionally to a common node between the at least one memory element and the one or more further elements, such that a voltage division is provided to a gate electrode of the at least one output transistor, the at least one output transistor being coupled to a match line, thereby controlling the match line in response to the voltage division.

[0016] At least one memory element may be a capacitive component, and one or more further elements may comprise a further capacitor.

[0017] The at least one output transistor may include a threshold voltage such that the match line is switched depending on whether the data represented by the first data line and the second data line matches the data stored in the memory element.

[0018] The device may further comprise at least one write transistor connected between the at least one memory element and the one or more further elements, the at least one write transistor operable to apply a voltage to the at least one memory element, thereby writing data to the at least one memory element. The at least one write transistor may have a drain electrode connected to a common node.

[0019] The memory device may further comprise at least one further transistor operable to enable data to be read from the at least one memory element and / or forming part of a read transistor arrangement, The at least one further transistor may be operable to enable data to be read from the at least one memory element as part of a content addressable read operation.

[0020] The voltage divider circuit may be coupled to one or more, optionally two, search lines for providing an input voltage representing query data. The voltage divider circuit may be configured to output a voltage representing a match and / or a mismatch between the stored data and the query data. The search lines may also be referred to as data lines.

[0021] The memory device may be configured to perform a content addressable search process. The memory device may be configured to divide the voltage as part of a content addressable read operation. The read operation may include a content addressable read operation and may form part of the content addressable search.

[0022] The voltage divider circuit may be further configured to receive one or more signals representative of the search data and to output signals representative of matches and / or mismatches between the stored data and the search data.

[0023] The device may further comprise a read circuit for performing a data read operation, the data read operation including receiving an output voltage from the voltage divider circuit, the output voltage depending at least on the resistance and / or impedance state of the memory element.

[0024] The readout circuit may comprise at least one output transistor driven by the output voltage of the voltage divider circuit.

[0025] The device may further comprise a write circuit for setting the resistance and / or impedance state of the at least one memory element by applying a voltage to at least one memory state.

[0026] The write circuit may comprise at least one write transistor coupled to a voltage divider circuit.

[0027] At least one memory element can be selected or operable to be in one of a plurality of resistance and / or impedance states.

[0028] The at least one memory element may comprise a variable resistance and / or variable impedance memory element operable to be in one of two or more resistance and / or impedance states.

[0029] The at least one memory element may comprise a memory element having a selected resistance and / or impedance corresponding to a resistance state.

[0030] The plurality of resistance states may include a high resistance state and a low resistance state. The low resistance state may correspond to a resistance in the range of 100-1000 ohms, optionally 0-1000 ohms. The high resistance state may correspond to a resistance greater than 10 Mohm. The high resistance state may correspond to a resistance such that in the high resistance state, the voltage divider circuit operates as a voltage divider. The low resistance state may correspond to a resistance such that the voltage divider circuit does not operate as a voltage divider. The low resistance state may correspond to a resistance such that the voltage divider circuit bypasses one or more elements in the voltage divider, for example, at least one memory element. The low resistance state may correspond to a resistance such that the voltage divider circuit divides the voltage across at least one fewer element than in the high resistance state.

[0031] At least one memory element, and optionally one or more further elements, may include a non-zero reactance. At least one memory element may include a variable reactance.

[0032] The at least one memory element may be configured to retain a resistance and / or impedance state without power.

[0033] At least one memory element may be operable to be in at least a first resistance and / or impedance state or a second resistance and / or impedance state, thereby representing a binary data bit and / or binary value.

[0034] The at least one memory element may comprise a memristor, an RRAM element, a memcapacitor, a phase change material (PCM) device, a magnetic tunnel junction (MTJ), a programmable resistor, a non-volatile switch, or a floating gate MOSFET.

[0035] The memory device may form part of a bit cell or a memory cell. The voltage divider circuit may be operable in one or more modes including at least a content addressable read mode, an address addressable read mode, and a write mode of operation.

[0036] The memory device may include control circuitry configured to select an operating mode of the memory device.

[0037] The memory device may comprise a non-volatile memory device. The memory device may comprise bit cells. The memory device may comprise memory cells. The memory device may be arrayable.

[0038] The at least one memory element may comprise one of a memristor device, a RRAM device, a memcapacitor device, a phase change material (PCM) device, a magnetic tunnel junction (MTJ) device, a programmable resistor device, a non-volatile switch device, and a floating gate MOSFET device.

[0039] The at least one memory element may include or form part of at least one memory device operable and / or selected to assume a resistance and / or impedance state that represents at least a portion of the data.

[0040] According to a further aspect, there is provided a memory system comprising a plurality of memory cells, each memory cell comprising: a voltage divider circuit comprising at least one memory element, the at least one memory element operable or selected to assume a resistance and / or impedance state that represents at least a portion of the data; The voltage divider circuit is configured to divide a voltage according to a resistance and / or impedance state of at least one memory element as part of a data read and / or data write operation. The memory system may include one or more common or shared read and / or write lines for one or more groups of a plurality of memory cells.

[0041] A plurality of memory cells may be arranged in an array, and the memory cells may be grouped into rows or columns of the array.

[0042] According to a further aspect, there is provided a method of performing data read and / or data write operations using a memory device, the memory device comprising a voltage divider circuit comprising at least one memory element, the at least one memory element operable or selected to be in a resistance and / or impedance state representative of at least a portion of data, providing the memory device voltage divider circuit; The method includes dividing a voltage applied to a voltage divider circuit according to a resistance and / or impedance as part of a data read and / or data write operation.

[0043] The method may further include performing a data read and / or data write operation. The method may further include operating the at least one memory element to place the at least one memory element in a resistance and / or impedance state representative of the data.

[0044] Features of any one aspect may be applied as features of any other aspect of the invention, as appropriate. For example, method features may be applied as system or device features, and vice versa. Furthermore, device features may be applied as system features, and vice versa.

[0045] Short description Various aspects of the present invention will now be described, by way of example only, with reference to the accompanying drawings, in which: [Brief explanation of the drawings]

[0046] [Figure 1] FIG. 2 is a circuit diagram of a memory cell according to one embodiment. [Figure 2(a)] FIG. 2 is a circuit diagram of a first equivalent circuit of a memory cell. [Figure 2(b)] FIG. 10 is a circuit diagram of a second equivalent circuit of a memory cell. [Figure 3] 1 is a table showing voltage levels within the circuit at different stages of a content addressable read operation. [Figure 4] FIG. 10 is a timing diagram of a content addressable read operation. [Figure 5] FIG. 10 is a circuit diagram showing an equivalent circuit of a memory cell for an addressable read operation. [Figure 6] FIG. 10 is a timing diagram of an addressable read operation. [Figure 7(a)] FIG. 1 is a first circuit diagram showing a first equivalent circuit of a memory cell for a write operation. [Figure 7(b)] FIG. 10 is a second circuit diagram showing a second equivalent circuit of the memory cell for a write operation. [Figure 7(c)] FIG. 10 is a timing diagram for a write operation. [Figure 8(a)] 1 is a cross-sectional view of an RRAM device according to one embodiment. [Figure 8(b)] FIG. 1 is a top view of an RRAM device. [Figure 9] 1 is a schematic diagram of a memory device having an array of memory cells, according to one embodiment. [Figure 10] FIG. 10 is a circuit diagram of a memory cell according to a further embodiment. [Figure 11] FIG. 10 is a circuit diagram of a memory cell according to a further embodiment, operating in DRAM mode. DETAILED DESCRIPTION OF THE INVENTION

[0047] Detailed Description Figure 1 is a circuit diagram of a portion of a memory device, specifically a memory cell 100. One embodiment of a memory device having a plurality of memory cells, such as those described with reference to Figures 1-7, in an array arrangement along with associated circuitry, including input and output circuitry, is described with reference to Figure 9. The memory cells may alternatively be referred to as memory pixels. It will be understood that memory cells may be arrayed and may be provided with a plurality of other memory cells.

[0048] The memory device shown in FIG. 1 is a capacitance-based RRAM memory capable of performing content-addressable read operations. As described below, the memory has RRAM elements with configurable resistance states that can be selected to be at different levels. As described below, the metal-insulator-metal (MIM) structure of the RRAM changes its resistance through a redox process, coupled with an ion migration effect. Thus, the RRAM resistance can be switched to a low resistance state (LRS) or a high resistance state (HRS) by applying set and reset threshold pulses, respectively. The content-addressable memory described below can reduce or avoid the use of DC resistance paths and therefore provide an improved power-efficient solution with low cost, high throughput rates, and high reliability for CAM designs. While some embodiments below relate to memory cells having RRAM elements, it will be understood that other types of memory elements may be used, as described in more detail below.

[0049] FIG. 1 illustrates a memory cell 100 according to one embodiment. For purposes of the following description, memory cell 100 is shown with additional components for controlling the voltage of the memory cell's output, particularly for controlling the voltage of the match line. In some embodiments, these additional components are considered to be part of memory cell 100. The memory cell also has associated power supply voltage circuitry not shown in FIG. 1.

[0050] Memory cell 100, described below, is configured to operate in several different modes: a content addressable read mode, an address addressable read mode, and a write mode. The content addressable read mode is described with reference to FIGS. 1-4, the address addressable read mode is described with reference to FIGS. 5 and 6, and the write mode is described with reference to FIG. 7. It will be appreciated that in some embodiments, memory cell 100 includes control circuitry and / or is provided with associated control circuitry for selecting the operating mode of the memory cell. A content addressable read operation may be performed as part of a content addressable search process.

[0051] The memory cell 100 is a 3T1C1R memory cell characterized by having three transistors, one capacitor, and an RRAM element. More specifically, the memory cell has a write transistor 102 (also referred to as a special resistor or simply Q1), an output transistor 104 (also referred to as Q2), and an additional transistor 106 (also referred to as an additional transistor, or for brevity as Q3). The write transistor 102 may be operable to enable writing of data to the memory element 108. The additional transistor 106 may further be operable as part of a read transistor configuration. The additional transistor may be referred to as a readable transistor, for example, during a content addressable read operation. For example, the output transistor 104 and the additional transistor 106 together operate as a read transistor configuration and may also be referred to as an output transistor. In a further embodiment, the two transistors Q2 and Q3 are replaced by a single device having two gates. It will be understood that, depending on the operation of the device, the output transistor and / or the additional transistor form part of a read circuit for performing a data read operation.

[0052] In this embodiment, these three transistors are nMOS transistors used to maximize cell density in an array configuration. Each nMOS transistor has a gate electrode, a drain electrode, and a source electrode. When the nMOS transistor receives a non-negligible voltage at the gate, current flows between the source and drain, and when the nMOS transistor receives zero voltage at the gate, substantially no current flows between the source and drain. In the following diagrams, the arrows of the transistors indicate the source electrodes. Transistor Q1 is reused for both write and addressable read operations, while transistors Q2 and Q3 are activated for CAR. Depending on the operating mode, appropriate control circuitry may be provided to activate specific components within the memory cell.

[0053] The memory cell 100 has a variable resistance element 108. In this embodiment, the variable resistance element 108 is a RRAM 110. The RRAM 110 has a capacitance. The capacitance C mr Reference numeral 112 represents the parasitic capacitance introduced by the RRAM MIM structure, whose size is determined by the structure area of ​​the fabricated RRAM. The parasitic capacitance also depends on the distance between the metal plates, which in this embodiment corresponds to the thickness of the insulating layer. The metal plates are formed by metal electrodes / lines disposed on the chip. For example, it will be understood that cue lines have physical lengths, widths, and heights and cross each other (albeit at different heights within the chip), so that cross-coupling parasitic capacitance exists between the cue lines and, for example, match lines. The structure of the RRAM will be described in more detail with reference to FIG. 8.

[0054] FIG. 1 shows a parallel-connected RRAM element 110 and a capacitor (C mr Although variable resistance element 108 is shown as RRAM element 112, it will be understood that in this embodiment variable resistance element 108 corresponds to RRAM element 110, which provides both resistance and capacitance. Thus, while variable resistance element 108 may be referred to as RRAM element 110, it will be understood that RRAM element 110 provides both resistance and capacitance.

[0055] The physical RRAM contains some parasitic capacitance, and therefore the RRAM element 110 and C mr The elements 112 together function as the actual physical RRAM device. In some embodiments, a larger C mr may be designed to intentionally keep the parasitic capacitance high. In some embodiments, it may be advantageous to increase the parasitic capacitance to ensure that other parasitics in the circuit do not substantially destroy the divider.

[0056] The variable resistance element 108 is a non-volatile element that retains stored data when power is turned off. In particular, the variable resistance element 108 can retain its resistance without power. In this embodiment, the variable resistance element is controllable to be in one of two resistance states, a high resistance state (HRS) and a low resistance state (LRS), and can be controlled to remain in each resistance state without power. The resistance element 108 can store binary data by switching to and remaining in one of the two resistance states. In the following embodiments, the high resistance state represents a 1 bit, and the low resistance state represents a 0 bit. Therefore, the memory cell may be referred to as a bit cell.

[0057] The variable resistance element 108 can be any type of resistance element capable of maintaining a resistance and thus storing data. For example, the variable resistance element may be formed from a phase change material (PCM) device, a magnetic tunnel junction (MTJ), or a memristor element. As described below, the variable resistance element 108 may (in this embodiment) be a programmable resistor that can be in one of two different resistance states. The memory element may be any type of non-volatile switch (including a floating gate MOSFET, such as flash memory). It will be understood that the variable resistance element can be operable to be in one of several resistance states and that the resistance of the element can be set using an electronic signal and the resistance can be maintained.

[0058] The memory cell 100 also includes a capacitor, referred to as the bottom capacitor, or ballast capacitor 114 (C b ) The electronic coupling between the RRAM 110 and the lower capacitor 116 may hereinafter be referred to as a capacitor divider link connection or a link connection for brevity. The link connection between the RRAM 110 and the lower capacitor has a node also referred to as a midpoint node 116 or a common node.

[0059] As mentioned above, the capacitance Cmr is the parasitic capacitance introduced by the RRAM MIM structure, and its size is determined by the area of ​​the RRAM to be fabricated. The bottom capacitor Cb is selected as a metal-oxide-metal (MOM) capacitor, which uses interdigitated fingers to create a higher unit capacitance than an MIM capacitor and can be constructed to a smaller minimum size (different capacitor choices for different technologies). MOM caps may have advantages over MIM. For example, MIM caps may be denser and have a larger minimum size than MOM caps. Therefore, MOM is selected in this embodiment.

[0060] In this embodiment, memory cell 100 is served by the following lines: cue 120, cue_bar 122, switch (sw) line 124, power switch (psw) line 126, match line 128, and enable (en) line 130. The power switch line may also be referred to as the pulse switch line.

[0061] As described below, for a content addressable read (CAR) operation, cue 120 and cue-bar 122 represent the data to be searched for and may be referred to as the first and second input data lines, or search lines, respectively. cue and cue-bar are connected across a capacitance divider configuration. The values ​​of cue and cue-bar represent query data for the CAR operation. In this embodiment, when searching for a "1," cue is set to VSEC and cue-bar is set to GND, and vice versa for a "0." Furthermore, if both cue and cue-bar are set to GND, the system performs a "don't care" search operation (also referred to as an "X" search operation).

[0062] In this embodiment, the RRAM LRS is specified as 112 kΩ and the HRS is specified as 8.04 MΩ. The circuit operates on a primary 1.8 V supply voltage VDD and an adjustable secondary supply voltage VSEC, here designed to be in the range of 1 to 1.4 V. VSEC applies only to the cue / cue-bar and precharge signals.

[0063] The switch line 124 and the power supply switch line 126 are connected to the write transistor 102 and control its operation. In a write operation, the switch line 124 and the power supply switch line 126 control the write transistor to switch the resistance state of the variable resistance element 108, thereby enabling data to be written to the variable resistance element 108. It will be understood that the write transistor forms part of a write circuit for writing data to the RRAM by applying a voltage to the RRAM. The switch line 124 and the power supply switch line 126, together or separately, may be referred to as write lines or RRAM programmable lines. In an address-addressable mode, the power supply switch line may be referred to as an address-addressable read line.

[0064] The match line 128 is coupled to the output transistor 104. In the case of a content addressable read operation, the value on the match line represents the result of the content addressable read.

[0065] The En line 130 is coupled to a further transistor 106. In this embodiment, the En line has a dual role: a) it ensures that the Match line is only disturbed when the intermediate node voltage is at a valid value, and a) it ensures that the exact duration for which the Match line is disturbed is precisely controlled. This can provide fully controllable and consistent dynamics.

[0066] The circuit layout of the memory cell 100 will now be described for this embodiment. The RRAM 108 is connected at a first end to the cue line 120 and at a second end to the link connection. The link connection connects the RRAM 108 to the lower capacitor 114. As described above, the RRAM 108 can be configured in either a high resistance state (HRS) or a low resistance state (LRS). The link connector, including the midpoint node 116 and the lower capacitor 114, together with the RRAM 108, can be considered to form a capacitance divider or capacitive voltage divider. The capacitance divider is connected at a first end to the cue line 120 and at a second end to the cue-bar line 122. The divider midpoint node 116 directly drives the output transistor. As will be described in more detail with reference to FIGS. 2(a) and 2(b), the capacitance divider is operable according to the resistance state of the RRAM.

[0067] The gate electrode of the write transistor 102 is connected to a switch line 124. The drain of the write transistor 102 is connected to a node between the RRAM 110 and the bottom capacitor 114. The source electrode of the write transistor 102 is connected to a psw line 126. As will be described with reference to FIG. 7 , the write transistor 102 is operable to set the resistance state of the RRAM and thus write data to the memory cell. During a read operation, the write transistor 102 acts as a deadweight capacitor. The write transistor 102 may alternatively be referred to as a programming transistor.

[0068] The gate electrode of the output transistor 104 is connected to the intermediate node 116 of the capacitance divider. The drain of the output transistor is connected to the match line 128. The source electrode of the output transistor 104 is connected to the drain electrode of a further transistor 106. The output transistor 104 has a threshold voltage corresponding to the minimum gate-source voltage required to form a conduction path between its source and drain. As mentioned above, the further transistor 106 is operable to enable reading of data and is also operable to form part of a read transistor configuration with the output transistor Q2, 104. In the case of a content addressable read, the further transistor 106 is used to enable content addressable read including a discharge path for the match line.

[0069] There may be a relationship between the threshold voltage and the values ​​of other components in the circuit. Selecting the threshold voltage can involve a complex process in which available transistors are checked (e.g., there may be several different types of low-voltage nMOS transistors available) and the system is designed to minimize energy in all of them. The general logic is that the lower the threshold voltage, the lower the VSEC supply, and therefore the more power can be saved. If the threshold is too low, even in the off state, Q2 may leak too much and discharge the match line when undesirable. In general, a lower threshold may be preferable for that reason.

[0070] The gate electrode of the further transistor 106 is connected to the en line 130. The drain electrode of the further transistor 106 is connected to the source electrode of the output transistor. The source electrode of the further transistor 106 is connected to ground. The further transistor 106 is coupled to the en line as described above.

[0071] In this embodiment, the memory cell 100 is connected to a precharge transistor 136. The precharge transistor 136 has its gate electrode connected to a precharge input (pre_1 line 132), its drain connected to a high power supply voltage 134 (Vdd), and its source connected to a match line. The precharge transistor 136 operates to raise the voltage of the memory cell's match line 128 to the high voltage supply level 134 in response to receiving the precharge input signal 132 at its gate.

[0072] As outlined with reference to FIG. 1, the capacitance divider is operable depending on the resistance state of the resistive element 108. For illustrative purposes, FIGS. 2(a) and 2(b) show an equivalent circuit of the capacitance divider configuration of FIG. 1 when the variable resistive element is in a high-resistance state and a low-resistance state, respectively. The RRAM element may be thought of as operating as a switch in these two states. In particular, the resistance value in the high-resistance state is high enough that the RRAM operates as an open switch while providing a capacitance value. Similarly, the resistance value in the low-resistance state is low enough that the RRAM operates as a closed switch, effectively bypassing the capacitance. Thus, when the variable resistive element 108 is in a high resistance state, the capacitance divider circuit operates in a capacitance divider mode. In capacitance divider mode, the voltage supplied to the capacitance divider is shared between the RRAM and the bottom capacitor. In such a mode, current is allowed to flow through the RRAM. When the variable resistive element is a long resistance state, the capacitance divider operates in a capacitance divider mode that divides the capacitance (C mr In an LRS, the cue line floods the intermediate node and charges the ballast capacitor Cb. Thus, in an LRS, there is essentially no DC path, but all of the current entering the intermediate node passes through the RRAM. In such an embodiment, in an LRS, the voltage shared with the RRAM across the voltage divider configuration is reduced compared to that in an HRS. In an HRS, the current flow is blocked, thereby allowing the capacitor to function as a voltage divider.

[0073] Therefore, as shown in FIG. 2(a), when the RRAM is in HRS (MΩ in this embodiment), the variable resistance element 108a is connected to the open switch 109 and the capacitor C mr 112 in parallel. Therefore, the RRAM has a parasitic capacitance C mr and the lower capacitor C b 2(b), when the RRAM is in the LRS, the capacitance divider operates in bypass mode, and thus the variable resistance element 108b can be represented as a closed switch 109b.

[0074] In operation, when the RRAM is in LRS, the voltage readout at the midpoint node (Vmid) depends on the value of cue, and in particular, the voltage readout at Vmid follows the cue. In practice, since the LRS used is relatively high (112 kOhms in this embodiment), the effective capacitive divider modulation is mr This is achieved by shifting the RC constant. This is especially important at high frequencies (100s of MHz). At the same time, the behavior of Vmid also depends on the cue / cue-bar values, as shown in Table 1 of Figure 3. In particular, if the cue input does not match the stored data (corresponding to a "miss"), Vmid rises, Q2 activates, and the match line ML discharges. Therefore, the match line can be considered an "OR match line." Furthermore, a cue line value equal to a cue-bar line value equal to GND results in a "don't care." In embodiments where two or more groups of cells are coupled to a common match line, if all cells in the group of cells (e.g., a column or row of an array) do not register a "miss," the match line remains high.

[0075] FIG. 3 is a table of results showing the values ​​of the resistance states of the RRAM, the corresponding voltages at the intermediate nodes (Vmid), and the resulting voltage levels at the match lines.

[0076] In the first two rows, the cue lines have values ​​corresponding to a 1 search. In rows 3 and 4, the cue lines have values ​​corresponding to a 0 search. In rows 4 and 5, the cue lines have values ​​corresponding to a "don't care" search (an X search). For each search, the table shows the results when the stored data corresponds to a 0 data bit (RRAM in LRS) or a 1 data bit (RRAM in HRS).

[0077] When the RRAM is in HRS, the circuit operates in capacitance divider mode. Therefore, in a search for a 1, the value of Vmid is low. Specifically, the value of Vmid is lower than the threshold voltage of the output transistor 104, and therefore the match line remains high. In a search for a 0, the value of Vmid is high, specifically higher than the threshold voltage of the output transistor 104. Therefore, the match line provides a low output. When the RRAM is in LRS, the circuit operates in bypass mode. Therefore, in a search for a 1, the value of Vmid is high, specifically higher than the threshold voltage of the output transistor 104, and therefore the match line remains low. In a search for a 0, the value of Vmid is low, and therefore lower than the threshold voltage of the output transistor 104, and therefore the match line remains high. In a search for a "don't care," in both the high-resistance state and the low-resistance state, the search for a 0 and the search for a 1 result in a low Vmid and therefore a high match line. The threshold voltage of the output transistor 104 is switched to a high or low value by the match line depending on whether the data represented by the first data line and the second data line matches the data stored in the memory element. In this embodiment, if there is a match, the match line remains high, and if there is a mismatch, the match line goes low.

[0078] The values ​​for LRS and HRS are: at LRS, the voltage divider operates in bypass mode, and C mr It will be appreciated that the HRS bypasses the capacitor divider such that the capacitor divider operates as a capacitor divider, also referred to as capacitor divider mode. It will be appreciated that the capacitor divider is an example of a voltage divider, and in some embodiments may be referred to as a capacitive voltage divider.

[0079] FIG. 4 is a timing diagram for performing a content-addressable read (CAR). It will be understood that the write transistor (Q1) is turned off for a content-addressable read operation. FIG. 4 details the CAR sequence of a spare portion 202 and three consecutive search operations: a search for a 1 data bit (search 1 operation 204), a search for a 0 data bit (search 0 operation 206), and a "don't care" search (search X operation 208). The elapsed time of each of the search 1, search 0, and search X operations can be further divided into a before-and-after portion, also referred to as the query phase and the result phase. The voltage values ​​shown in FIG. 5 are the sw line 210, the cue line 212, the cue-bar line 214, the psw line 216, the precharge line 218, the en line 220, the midpoint node voltage (Vmid) 222, and the match line 224 (also referred to as ML). FIG. 4 shows the waveforms for each of these lines.

[0080] In the initial stage 202, a precharge voltage is applied to the precharge transistor, causing the match line ML 224 to rise to the voltage level VDD, and then the precharge transistor is turned off. Before each search operation, the sw line 210 is opened to remove any residual charge at the midpoint node (shown as Vmid 222). The match line ML is then precharged to the power supply voltage level VSEC for 1x clock cycle. At the same time, cue and cue-bar begin to rise for 2 ns according to the data in cue. For the search 1 operation, during the search 1 query stage 204a, cue is set to a higher voltage (VSEC), and cue-bar is at a lower voltage (GND). For the search 0 operation 206, during the search 0 query stage 206a, cue is at a lower voltage (GND), and cue-bar is at a higher voltage (VSEC). During the search X operation 206, both cue and cue-bar are at a lower voltage (GND).

[0081] In response to the setting of the query data (cue and cue-bar lines), during the search 1 query phase 204a, the voltage at the intermediate node (Vmid) begins to accumulate charge and rise. In contrast, during the search 0 query phase 206a, the voltage at the intermediate node begins to dissipate and decrease. The voltage at the intermediate node exceeds the threshold voltage of the output transistor when a mismatch between the input data and the stored data is detected. Thus, for a search 1 operation, when in the low resistance state, the voltage at the intermediate node rises to a higher value faster than when in the low resistance state. Similarly, for a search 0 operation, when in the low resistance state, the voltage at the intermediate node falls to a lower value faster than when in the high resistance state. This is because in the high resistance state, the capacitance divider acts as a capacitance divider, and in the low resistance state, the capacitance divider acts as a capacitance C mr This is to bypass the

[0082] During the query phase, the match line voltage is initially substantially equal for both resistance states. Then, when the value of Vmid has sufficiently stabilized, the en line is strobed. Following the strobe, the voltage at the midpoint node is returned to 0 for both search operations. For a search 1 operation, following the strobe, the match line voltage increases to its upper limit when in the high resistance state and decreases to 0 when in the low resistance state. Similarly, for a search 0 operation, following the strobe, the match line voltage decreases to 0 when in the high resistance state and increases to its upper limit when in the low resistance state.

[0083] The query phase 204a, 206a of each type of search operation is followed by a result phase 204b, 206b. During the result phase, the cue and cue-bar voltages are both returned to 0, and the result can be read from the match line voltage. In the case of a "hit" (a search operation of 1 on the HRS and 0 on the LRS), the match line remains at a high level. In the case of a "miss" (a search operation of 1 on the HRS and 0 on the LRS), the match line is at a lower level.

[0084] It will be appreciated that the memory cells described above can store one bit of data. Multiple bits of data can be checked by chaining multiple cells together on the same match line. Every bit miss will lower the ML voltage level, and as a result, given a sufficiently sensitive sensing circuit, the hit / miss ratio can also be observed.

[0085] Addressable Read As mentioned above, the memory cell of Figure 1 can also be used for address addressable read (AAR) operations. Figure 5 is an equivalent circuit diagram of memory cell 300, also referred to as a memory pixel, for performing an AAR operation. It will be understood that the circuit of Figure 5 corresponds to the memory cell shown in Figure 1, where the 1T1R structure (Q1 and RRAM) is activated and the rest of the circuit remains off during the AAR operation.

[0086] According to one embodiment, the circuit has a memory cell 300 coupled to a peripheral circuit 303 for an addressable read operation. The cell components RRAM 310, midpoint node 316, bottom capacitor 314, switch line 324, power switch line 326, and write transistor 302 are substantially as described with reference to FIG. 1. In particular, RRAM 310 and bottom capacitor 314 are arranged in a capacitance divider configuration. For purposes of performing an AAR operation, both the cue line and the cue-bar line are set to ground.

[0087] The peripheral circuit 303 includes a first transistor 340, also referred to as Q4, a second transistor 342, also referred to as Q5, and a tank capacitor 352. The source electrode of the first transistor 340 is connected to the drain electrode of a second transistor 348. At the connection between the first transistor 340 and the second transistor 342 is a further intermediate node 344. The drain electrode of the first transistor 340 is connected to a power supply voltage (Vsec) 346. The gate electrode of the first transistor 346 is connected to a sec line 348. The source electrode of the gate electrode of the second transistor 342 is connected to ground. The gate electrode of the second transistor 342 is connected to a clr line 350. The further intermediate node 344 is connected to the write transistor 302 of the cell 300, in particular to the source electrode of the write transistor 302 via a psw line 326. A tank capacitor 352 is connected between the further intermediate point of the peripheral circuit and the source electrode of the program transistor 302.

[0088] The operation of the circuit of FIG. 5 will be described with reference to the timing diagram of FIG. 6. The timing diagram shows the timing of the clr 350, sec 348, sw 324, and psw 326 lines. The waveforms of each of these lines are represented by clr waveform 362, sec waveform 364, switch waveform 368, and psw waveform 370, respectively. For purposes of performing AAR, both cue and cue-bar are set to ground. In some embodiments, the PSW line 326 is connected to a group of multiple memory cells, such as a row or column of an array. In this embodiment, the parasitic capacitance of the line on the psw creates a charge tank that represents equivalent charge levels when the RRAM is in different states. The capacitor 352 can be represented by a line capacitance that services an entire row (or column) of pixels that share the PSW. Thus, in some embodiments, the capacitor 352 is not physically implemented. The more pixels hanging from the same PSW line, the larger the line capacitance. Depending on the value of the RRAM, that capacitance needs to be at a specific level. For example, when RRAM is in HRS, it should not be discharged in a single AAR cycle (e.g., a 4-5 ns SW strobe), but when in LRS, it should be discharged at the same interval. For any RRAM, resistance or resistance state, R, and strobe speed, there is an optimum capacitance. In some embodiments, the memory size is selected to optimize the line capacitance. Ideally, an explicitly implemented capacitor 352 is not necessary. Also, the smaller the capacitance, the lower the power consumption.

[0089] In the first step, the PSW line 326 is first cleared by signal clr 350, opening transistor Q5 342. In the next step, a 1 ns strobe on the sec line 348 sets the PSW line 326 to the supply voltage VSEC 346. Finally, the sw 324 line is strobed, discharging the PSW line capacitance. The discharge of the capacitance, and therefore the operation of the capacitance divider, depends on the resistance state of the RRAM being read. In particular, when the RRAM is in HRS, the line discharges at a slower rate than when it is in LRS. Additional sensing circuitry, such as a circuit associated with the tank capacitor, allows the result to be read. More specifically, as soon as the SW line is activated, capacitor 352 shares charge with all other capacitances (314) hanging on the same PSW line, thus providing the initial drop in Figure 6. This is when the difference in discharge rate described above occurs.

[0090] In this embodiment, the sense circuit senses the voltage and determines whether the voltage represents a 1 or a 0. As a non-limiting example, the sense circuit is a strong-arm latch type comparator. In some embodiments, only cells connected to a common psw line (e.g., a column or row of an array of cells) are activated.

[0091] Write Operation As described above, the memory cell of FIG. 1 is further configured to perform one or more write operations. Figures 7(a) and 7(b) show equivalent circuits 400a and 400b, respectively, to illustrate a write operation using the memory cell. The write operation performed may be a write forward operation or a write reverse operation. The write operation performed may also be an assisted write forward operation or an assisted write reverse operation.

[0092] The RRAM element 410, bottom capacitor 414, write transistor 402, and midpoint node 416 of equivalent circuits 400a, 400b are as described with reference to the memory cell of Figure 1. The cue line 414, sw line 424, and psw line 426 are also as described with reference to Figure 1. As described with reference to Figure 1, the write transistor 402 is connected at its drain electrode to the midpoint node 416. The write transistor 402 is connected at its gate electrode to the switch line 424 and at its source electrode to the psw line 426. It will be appreciated that in some embodiments, the write transistor 402 forms part of a write circuit for writing data to the RRAM element 410.

[0093] In FIG. 7(a), the cue-bar line is set to ground. The cue-bar is set so that the bottom capacitor 414 is connected to the RRAM device 410 at one end (via the midpoint node 416) and to the cue-bar, which is set to ground at its second end. In contrast, in FIG. 7(b), the bottom capacitor 414 is connected to the RRAM device 410 at one end (via the midpoint node 416) and to the cue-bar line at its second end. In both circuits, Cb is connected to the cue_bar at its second end, but it will be understood that the cue_bar may be set to a different voltage level. In FIG. 7(a), the cue_bar remains stationary at GND. In FIG. 7(b), the cue_bar may be changed to perform a "write boost" operation. It may also be placed at GND for non-boosting operations.

[0094] In the embodiments of Figures 7(a) and 7(b), writing or programming data to the RRAM element is performed using pulses. To write the RRAM element to its desired state, bias voltages can be applied to the cue and psw terminals. A forward direct write is defined when a bias voltage is applied to cue and psw is connected to GND. A reverse write is achieved by setting psw to Vdd and keeping cue grounded. After biasing, sw is pulsed, resulting in a voltage being applied across the RRAM. For a standard write operation, cue is either GND or a bias voltage, depending on the direction of the write.

[0095] The placement of Cb414 as shown in Figure 7(b) can enable an assisted write operation to boost the voltage supplied across the RRAM, as shown in Figure 7(b). The assisted write operation may prevent "stuck-at" failures. This assistance is achieved by sending a pulse on the cue-bar simultaneously with sensing a pulse on sw. The simultaneous delivery of pulses on sw and psw can temporarily boost the voltage delivered across the device via a charge pump action.

[0096] 7(c) shows a signal timing diagram for illustrating a write operation of a memory device according to one embodiment. It will be understood that the write operation may be performed by a memory device represented by the equivalent circuit of FIG. 7(a).

[0097] FIG. 7(c) shows a switch line waveform 702 on the switch line 424 and the resulting resistance state of the RRAM 410. For purposes of the following discussion, FIG. 7(c) has three phases. FIG. 7(c) shows a first phase 702 in which one data bit is written to the RRAM 410. Writing one data bit corresponds to changing the resistance state of the RRAM 410 from LRS to HRS. This is accomplished by providing a pulse voltage waveform on the switch line 424 while the cue line 414 is set to GND and the PSW line 426 is set to Vdd. While FIG. 7(c) shows three pulses, it will be understood that this is for illustrative purposes only. The number of pulses over a period of time depends on the RRAM characteristics.

[0098] The first phase is followed by a second phase 708, during which the RRAM 410 remains in a high resistance state. The RRAM 410 continues to store the written data during this phase 708. No signal is applied during the second phase.

[0099] 7(c) shows a third phase in which a 0 data bit is written to the RRAM 410. Writing the 0 data bit corresponds to changing the resistance of the RRAM 410 from HRS to LRS. This is accomplished by providing a pulse voltage waveform to the switch line 424 while setting the cue line 414 to Vdd and the PSW line 426 to GND.

[0100] Figure 8(a) is a first view of an RRAM device according to an embodiment, and Figure 8(b) is a cross-sectional view of the RRAM device. Figures 8(a) and 8(b) show a substrate 902 on which a CMOS metal layer 904 is provided. An RRAM top electrode layer 906, an RRAM dielectric layer 908, and an RRAM bottom electrode layer 910 are provided. The RRAM dielectric layer is provided between the top and bottom electrode layers. A via 912 is provided to connect the bottom electrode to the CMOS metal. Lines 922 delineate the active elements.

[0101] Figures 8(a) and 8(b) show the physical in-pixel RRAM location. Active devices are located above the CMOS metal layer 904. Figure 8 shows only the topmost CMOS metallization layer on top of Cb for clarity. The pixel transistors and other layers are hidden beneath this metal layer and therefore not shown. The cross-sectional view is taken from cut line 920, which cuts through the top view. Figure 8(b) shows the top view of the device. The via layer 912 is not exposed in the top view and is hidden beneath the top, dielectric, and bottom electrode layers. Similarly, the bottom electrode layer is partially exposed and partially hidden by the top layer. According to one embodiment, the RRAM device has an area of ​​0.35 μm × 0.35 μm, and its capacitance is approximately 2.2 fF based on measurements of the physical RRAM device.

[0102] 8 shows a structure according to one embodiment, it will be understood that the circuit may be implemented using different material stacks and structures. As non-limiting examples, the circuit may include metal oxide-based RRAM having Pt / AlOx / TiOx / Pt, Ag / SnOx / Pt, and Ag / ZnOx / Pt material stacks.

[0103] FIG. 9 illustrates a memory system 500 including a 64×64 array 502 of CAM pixels according to one embodiment. Each pixel substantially corresponds to a memory cell 100 of FIG. 1. It will be understood that a group of pixels may have one or more common or shared read and / or write lines. More specifically, in the embodiment of FIG. 9, each column of pixels in the array has a shared match line that allows data, e.g., in the form of a binary bit string, to be stored in the column. Each column of pixels has shared PRE, EN, and SW lines, allowing the connected match lines to provide equal voltage levels that indicate comparative similarity. In this embodiment, CUE and CUE_BAR are connected horizontally. PSWs are also connected horizontally to enable AAR operation for each row.

[0104] To analyze the results of the CAR and AAR operations, a first latch comparator 504 and a second latch comparator 506 are coupled to the output of the 64x64 array. The latch comparators are MOS-type latch comparators. The comparators may be, for example, either pMOS or nMOS differential pair types. The latch comparators are designed to resolve the potentially very small gap between the "all hit" and "1 bit miss" scenarios of the CAR, as well as the difference in results caused by the HRS and LRS on the PSW of the AAR.

[0105] The CUE operates from a secondary adjustable supply, VSEC, for CAR operations, but needs to reach the primary supply, VDD, for write operations. Additionally, the circuit is configured to switch the signal at PSW between multiple supply voltages and GND under different operating conditions. This is achieved via a 3x transistor, with PRI connected to the primary 1.8V supply and SEC connected to VSEC. As for the cue-bar, it operates from VSEC for CAR, but remains at VDD or GND for other operations. An additional signal, SUPSW, is introduced to swap between supply voltages.

[0106] To enable parallel CAR search, each row is provided with corresponding peripheral circuitry 510 and signal driver circuitry 512 so that the entire array can be activated simultaneously.

[0107] At a higher level, the chip has an input circuit including a deserializer 513, a finite state machine circuit 514, and a flip-flop circuit 516. The deserializer 513 receives input and processes the incoming information. The deserializer 513 splits the information into address information, data information, and instruction information. The finite state machine 514 receives the address, data, and instruction information and is configured to generate all control signals for the array 502. The signals are gated by a group of flip-flop components in the flip-flop circuit 516 for synchronization. The output of the flip-flop circuit 516 is then provided to the driver circuit 512 and the peripheral circuit 514.

[0108] The chip also has output circuits. The output circuits include a CAR serializer 518 and an AAR serializer 520. The outputs from the CAR and AAR operations are sent to their corresponding serializers and then output to additional components not shown in FIG. 9. Additional components may be provided on the same chip. In this embodiment, an internal clock operating at 800 MHz is used to synchronize the control signals. FIG. 9 also shows a ring oscillator 522, a multiplexer 524, and a divider 526. The ring oscillator 522 is configured to generate a clock signal. In this embodiment, the ring oscillator is an adjustable, current-starved oscillator. The multiplexer 524 provides a fail-safe so that the clock signal can be passed to the system if the ring oscillator fails during operation. The divider 526 is a standard module configured to generate a frequency-reduced version of the clock signal by a power of two. In this embodiment, it divides the clock signal by eight. This provides a readable backup / diagnostic signal off-chip to ensure the ring is operational.

[0109] In the above embodiment, the resistance states LRS and HRS were described as having values ​​of 112 kΩ and 8.04 MΩ, respectively.

[0110] It will be appreciated that different values ​​of LRS and HRS can be used to obtain the same functionality as described above. Furthermore, the actual values ​​may depend on the technology and manufacturing process used. The values ​​of HRS and LRS are such that LRS causes the voltage divider circuit to operate in bypass mode, and HRS causes the voltage divider circuit to operate in voltage divider mode.

[0111] In principle, an LRS that tends to 0 is C when in the LRS. mr If LRS tends to 0, there is no problem with functionality. As a non-limiting example, LRS can be in the range of 100-1000 ohms.

[0112] Regarding the HRS, in principle, an HRS that goes to infinity provides a clean cut for the bypass path. If the HRS goes to infinity, there is no problem with functionality. As a non-limiting example, the HRS may be greater than 10 M ohms.

[0113] Regarding the capacitance value, C mr may be substantially the same magnitude as the parasitic capacitance of an intermediate node, e.g., element 116 in FIG. 1. As a non-limiting example, using a CMOS 180 nm process, C mr can be in the range of 500-700 aF (atto-Farad), but it can also be 400 aF or less.

[0114] For Cb, this is C mr multiples of, e.g., C mr 5 to 10 times, preferably C mr However, the actual value depends on other factors such as parasitics in the circuit. As a non-limiting example, using a CMOS 180 nm process, e.g., C mr can be substantially about 6 fF (femtofarads). As a further non-limiting example, using a CMOS 90 nm process may further reduce this to about 5 fF or less depending on the configuration. mr It is limited by, but can be as small as desired.

[0115] Those skilled in the art will appreciate that variations of the disclosed arrangements are possible without departing from the scope of the invention.

[0116] As a first example, in the above embodiment, the midpoint node mainly comprises four capacitances: a) RRAM element C mr b) the capacitance of the bottom or ballast, C b , c) the parasitic capacitance of the write transistor Q1 (C q1 ), and d) the parasitic capacitance of the output transistor Q2 (C q2) is exposed to a voltage across the memory cell. Figure 10 shows an alternative embodiment in which the bottom capacitor is removed, and the bottom (or ballast) capacitor is removed from the memory cell, with part of the capacitance divider instead being provided by the parasitic capacitance of write transistor Q1. The parasitic capacitance of Q1 pairs with the parasitic capacitance of the RRAM to form the capacitance divider. In such an embodiment, the capacitance of Q1 provides all of the capacitance required for operation, and therefore no additional C b It plays the role of Cb without any components.

[0117] As described with reference to FIG. 1, the memory cell 600 includes the same components: a variable resistance element 608, a C mr The RRAM 610 has a parasitic capacitance represented by 612, a write transistor 602, an output transistor 604, and a further transistor 606. The memory cell is serviced by a cue 620, a cue-bar 622, a switch line 624, and a match line 628. In such an embodiment, C mr The capacitance value of can be reduced to a lower value than that used in FIG. 1. It will be understood that the value is determined based on the parasitics within the system, which is determined by the parasitics around the system. As a non-limiting example, the capacitance value may be as low as 0.44 fF (compared to 2.2 fF). In FIG. 10, the parasitic capacitance of write transistor Q1 is used in place of the bottom capacitance, serving the same role of equalizing the capacitance divider.

[0118] In the above embodiment, the bottom capacitor is the primary contributor to capacitance in the system. The bottom capacitor can be understood as the primary energy storage device where charge resides when memory contents are evaluated in the CAR. Then, C mr acts as a counterweight to it, which is either present or absent depending on the RRAM (as mentioned above, it may or may not be present depending on the resistance state of the RRAM).

[0119] In this embodiment, the PSW and CUE_BAR lines are combined. For CAR operations, it was observed in FIG. 4 that the PSW and CUE_BAR may be combined because they are synchronized. For AAR operations, peripheral circuit modifications can be made to allow the cue-bar peripheral to remain tri-stated (thus, in high-impedance state Z, no active drive is allowed to them) while the PSW peripheral controls and operates the combined PSW and CUE_BAR lines. Similarly, for write operations, the peripheral cue-bar circuit is tri-stated, and the PSW peripheral controls and operates the combined PSW-cue-bar line. In embodiments, the PSW and CUE_BAR drivers may be merged together. In such an embodiment, the three transistors previously coupled to the CUE_BAR now control the operation of the device. The only further modification is the logic that determines which of the transistors is controlling the line at any given time.

[0120] As a further example, the above-described embodiments have described capacitance divider configurations. It will be appreciated that alternative voltage divider configurations may be used in accordance with further embodiments. In general, any voltage divider configuration may be implemented that can divide a voltage based on the impedance or resistance state of the memory elements. For example, an impedance divider configuration in which the memory elements have high or low impedance states may be appropriate.

[0121] As a further example, according to an embodiment, a voltage divider may be any impedance divider having one or more impedances of the divider, or a component that provides the divider impedance with a reactive component. It will be understood that such an impedance divider may be implemented using different combinations of components. Both impedances may be described by Z = R + Xi, where Z is the impedance, R is the resistance, X is the reactance (either capacitor-reactance or inductor-reactance), i is a complex unit (the square root of -1), and ii) X is non-zero. In a first non-limiting class of examples, R is non-zero and may be variable / changeable. In a second non-limiting class of examples, for a purely capacitive divider, R may be 0, but the capacitance is variable / changeable. A further set of examples includes the case where R is non-zero and both R and C are variable / changeable. A further class of examples includes when R is non-zero and X is either C-type (capacitance) or L-type (inductance) or a mixture thereof, and X is variable / changeable via capacitance or inductance or both.

[0122] It will be appreciated that the one or more impedance states can be either reactive or resistive states alone, or a combination of reactance and resistance. In embodiments where high and low impedance states are discussed, it will be appreciated that the resistive and reactance contributions are combined in vector form to create a single overall impedance vector, and that the high and low impedance states refer to the magnitude of the impedance vector. Furthermore, the values ​​of the high and low impedance states are such that in the low impedance state, the voltage divider circuit operates in bypass mode, and C mr It will be appreciated that the voltage divider circuit is such that in the high impedance state, the voltage divider circuit acts as a voltage divider.

[0123] As a further example, the above-described embodiments relate to programmable memory elements in that the resistance state can be set by a write circuit. Alternative voltage divider embodiments using fixed-value components may also be implemented in accordance with the embodiments. As a first, non-limiting example, a voltage divider configuration based on a resistive divider may be used. In such an example, the resistors are not variable / programmable but rather have fixed resistance values. The resistors are selected so that different resistor configurations can represent data. While such a device may only provide read-only functionality, it may offer security benefits because the resistors can be visually inspected to identify tampering. In such an example, the resistors may be selected so that the high and low resistance states approximate an infinite, zero-resistance system. A capacitance-divider-based configuration using fixed-value capacitors may also be implemented. In a related alternative embodiment, a voltage divider configuration with a fixed impedance value is provided.

[0124] As a further non-limiting example, the RRAM elements may be replaced with memcapacitor elements. The memcapacitor may allow for the application of clean ones or zeros (no DC path, and therefore no charge shuttling to or from the intermediate node except upon reset), allowing operation at any frequency as long as leakage current is tolerable. In principle, the memcapacitor may allow all possible frequencies. Logically speaking, ones and zeros can be as clean as the ratio of component impedances allows. In the limiting case with a memcapacitor, there is never an exchange of charge between the intermediate node or CUE and CUE_bar except upon reset. In such an embodiment, the memcapacitor may be paired with additional elements, such as a resistor or capacitor in a voltage divider configuration.

[0125] As a further example, the above-described embodiments describe non-volatile RRAM elements. In alternative embodiments, volatile memory elements that only temporarily retain data may be used. Such devices may be used for so-called scratchpad memories or other temporary memories configured to store temporary data. Such temporary data may, for example, be related to the subject the system is currently addressing. Such embodiments may be implemented, for example, by changing the relative frequencies of read and write operations.

[0126] In the above-described embodiments, the memory circuitry has been described as operating as a content-addressable memory. In some embodiments, the same circuitry may function as one or all of a CAM, a non-volatile RAM, and a volatile RAM. As a further exemplary embodiment, the memory device may operate as a volatile DRAM for temporary storage of data. DRAM embodiments may be considered a polymorphism to associative memory. When retrieval is not required, the circuitry may operate in a dynamic random access memory (DRAM) mode as follows: In such a mode, a capacitor is used to store data as an electric charge.

[0127] Initially, the cue lines (cue and cue-bar) are set to ground, and the write transistors can function as DRAM mode transistors. The EN (not shown) on the match line is kept off, thus resulting in the equivalent circuit shown in Figure 12.

[0128] The equivalent circuit of FIG. 12 shows a write transistor 1202, an RRAM element 1210, a capacitor 1214, a cue line 1214, a cue-bar line 1222, a sw line 1224, and a psw line 1226.

[0129] To operate as a DRAM, the RRAM element 1210 is controlled to be set to a high resistance state, preferably an ultra-high resistance state. While operating as a DRAM device, the RRAM element remains in the high resistance state. Both cue lines are connected to ground. Data is then stored in the capacitor 1214 as trapped charges. The PSW line 1226 can then be operated as a bit line and the sw line 1222 can be operated as a word line, causing the write transistor 1202 to function as a DRAM mode transistor (i.e., perform read and write operations).

[0130] It will therefore be understood that the memory circuitry is operable to store all of the following: volatile and non-volatile content-addressable memory stored as component values; volatile and non-volatile address-addressable memory stored as component values; and volatile address-addressable memory stored as electrical signals (independent of component values).

[0131] It will be further understood that the variable resistance element may, in some embodiments, be a variable resistance device and may be formed from two or more components that operate together to achieve a resistance and / or impedance state that represents at least a portion of the data.

[0132] Accordingly, the above description of specific embodiments is intended to be illustrative and not limiting, as it will be apparent to those skilled in the art that minor modifications may be made without significantly altering the described operation.

Claims

1. 1. A memory device for storing data, comprising: a voltage divider circuit comprising at least one memory element, the at least one memory element operable or selected to assume a resistance and / or impedance state representative of at least a portion of the data; 10. A memory device, comprising: a memory cell configured to: provide a voltage divider circuit for dividing a voltage according to the resistance and / or impedance state of the at least one memory element as part of a data read and / or data write operation; and wherein the at least one memory element is capacitive and connected to one or more further capacitive elements such that the voltage divider circuit comprises a capacitor divider configuration.

2. 10. The memory device of any preceding claim, wherein the voltage divider circuit is configured to avoid and / or at least reduce a resistance path during the data read and / or data write operations of the at least one variable resistance memory element.

3. 10. A memory device according to any preceding claim, wherein the at least one memory element is operable to be in a high or low resistance and / or impedance state, and wherein the voltage divider circuit is configured to at least reduce the voltage shared with the at least one memory element of the voltage divider circuit when the at least one memory element is in a low resistance and / or impedance state.

4. 10. A memory device according to any preceding claim, wherein the voltage divider circuit is configured to share the voltage between the at least one memory element and the one or more further elements when the at least one memory element is in a high impedance state.

5. 10. A memory device according to any preceding claim, wherein the voltage divider circuit is configured to act as a capacitance divider when the at least one memory element is in a high resistance and / or high impedance state.

6. 6. The memory device of claim 5, wherein a parasitic capacitance of the memory element (and optionally one further element) provides a portion of the capacitance of the capacitance divider.

7. 10. The memory device of any preceding claim, wherein the at least one memory element is configured to substantially block and / or allow current flow through the at least one memory element depending on the resistance and / or impedance state of the memory element.

8. the voltage divider circuit comprising the at least one memory element connected to one or more further elements, the voltage divider being connected between a first data line and a second data line, and the device further comprising: at least one output transistor connected between the at least one memory element and the one or more further elements such that a voltage division is provided at a gate electrode of the at least one output transistor; 10. A memory device according to any preceding claim, comprising: said at least one output transistor coupled to a match line, thereby controlling said match line in response to said voltage division.

9. 9. The memory device of claim 8, wherein the at least one output transistor has a threshold voltage such that the match line is switched depending on whether data represented by the first data line and the second data line matches data stored in the at least one memory element.

10. 10. The memory device of claim 8, further comprising at least one write transistor connected between the at least one memory element and the one or more further elements, the at least one write transistor operable to apply a voltage to the memory element, thereby writing data to the memory element.

11. A memory device according to any one of claims 8 to 10, further comprising at least one further transistor operable to enable data to be read from said at least one memory element, for example as part of a content addressable read operation.

12. 10. A memory device according to any preceding claim, wherein the voltage divider circuit is coupled to one or more, optionally two, search lines for providing an input voltage representative of query data, the voltage divider circuit being configured to output a voltage representative of a match and / or a mismatch between the stored data and the query data.

13. 10. A memory device according to any preceding claim, wherein the memory device is configured to perform content addressable read operations.

14. 10. A memory device according to any preceding claim, wherein the device further comprises a read circuit for performing the data read operation, the data read operation comprising receiving an output voltage from the voltage divider circuit, the output voltage depending at least on the resistance state and / or the impedance state of the memory element, and optionally the read circuit comprising at least one output transistor driven by the output voltage of the voltage divider circuit.

15. 10. The memory device of any preceding claim, further comprising a write circuit for applying a voltage to the at least one memory state, thereby setting the resistance and / or impedance state of the at least one memory element, optionally wherein the write circuit comprises at least one write transistor coupled to the voltage divider circuit.

16. 10. A memory device according to any preceding claim, wherein the at least one memory element is selected or operable to be in one of a plurality of resistance and / or impedance states, and / or the at least one memory element comprises a variable resistance and / or variable impedance memory element operable to be in one of two or more resistance and / or impedance states.

17. 10. A memory device according to any preceding claim, wherein the at least one memory element and optionally the one or more further elements comprise a non-zero reactance.

18. 10. A memory device according to any preceding claim, wherein the at least one memory element is configured to retain the resistance and / or impedance state in the absence of power.

19. 10. A memory device according to any preceding claim, wherein the at least one memory element is operable to be in at least a first resistance and / or impedance state or a second resistance and / or impedance state, thereby representing a binary data bit.

20. 10. The memory device of any preceding claim, wherein the memory elements comprise memristors, RRAM elements, memcapacitors, phase change material (PCM) devices, magnetic tunnel junctions (MTJs), programmable resistors, non-volatile switches, floating gate MOSFETs.

21. 10. A memory device as described in any preceding claim, wherein the voltage divider circuit is operable in one or more modes including at least a content addressable read mode, an address addressable read mode, and a write mode of operation, and optionally the memory device comprises control circuitry configured to select the mode of operation of the memory device.

22. 10. A memory device according to any preceding claim, wherein the memory device comprises a non-volatile memory device and / or wherein the memory device forms part of a bit cell or memory cell.

23. 10. A memory device according to any preceding claim, wherein the memory device is further operable as a volatile memory and / or a dynamic RAM memory and / or operable to store data on a capacitor.

24. 1. A method of performing data read and / or data write operations using a memory device, the memory device comprising: a voltage divider circuit comprising at least one memory element, the at least one memory element operable or selected to be in a resistance and / or impedance state representative of at least a portion of data; providing a memory device voltage divider circuit, the at least one memory element being capacitive and connected to one or more further capacitive elements such that the voltage divider circuit comprises a capacitor divider configuration; The method includes dividing a voltage applied to the voltage divider circuit in response to the resistance and / or impedance as part of a data read and / or data write operation.

25. A memory system comprising a plurality of memory cells, each memory cell comprising: a voltage divider circuit comprising at least one memory element, said at least one memory element operable or selected to assume a resistance and / or impedance state representative of at least a portion of said data; the voltage divider circuit is configured to divide a voltage according to the resistance and / or impedance state of the at least one memory element as part of a data read and / or data write operation, the at least one memory element being capacitive and connected to one or more further capacitive elements such that the voltage divider circuit comprises a capacitor divider configuration; one or more common read and / or write lines for one or more groups of said plurality of memory cells; A memory system comprising:

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