Embedded cooling assembly for new device packaging and method of manufacturing same

Abstract

The device package includes a package substrate, a package cover disposed on the package substrate, and an integrated cooling assembly disposed between the package substrate and the package cover. Generally, an inlet opening and an outlet opening are formed through the package cover. The integrated cooling assembly includes a semiconductor device and a cold plate attached to the semiconductor device. The device package may include a material layer disposed between the package cover and the cold plate. The cold plate may have a patterned first side and an opposite second side. The patterned first side may include a base surface and sidewalls extending downwardly from the base surface, the base surface being spaced apart from the semiconductor device to thereby together form a coolant channel between the base surface and the semiconductor device. In this case, the coolant channel is in fluid communication with the inlet opening and the outlet opening via a plurality of openings each extending through corresponding portions of the material layer.

Description

[Technical Field]

[0001] FIELD OF THE DISCLOSURE The present disclosure relates to novel packaging techniques for microelectronic devices, and more particularly to embedded cooling systems for device packaging and methods of fabricating the same. [Background technology]

[0002] Energy consumption poses a very serious challenge for the future of large-scale computing, as global computing energy needs are growing at a rate considered unsustainable by most. Some models predict that the information, communications, and technology (ICT) ecosystem could exceed 20% of global electricity use by 2030, with direct electricity consumption by large computing centers accounting for more than one-third of that energy use. Cooling costs account for a significant portion of a computing center's energy needs, as even small increases in operating temperature can adversely affect the performance of microprocessors, memory devices, and other electronic components.

[0003] Heat dissipation in high-power-density chips is also a significant challenge due to increased power density and correspondingly increased heat flux, which contributes to high chip temperatures, resulting from improved chip performance, for example, through increased gate density and the use of multicore microprocessors. These high temperatures are undesirable because they reduce the chip's operational performance, efficiency, and reliability. Cooling systems used to maintain a chip at a desired operating temperature typically employ one or more heat-dissipating devices, such as thermal spreaders, heat pipes, cold pipes, or heat sinks, to remove heat. These heat-dissipating devices are thermally coupled to the chip using compliant, thermally conductive materials, such as thermal pastes, thermal adhesives, and thermal gap fillers. Thermal interface materials (TIMs) maintain thermal contact between the chip and the heat-dissipating device surfaces to facilitate heat transfer between them. Unfortunately, the thermal resistance of the thermal interface material, combined with the thermal resistance at the interface region, can impede heat transfer from the chip to the heat-dissipating device, undesirably reducing the cooling efficiency of the cooling system. Summary of the Invention [Problem to be solved by the invention]

[0004] Therefore, there is a need in the art for improved energy efficient cooling systems and methods of manufacturing same. [Means for solving the problem]

[0005] Embodiments herein provide an integrated device cooling assembly embedded within a novel device package that advantageously shortens the thermal resistance path between the device and the heat sink, as well as reduces thermal communication between devices within the same package.

[0006] In one general aspect, the device package includes a package substrate, a package cover disposed on the package substrate, and an integrated cooling assembly disposed between the package substrate and the package cover. The package cover generally has an inlet opening and an outlet opening therethrough. The integrated cooling assembly includes a semiconductor device and a cold plate attached to the semiconductor device. The device package further includes a material layer disposed between the package cover and the cold plate. The cold plate may have a patterned first side and an opposite second side. The patterned first side may have a bottom surface and sidewalls extending downwardly from the bottom surface, the bottom surface being spaced apart from the semiconductor device to thereby together form a coolant channel between the bottom surface and the semiconductor device. In this case, the coolant channel is in fluid communication with the inlet opening and the outlet opening via a plurality of openings each extending through corresponding portions of the material layer.

[0007] An embodiment may include a method for manufacturing a device package, the method including: direct-bonding a first substrate having a semiconductor device to a second substrate having a cold plate; and singulating an integrated cooling assembly including the semiconductor device and the cold plate from the bonded first and second substrates. The method further includes sealing a package cover to the second side using a material layer disposed between the package cover and the second side; and forming openings in the material layer, either before or after attaching the package cover to the second side, to fluidly couple the inlet and outlet openings to the coolant channels. In this case, the cold plate may have a first side directly bonded to the semiconductor device and a second side opposite the first side. Typically, one or more surfaces of the first side are spaced apart from the semiconductor device to form coolant channels between the first side and the semiconductor device. The package cover may have inlet and outlet openings. The openings in the material layer may fluidly couple the inlet and outlet openings to the coolant channels.

[0008] These and other objects and advantages of the present disclosure will become apparent from a consideration of the following detailed description taken in conjunction with the accompanying drawings. [Brief explanation of the drawings]

[0009] [Figure 1] FIG. 1 is a schematic plan view of an example of a system panel according to embodiments of the present disclosure. [Figure 2] 2 is a schematic, partial cross-sectional side view of a portion of the system panel of FIG. 1. [Figure 3A] FIG. 1 is a schematic exploded isometric view of an exemplary device package according to embodiments of the present disclosure. [Figure 3B] 3B is a schematic cross-sectional view of the device package taken along line A-A' in FIG. 3A. [Figure 3C] FIG. 3C is a schematic exploded isometric bottom-up view of the integrated cooling assembly shown in FIG. 3B. [Figure 4A] 1 is a schematic cross-sectional view of another embodiment of a device package that can be used with a system panel. [Figure 4B] FIG. 4B is an exploded isometric bottom-up view of the integrated cooling assembly shown in FIG. 4A. [Figure 5] 1A-1C are a series of schematic cross-sectional side views of a multi-component device package including a cold plate directly bonded to the backside of two or more devices. [Figure 6] 1 is a schematic cross-sectional side view of an exemplary multi-component device package according to one embodiment of the present disclosure. [Figure 7] 1 is a schematic cross-sectional side view of a 3DIC device package according to an embodiment of the present disclosure. [Figure 8] 1 is a schematic cross-sectional side view of a device package according to one embodiment of the present disclosure. [Figure 9] FIG. 1 illustrates a method that can be used to manufacture the device packages described herein. [Figure 10]1A-1C show device packages at different stages of manufacture to illustrate aspects of the present method. DETAILED DESCRIPTION OF THE INVENTION

[0010] While the figures herein illustrate various embodiments of the present disclosure, these are by way of example only, and it will be recognized that additional or alternative structures, assemblies, systems, and methods may be embodied within the principles illustrated by the present disclosure.

[0011] Embodiments herein provide an integrated cooling assembly embedded within a device package that shortens the thermal resistance path between the device and the heat sink, as well as reduces thermal communication between devices within the same package.

[0012] As used herein, the term "substrate" means and includes any workpiece, wafer, or article that provides a base material or support surface upon which components, elements, devices, assemblies, modules, systems, or features of the heat-generating devices, packaging components, and cooling assemblies described herein can be mounted or configured. The term substrate further includes a "semiconductor substrate" that provides a support material upon which or on which elements of a semiconductor device can be fabricated or attached and any material layers, features, and / or electronic devices formed thereon, in, or through.

[0013] As described below, semiconductor substrates herein generally have a "device side," e.g., a side (surface) carrying semiconductor device elements such as transistors, resistors, and capacitors, and a "back side" opposite the device side. The term "active side" should be understood to include the device-side surface of a substrate, and may also include the device-side surface of a semiconductor device and / or the surface of any material layers, device elements, or features formed thereon or extending outward therefrom, and / or any openings formed therein. Thus, it should be understood that the material forming the active side can vary depending on the device fabrication and assembly stage. Similarly, the term "non-active side" (opposite the active side) includes the non-active side of a substrate at any device fabrication stage, including the surface of any material layers, device elements, or features formed thereon or extending outward therefrom, and / or any openings formed therein. Thus, the terms "active side" and "non-active side" may include the respective surfaces of a semiconductor substrate at the start of device fabrication as well as any surfaces formed during material removal, e.g., after a substrate thinning operation. Depending on the device fabrication or assembly stage, the terms "active side" and "non-active side" may also be used to refer to surfaces of material layers or features formed on, in, or through a semiconductor substrate, whether or not the material layers or features are ultimately present in the fabricated or assembled device.

[0014] Spatial terms are used herein to describe relationships between various elements, such as substrates, heat-generating devices, cooling assembly components, device package components, and other features described below. Unless otherwise specified, terms such as "above," "over," "upper," "outward," "on," "below," "under," "below," and the like are generally defined with respect to the X, Y, and Z directions depicted in the drawings. Thus, it should be understood that spatial terms used herein encompass different orientations of the substrate and are not limited by the direction of gravity, unless otherwise specified. Unless otherwise specified, terms describing relationships between elements, such as "on," "embedded in," "coupled to," "connected by," "mounted to," and "bonded to," alone or in combination with spatial terms, include both relationships with intervening elements and direct relationships without intervening elements.

[0015] Unless otherwise specified, the term "cold plate" generally refers to a base plate or a stack of base plates directly bonded to one another, which may be bonded to a semiconductor device. The cold plate may have material layers and / or metallic features formed within or on the surface of the base plate or stack of base plates that facilitate direct dielectric or hybrid bonding with the semiconductor device. The term "integrated cooling assembly" generally refers to a cold plate attached to a semiconductor device, the assembly being attached to form a single piece, for example, by using a direct bonding method described below. The direct bonding method can transfer heat from the semiconductor device from the cold plate to a fluid flowing thereover without the use of a thermal interface material. Unless otherwise specified, the device packages and cold plates described herein can be used with any desired fluid coolant, for example, a liquid-phase, gas-phase, and / or vapor-phase coolant. Thus, these terms should not be construed as limiting the coolant to any one fluid phase.

[0016] Typically, device packages for high heat flux devices are cooled by an external heat sink attached to a thermal spreader that forms the package cover. The devices within the device package are thermally coupled to the package cover using one or more thermally conductive materials, such as a thermal interface material (TIM) layer disposed therebetween, where the TIM layer is formed of a compliant material, such as a thermally conductive paste, grease, adhesive, or other thermally conductive material, such as a fusible metal alloy, e.g., solder, or a combination thereof. Unfortunately, as heat flux density increases with shrinking device size, the cumulative thermal resistance of the components in such device packages becomes increasingly problematic because the heat cannot be dissipated quickly enough to enable the device to operate at optimal power, thereby reducing the energy efficiency of the device. Heat transfer between devices within a single package is also problematic, where heat may follow a thermal path from a device with a high heat flux, such as a CPU or GPU, to one or more devices with a low heat flux, such as memory.

[0017] Typically, the thermal resistance of the TIM layer accounts for 80% or more of the cumulative thermal resistance of the heat transfer path between the device and an external heat sink, which prevents the cooling efficiency levels desired for next generation device packages. Accordingly, embodiments herein provide an integrated cooling assembly embedded within a device package that shortens the thermal resistance path between the device and the heat sink, thereby reducing thermal communication between devices mounted within the same package.

[0018] 1 is a schematic plan view of an example system panel 100 according to embodiments of the present disclosure. In this case, the system panel 100 includes a printed circuit board, here a PCB 102, a plurality of device packages 301 mounted on the PCB 102, and a plurality of coolant lines 108 fluidly coupling each of the device packages 301 to a coolant source 110. It is contemplated that the coolant may be delivered to each of the device packages 301 in any desired fluid phase, such as a liquid, vapor, gas, or a combination thereof, and may exit the device packages 301 in the same phase or a different phase. In some embodiments, the coolant may be delivered to and returned from the device packages 301 as a liquid, and the coolant source 110 may include a heat exchanger or chiller to maintain the coolant at a desired temperature. In other embodiments, the coolant may be delivered to the device packages 301 as a liquid, evaporate to a gas within the device packages, and return to the coolant source 110 as a vapor. In these embodiments, the device package 301 may be fluidly coupled in parallel to the coolant source 110, which may have or further include a compressor (not shown) to condense the received vapor into liquid form.

[0019] 2 is a schematic, partial cross-sectional side view of a portion of the system panel 100 of FIG. 1. As shown, each device package 301 is mounted within a socket 204 of a PCB 102 and coupled to the socket using a plurality of pins 202 or other suitable coupling method, such as solder bumps (not shown). The device package 301 may be seated within the socket 204 and secured to the PCB 102 using a mounting frame 106 and a plurality of fasteners 112, such as compression springs, configured to together exert a relatively uniform downward force on the upwardly facing edge of the device package 301. The uniform downward force ensures proper pin contact between the device package 301 and the socket 204.

[0020] FIG. 3A is a schematic exploded isometric view of an exemplary device package 301 according to embodiments of the present disclosure. FIG. 3B is a schematic cross-sectional view of the device package 301 taken along line A-A′ in FIG. 3A . The device package 301 includes, as its main components, a package substrate 302, an integrated cooling assembly 303 disposed on the package substrate 302, and a package cover 308 disposed on a peripheral portion of the package substrate 302 and extending over the integrated cooling assembly 303, such that the integrated cooling assembly 303 is disposed between the package substrate 302 and the package cover 308. As shown, the device package 301 further includes an encapsulant layer 322 that forms a coolant-impermeable barrier for the package cover against the integrated cooling assembly. Coolant is delivered to the integrated cooling assembly 303 through inlet / outlet openings 312 in the package cover 308 and corresponding openings 322A formed through the encapsulant layer 322. In some embodiments, the device package 301 may further include a support member 307 attached to the integrated cooling assembly 303 .

[0021] Generally, package substrate 302 comprises a rigid material, such as an epoxy or resin-based laminate, that supports integrated cooling assembly 303 and package cover 308. Package substrate 302 may have conductive features disposed in or on the rigid material that electrically couple integrated cooling assembly 303 to a system panel, such as PCB 102.

[0022] 3C is a schematic, bottom-up, exploded isometric view of the integrated cooling assembly 303 shown in FIG. 3B. As shown, the integrated cooling assembly 303 may include a semiconductor device, in this case, device 304, and a cold plate 306 bonded to device 304. In this case, device 304 includes an active side 318 on or within which device components, such as transistors, resistors, and capacitors, are formed, and device 304 includes a non-active back side opposite active side 318, in this case, device back side 320. As shown, active side 318 is positioned adjacent to and facing package substrate 302. Active side 318 may be electrically coupled to package substrate 302 using conductive bumps 319, which are encapsulated by a first underfill layer 321 disposed between device 304 and package substrate 302. The first underfill layer 321 may be comprised of a cured polymer resin or epoxy that provides mechanical support to the conductive bumps 319 and prevents thermal fatigue.

[0023] 3B and 3C, the cold plate 306 generally has a patterned side that faces the device 304 and defines an upper portion of the coolant channels 310 when the cold plate 306 is attached to the device backside 320, and an opposite side that faces the package cover 308. In this case, the patterned side forms a device-facing cavity having a base surface 309 and sidewalls 311 that surround and project downwardly from the base surface 309. When attached to the underlying device 304, the sidewalls 311 form the perimeter of the coolant channels 310, and the base surface 309 forms the uppermost surface of the coolant channels 310. The device backside 320 forms the bottom of the coolant channels 310 and is in direct thermal contact with the coolant flowing therethrough. In this case, coolant circulates through coolant channels 310 via openings provided through cold plate 306, in this case shown as opening 306A provided between downwardly facing base surface 309 and the opposite upwardly facing surface. Opening 306A is in fluid communication with inlet / outlet openings 312 of package cover 308 through opening 322A formed in an encapsulant layer 322 provided between opening 306A and package cover 308.

[0024] In some embodiments, the cold plate 306 has a plurality of protruding features 324, such as fins, columns, or pillars, extending downward from the base surface 309. The protruding features 324 increase surface area and facilitate laminar flow of fluid at the interface between the coolant and the cold plate 306, thereby increasing heat transfer therebetween. To further increase heat dissipation from the device, the protruding features 324 may be comprised of and / or formed from a thermally conductive metal, such as copper. The protruding features 324 may be arranged in a repeating pattern, as shown, or in a random or non-repeating pattern. As envisioned, each embodiment of the device package described herein may have a cold plate having a base surface 309, a sidewall 311, and a patterned side that includes a plurality of protruding features 324, even if they are not explicitly described.

[0025] In this case, the cold plate 306 is attached to the device backside 320 without an intervening adhesive material; for example, the cold plate 306 may be directly bonded to the device backside 320, such that the cold plate 306 and the device backside 320 are in direct thermal contact. In some embodiments, the cold plate 306 is attached to the device backside 320 using a direct dielectric bonding process. In other embodiments, the cold plate 306 is attached to the device backside 320 using a hybrid of a direct dielectric and direct metallic bond formed therebetween. For example, in some embodiments, one or both of the device backside 320 and the device-facing side of the cold plate 306 are comprised of a dielectric layer, e.g., a first dielectric layer 334A and a second dielectric layer 334B, and the cold plate 306 is directly bonded to the device backside 320 via a bond formed between the dielectric layers 334A and 334B. In some embodiments, the cold plate 306 is directly bonded to the device backside 320 using a hybrid bonding technique, with bonds formed between the dielectric layers 334A, 334B and between metal features disposed within the dielectric layers 334A, 334B, such as between the first metal pad 336A and the second metal pad 336B.

[0026] Suitable dielectrics that can be used for the dielectric layers 334A, 334B include silicon oxide, silicon nitride, silicon oxynitride, silicon carbonitride, metal oxides, metal nitrides, silicon carbide, silicon oxycarbide, silicon oxycarbonitride, silicon carbonitride, diamond-like carbon (DLC), or combinations thereof. In some embodiments, one or both of the dielectric layers 334A, 334B are formed of an inorganic dielectric, i.e., a dielectric that is substantially free of organic polymers. Typically, one or both of the dielectric layers 334A, 334B are deposited to a thickness greater than that of a native oxide, e.g., about 1 nm or more, 5 nm or more, 10 nm or more, 50 nm or more, 100 nm or more, or 200 nm or more. In some embodiments, one or both of the layers 334A, 334B are deposited to a thickness of 300 nm or less, e.g., 200 nm or less, 100 nm or less, or 50 nm or less.

[0027] In some embodiments, the cold plate 306 is formed from a material having a coefficient of thermal expansion (CTE) that is approximately the same as the CTE of the bulk semiconductor substrate of the device 304. For example, in some embodiments, the device 304 may be formed on a single crystal silicon substrate, and the cold plate 306 may be made from a single crystal silicon or polycrystalline silicon substrate. Forming the cold plate 306 from a CTE-matched material (with respect to the bulk substrate material of the device 304) prevents undesired separation of the device 304 and the cold plate 306 throughout repeated thermal cycling.

[0028] In some embodiments, the cold plate 306 may be made from bulk substrate materials, including amorphous silicon materials, such as metals, metal alloys, ceramics, composites, and other low CTE materials suitable for bonding using the methods described below. For example, the cold plate 306 may be made from a bulk material selected from the group consisting of copper, aluminum, copper alloys (e.g., copper-molybdenum alloys and copper-tungsten alloys), iron-cobalt-nickel alloys (e.g., Kovar® available from Magellan Industrial Trading Co., Inc., South Norwalk, Connecticut, USA), iron-cobalt-nickel-silver alloys, iron-nickel alloys (e.g., Invar® superalloy available from Magellan), iron-nickel-silicon alloys, aluminum-silicon carbide, aluminum-silicon alloys, beryllium-beryllium oxide, beryllium composites, beryllium oxide composites, aluminum-graphite fibers, copper-graphite fibers, metal-diamond composites (e.g., aluminum-diamond composites and silver-diamond composites), metal oxides, metal nitrides, and combinations thereof. The non-silicon substrate material may be prepared for bonding as described below, and may or may not include a dielectric layer deposited on the side facing the device to form a bonding surface. Methods for forming direct dielectric bonds and direct hybrid bonds are described below.

[0029] Beneficially, device package 301 reduces the thermal resistance of heat transfer path 326 compared to a heat transfer path to an external heat sink. In some embodiments, the cumulative thermal resistance of heat transfer path 326 is reduced by a factor of 50 compared to the cumulative thermal resistance of the device package when cooled using an external heat sink.

[0030] The package cover 308 generally has one or more vertical or sloped sidewall portions 308A and a lateral portion 308B spanning and connected to the sidewall portions 308A. The sidewall portions 308A extend upward from the periphery of the package substrate 302 to enclose the device 304 and a cold plate 306 mounted thereon. The lateral portion 308B is attached to the cold plate 306 and is typically spaced from the cold plate 306 by a gap corresponding to the thickness of the encapsulant layer 322. Coolant circulates through the coolant channels 310 through inlet / outlet openings 312 formed through the lateral portion 308B. For each of the embodiments described herein, the cooling lines 108 may be attached to the device package 301 by using connector features formed in the package cover 308, such as threads formed in the sidewall of the inlet / outlet openings 312 and / or protruding features 314 surrounding the openings 312 and extending upward from the surface of the lateral portion 308B.

[0031] Typically, the package cover 308 is formed of a semi-rigid or rigid material such that at least a portion of the downward force exerted by the mounting frame 106 (FIG. 2) on the package cover 308 is transferred to the support surface of the package substrate 302, but not to the cold plate 306 and underlying device 304. In some embodiments, the package cover 308 is made of a thermally conductive metal, such as aluminum or copper. In some embodiments, the package cover 308 functions as a heat spreader to redistribute heat from one or more electronic components within a multi-component device package, for example, as described below.

[0032] The encapsulant layer 322 is disposed between the integrated cooling assembly 303 and the package cover 308 and forms an impermeable barrier that prevents coolant from reaching and damaging the active side 318 of the device 304. In some embodiments, the encapsulant layer 322 is comprised of a polymer or epoxy material that extends upward from the package substrate 302 to encapsulate and / or surround at least a portion of the device 304. In other embodiments, the encapsulant layer 322 may be disposed between only the upwardly facing surface of the cold plate 306 and the portion of the package cover 308 that covers it. In some embodiments, the encapsulant layer is formed from a molding compound, such as a thermosetting resin, that, when polymerized, forms an airtight seal between the package cover 308 and the cold plate 306. In this case, the coolant is delivered to the cold plate 306 through openings 322A disposed through the encapsulant layer 322. As shown, opening 322A is aligned with and in fluid communication with inlet / outlet opening 312 in the overlying package cover 308 and inlet / outlet opening 306A in the underlying cold plate 306. Typically, coolant line 108 is attached to device package 301 by use of connector features formed in package cover 308, such as threads formed in the sidewall of inlet / outlet opening 312 and / or protruding features 314 that surround inlet / outlet opening 312 and extend upward from the surface of lateral portion 308B.

[0033] Beneficially, the encapsulant layer 322 provides mechanical support that improves system reliability and extends the useful life of the device package 301. For example, the second encapsulant layer 322 can reduce mechanical stresses, such as stresses caused by vibration, mechanical and thermal shock, and / or fatigue caused by repeated thermal cycling, that can weaken interface bonds and / or electrical connections between electrical components of the device package 301. In some embodiments, the encapsulant layer 322 can be a thermally conductive material, such as a polymer or epoxy containing one or more thermally conductive additives, such as silver and / or graphite. In some embodiments, the device package 301 further includes a support member 307 attached to the upward-facing side of the cold plate 306, which can be formed of a rigid material, such as a metal or ceramic plate, that provides mechanical support to the cold plate 306. The support member 307 can be attached to the cold plate 306 using a direct bonding method or by using an intervening adhesive layer (not shown).

[0034] 4A is a schematic cross-sectional view of another embodiment of a device package 401 that can be used with system panel 100. In this case, device package 401 includes package substrate 302, package cover 308, integrated cooling assembly 403 disposed between package substrate 302 and package cover 308, and encapsulant layer 422 disposed between integrated cooling assembly 403 and package cover 308.

[0035] 4B is a bottom-up exploded isometric view of the integrated cooling assembly 403 shown in FIG. The cooling assembly 403 includes, as its main components, the device 304 and a cold plate 406 attached to the back side of the device 304, for example, by using the direct bonding method described above. The cold plate 406 generally has a patterned side facing the device 304 and defining an upper portion of the coolant channels 410, and an opposite side facing the package cover 308. In this case, the patterned side forms a cavity facing the device having a base surface 409 and opposing sidewalls 411 projecting downwardly from the base surface 409. When sidewall 411 is attached to an underlying device 304, for example by direct bonding sidewall 413 to device backside 320, it forms the sides of coolant channel 410, base surface 309 forms the top surface of coolant channel 410, and device backside 320 forms the bottom surface of coolant channel 410. In this case, coolant circulates through coolant channel 410 via openings 406A at opposite ends of cooling assembly 403.

[0036] As shown, each opening 406A defines a gap between the cooling assembly 403 and the underlying device cover 320. The gap is formed at the edge of the cold plate 406, which either has no sidewalls (as shown) or has sidewalls that extend at least partially toward, but are not bonded to, the backside of the device 304. The openings 406A are in fluid communication with the inlet / outlet openings 312 of the package cover 308 through openings 422A formed in the encapsulant layer 422. As shown, the length of the cold plate 406 in the X direction is less than the length of the device 304, and the openings 422A through the encapsulant layer 422 extend from the package cover 308 to an edge portion of the backside of the underlying device. In other embodiments, the sidewalls 411 may have substantially the same length as the device 304, as shown in phantom, and the base surface 409 may have a length that is less than the length of the device 304. In either embodiment, device backside 320 is in direct thermal contact with the coolant circulating through coolant channels 410 and entering and exiting coolant channels 410 on either side of opening 406A. As envisioned, cooling layer 403 and encapsulant layer 422 shown in Figures 4A and 4B can be used with any of the device packages described herein.

[0037] 5 is a schematic cross-sectional side view of an example multi-component device package 501 having a cold plate 506 directly bonded to the backside surface of two or more devices. As shown, the device package 501 includes a package substrate 502, e.g., an interposer that facilitates communication between the devices 304 and a device stack 504, an integrated cooling assembly 503, a package cover 308, and an adhesive layer 522. The integrated cooling assembly 503 may include multiple devices 304 (one shown), singulated and / or arranged in a vertical device stack 504 (one shown), and a cold plate 506 attached to each of the devices 304 and device stack 504, e.g., by direct bonding methods described herein. In some embodiments, the devices 304 may comprise processors, and the device stack 504 may comprise multiple memory devices. In this case, device 304 and device stack 504 are provided in a side-by-side arrangement on package substrate 302 and are in electrical communication with each other via conductive elements formed in, on, or through package substrate 502. In this case, cold plate 506 is sized to provide an attachable bonding surface for both device 304 and device stack 504, but may otherwise be the same or substantially the same as other cold plates described herein. For example, in this case, cold plate 506 has a patterned side with a base surface 509 and sidewalls 511 extending downwardly from base surface 509 to form a cavity. The cavity may be closed as shown, for example, surrounded by sidewalls 511, or may be open at either end, as shown in FIGS. 4A and 4B . The base surface 509 may define the uppermost surface of the coolant channel 510 , and the sidewalls 511 may define the perimeter or lateral boundaries of the coolant channel 510 .In this case, the device 304 and the device stack 504 define respective portions of the bottom of the coolant channel 510, and a second underfill layer 521 or other molding material provided in the gap region between the device 304 and the device stack 504 provides the intervening bottom portion of the coolant channel provided between the device 304 and the device stack 504.

[0038] An encapsulant layer 522 disposed between the cold plate 506 and the package cover 308 attaches the cold plate 506 to the package cover 308 and forms a coolant-impermeable barrier therebetween. Coolant circulates to the device package 501 through the inlet / outlet openings 312 in the package cover 308 and flows through the coolant channels 510 via openings 506A in the cooling assembly 503 and corresponding openings 522A formed through the encapsulant layer 522. In this case, the encapsulant layer 522 may be formed of, for example, the polymer or epoxy molding compounds described above, or a compliant adhesive layer, such as a TIM layer.

[0039] 6 is a schematic cross-sectional side view of an exemplary multi-component device package according to one embodiment of the present disclosure. In this case, device package 601 includes package substrate 502, integrated cooling assembly 303, one or more second devices (shown in this case as device stack 604), and package cover 608. Device package 601 further includes an encapsulant layer 622 disposed between integrated cooling assembly 303 and the portion of package cover 608 disposed thereover. encapsulant layer 522 forms a coolant-impermeable barrier between cold plate 306 and package cover 308. In this case, device stack 604 is disposed on package substrate 502 in a side-by-side arrangement with device 304. Heat generated by device 304 is dissipated into coolant circulating through coolant channels 310. In this case, the coolant circulates through the inlet / outlet opening 312 provided in the package cover 608, an opening 622A provided through the sealing material layer 622 that is aligned with and in fluid communication with the inlet / outlet opening 312, and an opening 306A in the cold plate 306 that is in fluid communication with the opening 622A.

[0040] The package cover 608 may be formed of a thermally conductive material, and the package cover functions as a thermal spreader. Advantageously, the cold plate 306 blocks the thermal path between the device 304 and the device stack 604, preventing heat from being transferred between the device 304 and the device stack 604. Thus, heat generated by the device stack 604 is dissipated to a coolant via the package cover 608, which is thermally coupled to the device stack 604 through the use of the TIM layer 616. Thus, the device package 601 may be advantageously used to facilitate low latency while eliminating undesirable heat transfer between closely spaced devices on the interposer, such as high-power devices or memory stacks. In some embodiments, the device package 601 further includes a heat sink 608A disposed on a portion of the package cover 601 above the device stack 604. The heat sink 608A may be thermally coupled to the package cover 608 through the use of a TIM layer (not shown) or by direct bonding using methods described herein.

[0041] 7 is a schematic cross-sectional side view of a 3DIC device package 701 according to one embodiment of the present disclosure. The device package 701 includes, as its main components, an integrated cooling assembly 703 disposed on and electrically connected to a package substrate 302, a package cover 708 disposed over the integrated cooling assembly 703, and an encapsulant layer 722 disposed between the cooling assembly 703 and the cover 708. In this case, the integrated cooling assembly 703 includes a 3DIC device 704, which includes a first device 704A, one or more second devices 704B (one shown), and one or more cold plates 706 (two shown). In this case, the first device 704A is disposed facing the package substrate 302, i.e., active side down, and the second device 704B is disposed on and bonded to a portion of the back side of the first device 704. The package substrate 302 and the second device 704B and / or the first device 704A and the second device 704B may be interconnected using a plurality of through-substrate vias (TSVs 718) disposed through the first device 704A and hybrid bonds formed between the active side of the second device 704B and the backside of the first device 704A. In some embodiments, one or more second devices 704B have a device stack, such as device stack 604, directly bonded to and interconnected with the first device 704A using direct hybrid bonds.

[0042] In this case, a first device 704A is cooled using one or more cold plates 706 that are disposed on and bonded to a backside of the first device 704A in a juxtaposed arrangement with a second device 704B. Each of the one or more cold plates 706 is attached to a package cover 708 using an encapsulant layer 722 that forms a coolant-impermeable barrier between the cold plate 706 and the package cover 708.

[0043] In this case, each cold plate 706 has a base surface 709 and sidewalls 711 extending downwardly from the base surface 709, which are attached to the first device 704A, for example, using a direct bonding method, to form coolant channels 710 between the cold plate 706 and the underlying portion of the first device 704A. Heat generated by each portion of the first device 704A is dissipated from the device package 701 via coolant flowing through the coolant channels 710. In this case, the coolant is routed to each of the coolant channels 710 through a flow path that includes the inlet / outlet openings 312 in the package cover 708, the openings 722A in the encapsulant layer 722, and the openings 706A in the cold plate 706.

[0044] In this case, the second device 704B is thermally coupled to the package cover 708 through the use of the TIM layer 716, and the encapsulant layer 722 and the package cover 708 are each made of a thermally conductive material. Thus, heat generated by the second device 704B is transferred to the coolant in the coolant channels 710 via a heat transfer path that includes the TIM layer 716, the package cover 708, the encapsulant layer 722, and the cold plate 706. In some embodiments, the heat from the second device 704B is dissipated using a heat sink, such as the heat sink 608A described above, attached to the portion of the package cover 708 that covers the second device 704B.

[0045] For each of the above-described embodiments, the encapsulant layer and the openings therethrough facilitate delivery of coolant to the integrated device assembly without direct attachment of coolant lines to the integrated device assembly. Attachment of the coolant lines to the package cover reduces manufacturing complexity and cost because the package cover is typically formed of a less brittle material than the material used to form the cold plate and is thus less susceptible to breakage.

[0046] FIG. 8 is a schematic cross-sectional side view of a device package 801 according to one embodiment of the present disclosure. In this case, device package 801 includes a package substrate 302, a cooling assembly 303 disposed on package substrate 302, and a material layer 822 disposed over and at least partially encapsulating cooling assembly 303. Material layer 822 forms a coolant-impermeable seal with cooling assembly 303 and may be comprised of a polymer or epoxy made resin or molding compound. Coolant is delivered to cooling assembly 303 and circulated therethrough via openings 822A disposed through material layer 822. In this case, material layer 822 includes one or more features 814, such as threads or protrusions, extending upward to surround each of openings 822A, which allow for connection of cooling lines 108 (shown in phantom) directly to material layer 822. In some embodiments, the device package 801 further includes a package cover (not shown), and the coolant lines are coupled to the material layer 822 through openings in the package cover.

[0047] Figure 9 illustrates a method 900 that can be used to manufacture the device packages described herein. Figure 10 illustrates device package 301 at different stages of manufacture to explain aspects of method 900. As envisioned, method 900 can be used to manufacture any of the device packages described herein. To reduce clutter, any of the features of device package 301 shown in Figure 10 have been labeled with the reference numerals that appear in Figure 3.

[0048] At block 902, the method 900 includes aligning a first substrate 1004 with a second substrate 1006, the first substrate 1004 having a plurality of dies, e.g., devices 304, to be singulated, and the second substrate 1006 having a plurality of cold plates 306 to be singulated. As shown, the first substrate 1004 has a plurality of devices 304 arranged in a rectangular array and spaced apart from one another by a plurality of scribe lines 1008 extending in the X and Y directions to form a grid pattern.

[0049] The first substrate 1004 may comprise a bulk material and multiple material layers disposed on the bulk material. The bulk material may include any semiconductor material suitable for fabricating semiconductor devices, such as silicon, silicon germanium, germanium, III-V semiconductor materials, II-VI semiconductor materials, or combinations thereof. For example, in some embodiments, the first substrate 1004 may comprise a monocrystalline wafer, such as a silicon wafer, multiple device components formed in or on the silicon wafer, and multiple interconnect layers formed on the multiple device components. In other embodiments, the substrate may include a reconstituted substrate, such as a substrate formed from multiple singulated devices embedded in a support material.

[0050] The bulk material of the first substrate 1004 may be thinned after the devices 304 are formed using one or more backgrinding, etching, and polishing operations to remove material from the backside. The first substrate 1004 may be thinned using a combination of polishing and etching processes to reduce the thickness (as viewed in the Z direction) to about 450 nm or less, e.g., about 301 nm or less, or about 150 nm or less. After thinning, the backside may be polished to a desired smoothness using a chemical mechanical polishing (CMP) process, and a dielectric layer may be deposited thereon. In some embodiments, the dielectric layer may be polished to a desired smoothness to prepare the substrate 1004 for a bonding process. In some embodiments, the method 900 includes forming a plurality of metal features in the dielectric layer in preparation for a hybrid bonding process, for example, by using a damascene process.

[0051] In some embodiments, the active side is temporarily bonded to a carrier substrate (not shown) before or after the thinning process. In use, the carrier substrate provides support for the thinning operation and / or the thinned material to facilitate substrate handling during one or more of the following manufacturing operations described herein. In some embodiments, the second substrate 1006 is formed of multiple substrates (not shown), each of which is comprised of a single bulk material patterned to form multiple base plates that, when bonded together, form the multiple cold plates 306. Each of the multiple substrates may be of substantially the same size and shape as the first substrate 1004 in a top-down view (viewed in the Z direction), such that the interface surfaces are substantially coextensive with one another. In some embodiments, each of the substrates has a thickness (viewed in the Z direction) of about 0.5 mm to about 10 mm, about 1 mm to about 8 mm, about 1 mm to 6 mm, for example, about 0.5 mm or more, for example, about 1 mm or more, about 2 mm or more, about 10 mm or less, for example, about 8 mm or less, or about 6 mm or less.

[0052] In some embodiments, the second substrate 1006 is formed of a bulk material having substantially the same CTE as the bulk material of the first substrate 1004, where CTE is the fractional change in length of the material per degree change in temperature measured over a desired temperature range. In some embodiments, the CTEs of the first and second substrates are matched such that the CTE of the second substrate 1006 is within about ±20% or less of the CTE of the first substrate 1004, e.g., within ±15% or less, within ±10% or less, or within about ±5% or less. In some embodiments, the CTEs are matched throughout a temperature range of about −60° C. to about 200° C., or about 60° C. to about 175° C. In one exemplary embodiment, the materials whose CTEs are matched each comprise silicon. For example, the bulk material of the first substrate 1004 may include monocrystalline silicon, and the bulk material of the second substrate 1006 may include monocrystalline silicon or may include polycrystalline silicon. In some embodiments, the method 900 includes forming a dielectric layer and optionally a plurality of metal features on a bottom surface of the second substrate 1006. In some embodiments, the method includes patterning the second substrate 1006, for example, by using lithography and etching processes, to form the surfaces, sidewalls, and protruding features of each of the cold plates described herein.

[0053] At block 904, the method 900 includes direct bonding a plurality of cold plates 306 formed in the second substrate 1006 to a plurality of devices 304 in the first substrate 1004. As described above, the bonding surfaces may each comprise a dielectric layer, and direct bonding the first substrate 1004 and the second substrate 1006 includes forming a dielectric bond between the first dielectric layer 334A and the second dielectric layer 334B. Optionally, the first substrate 1004 and the second substrate 1006 may be direct bonded using a hybrid of dielectric and metallic bonds formed between metallic features.

[0054] Generally, direct bonding surfaces (surfaces of dielectric layers) involves pre-treating, aligning, and contacting the surfaces. Pre-treating the surfaces may include smoothing each surface to a wear surface roughness, e.g., 0.1-3.0 nm RMS, activating the surfaces to weaken or open chemical bonds in the dielectric, and terminating the surfaces with desired chemical species. Smoothing the surfaces may include polishing the substrates 1004, 1006 using a CMP process. Activating the surfaces and terminating them with desired chemical species may include exposing the surfaces to radical species formed in a plasma.

[0055] In some embodiments, a nitrogen-containing gas, such as N, is used to form the plasma, and the terminating species include nitrogen and hydrogen. In some embodiments, a wet cleaning process may be used to activate the surfaces, for example, by exposing the surfaces to an aqueous ammonia solution. In some embodiments, a dielectric bond may be formed using a dielectric layer deposited on only one of the substrates 1202, 1204, but not both. In such embodiments, a direct dielectric bond may be formed by contacting a deposited dielectric layer of one substrate with a bulk material surface, such as a bulk semiconductor or polysilicon material surface, of the other substrate. In such embodiments, the bulk material surface may have a thin layer of native oxide or may be cleaned to be substantially free of native oxide prior to contact.

[0056] Forming a direct dielectric bond between the substrates at block 904 involves directly contacting the pre-treated and aligned surfaces with each other at temperatures below 150°C, e.g., below 100°C, e.g., below 30°C, or at about room temperature, e.g., 20°C to 30°C. Without being bound by theory, it is believed that the hydrogen-terminated species diffuse from the bonding surface as an interface, and chemical bonds are formed between the remaining nitrogen species during the direct bonding process. In some embodiments, the direct bond is strengthened using an annealing process in which the substrates are heated to and maintained at a temperature of about 30°C or more and about 450°C or less, e.g., about 50°C or more and about 250°C or less, or about 150°C, for a duration of about 5 minutes or more, e.g., about 15 minutes. Typically, the bond will strengthen over time without the application of heat. Thus, in some embodiments, the method does not include heating the substrates.

[0057] In embodiments in which the substrates are bonded using a hybrid dielectric-metal bond, the method may further include planarizing or recessing the metal features below the field plane before contacting and bonding to the dielectric layer. After forming the dielectric bond, the substrates 1004, 1006 may be heated to a temperature of 150°C or greater and maintained at this elevated temperature for a duration of about 1 hour or greater, e.g., 8-24 hours, thereby forming a direct metallurgical bond between the metal features. Suitable direct dielectric-hybrid bonding technologies that can be used to practice aspects of the methods described herein include ZiBond® and DBI®, each of which is commercially available from Adeia Holding Corp., San Jose, California, USA.

[0058] At block 906, the method 900 includes singulating the plurality of integrated cooling assemblies 303 from the bonded substrate. Singulation after bonding imposes distinct structural properties on the integrated cooling assemblies 303 because the bonding surface of each cold plate 306 has the same perimeter as the backside of the device 304 bonded thereto. Thus, the sidewalls of the cold plate 306 are typically flush with the edges of the device 304 along their common perimeter. In some embodiments, the cold plates 306 are singulated from the second substrate 1006 using a process that cuts or separates the second substrate 1006 in a vertical plane, i.e., parallel to the Z-direction. In such embodiments, the sides of the cold plate 306 are substantially perpendicular to the backside of the device, i.e., the horizontal (X-Y) plane of the mounting interface between the device 304 and the cold plate 306. In some embodiments, a saw or laser dicing process is used to singulate the cold plate 306 .

[0059] At block 908, the method 900 includes coupling the integrated cooling assembly to the package substrate 302 and sealing the package cover 308 to the integrated cooling assembly 303 through the use of a molding compound that, upon curing, forms an encapsulant layer 322. In some embodiments, the method 900 further includes forming an opening 322A in the encapsulant layer 322.

[0060] The above-described method advantageously provides an embedded cold plate that eliminates and / or substantially reduces the thermal resistance path typically associated with cooling systems mounted externally to the device package. The cold plate may be attached to the semiconductor device using direct dielectric or direct hybrid dielectric-metal bonding methods. Such bonding methods may enable a relatively low thermal budget while substantially increasing bond strength compared to conventional silicon-to-silicon bonding methods, such as thermocompression bonding.

[0061] The cold plate and semiconductor device may be made of CTE-matched materials, thereby eliminating the need for an intervening TIM layer. In some embodiments, the integrated cooling assembly and package cover may be formed of CTE-mismatched materials and attached to one another using a flexible material to form an encapsulant layer or by the use of a decoupling adhesive layer between the encapsulant layer and one of the cold plate or package cover. The flexible material can accommodate differences in linear expansion between the package cover and the cold plate during repeated thermal cycling, thereby extending the useful life of the device package.

[0062] The above-described embodiments are for illustrative purposes only and are not intended to limit the present invention. As will be appreciated by those skilled in the art, individual aspects of the cooling assemblies, device packages, and methods described herein may be omitted, modified, combined, and / or rearranged without departing from the scope of the present disclosure. Only the following claims define the scope of protection of the present disclosure.

Claims

1. 1. A device package comprising: a package substrate; a package cover disposed on the package substrate, the package cover having an inlet opening and an outlet opening therethrough; an integrated cooling assembly disposed between the package substrate and the package cover, the integrated cooling assembly including a semiconductor device and a cold plate attached to the semiconductor device; a material layer disposed between the package cover and the cold plate; the cold plate having a patterned first side and an opposite second side; the patterned first side has a base surface and a sidewall extending downwardly from the base surface; the base surface is spaced apart from the semiconductor device, thereby together forming a coolant channel between the base surface and the semiconductor device; The coolant channel is in fluid communication with the inlet opening and the outlet opening via a plurality of openings each extending through a corresponding portion of the material layer.

2. The device package of claim 1 , wherein the cold plate is attached to the semiconductor device by a direct dielectric bond.

3. The device package of claim 1 , wherein the cold plate is attached to the semiconductor device by a direct hybrid bond.

4. The device package of claim 1 further comprising a fluid coolant contained within the coolant channels.

5. 2. The device package of claim 1, wherein the openings in the integrated cooling assembly have multiple portions of a fluid path further including the inlet opening and the outlet opening, the openings extending through the material layer and the coolant channel.

6. 6. The device package of claim 5, wherein the opening in the integrated cooling assembly extends between the first side and the second side of the cold plate.

7. 6. The device package of claim 5, wherein the opening in the integrated cooling assembly comprises a gap between the first side of the cold plate and the semiconductor device.

8. The device package of claim 5 , wherein the first side of the cold plate has a plurality of protruding features extending downward from the base surface to interrupt at least some portions of a fluid flow path through the coolant channels.

9. The device package of claim 8 , wherein the protruding feature is directly bonded to the semiconductor device.

10. 8. The device package of claim 7, wherein the gaps are located at opposite ends of the base surface.

11. The device package of claim 1 , wherein the package cover has one or more coolant line attachment features.

12. The device package of claim 1 , further comprising an underfill layer at least partially encapsulating the integrated cooling assembly in areas located outside the coolant channels.

13. 2. The device package of claim 1, wherein the layer of material forms an impermeable barrier between the package cover and the cold plate.

14. The device package of claim 1 , wherein the cold plate and the side of the semiconductor device are substantially flush with each other.

15. the semiconductor device is a first semiconductor device, and the integrated cooling assembly further includes a plurality of second semiconductor devices vertically arranged in a device stack; The device package of any one of claims 1 to 13, wherein the device stack is attached to the first side of the cold plate in a side-by-side arrangement with the first semiconductor device.

16. The device package of claim 15 , wherein the cold plate is attached to the second semiconductor device by a direct dielectric bond.

17. The device package of claim 15 , wherein the cold plate is attached to the second semiconductor device by a direct hybrid bond.

18. The semiconductor device is a first semiconductor device, and the device package comprises: a device stack electrically connected to the package substrate in a side-by-side arrangement with the integrated cooling assembly; The device package of any one of claims 1 to 13, further comprising a first TIM layer disposed between the device stack and the package cover.

19. The device package of claim 18 , wherein the package cover is made of a thermally conductive material that forms a portion of a heat transfer path between the device stack and the coolant channel.

20. 20. The device package of claim 18, further comprising a heat sink thermally coupled to an outer surface of the package cover, the package cover being made of a thermally conductive material that forms a portion of a heat transfer path between the device stack and the heat sink.

21. the semiconductor device includes a first device and a second device directly bonded to the first device; the integrated cooling assembly includes one or more cold plates attached to the first device; A device package as described in any one of claims 1 to 13, wherein each of the one or more cold plates is sealed to the package cover by an adhesive layer to define the periphery of the coolant channel respectively provided between the cold plate and the package cover.

22. 22. The device package of claim 21, wherein the second device is thermally coupled to the package cover by a TIM layer disposed between the second device and the package cover.

23. 22. A method for manufacturing the device package of claim 21, comprising: Direct bonding a first substrate having a semiconductor device to a second substrate having a cold plate; singulating an integrated cooling assembly from the bonded first and second substrates, the assembly including the semiconductor device and the cold plate, the cold plate having a first side directly bonded to the semiconductor device and a second side opposite the first side, one or more surfaces of the first side spaced apart from the semiconductor device to form a coolant channel between the first surface and the semiconductor device; sealing a package cover to the second side by using a layer of material disposed between the package cover and the second side; forming openings in the layer of material before or after attaching the package cover to the second side to fluidly couple the inlet opening and the outlet opening to the coolant channel.

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