Embedded Liquid Cooling

Abstract

The device package may include a package substrate, a package cover disposed on the package substrate, and an integrated cooling assembly disposed between the package substrate and the package cover. Generally, an inlet opening and an outlet opening are provided through the package cover. The integrated cooling assembly includes a semiconductor device and a cold plate attached to the semiconductor device. The device package may include a material layer disposed between the package cover and the cold plate. The cold plate may have a patterned first side and an opposite second side. The patterned first side has a base surface and sidewalls extending downwardly from the base surface, the base surface being spaced apart from the semiconductor device, thereby forming a coolant channel. In this case, the coolant channel is in fluid communication with the inlet opening and the outlet opening through a plurality of openings provided through portions of the material layer.

Description

[Technical Field]

[0001] FIELD OF THE DISCLOSURE The present disclosure relates to novel packaging techniques for microelectronic devices, and more particularly to embedded cooling systems for device packaging and methods of fabricating the same.

[0002] [Citation of Related Applications] This application claims priority to U.S. Provisional Patent Application No. 63 / 478,148, filed December 31, 2022, which is incorporated by reference in its entirety. [Background technology]

[0003] Energy consumption poses a very serious challenge for the future of large-scale computing, as global computing energy needs are growing at a rate considered unsustainable by most. Some models predict that the information, communications, and technology (ICT) ecosystem could exceed 20% of global electricity use by 2030, with direct electricity consumption by large computing centers accounting for more than one-third of that energy use. Cooling costs account for a significant portion of a computing center's energy needs, as even small increases in operating temperature can adversely affect the performance of microprocessors, memory devices, and other electronic components.

[0004] Heat dissipation in high-power-density chips is also a significant challenge due to increased power density and correspondingly increased heat flux, which contributes to high chip temperatures, resulting from improved chip performance, for example, through increased gate density and the use of multicore microprocessors. These high temperatures are undesirable because they reduce the chip's operational performance, efficiency, and reliability. Cooling systems used to maintain a chip at a desired operating temperature typically remove heat using one or more heat-dissipating devices, such as thermal spreaders, heat pipes, cold pipes, or heat sinks, which are thermally coupled to the chip using compliant, thermally conductive materials, such as thermal pastes, thermal adhesives, or thermal gap fillers. Thermal interface materials (TIMs) maintain thermal contact between the chip and the heat-dissipating device surfaces to facilitate heat transfer between them. Unfortunately, the thermal resistance of the thermal interface material, combined with the thermal resistance at the interface region, can impede heat transfer from the chip to the heat-dissipating device, undesirably reducing the cooling efficiency of the cooling system. Summary of the Invention [Problem to be solved by the invention]

[0005] Therefore, there is a need in the art for improved energy efficient cooling systems and methods of manufacturing same. [Means for solving the problem]

[0006] Embodiments herein provide an integrated device cooling assembly embedded within a novel device package that advantageously shortens the thermal resistance path between the device and the heat sink, as well as reduces thermal communication between devices within the same package.

[0007] In one embodiment, the integrated cooling assembly includes a semiconductor device and a cold plate bonded to the semiconductor device. The cold plate has a patterned first side, the patterned first side having a base surface, a sidewall, and a plurality of support features. The base surface is spaced from the semiconductor device to together form a coolant channel between the base surface and the semiconductor device. The sidewalls slope away from the base surface at an angle greater than 90° and are bonded to the semiconductor device to define a perimeter of the coolant channel. The plurality of support features are bonded to the semiconductor device inwardly of the perimeter, each of the plurality of support features being wider at the base surface than at a bonding interface with the semiconductor device.

[0008] These and other objects and advantages of the present disclosure will become apparent from a consideration of the following detailed description taken in conjunction with the accompanying drawings. [Brief explanation of the drawings]

[0009] [Figure 1A] FIG. 1 is a schematic plan view of an example of a system panel according to embodiments of the present disclosure. [Figure 1B] 1 is a schematic partial cross-sectional side view of a device package mounted on a PCB according to embodiments of the present disclosure. [Figure 2A] FIG. 1C is a schematic exploded isometric view of the device package of FIG. 1B. [Figure 2B] FIG. 1C is a schematic cross-sectional view of the device package of FIG. 1B. [Figure 3A] 10A-10C illustrate methods that can be used to manufacture the integrated cooling assemblies described herein. [Figure 3B] 3B-3D show an integrated cooling assembly at different stages of manufacture to illustrate aspects of the method of FIG. 3A. [Figure 3C] 3B-3D show an integrated cooling assembly at different stages of manufacture to illustrate aspects of the method of FIG. 3A. [Figure 3D]3B-3D show an integrated cooling assembly at different stages of manufacture to illustrate aspects of the method of FIG. 3A. [Figure 4] 1 is a schematic cross-sectional view of a device package according to an embodiment of the present disclosure. [Figure 5] FIG. 2 is a schematic cross-sectional view of a device package according to another embodiment of the present disclosure. [Figure 6] FIG. 2 is a schematic cross-sectional view of a device package according to another embodiment of the present disclosure. [Figure 7] FIG. 2 is a schematic cross-sectional view of a device package according to another embodiment of the present disclosure. [Figure 8] FIG. 2 is a schematic cross-sectional view of a device package according to another embodiment of the present disclosure. DETAILED DESCRIPTION OF THE INVENTION

[0010] While the figures herein depict various embodiments of the present invention, these are by way of example only, and it will be recognized that additional or alternative structures, assemblies, systems, and methods may be implemented within the principles illustrated by this disclosure.

[0011] Embodiments herein provide an integrated cooling assembly embedded within a device package that provides direct heat transfer between a semiconductor device and a flowing fluid coolant.

[0012] As used herein, the term "substrate" means and includes any workpiece, wafer, or article that provides a base material or support surface upon which components, elements, devices, assemblies, modules, systems, or features of the heat-generating devices, packaging components, and cooling assemblies described herein can be mounted or configured. The term substrate further includes a "semiconductor substrate" that provides a support material upon which or on which elements of a semiconductor device can be fabricated or attached and any material layers, features, and / or electronic devices formed thereon, in, or through.

[0013] As described below, semiconductor substrates herein generally have a "device side," e.g., a side (surface) carrying semiconductor device elements such as transistors, resistors, and capacitors, and a "back side" (surface) opposite the device side. The term "active side" should be understood to include the device side surface of a substrate, and may also include the device side surface of a semiconductor device and / or the surface of any material layers, device elements, or features formed thereon or extending outward therefrom, and / or any openings formed therein. Thus, it should be understood that the material forming the active side can vary depending on the device fabrication and assembly stage. Similarly, the term "non-active side" (opposite the active side) includes the non-active side of a substrate at any device fabrication stage, including the surface of any material layers, device elements, or features formed thereon or extending outward therefrom, and / or any openings formed therein. Thus, the terms "active side" and "non-active side" may include the respective surfaces of a semiconductor substrate at the start of device fabrication and any surfaces formed during material removal, e.g., after a substrate thinning operation. Depending on the device fabrication or assembly stage, the terms "active side" and "non-active side" may also be used to refer to surfaces of material layers or features formed on, in, or through a semiconductor substrate, whether or not the material layers or features are ultimately present in the fabricated or assembled device.

[0014] Spatial terms are used herein to describe relationships between various elements, such as substrates, heat-generating devices, cooling assembly components, device package components, and other features described below. Unless otherwise specified, terms such as "above," "over," "upper," "outward," "on," "below," "under," "beneath," and "belowside" are generally defined with respect to the X, Y, and Z directions depicted in the drawings. Thus, it should be understood that spatial terms used herein encompass different orientations of the substrate and are not limited by the direction of gravity, unless otherwise specified. Unless otherwise specified, terms describing relationships between elements, such as "on," "embedded in," "coupled to," "connected by," "mounted to," and "bonded to," alone or in combination with spatial terms, include both relationships with intervening elements and direct relationships without intervening elements.

[0015] Unless otherwise specified, the term "cold plate" generally refers to a base plate or a stack of base plates directly bonded to one another, which may be bonded to a semiconductor device. The cold plate may have material layers and / or metallic features formed within or on the surface of the base plate or stack of base plates that facilitate direct dielectric or hybrid bonding with the semiconductor device. The term "integrated cooling assembly" generally refers to a cold plate attached to a semiconductor device, the assembly being attached to form a single piece, for example, by using a direct bonding method described below. The direct bonding method can transfer heat from the semiconductor device from the cold plate to a fluid flowing thereover without the use of a thermal interface material. Unless otherwise specified, the device packages and cold plates described herein can be used with any desired fluid coolant, for example, liquid, gas, and / or vapor phase coolants. Thus, these terms should not be construed as limiting the coolant to any one fluid phase.

[0016] 1 is a schematic plan view of an example system panel 100 according to embodiments of the present disclosure. As its main components, the system panel 100 includes a printed circuit board, here a PCB 102, a plurality of device packages 201 mounted on the PCB 102, and a plurality of coolant lines 108 fluidly coupling each of the device packages 201 to a coolant source 110. It is contemplated that the coolant may be delivered to each of the device packages 201 in any desired fluid phase, such as a liquid, vapor, gas, or a combination thereof, and may exit the device packages 201 in the same phase or different phases. In some embodiments, the coolant may be delivered to and returned from the device packages 201 as a liquid, and the coolant source 110 may include a heat exchanger or chiller to maintain the coolant at a desired temperature. In other embodiments, the coolant may be delivered to the device packages 201 as a liquid, evaporate to a gas within the device packages, and return to the coolant source 110 as a vapor. In these embodiments, the device package 201 may be fluidly coupled in parallel to the coolant source 110, which may have or further include a compressor (not shown) to condense the received vapor into liquid form.

[0017] 1B is a schematic, partial cross-sectional side view of a portion of the system panel 100 of FIG. 1A. As shown, each device package 201 is mounted within a socket 114 of a PCB 102 and coupled to the socket using a plurality of pins 202 or other suitable coupling method, such as solder bumps (not shown). The device package 201 may be seated within the socket 114 and secured to the PCB 102 using a mounting frame 106 and a plurality of fasteners 112, such as compression springs, configured to together exert a relatively uniform downward force on the upwardly facing edge of the device package 201. The uniform downward force ensures proper pin contact between the device package 201 and the socket 114.

[0018] FIG. 2A is a schematic exploded isometric view of an exemplary device package 201 according to embodiments of the present disclosure. FIG. 2B is a schematic cross-sectional view of the device package 201 taken along line A-A′ in FIG. 2A . As its main components, the device package 201 includes a package substrate 202, an integrated cooling assembly 203 disposed on the package substrate 202, and a package cover 208 disposed on a peripheral portion of the package substrate 202. The package cover 208 extends over the integrated cooling assembly such that the integrated cooling assembly 203 is disposed between the package substrate 202 and the package cover 208. As shown, the device package 201 further includes an encapsulant layer 222 that forms a coolant-impermeable barrier for the package cover against the integrated cooling assembly. Coolant is delivered to the integrated cooling assembly 203 through inlet / outlet openings 212 in the package cover 208 and corresponding openings 222A formed through the encapsulant layer 222. In some embodiments, the device package 201 may further include a support member 207 attached to the integrated cooling assembly 203 .

[0019] Generally, the package substrate 202 comprises a rigid material, such as an epoxy or resin-based laminate, that supports the integrated cooling assembly 203 and the package cover 208. The package substrate 202 may have conductive features disposed in or on the rigid material that electrically couple the integrated cooling assembly 203 to a system panel, such as the PCB 102.

[0020] The integrated cooling assembly 203 may typically include a semiconductor device, in this case, device 204, and a cold plate 206 bonded to device 204. In this case, device 204 includes an active side 218 on or within which device components, such as transistors, resistors, and capacitors, are formed, and device 204 includes a non-active backside opposite active side 218, in this case, device backside 220. As shown, active side 218 is positioned adjacent to and facing package substrate 202. Active side 218 may be electrically coupled to package substrate 202 using conductive bumps 219, which are encapsulated by a first underfill layer 221 disposed between device 204 and package substrate 202. First underfill layer 221 may be comprised of a cured polymer resin or epoxy that provides mechanical support for conductive bumps 219 and prevents thermal fatigue.

[0021] The cold plate 206 generally has a patterned side facing the device 204 and an opposite side facing the package cover 208. The patterned side forms a cavity facing the device, having a base surface 209 and a sidewall 211 surrounding and projecting downwardly from the base surface 209, and a plurality of support features 224 disposed inwardly of the sidewall 211. When attached to the underlying device 204, the sidewall 211 forms the perimeter of the coolant channels 210, the base surface 209 forms the uppermost surface of the coolant channels 210, and the device backside 220 forms the bottom of the coolant channels 210. The device backside 220 is thus in direct thermal contact with the coolant flowing therethrough. The support features 224 generally extend from the base surface 209 to a bonding interface with the device backside 220. The support features 224 provide structural support to the integrated cooling assembly 303 and disrupt the laminar fluid flow at the interface between the coolant and the device backside 220, thereby increasing heat transfer therebetween.

[0022] In this case, coolant circulates through coolant channels 210 via openings provided through cold plate 206, in this case shown as opening 206A provided between downwardly facing base surface 209 and the opposite upwardly facing surface. Opening 206A is in fluid communication with inlet / outlet openings 212 in package cover 208 through opening 222A formed in an encapsulant layer 222 provided between the openings and package cover 208.

[0023] As described in the methods below, the cold plate 206 may be patterned using an anisotropic etching process, which causes the sidewalls and surfaces of the protruding features 224 to be sloped, i.e., to form an angle of less than 90° with the bonding surface of the device 204. The anisotropic etching process causes the protruding features 224 to take on a trapezoidal cross-section, with each of the protruding features 224 being wider at the base surface 209 than at its interface with the device 204. Similarly, the sidewalls slope away from the base surface 209, and the sidewalls are wider at their base than at the interface with the device 204.

[0024] The angled surfaces desirably increase the stability of the sidewalls 211 and protruding features 224 during manufacturing of the integrated cooling assembly 203. The increased stability allows the field surfaces of the sidewalls 211 to be narrower and the coolant channels to be deeper compared to cold plates with orthogonal surfaces, because narrow features at the base can undesirably buckle and break if their aspect ratio (height to width) increases.

[0025] In this case, the cold plate 206 is attached to the device backside 220 without an intervening adhesive material; for example, the cold plate 206 may be directly bonded to the device backside 220, such that the cold plate 206 and the device backside 220 are in direct thermal contact. The package cover 208 generally has one or more vertical or sloped sidewall portions 208A and a lateral portion 208B spanning and connected to the sidewall portions 208A. The sidewall portion 208A extends upward from the periphery of the package substrate 202 to enclose the device 204 and the cold plate 206 disposed thereon. The lateral portion 208B is attached to the cold plate 206 and is typically spaced from the cold plate 206 by a gap corresponding to the thickness of the encapsulant layer 222. Coolant is circulated in coolant channels 210 through inlet / outlet openings 212 formed through lateral portion 208B. For each of the embodiments described herein, cooling lines 108 may be attached to device package 201 by using connector features formed in package cover 208, such as threads formed in the sidewalls of inlet / outlet openings 212 and / or protruding features 214 surrounding openings 212 and extending upward from the surface of lateral portion 208B.

[0026] Typically, the package cover 208 is formed of a semi-rigid or rigid material such that at least a portion of the downward force exerted by the mounting frame 106 (FIG. 2) on the package cover 208 is transferred to the support surface of the package substrate 202, but not to the cold plate 206 and underlying device 204. In some embodiments, the package cover 208 is made of a thermally conductive metal, such as aluminum or copper. In some embodiments, the package cover 208 functions as a heat spreader to redistribute heat from one or more electronic components within a multi-component device package, for example, as described below.

[0027] The encapsulant layer 222 is disposed between the integrated cooling assembly 203 and the package cover 208 and forms an impermeable barrier that prevents coolant from reaching and damaging the active side 218 of the device 204. In some embodiments, the encapsulant layer 222 is comprised of a polymer or epoxy material that extends upward from the package substrate 202 to encapsulate and / or surround at least a portion of the device 204. In other embodiments, the encapsulant layer 222 may be disposed between only the upwardly facing surface of the cold plate 206 and the portion of the package cover 208 that covers it. In some embodiments, the encapsulant layer is formed from a molding compound, such as a thermosetting resin, that, when polymerized, forms an airtight seal between the package cover 208 and the cold plate 206. In this case, the coolant is delivered to the cold plate 206 through openings 222A disposed through the encapsulant layer 222. As shown, opening 222A is aligned with and in fluid communication with the overlying inlet / outlet opening 212 in package cover 208 and the underlying inlet / outlet opening 206A in cold plate 206. Typically, coolant line 108 is attached to device package 201 by use of connector features formed in package cover 208, such as threads formed in the sidewall of inlet / outlet opening 212 and / or protruding features 214 that surround inlet / outlet opening 212 and extend upward from the surface of lateral portion 208B.

[0028] Beneficially, the encapsulant layer 222 provides mechanical support that improves system reliability and extends the useful life of the device package 201. For example, the second encapsulant layer 222 can reduce mechanical stresses, such as stresses caused by vibration, mechanical and thermal shock, and / or fatigue caused by repeated thermal cycling, that can weaken interface bonds and / or electrical connections between electrical components of the device package 201. In some embodiments, the encapsulant layer 222 can be a thermally conductive material, such as a polymer or epoxy containing one or more thermally conductive additives, such as silver and / or graphite. In some embodiments, the device package 201 further includes a support member 207 attached to the upward-facing side of the cold plate 206, which can be formed of a rigid material, such as a metal or ceramic plate, that provides mechanical support to the cold plate 206. The support member 207 can be attached to the cold plate 206 using a direct bonding method or by using an intervening adhesive layer (not shown).

[0029] Figure 3A is a flow diagram describing a method 30 of forming an integrated cooling assembly according to embodiments of the disclosure. Figure 3B schematically illustrates the integrated cooling assembly 203 at various stages of the method 30. Generally, the method includes bonding a first substrate 304 carrying a plurality of devices 304 to a second substrate 306 carrying a plurality of cold plates 206, and singulating the plurality of cold plates 303 from the bonded substrates.

[0030] In block 32, the method 30 includes patterning the surface of the second substrate 306A, e.g., a single crystal silicon wafer, using a patterned mask layer 308A formed on the surface of the second substrate 306A. The anisotropic etching process utilizes the inherently different etch rates of silicon material between {100} and {111} planar surfaces upon exposure to an anisotropic etchant.

[0031] In some embodiments, the etching process is controlled so that the etch rates of the {111} planar surfaces and the {100} planar surfaces are in a ratio of about 1:10 to about 1:200, e.g., about 1:10 to about 1:100, e.g., about 1:10 to about 1:15, or about 1.25 to 1.75. Examples of suitable anisotropic wet etchants include aqueous solutions of potassium hydroxide (KOH), ethylenediamine-pyrocatechol (EPD), ammonium hydroxide (HN4OH), hydrazine (NH2H4), or tetramethylammonium hydroxide (TMAH). The actual various etch rates of the silicon substrate to the {100} planar surfaces and the {111} planar surfaces depend on the concentration of the etchant in the aqueous solution, the temperature of the aqueous solution, and the concentration of dopants, if any, in the substrate.

[0032] Typically, the {100} planes of a single crystal silicon substrate intersect with the {111} planes in the bulk of the substrate at an angle 312 of 54.74°. Thus, in some embodiments, the surfaces of the sidewalls and protruding features, when formed in a single crystal silicon substrate, may form an angle of approximately 54.74° with the plane of the field surface of the substrate (or device 304 bonded thereto).

[0033] Typically, mask layer 308A is made of a material that is selective to anisotropic etching compared to the underlying single crystal silicon substrate. Examples of suitable mask materials include silicon dioxide (Si x O y ) or silicon nitride (Si x N y In some embodiments, the mask layer 308A has a thickness of about 100 nm or less, such as about 50 nm or less, or about 30 nm or less. The mask layer 308A may be patterned using any suitable combination of lithography and material etch patterning methods.

[0034] In block 34, the method 30 includes aligning a first substrate 304 to a second substrate 306A, where the first substrate 304 includes a plurality of dies, e.g., devices 204, to be singulated, and the second substrate 306 includes a plurality of cold plates 206 to be singulated.

[0035] The first substrate 1004 may comprise a bulk material and multiple material layers disposed on the bulk material. The bulk material may include any semiconductor material suitable for fabricating semiconductor devices, such as silicon, silicon germanium, germanium, III-V semiconductor materials, II-VI semiconductor materials, or combinations thereof. For example, in some embodiments, the first substrate 304 may comprise a monocrystalline wafer, such as a silicon wafer, multiple device components formed in or on the silicon wafer, and multiple interconnect layers formed on the multiple device components. In other embodiments, the substrate may include a reconstituted substrate, such as a substrate formed from multiple singulated devices embedded in a support material.

[0036] The bulk material of the first substrate 304 may be thinned after the device 304 is formed using one or more backgrinding, etching, and polishing operations to remove material from the backside. Thinning the first substrate 304 may involve using a combination of polishing and etching processes to reduce the thickness (as viewed in the Z direction) to about 450 nm or less, e.g., about 301 nm or less, or about 150 nm or less. After thinning, the backside may be polished to a desired smoothness using a chemical mechanical polishing (CMP) process, and a dielectric layer may be deposited thereon. In some embodiments, polishing the dielectric layer to a desired smoothness may prepare the first substrate 304 for a bonding process. In some embodiments, the method 30 includes forming a plurality of metal features in the dielectric layer in preparation for a hybrid bonding process, for example, by using a damascene process.

[0037] In some embodiments, the active side is temporarily bonded before or after the thinning process to a carrier substrate (not shown), which, in use, provides support for the thinning operation and / or the thinned material to facilitate substrate handling during one or more of the following manufacturing operations described herein.

[0038] In block 36, the method 30 includes direct bonding the patterned second substrate 306A to the first substrate 304. In this case, the method 30 may include forming dielectric layers 310, 312 on the first substrate 304 and the second substrate 306A, and direct bonding the first and second substrates 304A, 306A includes forming a dielectric bond between the first dielectric layer 310 and the second dielectric layer 312.

[0039] Generally, direct bonding surfaces (surfaces of dielectric layers) involves pre-treating, aligning, and contacting the surfaces. Pre-treating the surfaces may include smoothing the respective surfaces to a wear surface roughness, e.g., 0.1-3.0 nm RMS, activating the surfaces to weaken or open chemical bonds in the dielectric, and terminating the surfaces with desired chemical species. Smoothing the surfaces may include polishing the substrates 304, 306A using a chemical mechanical polishing (CMP) process. Activating the surfaces and terminating them with desired chemical species may include exposing the surfaces to radical species formed in a plasma.

[0040] In some embodiments, a nitrogen-containing gas, such as N, is used to form the plasma, and the terminating species include nitrogen and hydrogen. In some embodiments, a wet cleaning process may be used to activate the surfaces, for example, by exposing the surfaces to an aqueous ammonia solution. In some embodiments, a dielectric bond may be formed using a dielectric layer deposited on only one of the substrates 304, 306A, but not both. In such embodiments, a direct dielectric bond may be formed by contacting a deposited dielectric layer of one substrate with the bulk material surface of the other substrate.

[0041] Forming a direct dielectric bond between the substrates in block 36 involves directly contacting the pre-treated and aligned surfaces with each other at temperatures below 150°C, e.g., below 100°C, e.g., below 30°C, or at about room temperature, e.g., 20°C to 30°C. Without being bound by theory, it is believed that the hydrogen-terminated species diffuse from the bonding surface as an interface, and chemical bonds are formed between the remaining nitrogen species during the direct bonding process. In some embodiments, the direct bond is strengthened using an annealing process in which the substrates are heated to and maintained at a temperature of about 30°C or higher and about 450°C or lower, e.g., about 50°C or higher and about 250°C or lower, or about 150°C, for a duration of about 5 minutes or longer, e.g., about 15 minutes. Typically, the bond will strengthen over time without the application of heat. Thus, in some embodiments, the method does not include heating the substrates.

[0042] In embodiments in which the substrates are bonded using a hybrid dielectric-metal bond, the method may further include planarizing or recessing the metal features below the field plane before contacting and bonding to the dielectric layer. After forming the dielectric bond, the substrates 304, 306A may be heated to a temperature of 150°C or greater and maintained at this elevated temperature for a duration of about 1 hour or greater, e.g., 8-24 hours, thereby forming a direct metallurgical bond between the metal features. Suitable direct dielectric-hybrid bonding technologies that can be used to practice aspects of the methods described herein include ZiBond® and DBI®, each of which is commercially available from Adeia Holding Corp., San Jose, California, USA.

[0043] At block 38, the method 30 includes singulating the integrated cooling assemblies 203 from the bonded substrate. Singulation after bonding imparts distinct structural properties to the integrated cooling assemblies 203 because the bonding surface of each cold plate 206 has the same perimeter as the backside of the device 204 bonded thereto. Thus, the sidewalls of the cold plates 206 are typically flush with the edges of the devices 204 along their common perimeter. In some embodiments, the cold plates 206 are singulated from the second substrate 306A using a process that cuts or separates the second substrate 306A in a vertical plane, i.e., parallel to the Z direction. In such embodiments, the sides of the cold plates 206 are substantially perpendicular to the backside of the devices, i.e., the horizontal (X-Y) plane of the mounting interface between the devices 204 and the cold plates 206. In some embodiments, the cold plates 206 are singulated using a saw or laser dicing process.

[0044] At block 40, the method includes coupling the integrated cooling assembly to the package substrate 202 and sealing the package cover 208 to the integrated cooling assembly 203 with the use of a molding compound that, upon curing, forms an encapsulant layer 222. In some embodiments, the method further includes forming an opening 222A in the encapsulant layer 222.

[0045] In other embodiments, the cold plate may be formed from two or more patterned substrates. For example, in FIG. 3C , the cold plate includes a second substrate 306A patterned using the methods described above and a third substrate 306B bonded to the patterned surface of the second substrate 306A. The third substrate 306B is patterned using a mask layer 308B, which may have the same pattern as the mask layer 308A or a different pattern. In this case, the third substrate 306B is anisotropically etched through the mask layer 308A to form openings that extend all the way to the patterned surface of the second substrate 306B. The resulting coolant channels thus have a depth that is more than twice the thickness of the coolant channels formed by a single substrate of the same thickness. For example, if the substrate is a 700-800 nm thick silicon wafer, the depth of the coolant channels may be 1 mm or greater, e.g., 1.2 mm or greater, or 1.4 mm or greater. In Figure 3D, the cold plate includes two of the second substrates 306A, each of which is patterned and then bonded to the patterned surface. An opening is then formed in one of the second substrates 306B, and the substrate (with the opening formed therethrough) is then bonded to the device 304, such that the device 304 is exposed to the coolant through the opening formed in the second substrate.

[0046] As envisioned, the above-described methods are not limited to crystalline silicon, as other methods known to those skilled in the art can be used to form the sloped surface. Thus, in some embodiments, the cold plate may be formed of a bulk material having substantially the same coefficient of linear thermal expansion (CTE) as the bulk material of the device, where CTE is the fractional change in length (in the X-Y plane) of the material per degree change in temperature. In some embodiments, the CTEs of the first and second substrates are matched such that the CTE of the second substrate 1006 is within about ±20% or less of the CTE of the first substrate 1004 when measured over a desired temperature range, e.g., within ±15% or less, within ±10% or less, or within about ±5% or less. In some embodiments, the CTEs are matched throughout a temperature range of about −60° C. to about 200° C., or a temperature range of about 60° C. to about 175° C. In one exemplary embodiment, the CTE-matched materials each comprise silicon. For example, the bulk material of the first substrate 1004 may include monocrystalline silicon, and the bulk material of the second substrate 1006 may include monocrystalline silicon or may include polycrystalline silicon. In some embodiments, the method 30 includes forming a dielectric layer and optionally a plurality of metal features on a bottom surface of the second substrate 306A.

[0047] 4A is a schematic cross-sectional view of another embodiment of a device package 401 that can be used with system panel 100. In this case, device package 401 includes package substrate 202, package cover 208, integrated cooling assembly 403 disposed between package substrate 202 and package cover 208, and encapsulant layer 422 disposed between integrated cooling assembly 403 and package cover 208.

[0048] 4B is a bottom-up exploded isometric view of the integrated cooling assembly 403 shown in FIG. The cooling assembly 403 includes, as its main components, the device 204 and a cold plate 406 attached to the backside of the device 204, for example, by using the direct bonding method described above. The cold plate 406 generally has a patterned side facing the device 204 and defining an upper portion of the coolant channels 410, and an opposite side facing the package cover 208. In this case, the patterned side forms a cavity facing the device having a base surface 409 and opposing sidewalls 411 projecting downwardly from the base surface 409. When sidewall 411 is attached to an underlying device 204, for example by direct bonding sidewall 413 to device backside 320, it forms the sides of coolant channel 410, base surface 209 forms the top surface of coolant channel 410, and device backside 320 forms the bottom surface of coolant channel 410. In this case, coolant circulates through coolant channel 410 via openings 406A at opposite ends of cooling assembly 403.

[0049] As shown, each opening 406A defines a gap between the cooling assembly 403 and the underlying device cover 320. The gap is formed at the edge of the cold plate 406, which either has no sidewalls (as shown) or has sidewalls that extend at least partially toward, but are not bonded to, the backside of the device 204. The openings 406A are in fluid communication with the inlet / outlet openings 212 of the package cover 208 through openings 422A formed in the encapsulant layer 422. As shown, the length of the cold plate 406 in the X direction is less than the length of the device 204, and the openings 422A through the encapsulant layer 422 extend from the package cover 208 to an edge portion of the backside of the underlying device. In other embodiments, the sidewalls 411 may have substantially the same length as the device 204, as shown in phantom, and the base surface 409 may have a length that is less than the length of the device 204. In either embodiment, the device backside 320 is in direct thermal contact with the coolant circulating through the coolant channels 410 and entering and exiting the coolant channels 410 on either side of the opening 406A. As envisioned, the cooling layer 403 and encapsulant layer 422 shown in Figures 4A and 4B can be used with any of the device packages described herein.

[0050] 5 is a schematic cross-sectional side view of an example multi-component device package 501 having a cold plate 506 directly bonded to the backside surface of two or more devices. As shown, the device package 501 includes a package substrate 502, e.g., an interposer that facilitates communication between the devices 204 and a device stack 504, an integrated cooling assembly 503, a package cover 208, and an adhesive layer 522. The integrated cooling assembly 503 may include multiple devices 204 (one shown), singulated and / or arranged in a vertical device stack 504 (one shown), and a cold plate 506 attached to each of the devices 204 and device stack 504, e.g., by direct bonding methods described herein. In some embodiments, the devices 204 may comprise processors, and the device stack 504 may comprise multiple memory devices. In this case, the device 204 and the device stack 504 are disposed in a side-by-side arrangement on the package substrate 202 and are in electrical communication with each other via conductive elements formed in, on, or through the package substrate 502. In this case, the cold plate 506 is sized to provide an attachable bonding surface for both the device 204 and the device stack 504, but may otherwise be the same or substantially the same as the other cold plates described herein. For example, in this case, the cold plate 506 has a patterned side with a base surface 509 and sidewalls 511 extending downwardly from the base surface 509 to form a cavity. The cavity may be closed as shown, for example, surrounded by sidewalls 511, or may be open at either end, as shown in FIGS. 4A and 4B. The base surface 509 may define the uppermost surface of the coolant channel 510 , and the sidewalls 511 may define the perimeter or lateral boundaries of the coolant channel 510 .In this case, the device 204 and the device stack 504 define respective portions of the bottom of the coolant channel 510, and a second underfill layer 521 or other molding material provided in the gap region between the device 204 and the device stack 504 provides the intervening bottom portion of the coolant channel provided between the device 204 and the device stack 504.

[0051] An encapsulant layer 522 disposed between the cold plate 506 and the package cover 208 attaches the cold plate 506 to the package cover 208 and forms a coolant-impermeable barrier therebetween. Coolant circulates to the device package 501 through the inlet / outlet openings 212 in the package cover 208 and flows through the coolant channels 510 via openings 506A in the cooling assembly 503 and corresponding openings 522A formed through the encapsulant layer 522. In this case, the encapsulant layer 522 may be formed of, for example, the polymer or epoxy molding compounds described above, or a compliant adhesive layer, such as a TIM layer.

[0052] 6 is a schematic cross-sectional side view of an exemplary multi-component device package according to one embodiment of the present disclosure. In this case, device package 601 includes package substrate 502, integrated cooling assembly 203, one or more second devices (shown in this case as device stack 604), and package cover 608. Device package 601 further includes an encapsulant layer 622 disposed between integrated cooling assembly 203 and the portion of package cover 608 disposed thereover. encapsulant layer 522 forms a coolant-impermeable barrier between cold plate 206 and package cover 208. In this case, device stack 604 is disposed on package substrate 502 in a side-by-side arrangement with device 204. Heat generated by device 204 is dissipated into coolant circulating through coolant channels 210. In this case, the coolant circulates through the inlet / outlet opening 212 provided in the package cover 608, an opening 622A provided through the sealing material layer 622 that is aligned with and in fluid communication with the inlet / outlet opening 212, and an opening 206A in the cold plate 206 that is in fluid communication with the opening 622A.

[0053] The package cover 608 may be formed of a thermally conductive material, and the package cover functions as a thermal spreader. Advantageously, the cold plate 206 blocks the thermal path between the device 204 and the device stack 604, preventing heat from being transferred between the device 204 and the device stack 604. Thus, heat generated by the device stack 604 is dissipated to a coolant via the package cover 608, which is thermally coupled to the device stack 604 through the use of the TIM layer 616. Thus, the device package 601 may be advantageously used to facilitate low latency while eliminating undesirable heat transfer between closely spaced devices on the interposer, such as high-power devices or memory stacks. In some embodiments, the device package 601 further includes a heat sink 608A disposed on a portion of the package cover 601 above the device stack 604. The heat sink 608A may be thermally coupled to the package cover 608 through the use of a TIM layer (not shown) or by direct bonding using methods described herein.

[0054] 7 is a schematic cross-sectional side view of a 3DIC device package 701 according to one embodiment of the present disclosure. The device package 701 includes, as its main components, an integrated cooling assembly 703 disposed on and electrically connected to a package substrate 202, a package cover 708 disposed over the integrated cooling assembly 703, and an encapsulant layer 722 disposed between the cooling assembly 703 and the cover 708. In this case, the integrated cooling assembly 703 includes a 3DIC device 704, which includes a first device 704A, one or more second devices 704B (one shown), and one or more cold plates 706 (two shown). In this case, the first device 704A is disposed facing the package substrate 202, i.e., active side down, and the second device 704B is disposed on and bonded to a portion of the backside of the first device 704. The package substrate 202 and the second device 704B and / or the first device 704A and the second device 704B may be interconnected using a plurality of through-substrate vias (TSVs 718) disposed through the first device 704A and hybrid bonds formed between the active side of the second device 704B and the backside of the first device 704A. In some embodiments, one or more second devices 704B have a device stack, such as device stack 604, directly bonded to and interconnected with the first device 704A using direct hybrid bonds.

[0055] In this case, a first device 704A is cooled using one or more cold plates 706 that are disposed on and bonded to a backside of the first device 704A in a juxtaposed arrangement with a second device 704B. Each of the one or more cold plates 706 is attached to a package cover 708 using an encapsulant layer 722 that forms a coolant-impermeable barrier between the cold plate 706 and the package cover 708.

[0056] In this case, each cold plate 706 has a base surface 709 and sidewalls 711 extending downwardly from the base surface 709, which are attached to the first device 704A, for example, using a direct bonding method, to form coolant channels 710 between the cold plate 706 and the underlying portion of the first device 704A. Heat generated by each portion of the first device 704A is dissipated from the device package 701 via coolant flowing through the coolant channels 710. In this case, the coolant is routed to each of the coolant channels 710 through a flow path that includes the inlet / outlet openings 212 in the package cover 708, the openings 722A in the encapsulant layer 722, and the openings 706A in the cold plate 706.

[0057] In this case, the second device 704B is thermally coupled to the package cover 708 through the use of the TIM layer 716, and the encapsulant layer 722 and the package cover 708 are each made of a thermally conductive material. Thus, heat generated by the second device 704B is transferred to the coolant in the coolant channels 710 via a heat transfer path that includes the TIM layer 716, the package cover 708, the encapsulant layer 722, and the cold plate 706. In some embodiments, the heat from the second device 704B is dissipated using a heat sink, such as the heat sink 608A described above, attached to the portion of the package cover 708 that covers the second device 704B.

[0058] For each of the above-described embodiments, the encapsulant layer and the openings therethrough facilitate delivery of coolant to the integrated device assembly without direct attachment of coolant lines to the integrated device assembly. Attachment of the coolant lines to the package cover reduces manufacturing complexity and cost because the package cover is typically formed of a less brittle material than the material used to form the cold plate and is thus less susceptible to breakage.

[0059] 8 is a schematic cross-sectional side view of a device package 801 according to one embodiment of the present disclosure. In this case, device package 801 includes a package substrate 202, a cooling assembly 203 disposed on package substrate 202, and a material layer 822 disposed over and at least partially encapsulating cooling assembly 203. Material layer 822 forms a coolant-impermeable seal with cooling assembly 203 and may be comprised of a polymer or epoxy made resin or molding compound. Coolant is delivered to cooling assembly 203 and circulated therethrough via openings 822A disposed through material layer 822. In this case, material layer 822 includes one or more features 814, such as threads or protrusions, extending upward to surround each of openings 822A, which allow for connection of cooling lines 108 (shown in phantom) directly to material layer 822. In some embodiments, the device package 801 further includes a package cover (not shown), and the coolant lines are coupled to the material layer 822 through openings in the package cover.

[0060] The above-described method advantageously provides an embedded cold plate that eliminates and / or substantially reduces the thermal resistance path typically associated with cooling systems mounted externally to the device package. The cold plate may be attached to the semiconductor device using direct dielectric or direct hybrid dielectric-metal bonding methods. Such bonding methods may enable a relatively low thermal budget while substantially increasing bond strength compared to conventional silicon-to-silicon bonding methods, such as thermocompression bonding.

[0061] The cold plate and semiconductor device may be made of CTE-matched materials, thereby eliminating the need for an intervening TIM layer. In some embodiments, the integrated cooling assembly and package cover may be formed of CTE-mismatched materials and attached to one another using a flexible material to form an encapsulant layer or by the use of a decoupling adhesive layer between the encapsulant layer and one of the cold plate or package cover. The flexible material can accommodate differences in linear expansion between the package cover and the cold plate during repeated thermal cycling, thereby extending the useful life of the device package.

[0062] The above-described embodiments are for illustrative purposes only and are not intended to limit the present invention. Those skilled in the art will recognize that individual aspects of the cooling assemblies, device packages, and methods described herein may be omitted, modified, combined, and / or rearranged without departing from the scope of the present invention. Only the following claims define the scope of protection of the present invention.

Claims

1. 1. A device package comprising: an integrated cooling assembly including a semiconductor device and a cold plate bonded to the semiconductor device, the cold plate having a patterned first side and an opposite second side; the patterned first side having a base surface, a sidewall, and a plurality of support features; the base surface is spaced from the semiconductor device so as to together form a coolant channel between the base surface and the semiconductor device; the sidewalls slope away from the base surface at an angle greater than 90° and are bonded to the semiconductor device to define a perimeter of the coolant channel; the plurality of support features are bonded to the semiconductor device within the perimeter; A device package, wherein each of the plurality of support features is wider at the base surface than at a bonding interface with the semiconductor device.

2. The device package of claim 1 , wherein the cold plate is attached to the semiconductor device by a direct dielectric bond.

3. 10. The device package of claim 1, wherein the cold plate is attached to the semiconductor device by a direct hybrid bond.

4. 2. The device package of claim 1, wherein the opening in the integrated cooling assembly extends between the first side and the second side of the cold plate.

5. The device package of claim 1 , wherein the opening in the integrated cooling assembly comprises a gap between the first side of the cold plate and the semiconductor device.

6. a package substrate carrying the integrated cooling assembly; a package cover disposed on the package substrate and extending over the integrated cooling assembly, the package cover having an inlet opening and an outlet opening therethrough; a layer of material disposed between the package cover and the cold plate; The device package of claim 1 , wherein the coolant channels are in fluid communication with the inlet and outlet openings via openings extending through the respective layers of material.

7. The device package of claim 6 further comprising a fluid coolant contained within the coolant channels.

8. 7. The device package of claim 6, wherein the openings provided in the integrated cooling assembly include multiple portions of a fluid path further including the inlet opening and the outlet opening, the openings extending through the material layer and the coolant channel.

9. The device package of claim 6 , wherein the package cover has one or more coolant line attachment features.

10. The device package of claim 6 , further comprising an underfill layer at least partially encapsulating the integrated cooling assembly in areas located outside the coolant channels.

11. 7. The device package of claim 6, wherein the layer of material forms an impermeable barrier between the package cover and the cold plate.

12. The device package of claim 6 , wherein the cold plate and the side of the semiconductor device are substantially flush with each other.

13. the semiconductor device is a first semiconductor device, and the integrated cooling assembly further includes a plurality of second semiconductor devices vertically arranged in a device stack; The device package of claim 6 , wherein the device stack is mounted on the first side of the cold plate in a side-by-side arrangement with the first semiconductor device.

14. The device package of claim 6 , wherein the cold plate is attached to the second semiconductor device by a direct dielectric bond.

15. The device package of claim 6 , wherein the cold plate is attached to the second semiconductor device by a direct hybrid bond.

16. The semiconductor device is a first semiconductor device, and the device package comprises: a device stack electrically connected to the package substrate in a side-by-side arrangement with the integrated cooling assembly; The device package of claim 6 , further comprising a first TIM layer disposed between the device stack and the package cover.

17. The device package of claim 16 , wherein the package cover is made of a thermally conductive material that forms a portion of a heat transfer path between the device stack and the coolant channel.

18. 17. The device package of claim 16, further comprising a heat sink thermally coupled to an outer surface of the package cover, the package cover being made of a thermally conductive material that forms a portion of a heat transfer path between the device stack and the heat sink.

19. the semiconductor device includes a first device and a second device directly bonded to the first device; the integrated cooling assembly includes one or more cold plates attached to the first device; 7. The device package of claim 6, wherein each of the one or more cold plates is sealed to the package cover by an adhesive layer to define a periphery of the coolant channel provided between the cold plate and the package cover.

20. 20. The device package of claim 19, wherein the second device is thermally coupled to the package cover by a TIM layer disposed between the second device and the package cover.

Images