Wiring board, semiconductor device, and method of manufacturing wiring board

Abstract

To provide a wiring board capable of improving connection reliability.SOLUTION: The wiring substrate 10 includes a core substrate 20, a first wiring structure 30 formed on the upper surface of the core substrate 20, and a second wiring structure 40 formed on the upper surface of the first wiring structure 30. The first wiring structure 30 has a structure in which a plurality of first wiring layers 31,33,35 and a plurality of first insulating layers 32,34,36 are stacked. The second wiring structure 40 has a structure in which a plurality of second wiring layers 41,43,45 and a plurality of second insulating layers 42,44 are stacked. The interconnect density of the second interconnect structure 40 is higher than the interconnect density of the first interconnect structure 30. The linear expansion coefficient of the second insulating layer 42,44 is higher than the linear expansion coefficient of the core substrate 20 and lower than the linear expansion coefficient of the first insulating layer 32,34,36.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present invention relates to a wiring board, a semiconductor device, and a method for manufacturing a wiring board. [Background technology]

[0002] Conventionally, as a wiring board on which electronic components such as semiconductor chips are mounted, a wiring board in which a plurality of wiring layers and insulating layers are laminated on both the upper and lower surfaces of a core substrate by a build-up method in order to increase the density of the wiring pattern has been known. As this type of wiring board, a wiring board has been proposed in which a high-density wiring layer including an insulating layer made of a photosensitive resin is formed on a low-density wiring layer including an insulating layer made of a non-photosensitive thermosetting resin (see, for example, Patent Document 1). [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Laid-Open No. 2014-225632 Summary of the Invention [Problem to be solved by the invention]

[0004] In the above-mentioned wiring board, it is desired to improve the reliability of connection with electronic components such as semiconductor chips. [Means for solving the problem]

[0005] According to one aspect of the present invention, a semiconductor device comprises a core substrate, a first wiring structure formed on an upper surface of the core substrate, and a second wiring structure formed on an upper surface of the first wiring structure, wherein the first wiring structure comprises one or more first wiring layers and one or more first insulating layers, and the second wiring structure comprises a structure in which a plurality of second wiring layers and a plurality of second insulating layers are stacked, and the wiring density of the second wiring structure is higher than the wiring density of the first wiring structure, and the linear expansion coefficient of the second insulating layer is higher than the linear expansion coefficient of the core substrate and lower than the linear expansion coefficient of the first insulating layer. [Effects of the Invention]

[0006] According to one aspect of the present invention, an effect is achieved in that connection reliability can be improved. [Brief explanation of the drawings]

[0007] [Figure 1] FIG. 1 is a schematic cross-sectional view showing a semiconductor device according to an embodiment. [Figure 2] FIG. 2(a) is a schematic cross-sectional view showing an enlarged view of a portion of a semiconductor device according to one embodiment, and FIG. 2(b) is a schematic cross-sectional view showing an enlarged view of a portion surrounded by a dashed line in FIG. 2(a). [Figure 3] FIG. 3 is a schematic cross-sectional view showing a method for manufacturing a wiring board according to an embodiment. [Figure 4] FIG. 4 is a schematic cross-sectional view showing a method for manufacturing a wiring board according to an embodiment. [Figure 5] FIG. 5 is a schematic cross-sectional view showing a method for manufacturing a wiring board according to an embodiment. [Figure 6] FIG. 6 is a schematic cross-sectional view showing a method for manufacturing a wiring board according to an embodiment. [Figure 7] FIG. 7 is a schematic cross-sectional view showing a method for manufacturing a wiring board according to an embodiment. [Figure 8] FIG. 8 is a schematic cross-sectional view showing a method for manufacturing a wiring board according to an embodiment. [Figure 9] FIG. 9 is a schematic cross-sectional view showing a method for manufacturing a wiring board according to an embodiment. [Figure 10] FIG. 10 is a schematic cross-sectional view showing a method for manufacturing a wiring board according to an embodiment. [Figure 11] FIG. 11 is a schematic cross-sectional view showing a method for manufacturing a wiring board according to an embodiment. [Figure 12] FIG. 12 is a schematic cross-sectional view showing a method for manufacturing a wiring board according to an embodiment. [Figure 13] FIG. 13 is a schematic cross-sectional view showing a method for manufacturing a semiconductor device according to one embodiment. [Figure 14]14(a) and 14(b) are schematic cross-sectional views showing a conventional semiconductor device. [Figure 15] 15(a) and 15(b) are schematic cross-sectional views showing a semiconductor device according to one embodiment. [Figure 16] 16(a) and 16(b) are schematic cross-sectional views showing a semiconductor device of a comparative example. [Figure 17] FIG. 17 is a graph showing the simulation results. [Figure 18] FIG. 18 is a schematic cross-sectional view showing a semiconductor device according to a modified example. DETAILED DESCRIPTION OF THE INVENTION

[0008] An embodiment will be described below with reference to the accompanying drawings. For convenience, the accompanying drawings may show characteristic portions enlarged to make the features easier to understand, and the dimensional ratios of each component may differ from one drawing to another. Also, in the cross-sectional views, the hatching of some components is shown with a matte finish, and the hatching of some components is omitted, in order to make the cross-sectional structure of each component easier to understand.

[0009] (Overall configuration of semiconductor device 1) As shown in FIG. 1, the semiconductor device 1 includes a wiring substrate 10, one or more (in this embodiment, five) semiconductor chips 70 mounted on the wiring substrate 10, an underfill resin 75, and external connection terminals 80.

[0010] (Overall configuration of wiring board 10) The wiring board 10 has a core substrate 20, a first wiring structure 30, a second wiring structure 40, a third wiring structure 50, a solder resist layer 60, and a solder resist layer 61. The first wiring structure 30, the second wiring structure 40, and the solder resist layer 60 are arranged on one side of the core substrate 20, and the third wiring structure 50 and the solder resist layer 61 are arranged on the other side of the core substrate 20.

[0011] In this embodiment, for convenience, the solder resist layer 60 side of the wiring board 10 in FIG. 1 will be referred to as the upper side or one side, and the solder resist layer 61 side will be referred to as the lower side or other side. Also, in this embodiment, for convenience, the surface of each portion facing the solder resist layer 60 will be referred to as one side or upper side, and the surface facing the solder resist layer 61 will be referred to as the other side or lower side. However, the semiconductor device 1 can be used upside down or positioned at any angle. In this specification, the term "planar view" refers to viewing an object from the normal direction of one side of the solder resist layer 60, and the term "planar shape" refers to the shape of the object viewed from the normal direction of one side of the solder resist layer 60.

[0012] The planar shape of the wiring board 10 can be any shape and any size. The planar shape of the wiring board 10 is, for example, rectangular. The planar size of the wiring board 10 can be approximately 30 mm x 30 mm to 80 mm x 80 mm.

[0013] (Configuration of core substrate 20) The core substrate 20 may be, for example, a so-called glass epoxy substrate in which glass cloth is impregnated with a thermosetting insulating resin such as an epoxy resin. Alternatively, the core substrate 20 may be, for example, a substrate in which a woven or nonwoven fabric such as glass fiber, carbon fiber, or aramid fiber is impregnated with a thermosetting insulating resin such as an epoxy resin. The coefficient of thermal expansion (CTE) of the core substrate 20 may be, for example, about 4 ppm / °C to 8 ppm / °C. The thickness of the core substrate 20 may be, for example, about 400 μm to 1600 μm. Note that glass cloth and the like are omitted from the drawings.

[0014] The core substrate 20 has a plurality of through holes 20X formed therein, penetrating the core substrate 20 in the thickness direction. The planar shape of the through holes 20X can be any shape and any size. The planar shape of the through holes 20X can be, for example, a circle with a diameter of about 50 μm to 200 μm. The pitch of the through holes 20X can be, for example, about 100 μm to 400 μm.

[0015] A through electrode 21 is formed on the inner wall surface of the through hole 20X, penetrating the core substrate 20 in the thickness direction. A resin portion 22 is filled in the center of the through hole 20X, specifically the through hole 20X located inside the through electrode 21. The through electrode 21 can be made of, for example, copper (Cu) or a copper alloy. The through electrode 21 can have a thickness of, for example, about 15 μm to 35 μm. The resin portion 22 can be made of, for example, an insulating resin such as an epoxy resin.

[0016] (Configuration of first wiring structure 30) The first wiring structure 30 is laminated on the upper surface of the core substrate 20. The first wiring structure 30 is a wiring structure having one or more first wiring layers and one or more first insulating layers. The first wiring structure 30 of this embodiment has a structure in which a first wiring layer 31, a first insulating layer 32, a first wiring layer 33, a first insulating layer 34, a first wiring layer 35, and a first insulating layer 36 are laminated in this order on the upper surface of the core substrate 20.

[0017] The first wiring layers 31, 33, and 35 may be made of, for example, copper or a copper alloy. The linear expansion coefficient of the first wiring layers 31, 33, and 35 may be, for example, about 15 ppm / °C to 18 ppm / °C. The thickness of each of the first wiring layers 31, 33, and 35 may be, for example, about 8 μm to 35 μm. The line / space (L / S) of the first wiring layers 31, 33, and 35 may be, for example, about 10 μm / 10 μm to 50 μm / 50 μm. Here, the "line" in "line / space" refers to the wiring width, and the "space" refers to the spacing between adjacent wirings (wiring spacing). For example, if the line / space is described as 10 μm / 10 μm to 50 μm / 50 μm, this means that the wiring width is 10 μm or more and 50 μm or less, and the wiring spacing between adjacent wirings is 10 μm or more and 50 μm or less. The wiring width and the wiring interval do not necessarily have to be equal.

[0018] The first insulating layers 32, 34, 36 are insulating layers whose main component is a non-photosensitive resin. The first insulating layers 32, 34, 36 can be made mainly of a thermosetting non-photosensitive resin such as an epoxy resin, an imide resin, a phenol resin, or a cyanate resin. The first insulating layers 32, 34, 36 contain a first filler F1 (see FIG. 2(b)) such as silica or alumina. The linear expansion coefficient of the first insulating layers 32, 34, 36 is higher than that of the core substrate 20. The linear expansion coefficient of the first insulating layers 32, 34, 36 can be, for example, approximately 15 ppm / °C to 25 ppm / °C. Here, the "linear expansion coefficient of the first insulating layers 32, 34, 36" in this specification may be a composite value of the linear expansion coefficients of the multiple first insulating layers 32, 34, 36, or may be the linear expansion coefficient of each of the multiple first insulating layers 32, 34, 36. The thickness of each of the first insulating layers 32, 34, 36 is, for example, thinner than the thickness of the core substrate 20. The thickness of each of the first insulating layers 32, 34, 36 can be, for example, approximately 30 μm to 70 μm. The thicknesses of the first insulating layers 32, 34, 36 may be the same or different from each other.

[0019] The first wiring layer 31 is laminated on the upper surface of the core substrate 20. The first wiring layer 31 is electrically connected to the through electrodes . The first insulating layer 32 is formed on the upper surface of the core substrate 20 so as to cover the first wiring layer 31. The first insulating layer 32 has through holes 32X formed in required locations that penetrate the first insulating layer 32 in the thickness direction and expose part of the upper surface of the first wiring layer 31.

[0020] The first wiring layer 33 is laminated on the upper surface of the first insulating layer 32. The first wiring layer 33 is electrically connected to the first wiring layer 31 through via wiring formed in the through hole 32X. The first wiring layer 33 is formed integrally with the via wiring filled in the through hole 32X, for example.

[0021] The first insulating layer 34 is formed on the upper surface of the first insulating layer 32 so as to cover the first wiring layer 33. The first insulating layer 34 has through-holes 34X formed in required locations, which penetrate the first insulating layer 34 in the thickness direction and expose part of the upper surface of the first wiring layer 33.

[0022] The first wiring layer 35 is laminated on the upper surface of the first insulating layer 34. The first wiring layer 35 is electrically connected to the first wiring layer 33 through via wiring formed in the through hole 34X. The first wiring layer 35 is formed integrally with the via wiring filled in the through hole 34X, for example.

[0023] The first insulating layer 36 is formed on the upper surface of the first insulating layer 34 so as to cover the first wiring layer 35. The first insulating layer 36 has through-holes 36X formed in required locations, which penetrate the first insulating layer 36 in the thickness direction and expose part of the upper surface of the first wiring layer 35.

[0024] Here, the through holes 32X, 34X, and 36X are formed in a tapered shape such that the diameter (opening width) decreases from the upper side (second wiring structure 40 side) to the lower side (core substrate 20 side) in Fig. 1. For example, the through holes 32X, 34X, and 36X are formed in an inverted truncated cone shape in which the opening diameter at the upper opening end is larger than the opening diameter at the lower opening end. The opening diameter at the upper opening end of the through holes 32X, 34X, and 36X can be, for example, approximately 60 μm to 70 μm.

[0025] (Configuration of third wiring structure 50) The third wiring structure 50 is laminated on the lower surface of the core substrate 20. The third wiring structure 50 is a wiring structure having one or more third wiring layers and one or more third insulating layers. The third wiring structure 50 of this embodiment has a structure in which a third wiring layer 51, a third insulating layer 52, a third wiring layer 53, a third insulating layer 54, and a third wiring layer 55 are laminated in this order on the lower surface of the core substrate 20.

[0026] The third wiring layers 51, 53, and 55 may be made of, for example, copper or a copper alloy. The third wiring layers 51, 53, and 55 may have a linear expansion coefficient of, for example, about 15 ppm / °C to 18 ppm / °C. The third wiring layers 51, 53, and 55 may each have a thickness of, for example, about 8 μm to 35 μm. The third wiring layers 51, 53, and 55 may have a line / space (L / S) of, for example, about 10 μm / 10 μm to 50 μm / 50 μm.

[0027] The third insulating layers 52 and 54 are insulating layers whose main component is a non-photosensitive resin. The third insulating layers 52 and 54 may be made mainly of a thermosetting non-photosensitive resin such as an epoxy resin, an imide resin, a phenol resin, or a cyanate resin. The third insulating layers 52 and 54 may contain, for example, a filler similar to the first filler F1 shown in FIG. 2(b). The linear expansion coefficient of the third insulating layers 52 and 54 is higher than that of the core substrate 20. The linear expansion coefficient of the third insulating layers 52 and 54 is, for example, approximately the same as that of the first insulating layers 32, 34, and 36. The linear expansion coefficient of the third insulating layers 52 and 54 may be, for example, approximately 15 ppm / °C to 25 ppm / °C. Here, the "linear expansion coefficient of the third insulating layers 52, 54" in this specification may be a composite value of the linear expansion coefficients of the plurality of third insulating layers 52, 54, or may be the linear expansion coefficient of each of the plurality of third insulating layers 52, 54. The thickness of each of the third insulating layers 52, 54 is, for example, the same as the thickness of each of the first insulating layers 32, 34, 36, or is thicker than the thickness of each of the first insulating layers 32, 34, 36. The thickness of each of the third insulating layers 52, 54 is, for example, thinner than the thickness of the core substrate 20. The thickness of each of the third insulating layers 52, 54 may be, for example, approximately 35 μm to 100 μm. The thicknesses of the third insulating layers 52, 54 may be the same as or different from each other.

[0028] The third wiring layer 51 is laminated on the lower surface of the core substrate 20. The third wiring layer 51 is electrically connected to the first wiring layer 31 via the through electrodes . The third insulating layer 52 is formed on the lower surface of the core substrate 20 so as to cover the third wiring layer 51. The third insulating layer 52 has through holes 52X formed in required locations, which penetrate the third insulating layer 52 in the thickness direction and expose part of the lower surface of the third wiring layer 51.

[0029] The third wiring layer 53 is laminated on the lower surface of the third insulating layer 52. The third wiring layer 53 is electrically connected to the third wiring layer 51 through a via wiring formed in the through hole 52X. The third wiring layer 53 is formed integrally with the via wiring filled in the through hole 52X, for example.

[0030] The third insulating layer 54 is formed on the lower surface of the third insulating layer 52 so as to cover the third wiring layer 53. The third insulating layer 54 has through-holes 54X formed in required locations, which penetrate the third insulating layer 54 in the thickness direction and expose part of the lower surface of the third wiring layer 53.

[0031] The third wiring layer 55 is laminated on the lower surface of the third insulating layer 54. The third wiring layer 55 is electrically connected to the third wiring layer 53 through via wiring formed in the through hole 54X. The third wiring layer 55 is formed integrally with the via wiring filled in the through hole 54X, for example.

[0032] Here, the through holes 52X, 54X are formed in a tapered shape such that the diameter (opening width) decreases from the lower side (solder resist layer 61 side) to the upper side (core substrate 20 side) in Fig. 1. For example, the through holes 52X, 54X are formed in a truncated cone shape in which the opening diameter of the lower opening end is larger than the opening diameter of the upper opening end. The opening diameter of the lower opening end of the through holes 52X, 54X can be, for example, approximately 60 μm to 70 μm.

[0033] (Configuration of solder resist layer 61) The solder resist layer 61 is an outermost insulating layer provided on the outermost layer (here, the lowest layer) of the wiring board 10. The solder resist layer 61 is formed on the lower surface of the third wiring structure 50, specifically on the lower surface of the third insulating layer 54 formed on the lowest layer of the third wiring structure 50, so as to cover the lowest third wiring layer 55. The solder resist layer 61 is an insulating layer containing a photosensitive resin as its main component. The material of the solder resist layer 61 can be, for example, a photosensitive insulating resin containing a phenolic resin, a polyimide resin, or the like as its main component. The solder resist layer 61 may contain a filler such as silica or alumina.

[0034] Openings 61X are formed in the solder resist layer 61 to expose portions of the lower surface of the third wiring layer 55, which is the lowest layer, as external connection pads P1. The external connection pads P1 are adapted to be connected to external connection terminals 80 that are used when mounting the wiring board 10 on a mounting board such as a motherboard.

[0035] If necessary, a surface treatment layer may be formed on the third wiring layer 55 exposed through the opening 61X. Examples of the surface treatment layer include an Au layer, a Ni layer / Au layer (a metal layer formed by laminating a Ni layer and an Au layer in this order), and a Ni layer / Pd layer / Au layer (a metal layer formed by laminating a Ni layer, a Pd layer, and an Au layer in this order). The Au layer is a metal layer made of Au or an Au alloy, the Ni layer is a metal layer made of Ni or an Ni alloy, and the Pd layer is a metal layer made of Pd or a Pd alloy. The Au layer, Ni layer, and Pd layer may be, for example, a metal layer formed by electroless plating (electroless plated metal layer). Alternatively, the surface treatment layer may be an OSP (organic solderability preservative) film formed by applying an anti-oxidation treatment such as an OSP treatment to the surface of the external connection pad P1. For example, an organic coating such as an azole compound or an imidazole compound may be used as the OSP film. The third wiring layer 55 exposed from the opening 61X (or, if a surface treatment layer is formed on the third wiring layer 55, the surface treatment layer) itself may be used as an external connection terminal.

[0036] The external connection pads P1 and the openings 61X may have any shape and size in plan view, and may have a circular shape with a diameter of, for example, about 200 μm to 300 μm in plan view.

[0037] (Configuration of second wiring structure 40) The second wiring structure 40 is laminated on the upper surface of the first wiring structure 30. The second wiring structure 40 is a wiring structure in which a plurality of second wiring layers and a plurality of second insulating layers are laminated. The second wiring structure 40 of this embodiment has a structure in which a second wiring layer 41, a second insulating layer 42, a second wiring layer 43, a second insulating layer 44, and a second wiring layer 45 are laminated in this order on the upper surface of the first insulating layer 36 formed on the uppermost layer of the first wiring structure 30.

[0038] The wiring density of the second wiring structure 40 is higher than that of the first wiring structure 30. The second wiring structure 40 is a high-density wiring layer (fine-wiring layer) in which a wiring layer with a higher wiring density than that of the first wiring structure 30 is formed. The wiring width and wiring spacing of the second wiring layers 41, 43, and 45 are smaller than the wiring width and wiring spacing of the first wiring layers 31, 33, and 35. The wiring density of the second wiring structure 40 is higher than the wiring density of the third wiring structure 50. The second wiring structure 40 is a high-density wiring layer in which a wiring layer with a higher wiring density than that of the third wiring structure 50 is formed. The wiring width and wiring spacing of the second wiring layers 41, 43, and 45 are smaller than the wiring width and wiring spacing of the third wiring layers 51, 53, and 55. The line / space (L / S) of the second wiring layers 41, 43, and 45 can be, for example, approximately 3 μm / 3 μm to 8 μm / 8 μm.

[0039] The second wiring layers 41, 43, and 45 may be made of, for example, copper or a copper alloy. The second wiring layers 41, 43, and 45 may have a linear expansion coefficient of, for example, about 15 ppm / °C to 18 ppm / °C. The thickness of each of the second wiring layers 41, 43, and 45 is, for example, approximately the same as or thinner than the thickness of each of the first wiring layers 31, 33, and 35. The thickness of each of the second wiring layers 41, 43, and 45 may be, for example, about 8 μm to 15 μm.

[0040] The second insulating layers 42, 44 are insulating layers whose main component is a non-photosensitive resin. The second insulating layers 42, 44 may be made primarily of a thermosetting non-photosensitive resin, such as an epoxy resin, an imide resin, a phenol resin, or a cyanate resin. The linear expansion coefficient of the second insulating layers 42, 44 is higher than that of the core substrate 20 and lower than that of the first insulating layers 32, 34, 36. The linear expansion coefficient of the second insulating layers 42, 44 is lower than that of the third insulating layers 52, 54. The linear expansion coefficient of the second insulating layers 42, 44 may be, for example, approximately 8 ppm / °C to 18 ppm / °C. In this specification, the "linear expansion coefficient of the second insulating layers 42, 44" may refer to a composite value of the linear expansion coefficients of the plurality of second insulating layers 42, 44, or may refer to the linear expansion coefficient of each of the plurality of second insulating layers 42, 44.

[0041] As shown in FIG. 2(b), the second insulating layers 42, 44 contain a second filler F2 such as silica or alumina. The average particle size of the second filler F2 is smaller than the average particle size of the first filler F1 contained in the first insulating layers 32, 34, 36. The maximum particle size of the second filler F2 is smaller than the maximum particle size of the first filler F1. Here, the average particle size of the first filler F1 can be, for example, 0.5 μm or less. The maximum particle size of the first filler F1 can be, for example, 5 μm or less. The average particle size of the second filler F2 can be, for example, 0.1 μm or less. The maximum particle size of the second filler F2 can be, for example, 1 μm or less. The average particle sizes and maximum particle sizes of the first filler F1 and the second filler F2 can be measured using, for example, a scanning electron microscope.

[0042] In the second insulating layers 42, 44, for example, the linear expansion coefficient of the second insulating layers 42, 44 can be adjusted by adjusting the content of the second filler F2. The content of the second filler F2 is, for example, higher than the content of the first filler F1. The content of the first filler F1 can be, for example, approximately 60 wt% to 70 wt%. The content of the second filler F2 can be, for example, approximately 75 wt% to 85 wt%.

[0043] In this embodiment, the content of the second filler F2 is adjusted to be higher than the content of the first filler F1, thereby adjusting the linear expansion coefficient of the second insulating layers 42, 44 to be lower than the linear expansion coefficient of the first insulating layers 32, 34, 36. Here, in an insulating layer whose main component is a photosensitive resin, a high filler content makes exposure impossible, so there is a limit (upper limit) to the amount of filler that can be contained. Therefore, the linear expansion coefficient of an insulating layer whose main component is a photosensitive resin tends to be higher than the linear expansion coefficient of an insulating layer whose main component is a non-photosensitive resin. For this reason, when adjusting the linear expansion coefficient of the second insulating layers 42, 44 by adjusting the content of the second filler F2, it is preferable that the second insulating layers 42, 44 be made mainly of a non-photosensitive resin.

[0044] 2(a), the thickness of each of the second insulating layers 42, 44 is thinner than the thickness of the core substrate 20, for example. The thickness of each of the second insulating layers 42, 44 is thinner than the thickness of each of the first insulating layers 32, 34, 36, for example. The thickness of each of the second insulating layers 42, 44 is thinner than the thickness of each of the third insulating layers 52, 54, for example. The thickness of each of the second insulating layers 42, 44 can be, for example, approximately 1 μm to 10 μm. The thicknesses of the second insulating layers 42, 44 may be the same as each other or may be different from each other.

[0045] The second wiring layer 41 is stacked on the upper surface of the first insulating layer 36 formed on the uppermost layer of the first wiring structure 30. The second wiring layer 41 is electrically connected to the first wiring layer 35 through via wiring formed in the through hole 36X. The second wiring layer 41 is formed integrally with the via wiring filled in the through hole 36X, for example.

[0046] The second insulating layer 42 is formed on the upper surface of the first insulating layer 36 formed on the uppermost layer of the first wiring structure 30 so as to cover the second wiring layer 41. The second insulating layer 42 has through-holes 42X formed in required locations that penetrate the second insulating layer 42 in the thickness direction and expose part of the upper surface of the second wiring layer 41.

[0047] The second wiring layer 43 is laminated on the upper surface of the second insulating layer 42. The second wiring layer 43 is electrically connected to the second wiring layer 41 through a via wiring V1 formed in the through hole 42X. The second wiring layer 43 is formed integrally with the via wiring V1 filled in the through hole 42X, for example.

[0048] The second insulating layer 44 is formed on the upper surface of the second insulating layer 42 so as to cover the second wiring layer 43. The second insulating layer 44 has through-holes 44X formed in required locations, which penetrate the second insulating layer 44 in the thickness direction and expose part of the upper surface of the second wiring layer 43.

[0049] Here, the through holes 42X, 44X are formed in a tapered shape such that the diameter (opening width) decreases from the upper side (the solder resist layer 60 side) to the upper side (the first wiring structure 30 side) in FIG. 2(a). For example, the through holes 42X, 44X are formed in an inverted truncated cone shape in which the opening diameter at the upper opening end is larger than the opening diameter at the lower opening end. The opening diameter of each of the through holes 42X, 44X is, for example, smaller than the opening diameter of each of the through holes 32X, 34X, 36X. The opening diameter of the upper opening end of the through holes 42X, 44X can be, for example, approximately 5 μm to 10 μm.

[0050] The second wiring layer 45 is laminated on the upper surface of the second insulating layer 44. The second wiring layer 45 is electrically connected to the second wiring layer 43 through via wiring V2 formed in the through hole 44X. The second wiring layer 45 is, for example, formed integrally with the via wiring V2 filled in the through hole 44X. The second wiring layer 45 has, for example, pads P2. The planar shape of the pads P2 can be any shape and any size. The planar shape of the pads P2 can be, for example, a circle with a diameter of approximately 20 μm to 30 μm. The pitch of the pads P2 can be, for example, approximately 40 μm to 60 μm. The pads P2 function as pads for mounting electronic components such as the semiconductor chip 70 for electrical connection thereto.

[0051] If necessary, a surface treatment layer may be formed on the surface of the pad P2 (top and side surfaces, or only the top surface). The surface treatment layer may be a metal layer such as an Au layer, a Ni / Au layer, or a Ni / Pd / Au layer, or an OSP film.

[0052] (Configuration of solder resist layer 60) The solder resist layer 60 is an outermost insulating layer provided on the outermost layer (here, the uppermost layer) of the wiring board 10. The solder resist layer 60 is laminated on the upper surface of the second wiring structure 40, specifically on the upper surface of the second insulating layer 44 formed on the uppermost layer of the second wiring structure 40. The solder resist layer 60 is an insulating layer containing a photosensitive resin as its main component. The material of the solder resist layer 60 can be, for example, a photosensitive insulating resin containing a phenolic resin, a polyimide resin, or the like as its main component. The solder resist layer 60 may contain a filler such as silica or alumina.

[0053] The solder resist layer 60 is laminated on the upper surface of the second insulating layer 44 so as to expose the multiple pads P2. For example, in a plan view, the solder resist layer 60 is formed so as to surround a mounting area where multiple semiconductor chips 70 are mounted. In other words, the solder resist layer 60 has openings 60X that expose the upper surface of the second wiring structure 40 in the mounting area. The openings 60X are formed so as to overlap the mounting area in a plan view. The openings 60X are formed so as to penetrate the solder resist layer 60 in the thickness direction. The openings 60X are formed so as to expose the upper surface of the second insulating layer 44 and the pads P2 in the mounting area.

[0054] (Configuration of semiconductor chip 70) Each semiconductor chip 70 has a plurality of connection terminals 71 formed on a circuit formation surface (here, the lower surface) of the semiconductor chip 70. Each semiconductor chip 70 is a component made of, for example, silicon (Si). Each semiconductor chip 70 has a structure in which, on a thinned semiconductor substrate made of, for example, silicon, the circuit formation surface on which a semiconductor integrated circuit (not shown) is formed is covered with a passivation film, and the connection terminals 71 are provided on the circuit formation surface.

[0055] Each semiconductor chip 70 is mounted on the wiring substrate 10. For example, each semiconductor chip 70 is flip-chip mounted on the wiring substrate 10. For example, a connection terminal 71 of each semiconductor chip 70 is electrically connected to a pad P2 of the wiring substrate 10 via a solder layer 72. As a result, each semiconductor chip 70 is electrically connected to the pad P2 via the connection terminal 71 and the solder layer 72. The multiple semiconductor chips 70 are electrically connected to one another, for example, via a second wiring layer 45 having the pad P2.

[0056] For example, logic chips such as a CPU (Central Processing Unit) chip or a GPU (Graphics Processing Unit) chip can be used as the semiconductor chip 70. Furthermore, for example, memory chips such as a DRAM (Dynamic Random Access Memory) chip or a flash memory chip can be used as the semiconductor chip 70. The plurality of semiconductor chips 70 includes, for example, a logic chip and a memory chip.

[0057] The planar shape of each semiconductor chip 70 can be any shape and any size. The planar shape of each semiconductor chip 70 is, for example, rectangular. The planar size of each semiconductor chip 70 can be, for example, approximately 3 mm x 3 mm to 12 mm x 12 mm. The thickness of each semiconductor chip 70 can be, for example, approximately 50 μm to 300 μm. The linear expansion coefficient of each semiconductor chip 70 is, for example, lower than the linear expansion coefficient of the second insulating layers 42, 44. The linear expansion coefficient of each semiconductor chip 70 is, for example, lower than the linear expansion coefficient of the first insulating layers 32, 34, 36. The linear expansion coefficient of each semiconductor chip 70 is, for example, lower than the linear expansion coefficient of the core substrate 20. The linear expansion coefficient of each semiconductor chip 70 can be, for example, approximately 2 ppm / °C to 5 ppm / °C.

[0058] The connection terminals 71 may be, for example, metal posts. The connection terminals 71 are columnar connection terminals extending downward from the circuit formation surface of the semiconductor chip 70. The connection terminals 71 in this example are formed in, for example, a cylindrical shape. The thickness of the connection terminals 71 may be, for example, about 10 μm to 20 μm. The diameter of the connection terminals 71 may be, for example, about 20 μm to 30 μm. The pitch of the connection terminals 71 may be, for example, about 40 μm to 60 μm. The connection terminals 71 may be made of, for example, copper or a copper alloy. Note that, instead of metal posts, gold bumps may also be used as the connection terminals 71.

[0059] The solder layer 72 is bonded to the pad P2 and also to the connection terminal 71. For example, tin (Sn)-silver (Ag)-based, Sn-Cu-based, or Sn-Ag-Cu-based lead (Pb)-free solder can be used as the material for the solder layer 72. The thickness of the solder layer 72 can be, for example, about 5 μm to 15 μm.

[0060] (Composition of Underfill Resin 75) 1, underfill resin 75 is provided to fill the gap between wiring substrate 10 and semiconductor chip 70. Underfill resin 75 is provided to fill the gap between the upper surface of second insulating layer 44 exposed from opening 60X and the lower surface of semiconductor chip 70. As a material for underfill resin 75, for example, an insulating resin such as an epoxy resin can be used.

[0061] (Configuration of external connection terminal 80) The external connection terminals 80 are formed on the external connection pads P1 of the wiring substrate 10. The external connection terminals 80 are connection terminals that are electrically connected to pads provided on a mounting substrate such as a motherboard (not shown). For example, solder balls or lead pins can be used as the external connection terminals 80. The external connection terminals 80 of this embodiment are solder balls.

[0062] As described above, in the semiconductor device 1, the linear expansion coefficients of the components are set so that they increase in the order of semiconductor chip 70, core substrate 20, second insulating layers 42, 44, first insulating layers 32, 34, 36, and third insulating layers 52, 54. By setting the linear expansion coefficients of the components in this manner, it is possible to suitably reduce warpage of the wiring board 10 and the semiconductor device 1. Details will be described in the sections on operation and warpage simulation.

[0063] (Method of manufacturing wiring board 10) Next, a description will be given of a method for manufacturing the wiring board 10. For ease of explanation, the parts that will ultimately become the components of the wiring board 10 will be described using the reference numerals of the final components.

[0064] 3, a structure is formed that includes a core substrate 20, through electrodes 21, a resin portion 22, a first wiring layer 31 formed on the upper surface of the core substrate 20, and a third wiring layer 51 formed on the lower surface of the core substrate 20. This structure can be manufactured by a known manufacturing method, and will be described in detail here.

[0065] Next, in the process shown in FIG. 4, a first insulating layer 32 is formed to cover the upper surface of the core substrate 20 and the first wiring layer 31, and a third insulating layer 52 is formed to cover the lower surface of the core substrate 20 and the third wiring layer 51. When a resin film is used as the first insulating layer 32 and the third insulating layer 52, the resin film is laminated, for example, on the upper and lower surfaces of the core substrate 20. Then, the resin film is pressed and heat-treated at a temperature equal to or higher than the curing temperature (for example, about 130°C to 200°C) to harden it, thereby forming the first insulating layer 32 and the third insulating layer 52. For example, a thermosetting resin film containing an epoxy resin as a main component can be used as the resin film. When a liquid or paste-like insulating resin is used as the first insulating layer 32 and the third insulating layer 52, the liquid or paste-like insulating resin is applied to the upper and lower surfaces of the core substrate 20 by a method such as spin coating. The applied insulating resin is then cured by heat treatment at a temperature equal to or higher than the curing temperature, thereby forming the first insulating layer 32 and the third insulating layer 52. As the liquid or paste insulating resin, for example, a thermosetting resin containing an epoxy resin as a main component can be used.

[0066] 5, through holes 32X are formed in predetermined locations of the first insulating layer 32 so as to expose part of the upper surface of the first wiring layer 31. Furthermore, through holes 52X are formed in predetermined locations of the third insulating layer 52 so as to expose part of the lower surface of the third wiring layer 51. The through holes 32X, 52X can be formed by laser processing using, for example, a CO laser, a UV-YAG laser, or the like.

[0067] Next, in the case where the through holes 32X, 52X are formed by laser processing, a desmearing process is performed to remove resin smears adhering to the exposed surfaces of the first wiring layer 31 and the third wiring layer 51 exposed at the bottoms of the through holes 32X, 52X. The desmearing process in this step may be, for example, a wet desmearing process using a potassium permanganate solution or the like.

[0068] 6, via wirings are filled in the through holes 32X of the first insulating layer 32, and a first wiring layer 33 is formed that is electrically connected to the first wiring layer 31 through the via wirings and laminated on the upper surface of the first insulating layer 32. Also, via wirings are filled in the through holes 52X of the third insulating layer 52, and a third wiring layer 53 is formed that is electrically connected to the third wiring layer 51 through the via wirings and laminated on the lower surface of the third insulating layer 52. The first wiring layer 33 and the third wiring layer 53 can be formed using various wiring formation methods, such as a semi-additive method or a subtractive method.

[0069] 7, steps similar to those shown in FIGS. 4 to 6 are performed to laminate a first insulating layer 34 and a first wiring layer 35 on the upper surface of the first insulating layer 32, and a third insulating layer 54 and a third wiring layer 55 on the lower surface of the third insulating layer 52. Furthermore, steps similar to those shown in FIGS. 4 to 6 are performed to laminate a first insulating layer 36 and a second wiring layer 41 on the upper surface of the first insulating layer 34. Through this step, a first wiring structure 30 is formed on the upper surface of the core substrate 20, and a third wiring structure 50 is formed on the lower surface of the core substrate 20. Here, the line / space of the second wiring layer 41 is formed to be smaller than the line / space of the first wiring layers 31, 33, and 35.

[0070] 8, a second insulating layer 42 is formed to cover the upper surface of the first insulating layer 36 and the second wiring layer 41. When a resin film is used as the second insulating layer 42, for example, the resin film is laminated on the upper surface of the first insulating layer 36. Then, the resin film is pressed and heat-treated at a temperature equal to or higher than the curing temperature (for example, about 130°C to 200°C) to harden it, thereby forming the second insulating layer 42. When a liquid or paste insulating resin is used as the second insulating layer 42, the liquid or paste insulating resin is applied to the upper surface of the first insulating layer 36 by a spin coating method or the like. Then, the applied insulating resin is hardened by heat-treating it at a temperature equal to or higher than the curing temperature to form the second insulating layer 42. The insulating resin that becomes the second insulating layer 42 can be, for example, a thermosetting resin such as an epoxy resin or a polyimide resin.

[0071] Here, the second insulating layer 42 preferably contains, as its main component, a thermosetting non-photosensitive resin such as an epoxy resin or a polyimide resin. The second insulating layer 42 contains a second filler F2 (see FIG. 2(b)), such as silica or alumina. The average particle size and maximum particle size of the second filler F2 contained in the second insulating layer 42 are smaller than the average particle size and maximum particle size of the first filler F1 (see FIG. 2(b)) contained in the first insulating layers 32, 34, and 36. The content of the second filler F2 is higher than the content of the first filler F1. The linear expansion coefficient of the second insulating layer 42 is adjusted to be higher than the linear expansion coefficient of the core substrate 20 and lower than the linear expansion coefficient of the first insulating layers 32, 34, and 36. The second insulating layer 42 is formed thinner than the first insulating layers 32, 34, and 36.

[0072] 9, through holes 42X are formed in predetermined locations of the second insulating layer 42 so as to expose portions of the upper surface of the second wiring layer 41. The through holes 42X can be formed, for example, by laser processing. However, the opening diameter of the through holes 42X is smaller than the opening diameters of the through holes 32X, 34X, and 36X of the first wiring structure 30. For this reason, it is preferable to form the through holes 42X using an excimer laser that is suitable for microfabrication.

[0073] Subsequently, when the through holes 42X are formed by laser processing, a desmear process is performed to remove resin smears adhering to the exposed surface of the second wiring layer 41 exposed at the bottom of the through holes 42X. The desmear process in this step may be, for example, a dry desmear process using carbon tetrafluoride (CF4) gas or the like.

[0074] 10, via wirings V1 are filled in the through holes 42X of the second insulating layer 42, and a second wiring layer 43 is formed which is electrically connected to the second wiring layer 41 through the via wirings V1 and is laminated on the upper surface of the second insulating layer 42. Here, the line / space of the second wiring layer 43 is formed to be smaller than the line / space of the first wiring layers 31, 33, and 35. The second wiring layer 43 and the via wirings V1 can be formed using various wiring formation methods, such as a semi-additive method or a subtractive method.

[0075] 11, a second insulating layer 44 and a second wiring layer 45 are laminated on the upper surface of the second insulating layer 42 by performing the same steps as those shown in FIGS. 8 to 10. At this time, the second wiring layer 45 has a pad P2. By this step, the second wiring structure 40 is formed on the upper surface of the first wiring structure 30.

[0076] 12, a solder resist layer 60 having openings 60X that expose the pads P2 is formed on the upper surface of the second insulating layer 44. Also, a solder resist layer 61 having openings 61X that expose part of the lower surface of the third wiring layer 55 as the external connection pads P1 is formed on the lower surface of the third insulating layer 54. The solder resist layers 60, 61 can be formed, for example, by laminating a photosensitive solder resist film or by applying a liquid solder resist layer and patterning the resist into the required shape.

[0077] If necessary, a surface treatment layer may be formed on the external connection pads P1 and P2. The solder resist layer 61 may be formed at any time after the formation of the lowermost third wiring layer 55. For example, the solder resist layer 61 may be formed after the step shown in FIG.

[0078] By the above manufacturing process, the wiring board 10 of this embodiment can be manufactured. (Method of manufacturing semiconductor device 1) Next, a method for manufacturing the semiconductor device 1 will be described.

[0079] 13, a plurality of semiconductor chips 70 are prepared, each having connection terminals 71 and a solder layer 72 formed on the lower surface of the connection terminal 71. Each semiconductor chip 70 can be manufactured by a known manufacturing method, and therefore detailed description thereof will be omitted here.

[0080] Next, the connection terminals 71 of each semiconductor chip 70 are bonded onto the pads P2 of the wiring substrate 10. For example, after aligning the wiring substrate 10 and each semiconductor chip 70, a reflow process is performed to melt the solder layer 72 and electrically connect the connection terminals 71 to the pads P2. The temperature of the reflow process is, for example, about 260°C.

[0081] Thereafter, underfill resin 75 is filled between the semiconductor chip 70 and the wiring substrate 10, and the underfill resin 75 is cured. In addition, external connection terminals 80 (see FIG. 1) are formed on the external connection pads P1. The external connection terminals 80 may be formed at any time after the external connection pads P1 are formed. For example, the external connection terminals 80 may be formed before the semiconductor chip 70 is mounted on the wiring substrate 10.

[0082] Through the above manufacturing steps, the semiconductor device 1 of this embodiment can be manufactured. (Action of this embodiment) Next, the operation of the wiring board 10 and the semiconductor device 1 of this embodiment will be described with reference to FIGS. 14 to 16. FIG. 14 is a cross-sectional view schematically showing a conventional semiconductor device 1A. FIG. 15 is a cross-sectional view schematically showing the semiconductor device 1 of this embodiment. FIG. 16 is a cross-sectional view schematically showing a semiconductor device 1B of a comparative example. In FIGS. 14 to 16, the first wiring structure 30 is illustrated as a single layer for simplification of the drawings. Also, in FIGS. 14(a), 15(a), and 16(a), the third wiring structure 50 is illustrated as a single layer for simplification of the drawings. The arrows in FIGS. 14 to 16 schematically represent the amount of expansion or contraction of each component. The longer the arrows in FIGS. 14 to 16, the greater the amount of expansion or contraction of each component.

[0083] The semiconductor devices 1, 1A, and 1B have the same layer structure, but the linear expansion coefficients of the components of the semiconductor devices 1, 1A, and 1B are different from one another. First, a conventional semiconductor device 1A will be described with reference to FIG.

[0084] As shown in FIG. 14(a), the semiconductor device 1A includes a wiring board 10A. In the conventional wiring board 10A, the linear expansion coefficients are set to increase in the order of core substrate 20, first insulating layers 32, 34, and 36, third insulating layers 52 and 54, and second insulating layers 42 and 44. For example, in the wiring board 10A, the linear expansion coefficients of the third insulating layers 52 and 54, core substrate 20, first insulating layers 32, 34, and 36, and second insulating layers 42 and 44 are set to 20 ppm / °C, 7 ppm / °C, 20 ppm / °C, and 37 ppm / °C, respectively. Therefore, in the conventional wiring board 10A, the linear expansion coefficients are significantly different between the top and bottom of the core substrate 20.

[0085] When the conventional wiring board 10A is exposed to a high-temperature environment of approximately 260°C during mounting of the semiconductor chip 70, warping occurs in the wiring board 10A due to a difference (mismatch) in the linear expansion coefficients between the top and bottom of the core substrate 20. Specifically, in the wiring board 10A, the core substrate 20 is less likely to stretch relative to the first insulating layers 32, 34, 36, the second insulating layers 42, 44, and the third insulating layers 52, 54. In this case, the linear expansion coefficients of the second insulating layers 42, 44 provided above the core substrate 20 are higher than the linear expansion coefficients of the third insulating layers 52, 54 provided below the core substrate 20. Therefore, the second insulating layers 42, 44 provided above the core substrate 20 are more likely to stretch than the third insulating layers 52, 54 provided below the core substrate 20. 14(a), when the conventional wiring substrate 10A is exposed to a high-temperature environment, the second wiring structure 40 side warps convexly, that is, the upper surface of the uppermost second insulating layer 44 warps convexly. This warping distorts the second insulating layers 42 and 44. This distortion can cause cracks or breaks in the via wirings V1 and V2 in the second wiring structure 40, for example.

[0086] In this way, in the conventional semiconductor device 1A, the semiconductor chip 70 is mounted on the wiring board 10A in which the second insulating layers 42, 44, etc. are distorted. Thereafter, when the temperature returns to room temperature, the wiring board 10A attempts to return to its original state before the distortion, as shown in FIG. 14(b). This force of returning to its original state becomes internal stress, and cracks or breaks occur in, for example, the solder layer 72. This causes a problem of reduced connection reliability between the semiconductor chip 70 and the wiring board 10A.

[0087] 15(a), the coefficients of linear expansion are set to increase in the order of core substrate 20, second insulating layers 42, 44, first insulating layers 32, 34, 36, and third insulating layers 52, 54. For example, in wiring substrate 10, the coefficients of linear expansion of third insulating layers 52, 54, core substrate 20, first insulating layers 32, 34, 36, and second insulating layers 42, 44 are set to 20 ppm / °C, 7 ppm / °C, 20 ppm / °C, and 10 ppm / °C, respectively.

[0088] As described above, in the wiring board 10 of this embodiment, the linear expansion coefficients of the second insulating layers 42 and 44 are set lower than the linear expansion coefficients of the first insulating layers 32, 34, and 36 and higher than the linear expansion coefficient of the core substrate 20. This makes the linear expansion coefficients of the second insulating layers 42 and 44 closer to the linear expansion coefficient of the core substrate 20. Therefore, even if the wiring board 10 is exposed to a high-temperature environment of approximately 260°C when the semiconductor chip 70 is mounted, warping of the wiring board 10 can be effectively suppressed. In other words, the wiring board 10 of this embodiment can warp less than the conventional wiring board 10A when exposed to a high-temperature environment. This was also confirmed by a warping simulation described below.

[0089] In the wiring substrate 10, the amount of warping when exposed to a high-temperature environment can be reduced, and therefore the distortion of the second insulating layers 42, 44 can also be reduced. This can alleviate the stress applied to the via wirings V1, V2, etc. in the second wiring structure 40. Therefore, it is possible to suitably prevent cracks and breaks from occurring in the via wirings V1, V2, etc.

[0090] Thereafter, when the temperature returns to room temperature, the wiring substrate 10 attempts to return to its original state before distortion, as shown in FIG. 15(b). However, in the wiring substrate 10 of this embodiment, distortion in a high-temperature environment is small, and therefore dimensional fluctuations when the substrate is returned to room temperature are also small. This reduces the internal stress that occurs when the substrate returns to its original state before distortion. Therefore, cracks, breaks, etc., can be effectively prevented from occurring in the solder layer 72, etc., when the substrate is returned to room temperature. As a result, in the semiconductor device 1 of this embodiment, a decrease in the reliability of the connection between the semiconductor chip 70 and the wiring substrate 10 can be effectively prevented.

[0091] Next, a semiconductor device 1B of a comparative example will be described with reference to FIG. 16(a), the semiconductor device 1B of the comparative example includes a wiring board 10B. In the wiring board 10B of the comparative example, the linear expansion coefficients are set to increase in the order of the second insulating layers 42 and 44, the first insulating layers 32, 34, and 36, the third insulating layers 52 and 54, and the core substrate 20. For example, in the wiring board 10B, the linear expansion coefficients of the third insulating layers 52 and 54, the core substrate 20, the first insulating layers 32, 34, and 36, and the second insulating layers 42 and 44 are set to 20 ppm / °C, 25 ppm / °C, 20 ppm / °C, and 10 ppm / °C, respectively.

[0092] In the wiring board 10B of this comparative example, when exposed to a high-temperature environment of about 260°C during mounting of the semiconductor chip 70, the core substrate 20 is most likely to expand relative to the first insulating layers 32, 34, 36 and the second insulating layers 42, 44. At this time, the core substrate 20 is formed thicker than the first insulating layers 32, 34, 36 and the second insulating layers 42, 44. Therefore, the amount of thermal expansion of the wiring board 10B is dominated by the core substrate 20. Therefore, when the core substrate 20 expands, the entire wiring board 10B expands in response to the expansion of the core substrate 20. As a result, misalignment occurs between the pad P2 of the wiring board 10B and the connection terminal 71 of the semiconductor chip 70.

[0093] Thereafter, when the temperature returns to room temperature, as shown in FIG. 16(b), the wiring board 10B attempts to return to its original state before thermal expansion. At this time, the amount of thermal contraction in the wiring board 10B is dominated by the core substrate 20. Therefore, when the core substrate 20 shrinks, the entire wiring board 10B shrinks in response to the shrinkage of the core substrate 20. This thermal contraction causes internal stress to be applied to the solder layer 72, etc., which can cause cracks or breaks in the solder layer 72, etc. This causes a problem of reduced connection reliability between the semiconductor chip 70 and the wiring board 10B.

[0094] Thus, even if the linear expansion coefficient of the second insulating layers 42, 44 is set lower than the linear expansion coefficient of the first insulating layers 32, 34, 36, the problem of reduced connection reliability occurs if the linear expansion coefficient of the second insulating layers 42, 44 is lower than the linear expansion coefficient of the core substrate 20. Therefore, in order to improve the connection reliability with the semiconductor chip 70, it is important to set the linear expansion coefficient of the second insulating layers 42, 44 lower than the linear expansion coefficient of the first insulating layers 32, 34, 36 and higher than the linear expansion coefficient of the core substrate 20, as in the case of the wiring substrate 10.

[0095] (Warp simulation) A warpage simulation was performed on wiring board 10 shown in FIG. 1 and conventional wiring board 10A shown in FIG.

[0096] (Simulation conditions) The wiring board 10 of the example had a planar shape of a square measuring 55 mm × 55 mm. In the wiring board 10, the thickness of the core substrate 20 was 1.2 mm, the thickness of each of the first insulating layers 32, 34, and 36 was 30 μm, the thickness of each of the second insulating layers 42 and 44 was 10 μm, and the thickness of each of the third insulating layers 52 and 54 was 30 μm. In the wiring board 10, the linear expansion coefficient of the core substrate 20 was 7 ppm / °C, the linear expansion coefficient of the first insulating layers 32, 34, and 36 was 20 ppm / °C, and the linear expansion coefficient of the third insulating layers 52 and 54 was 20 ppm / °C. Warpage simulations were performed on the wiring board 10 when the linear expansion coefficients of the second insulating layers 42 and 44 were changed to 18 ppm / °C (Example 1), 12 ppm / °C (Example 2), and 8 ppm / °C (Example 3). Thus, the linear expansion coefficients of the second insulating layers 42, 44 in Examples 1, 2, and 3 are set higher than the linear expansion coefficient of the core substrate 20 and lower than the linear expansion coefficients of the first insulating layers 32, 34, 36 and the third insulating layers 52, 54.

[0097] The conventional wiring board 10A has the same structure as the wiring board 10 of the embodiment, except that the linear expansion coefficient of the second insulating layers 42, 44 is set to 37 ppm / °C. As described above, the linear expansion coefficient of the second insulating layers 42, 44 in the conventional wiring board 10A is set to be higher than the linear expansion coefficient of the core substrate 20, and higher than the linear expansion coefficients of the first insulating layers 32, 34, 36 and the third insulating layers 52, 54. A warpage simulation was performed on this wiring board 10A under the same conditions as in the embodiment.

[0098] (Simulation results) The results of the warpage simulation are shown in Fig. 17. As shown in Fig. 17, it was confirmed that the wiring board 10 of the example, that is, Examples 1, 2, and 3, had a smaller amount of warpage than the wiring board 10A of the conventional example. Furthermore, as is clear from the results of Examples 1, 2, and 3, it was confirmed that the amount of warpage was reduced as the linear expansion coefficient of the second insulating layers 42 and 44 decreased.

[0099] From the above results, it is clear that the amount of warping of wiring board 10 can be reduced by setting the linear expansion coefficient of second insulating layers 42, 44 higher than that of core substrate 20 and lower than that of first insulating layers 32, 34, 36 and third insulating layers 52, 54. Furthermore, it is clear that the amount of warping of wiring board 10 can be effectively reduced by bringing the linear expansion coefficient of second insulating layers 42, 44 closer to that of core substrate 20.

[0100] (Effects of this embodiment) Next, the effects of this embodiment will be described. (1) The wiring board 10 includes a core substrate 20, a first wiring structure 30 formed on the upper surface of the core substrate 20, and a second wiring structure 40 formed on the upper surface of the first wiring structure 30. The first wiring structure 30 has a structure in which a plurality of first wiring layers 31, 33, and 35 and a plurality of first insulating layers 32, 34, and 36 are stacked. The second wiring structure 40 has a structure in which a plurality of second wiring layers 41, 43, and 45 and a plurality of second insulating layers 42 and 44 are stacked. The wiring density of the second wiring structure 40 is higher than that of the first wiring structure 30. The linear expansion coefficients of the second insulating layers 42 and 44 are higher than that of the core substrate 20 and lower than that of the first insulating layers 32, 34, and 36.

[0101] This configuration allows the linear expansion coefficient of the second insulating layers 42, 44 to be closer to that of the core substrate 20 than that of the first insulating layers 32, 34, 36. This effectively reduces the amount of warping that occurs in the wiring substrate 10 when exposed to a high-temperature environment. As a result, stresses applied to the second wiring layers 41, 43, 45 and via wirings V1, V2, etc. of the second wiring structure 40 can be alleviated, thereby effectively preventing cracks and breakage in the second wiring layers 41, 43, 45 and via wirings V1, V2, etc. Furthermore, stresses applied to the solder layer 72, etc. can be alleviated when the temperature is returned to room temperature after mounting the semiconductor chip 70, thereby effectively preventing cracks and breakage in the solder layer 72, etc. These factors prevent a decrease in the reliability of the connection between the wiring substrate 10 and the semiconductor chip 70. In other words, the wiring substrate 10 can improve the reliability of the connection between the wiring substrate 10 and the semiconductor chip 70 compared to the conventional wiring substrate 10A.

[0102] (2) The wiring board 10 further includes a third wiring structure 50 formed on the lower surface of the core substrate 20. The third wiring structure 50 has a structure in which a plurality of third wiring layers 51, 53, 55 and a plurality of third insulating layers 52, 54 are stacked. The wiring density of the second wiring structure 40 is higher than that of the third wiring structure 50. The linear expansion coefficients of the second insulating layers 42, 44 are lower than that of the third insulating layers 52, 54.

[0103] According to this configuration, the linear expansion coefficient of the second insulating layers 42, 44 can be made closer to the linear expansion coefficient of the core substrate 20 compared to the linear expansion coefficient of the third insulating layers 52, 54. This makes it possible to suitably reduce the amount of warping that occurs in the wiring substrate 10 when exposed to a high-temperature environment. As a result, it is possible to suitably prevent cracks and breaks from occurring in the second wiring layers 41, 43, 45 and via wirings V1, V2, etc. of the second wiring structure 40, and also to suitably prevent cracks and breaks from occurring in the solder layer 72, etc. This allows the wiring substrate 10 to improve the connection reliability with the semiconductor chip 70.

[0104] (3) The first insulating layers 32, 34, 36 contain a first filler F1. The second insulating layers 42, 44 contain a second filler F2. The average particle size of the second filler F2 is smaller than that of the first filler F1. This allows fine through holes 42X, 44X to be suitably formed in the second insulating layers 42, 44 containing the second filler F2 with a small average particle size. This allows fine wiring to be suitably formed in the second wiring structure 40 including the second insulating layers 42, 44.

[0105] (4) The content of the second filler F2 is higher than the content of the first filler F1, which allows the linear expansion coefficient of the second insulating layers 42, 44 containing the second filler F2 to be preferably adjusted to be lower than the linear expansion coefficient of the first insulating layers 32, 34, 36 containing the first filler F1.

[0106] (5) The second insulating layers 42, 44 are insulating layers whose main component is a non-photosensitive resin. This makes it easier to adjust the linear expansion coefficient of the second insulating layers 42, 44 to be lower than when the second insulating layers 42, 44 are insulating layers whose main component is a photosensitive resin.

[0107] (6) However, if the linear expansion coefficient of the core substrate 20 is set to be equal to or less than the linear expansion coefficient of the semiconductor chip 70, the difference in the linear expansion coefficient between the core substrate 20 and the first insulating layers 32, 34, 36 and the third insulating layers 52, 54 becomes large. In this case, when exposed to a high-temperature environment, the first insulating layers 32, 34, 36 and the third insulating layers 52, 54 expand, but the core substrate 20 does not expand. This causes internal stress in the core substrate 20, which can cause cracks, breakage, or the like in the core substrate 20.

[0108] In contrast, in the semiconductor device 1 of this embodiment, the linear expansion coefficient of the core substrate 20 is set higher than the linear expansion coefficient of the semiconductor chip 70. With this configuration, the difference in the linear expansion coefficient between the core substrate 20 and the first insulating layers 32, 34, 36 and the third insulating layers 52, 54 can be made smaller than when the linear expansion coefficient of the core substrate 20 is set equal to or lower than the linear expansion coefficient of the semiconductor chip 70. This makes it possible to alleviate internal stress generated in the core substrate 20, and to suitably prevent cracks, breakage, and the like from occurring in the core substrate 20.

[0109] (Example of change) The above embodiment can be modified as follows: The above embodiment and the following modifications can be combined with each other within the scope of technical compatibility.

[0110] In the above embodiment, the via wiring that penetrates the first insulating layer 36, the top layer of the first wiring structure 30, in the thickness direction and the second wiring layer 41, the bottom layer of the second wiring structure 40, are formed continuously and integrally, but this is not limited to this.

[0111] For example, as shown in FIG. 18 , via wiring 37 penetrating the first insulating layer 36, which is the uppermost layer of the first wiring structure 30, in the thickness direction and the second wiring layer 41, which is the lowermost layer of the second wiring structure 40, may be formed as separate members. The via wiring 37 is, for example, filled in a through hole 36X of the first insulating layer 36. The upper surface of the via wiring 37 is exposed from the upper surface of the first insulating layer 36. The upper surface of the via wiring 37 is, for example, flush with the upper surface of the first insulating layer 36. For example, the upper surfaces of the via wiring 37 and the first insulating layer 36 are polished surfaces. In the first wiring structure 30 of this modified example, the via wiring 37 is the uppermost first wiring layer. The second wiring layer 41 of this modified example is stacked on the upper surfaces of the via wiring 37 and the first insulating layer 36.

[0112] The number of second wiring layers and second insulating layers in the second wiring structure 40 of the above embodiment, the layout of the wiring, and the like can be modified and changed in various ways. In the above embodiment, the second insulating layers 42, 44 are insulating layers whose main component is a non-photosensitive resin. However, the present invention is not limited to this, and the second insulating layers 42, 44 may be insulating layers whose main component is a photosensitive resin.

[0113] The number of first wiring layers and first insulating layers, wiring layout, etc. in the first wiring structure 30 of the above embodiment can be modified or changed in various ways. For example, the first wiring structure 30 may be modified to a structure having one first wiring layer and one first insulating layer.

[0114] The number of third wiring layers and third insulating layers and the layout of the wiring in the third wiring structure 50 of the above embodiment can be modified or changed in various ways. For example, the third wiring structure 50 may be modified to a structure having one third wiring layer and one third insulating layer.

[0115] In the above embodiment, the solder resist layers 60 and 61 are given as an example of the protective insulating layer that is the outermost layer of the wiring board 10, but the protective insulating layer can be formed from various types of photosensitive insulating resins.

[0116] The solder resist layers 60 and 61 in the above embodiment may be omitted. In the semiconductor device 1 of the above embodiment, the semiconductor chip 70 is mounted on the wiring substrate 10. However, the present invention is not limited to this, and instead of the semiconductor chip 70, electronic components other than semiconductor chips, such as chip components such as chip capacitors, chip resistors, and chip inductors, or crystal resonators, may be mounted on the wiring substrate 10.

[0117] Furthermore, the mounting method (for example, flip-chip mounting, wire bonding mounting, solder mounting, or a combination thereof) of electronic components such as the semiconductor chip 70, chip components, and crystal oscillators can be modified or changed in various ways.

[0118] The through electrodes 21 in the above embodiment may be changed to through electrodes in which the through holes 20X are completely filled with a plated metal layer (for example, a Cu layer), for example. In the above embodiment, the manufacturing method is embodied as a single-cavity manufacturing method, but the manufacturing method may be embodied as a multi-cavity manufacturing method. [Explanation of symbols]

[0119] 1. Semiconductor device 10. Wiring board 20 Core Board 30 1st wiring structure 31,33,35 1st wiring layer 32, 34, 36 First insulating layer 37 Via wiring (topmost first wiring layer) 40 Second wiring structure 41,43,45 2nd wiring layer 42, 44 Second insulating layer 50 Third wiring structure 51,53,55 3rd wiring layer 52,54 Third insulating layer 60 Solder resist layer 70 Semiconductor Chips F1 First Filler F2 Second filler V1, V2 via wiring

Claims

1. A core substrate; a first wiring structure formed on an upper surface of the core substrate; a second wiring structure formed on an upper surface of the first wiring structure, the first wiring structure includes one or more first wiring layers and one or more first insulating layers; the second wiring structure has a structure in which a plurality of second wiring layers and a plurality of second insulating layers are stacked, a wiring density of the second wiring structure is higher than a wiring density of the first wiring structure; A wiring board, wherein the linear expansion coefficient of the second insulating layer is higher than the linear expansion coefficient of the core substrate and lower than the linear expansion coefficient of the first insulating layer.

2. a third wiring structure formed on the lower surface of the core substrate; the third wiring structure includes one or more third wiring layers and one or more third insulating layers; a wiring density of the second wiring structure is higher than a wiring density of the third wiring structure; The wiring board according to claim 1 , wherein the second insulating layer has a lower linear expansion coefficient than the third insulating layer.

3. the first insulating layer contains a first filler; the second insulating layer contains a second filler; The wiring board according to claim 1 , wherein the second filler has an average particle size smaller than the average particle size of the first filler.

4. The wiring board according to claim 3 , wherein the content of the second filler is higher than the content of the first filler.

5. the first insulating layer is an insulating layer containing a non-photosensitive resin as a main component, 2. The wiring board according to claim 1, wherein the second insulating layer is an insulating layer containing a non-photosensitive resin as a main component.

6. The thickness of the second insulating layer is smaller than the thickness of the first insulating layer, The wiring board according to claim 1 , wherein the thickness of the first insulating layer is thinner than the thickness of the core substrate.

7. The wiring board according to claim 1 , further comprising a solder resist layer laminated on an upper surface of the second wiring structure.

8. the first wiring layer that is the uppermost layer of the first wiring structure is a via wiring that penetrates the first insulating layer that is the uppermost layer of the first wiring structure in a thickness direction; The wiring board according to claim 1 , wherein an upper surface of the via wiring is flush with an upper surface of the first insulating layer that is the uppermost layer of the first wiring structure.

9. The wiring board according to any one of claims 1 to 8, a semiconductor chip mounted on the second wiring layer, which is the uppermost layer of the second wiring structure; The semiconductor device, wherein the core substrate has a higher linear expansion coefficient than the semiconductor chip.

10. preparing a core substrate; forming a first wiring structure having one or more first wiring layers and one or more first insulating layers on the upper surface of the core substrate; forming a second wiring structure having a structure in which a plurality of second wiring layers and a plurality of second insulating layers are stacked on an upper surface of the first wiring structure; a wiring density of the second wiring structure is higher than a wiring density of the first wiring structure; A method for manufacturing a wiring substrate, wherein the second insulating layer has a linear expansion coefficient higher than that of the core substrate and lower than that of the first insulating layer.

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