Semiconductor device

Abstract

To provide a semiconductor device capable of increasing the degree of integration.SOLUTION: The semiconductor device 1 includes a semiconductor substrate 11, a buried semiconductor layer 13, an epitaxial semiconductor layer 14, a device 50, and an isolation structure 20. The isolation structure 20 includes a trench 21 extending from the 14a of the epitaxial layer 14 to a position penetrating the buried layer 13, an insulating film 22 covering the side 21b of the trench 21, and a conductive material 23 provided in the trench 21. The trench 21 has a first trench part 25 and a second trench part 26 arranged in the depth direction of the trench 21. At least one of the first trench part 25 and the second trench part 26 has a straight shape in which the width W is constant, or an inverted tapered shape in which the width increases along the depth direction. A gradient angle θ of the side surface side 21b with respect to the depth direction changes between the first trench part 25 and the second trench part 26.SELECTED DRAWING: Figure 3

Description

[Technical Field]

[0001] The present disclosure relates to semiconductor devices. [Background technology]

[0002] Patent Document 1 discloses a semiconductor device including a deep trench isolation (DTI) structure. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Patent Publication No. 2021-2623

[0004] [overview] The present disclosure provides a semiconductor device that can increase the degree of integration.

[0005] The semiconductor device disclosed herein includes a semiconductor substrate, a buried semiconductor layer provided on the semiconductor substrate, a first epitaxial semiconductor layer provided on the buried semiconductor layer, a device provided in the first epitaxial semiconductor layer, and an isolation structure surrounding the device. The isolation structure includes a trench extending from the surface of the first epitaxial semiconductor layer to a position penetrating the buried semiconductor layer, an insulating film covering the side surfaces of the trench, and a conductive region provided in the trench so as to be surrounded by the insulating film. The trench has a first trench portion and a second trench portion aligned in the depth direction of the trench. At least one of the first trench portion and the second trench portion has a straight shape with a constant width or an inverted tapered shape whose width increases along the depth direction. The gradient angle of the side surface with respect to the depth direction varies between the first trench portion and the second trench portion. [Brief explanation of the drawings]

[0006] [Figure 1] FIG. 1 is a plan view of a semiconductor device according to an embodiment. [Figure 2] FIG. 2 is a diagram showing a cross-sectional configuration of a device region in the semiconductor device of FIG. [Figure 3] FIG. 3 is an enlarged view showing the cross-sectional configuration of the isolation structure of FIG. [Figure 4] FIG. 4 is a diagram for explaining the gradient angle of the side surface of the trench. [Figure 5] FIG. 5 is a diagram illustrating a cross-sectional configuration of a device according to an example. [Figure 6] 6(A) to 6(H) are cross-sectional views for explaining a method for manufacturing a semiconductor device. [Figure 7] FIG. 7 is an enlarged view showing a cross-sectional configuration of an isolation structure according to a comparative example. [Figure 8] FIG. 8 is an enlarged view showing a cross-sectional configuration of an isolation structure according to a first modified example. [Figure 9] FIG. 9 is an enlarged view showing a cross-sectional configuration of an isolation structure according to a second modification. [Figure 10] FIG. 10 is an enlarged view showing a cross-sectional configuration of an isolation structure according to a third modified example.

[0007] [Detailed explanation] Various exemplary embodiments will be described in detail below with reference to the drawings. Note that the same or equivalent parts in the drawings will be denoted by the same reference numerals, and redundant explanations will be omitted.

[0008] (Semiconductor Devices) FIG. 1 is a plan view of a semiconductor device according to an embodiment. The semiconductor device 1 according to the embodiment is a semiconductor chip having a rectangular parallelepiped shape. The thickness direction of the semiconductor device 1 is defined as the Z-axis direction, the direction perpendicular to the Z-axis is defined as the X-axis direction, and the direction perpendicular to both the Z-axis and the X-axis is defined as the Y-axis direction. The semiconductor device 1 has a first main surface 3 and a second main surface 4 (see FIG. 2) that face opposite each other in the Z-axis direction. The direction from the first main surface 3 toward the second main surface 4 is defined as the positive direction of the Z-axis, and the direction from the second main surface 4 toward the first main surface 3 is defined as the negative direction of the Z-axis. The semiconductor device 1 has a first side surface 5A, a second side surface 5B, a third side surface 5C, and a fourth side surface 5D that connect the first main surface 3 and the second main surface 4.

[0009] The first main surface 3 and the second main surface 4 are each perpendicular to the Z axis. The planar shape (shape in plan view) of the first main surface 3 when viewed from the normal direction (Z axis direction) of the first main surface 3 is a rectangle (quadrilateral). The shape of the second main surface 4 is also a rectangle (quadrilateral). The first side surface 5A and the second side surface 5B, which constitute two opposing sides of the rectangle in plan view, each extend along the X axis direction. The third side surface 5C and the fourth side surface 5D, which constitute the other two opposing sides of the rectangle in plan view, each extend along the Y axis direction. These adjacent side surfaces are perpendicular to each other in plan view, but can also intersect at an angle other than perpendicular.

[0010] The semiconductor device 1 includes a plurality of device regions 10 provided on the first main surface 3. A gap is provided between each device region 10 and each side surface (first side surface 5A to fourth side surface 5D) of the semiconductor device 1. These device regions 10 are divisions used for convenience of explanation, and the actual device regions 10 do not have physical boundaries.

[0011] Various devices are formed in each device region 10. In this embodiment, at least one device region 10 includes a device 50 and an isolation structure 20. The isolation structure 20 is annular in plan view and surrounds the device 50.

[0012] The semiconductor material constituting the semiconductor device 1 of this embodiment is silicon (Si). Compound semiconductors can also be used as the semiconductor material constituting the semiconductor device 1. Compound semiconductors include III-V compound semiconductors, IV-IV compound semiconductors, and alloy semiconductors using these semiconductors. Ga-containing semiconductors such as GaAs and GaN can be used as III-V compound semiconductors. Silicon-containing semiconductors such as silicon carbide (SiC) and silicon germanium (SiGe) can be used as IV-IV compound semiconductors.

[0013] Figure 2 is a diagram showing a cross-sectional configuration of a device region in the semiconductor device of Figure 1. This figure shows a cross-sectional configuration of a device region 10 taken along the arrow line II-II in Figure 1. The semiconductor device 1 includes a semiconductor substrate 11, an epitaxial semiconductor layer 12 (second epitaxial semiconductor layer), a buried semiconductor layer 13, an epitaxial semiconductor layer 14 (first epitaxial semiconductor layer), and an insulating region 15.

[0014] The semiconductor substrate 11 has the second main surface 4 of the semiconductor device 1. The epitaxial semiconductor layer 12 is provided on the main surface of the semiconductor substrate 11 opposite to the second main surface 4. The epitaxial semiconductor layer 12 is provided between the semiconductor substrate 11 and the buried semiconductor layer 13. The buried semiconductor layer 13 is provided on the epitaxial semiconductor layer 12. The buried semiconductor layer 13 is provided on the semiconductor substrate 11 with the epitaxial semiconductor layer 12 interposed therebetween. The epitaxial semiconductor layer 14 is formed on the buried semiconductor layer 13.

[0015] The semiconductor substrate 11 and the epitaxial semiconductor layer 12 are made of silicon and have P-type conductivity. The buried semiconductor layer 13 and the epitaxial semiconductor layer 14 are made of silicon and have N-type conductivity. These conductivity types are interchangeable. An exemplary P-type impurity (trivalent element) is boron (B). An exemplary N-type impurity (pentavalent element) is phosphorus (P) or arsenic (As). Although the exemplary semiconductor material is silicon, other semiconductor materials may also be used.

[0016] The impurity concentration of the semiconductor substrate 11 is 1×10 17 cm -3 More than 1×10 20 cm -3 The thickness of the semiconductor substrate 11 may be 50 μm or more and 500 μm or less. The material of the semiconductor substrate 11 may be an insulator such as Al2O3, depending on the type of device. The impurity concentration of the epitaxial semiconductor layer 12 is lower than the impurity concentration of the semiconductor substrate 11, and is 1×10 14 cm -3 More than 1×10 17 cm -3 The thickness of the epitaxial semiconductor layer 12 may be 1 μm or more and 20 μm or less. The impurity concentration of the buried semiconductor layer 13 may be 1×10 16 cm -3 More than 1×10 21 cm -3 The thickness of the buried semiconductor layer 13 may be 0.1 μm or more and 5 μm or less. The impurity concentration of the epitaxial semiconductor layer 14 is lower than the impurity concentration of the buried semiconductor layer 13, and may be 1×10 14 cm -3 More than 1×10 17 cm -3 The thickness of the epitaxial semiconductor layer 14 may be 0.5 μm or more and 20 μm or less.

[0017] The insulating region 15 is formed on the surface 14a of the epitaxial semiconductor layer 14. The portion where the insulating region 15 is formed may constitute shallow trench isolation (STI). The material of the insulating region 15 is, for example, an insulator such as silicon dioxide (SiO2), but may also be an insulator such as silicon nitride (Si3N4). The insulating region 15 may be a field oxide film. The insulating region 15 constitutes a part of the first main surface 3 of the semiconductor device 1.

[0018] The isolation structure 20 is a deep trench isolation structure (DTI). The isolation structure 20 includes a trench 21, an insulating film 22, a conductive material 23 (conductive region), and a sinker region 24. In this embodiment, there is one isolation structure 20, but there may be more than one. DTI has traditionally been adopted in high-performance, high-reliability BCD (Bipolar CMOS DMOS) devices to absorb leakage current from the power section and suppress potential fluctuations within the silicon substrate.

[0019] FIG. 3 is an enlarged view of the cross-sectional configuration of the isolation structure of FIG. 2. As shown in FIG. 3, the trench 21 extends from the surface 14a of the epitaxial semiconductor layer 14 to a position where it penetrates the buried semiconductor layer 13. The trench 21 extends from the surface 14a to the semiconductor substrate 11. The depth direction of the trench 21 is the positive direction of the Z axis. The depth direction of the trench 21 is also the axial direction of the trench 21. Hereinafter, the depth direction of the trench 21 will also be simply referred to as the "depth direction." A tip 21a of the trench 21 in the depth direction is located in the semiconductor substrate 11. The trench 21 has a side surface 21b extending in the depth direction from the surface 14a to the tip 21a. The side surface 21b is the inner surface of the trench 21 facing inward.

[0020] The trench 21 has a first trench portion 25 and a second trench portion 26 that are aligned in the depth direction. The first trench portion 25 and the second trench portion 26 are aligned continuously in the depth direction. That is, the tip 25a of the first trench portion 25 is directly connected to the second trench portion 26. In FIG. 3, the boundary between the first trench portion 25 and the second trench portion 26 is indicated by a dashed line. The first trench portion 25 is disposed closer to the first main surface 3 than the second trench portion 26. The second trench portion 26 is disposed closer to the second main surface 4 than the first trench portion 25.

[0021] The first trench portion 25 extends from the surface 14a of the epitaxial semiconductor layer 14 to a position where it penetrates the buried semiconductor layer 13. A tip 25a in the depth direction of the first trench portion 25 is located in the epitaxial semiconductor layer 12. A tip 21a in the depth direction of the second trench portion 26 forms a tip 21a in the depth direction of the trench 21.

[0022] At least one of the first trench portion 25 and the second trench portion 26 has a straight shape with a constant width W, or an inversely tapered shape in which the width W increases along the depth direction. The first trench portion 25 or the second trench portion 26 may have a forwardly tapered shape in which the width W decreases along the depth direction. In the illustrated example, the first trench portion 25 has a forwardly tapered shape, and the second trench portion 26 has an inversely tapered shape.

[0023] 4 is a diagram illustrating the gradient angle of the side surface of a trench. The gradient angle θ of the side surface 21b of the trench 21 relative to the depth direction (Z-axis direction) is set to 0° for a straight shape, a positive value (0°<θ<90°) for a forward tapered shape, and a negative value (-90°<θ<0°) for a reverse tapered shape. In the illustrated example, the gradient angle θ in the first trench portion 25, that is, the first gradient angle θ1, is a positive value, and the gradient angle θ in the second trench portion 26, that is, the second gradient angle θ2, is a negative value. The gradient angle θ is ½ of the so-called taper angle of the trench 21.

[0024] The gradient angle θ changes between the first trench portion 25 and the second trench portion 26. That is, the side surface 21b is bent between the first trench portion 25 and the second trench portion 26. In this case, the first gradient angle θ1 and the second gradient angle θ2 are different from each other. The first gradient angle θ1 and the second gradient angle θ2 may be the same in absolute value. Even in this case, if one of the first trench portion 25 and the second trench portion 26 has a forward tapered shape and the other has a reverse tapered shape, it can be said that the first gradient angle θ1 and the second gradient angle θ2 are different from each other. It can also be said that the gradient angle θ changes between the first trench portion 25 and the second trench portion 26.

[0025] The first width W1, which is the width W of the trench 21 at the surface 14a of the epitaxial semiconductor layer 14, is the so-called top dimension of the trench 21. It is the maximum value of the width W at the first trench portion 25. The second width W2, which is the width W of the trench 21 at the tip 21a, is the so-called bottom dimension of the trench 21. In this embodiment, the maximum value of the width W is the first width W1, but it may also be the second width W2. The width W has a minimum value at the boundary between the first trench portion 25 and the second trench portion 26.

[0026] The insulating film 22 covers the side surface 21b of the trench 21. The insulating film 22 is provided inside the trench 21. The material of the insulating film 22 is, for example, an insulator such as silicon dioxide (SiO2), but may also be an insulator such as silicon nitride (Si3N4). The thickness of the insulating film 22 may be 0.1 μm or more and 1.0 μm or less.

[0027] The conductive material 23 is provided in the trench 21 so as to be surrounded by the insulating film 22. The conductive material 23 fills the inside of the insulating film 22. The conductive material 23 penetrates the insulating film 22 provided on the bottom surface of the trench 21 in the depth direction. The conductive material 23 contacts the semiconductor substrate 11 at the tip 21a of the trench 21. The material of the conductive material 23 is, for example, polysilicon doped with an impurity. A P-type additive such as boron (B) can be used as the impurity to be doped into the polysilicon. The conductive material 23 may be a metal such as copper (Cu) or aluminum (Al), a silicide, or an alloy. A bias potential application terminal E is electrically connected to the conductive material 23. The bias potential application terminal E may be connected to a ground potential.

[0028] The sinker region 24 is provided along the side surface 21b of the trench 21. The sinker region 24 has N-type conductivity. The sinker region 24 is provided outside the insulating film 22 so as to be adjacent to the insulating film 22. The impurity concentration of the sinker region 24 is higher than the impurity concentration of the epitaxial semiconductor layer 14. The impurity concentration of the sinker region 24 is 1×10 16 cm -3 More than 1×1020 cm -3 The sinker region 24 extends from the surface 14a of the epitaxial semiconductor layer 14 to a position where it penetrates the buried semiconductor layer 13, and applies a potential to the buried semiconductor layer 13. The tip 24a of the sinker region 24 in the depth direction is located in the epitaxial semiconductor layer 12. The tip 24a may also be located in the semiconductor substrate 11.

[0029] 5 is a diagram illustrating a cross-sectional configuration of a device according to an example. The device 50 may include at least one of a semiconductor switching device, a semiconductor rectifying device, and a passive device. The semiconductor switching device may include at least one of a JFET (Junction Field Effect Transistor), a FET (FET: Field-Effect Transistor), and a BJT (Bipolar Junction Transistor). The FET may be a MISFET (Metal Insulator Semiconductor Field Effect Transistor). The BJT may be an IGBT (Insulated Gate Bipolar Junction Transistor).

[0030] A MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor) can be used as the MISFET. The device 50 can also be a power transistor. A DMOS-FET (Double-Diffused MOSFET) can be used as the power MOSFET, and types such as a vertical (VDMOS) and a lateral (LDMOS) can be used. MISFETs with drain-source voltages of high voltage (HV: for example, 100 V or more and 1000 V or less), medium voltage (MV: for example, 30 V or more and 100 V or less), and low voltage (LV: for example, 1 V or more and 30 V or less) are known. Alternatively, an optical device such as a light-emitting element or a light-receiving element can be used as the device 50.

[0031] The device 50 in the illustrated example is a DMOS-FET. The device 50 is provided in the epitaxial semiconductor layer 14. The device 50 includes a semiconductor well region 51, a source region 54, a first drain region 521, a first insulating film 551, a first gate electrode 561, a second drain region 522, a second insulating film 552, a second gate electrode 562, a buried semiconductor layer 57, and a body region 53. The semiconductor well region 51, the source region 54, the first drain region 521, and the second drain region 522 are made of silicon and have N-type conductivity. The buried semiconductor layer 57 and the body region 53 are made of silicon and have P-type conductivity.

[0032] The semiconductor well region 51 is provided in the epitaxial semiconductor layer 14. Carriers constituting the channel of the FET can travel in the semiconductor well region 51. The semiconductor well region 51 includes a carrier drift region. The source region 54 is formed on the surface of the semiconductor well region 51. The first drain region 521 is formed on the surface of the semiconductor well region 51. The first drain region 521 is spaced apart from the source region 54 along the X-axis direction and is positioned at a distance from the source region 54.

[0033] The first insulating film 551 is formed on the semiconductor well region 51 between the source region 54 and the first drain region 521. The first insulating film 551 is a gate insulating film. The material of the first insulating film 551 is, for example, silicon dioxide (SiO2).

[0034] The first gate electrode 561 is formed on the first insulating film 551. The first gate electrode 561 is disposed between the source region 54 and the first drain region 521 with the first insulating film 551 interposed therebetween. The material of the first gate electrode 561 is, for example, polysilicon doped with impurities. The material of the first gate electrode 561 may be a metal such as copper (Cu) or aluminum (Al), an alloy containing one or more types of metal, or a compound (silicide) of metal and silicon.

[0035] The second drain region 522 is formed on the surface of the semiconductor well region 51. The second drain region 522 is spaced apart from the source region 54 along the X-axis direction and is located on the opposite side of the first drain region 521 with a gap therebetween.

[0036] The second insulating film 552 is formed on the semiconductor well region 51 between the source region 54 and the second drain region 522. The second insulating film 552 is a gate insulating film. In this embodiment, the second insulating film 552 is made of silicon dioxide (SiO2).

[0037] The second gate electrode 562 is formed on the second insulating film 552. The second gate electrode 562 is disposed between the source region 54 and the second drain region 522 with the second insulating film 552 interposed therebetween. The material of the second gate electrode 562 is, for example, polysilicon doped with impurities. The material of the second gate electrode 562 may be a metal such as copper (Cu) or aluminum (Al), an alloy containing one or more types of metal, or a compound (silicide) of metal and silicon. The first gate electrode 561 and the second gate electrode 562 may be physically and electrically connected at their ends in the Y-axis direction.

[0038] The buried semiconductor layer 57 is disposed in a region directly below the semiconductor well region 51, is in contact with the semiconductor well region 51, and is connected to the body region 53. The buried semiconductor layer 57 extends along the XY plane and is electrically connected to the body region 53. This makes it easier for the electric field strength in the semiconductor well region 51 to be distributed evenly.

[0039] More specifically, when a ground potential is applied to the source region 54 and a high voltage of, for example, +100 V is applied to the first drain region 521 and the second drain region 522, this high voltage is applied to the semiconductor well region 51 connected to the drain region. The buried semiconductor layer 57 is connected to the body region 53, which is connected to the ground potential. Therefore, an equipotential surface parallel to the surface of the buried semiconductor layer 57 is easily formed in the semiconductor well region 51. This structure suppresses the concentration of electric field strength at a specific location. Therefore, this structure further improves the breakdown voltage.

[0040] Electrons in the source region 54 are attracted to the positive potential of the drain region, but can move smoothly because the electric field distribution in the semiconductor well region 51 is not locally concentrated. The device 50 may also have a structure that does not include the buried semiconductor layer 57. In this case, the body region 53 does not need to penetrate the semiconductor well region 51.

[0041] The body region 53 has a source region 54 therein. The body region 53 extends from the surface position of the semiconductor well region 51 toward the depth thereof, reaching the inside of the buried semiconductor layer 57. The N-type semiconductor well region 51 and the P-type body region 53 are joined. The width of the body region 53 in the X-axis direction is wider than the width of the source region 54 in the X-axis direction. The body region 53 is interposed between the source region 54 and the semiconductor well region 51. The interposed region of the body region 53 is located directly below the gate electrode, and an N-type channel is formed in this region.

[0042] The insulating region 15 includes a first outer insulating region 151, a first inner insulating region 152, a second inner insulating region 153, and a second outer insulating region 154, which are arranged between the trenches 21 along the X-axis direction. The first outer insulating region 151 and the first inner insulating region 152 are spaced apart, and a first drain region 521 is formed therebetween. The second outer insulating region 154 and the second inner insulating region 153 are spaced apart, and a second drain region 522 is formed therebetween. The first inner insulating region 152 and the second inner insulating region 153 are spaced apart, and a body region 53 and a source region 54 are formed therebetween.

[0043] The impurity concentration of the semiconductor well region 51 is higher than the impurity concentration of the epitaxial semiconductor layer 14, and is 1×10 16 / cm 3 More than 1×10 18 / cm 3 The impurity concentration of the body region 53 is higher than the impurity concentration of the epitaxial semiconductor layer 14 and may be 1×10 16 / cm 3 More than 1×10 18 / cm 3 The impurity concentration of the buried semiconductor layer 57 is higher than the impurity concentration of the epitaxial semiconductor layer 14, and may be 1×10 16 / cm 3 More than 1×10 21 / cm 3 The impurity concentration in the drain region, source region, and contact region constituting the device 50 is higher than the impurity concentration in the well region, and may be 1×10 15 / cm 3 5x10 or more 19 / cm 3 It may be the following:

[0044] If device 50 is a P-channel FET, the N-type and P-type regions are swapped. The impurities added to the conductive material in the trench can be P-type, and it is also possible to add P-type impurities to a semiconductor region deeper than the bottom of the trench. The P-type impurity concentration added to the conductive material in the trench is 1×10 21 / cm 3 More than 1×10 22 / cm 3 It can also be the following:

[0045] (Method of manufacturing a semiconductor device) A description will now be given of a method for manufacturing the above-mentioned semiconductor device 1. Figures 6(A) to 6(H) are cross-sectional views for explaining the method for manufacturing the semiconductor device, and mainly show the manufacturing steps of the isolation structure.

[0046] First, as shown in FIG. 6(A), a first insulating film 301, a second insulating film 302, and a third insulating film 303 are stacked on a silicon substrate. The silicon substrate is formed by stacking a semiconductor substrate 11 (see FIG. 3), an epitaxial semiconductor layer 12 (see FIG. 3), a buried semiconductor layer 13, and an epitaxial semiconductor layer 14 (see FIG. 3) in this order. The material of the first insulating film 301 is silicon dioxide (SiO2). The material of the second insulating film 302 is silicon nitride (Si3N4). The material of the third insulating film 303 is silicon dioxide (SiO2).

[0047] When silicon dioxide is formed on the surface of an exposed silicon substrate, as in the first insulating film 301, thermal oxidation of silicon can be used. When silicon nitride is formed, as in the second insulating film 302, low-pressure CVD (chemical vapor deposition) for silicon nitride formation can be used. An example of a source gas for the CVD method for silicon nitride formation is a mixed gas of dichlorosilane gas (SiH2Cl2), ammonia gas (NH3), and nitrogen gas (N2). When a relatively thick silicon dioxide is formed, as in the third insulating film 303, the CVD method can be used. An example of a CVD method for silicon dioxide formation is a formation method using TEOS (Si(OC2H5)4).

[0048] Next, a first resist material 304 is formed on the third insulating film 303. The first resist material 304 is patterned to form a first opening 305.

[0049] As shown in FIG. 6(B), using the patterned first resist material 304 (see FIG. 6(A)) as a mask, the third insulating film 303, the second insulating film 302, and the first insulating film 301 are sequentially etched to pattern them into the same shape as the mask opening. Anisotropic dry etching for insulating films can be used as the etching method. A stack of the patterned third insulating film 303, the second insulating film 302, and the first insulating film 301 is used as a hard mask. When anisotropic dry etching for insulating films is performed, a fluorocarbon-based etching gas is exemplified. After etching, the first resist material 304 is removed. If the first resist material 304 is made of resin, it can be removed using an organic solvent.

[0050] 6(C), the front surface side of the silicon substrate is etched through the opening in the hard mask including the third insulating film 303 to form a front surface side recess 306. The front surface side recess 306 corresponds to the forward tapered first trench portion 25 (see FIG. 3) and is formed so as to penetrate the embedded semiconductor layer 13. As the etching method, wet etching for silicon can be used.

[0051] Examples of etching solutions used in wet etching of silicon include acidic etching solutions such as hydrofluoric acid and nitric acid, and alkaline etching solutions such as potassium hydroxide (KOH) and ammonia. When using these wet etching solutions, isotropic etching is performed on the underside of the hard mask. It is also possible to use wet etching at the initial stage of etching, followed by dry etching. Known dry etching methods include anisotropic etching such as reactive ion etching (RIE) and isotropic dry etching using activated species. Therefore, it is possible to use only isotropic dry etching to form the front-side recess 306. By changing the control parameters during etching (temperature, time, type of etching solution or etching gas, etc.), etching of a desired shape can be performed. An example of an anisotropic dry etching method for silicon is a method using reactive ion etching (RIE). Examples of etching gases for dry etching include fluorine-containing gases such as CF4 and SF6.

[0052] 6(C), the silicon substrate may be etched through an opening in a mask (a hard mask including the third insulating film 303) provided on the silicon substrate to form a space (first trench portion 25) directly below the opening and directly below a region outside both ends of the opening in the width direction. In this case, the width of the upper portion of the front-side recess 306 expands to a position where the lower surface of the first insulating film 301 is exposed.

[0053] Although not shown, when forming the sinker region 24 (see FIG. 3), N-type impurities are implanted into the inner surface of the front-side recess 306 using an ion implantation method. This forms the sinker region 24. During ion implantation, the direction of ion movement is tilted with respect to the depth direction of the front-side recess 306. After the Nth ion implantation is completed, the silicon substrate is rotated, for example, around the ion movement direction as the central axis, and the N+1th ion implantation is performed (N is a natural number). For example, the silicon substrate is rotated 90 degrees from the initial position for three rotations, for a total of four ion implantations. Note that the rotation angle and the number of rotations are not limited to these.

[0054] As shown in FIG. 6(D), the silicon substrate is further etched through the openings in the hard mask including the third insulating film 303, i.e., the bottoms of the front-side recesses 306 (see FIG. 6(C)) are etched to form second trench portions 26 having an inverse tapered shape and consisting of deep-bottom recesses 307. Dry etching for silicon can be used as the etching method. For example, anisotropic dry etching using RIE can be used. In this process, the silicon substrate is dry etched through the openings in the hard mask to form trenches (second trench portions 26 (see FIG. 3)) that are continuous with the spaces (first trench portions 25).

[0055] 6(E), an insulating film 22 is formed on the exposed surface of the deep recess 307 (trench). As a formation method, low-pressure CVD or thermal oxidation of silicon can be used, and silicon dioxide can be formed as the insulating film 22. In this process, the insulating film 22 is formed on the exposed surfaces of the space (first trench portion 25) and the trench (second trench portion 26).

[0056] As shown in FIG. 6(F), the portion of the insulating film 22 located on the bottom surface of the deep recess 307 (trench) is removed to expose the semiconductor substrate 11 (see FIG. 3) located on the bottom surface of the deep recess 307. Anisotropic dry etching for insulating films can be used as a removal method. Next, a conductive material 23 is filled into the trench 21 via the insulating film 22. The conductive material 23 is polysilicon doped with impurities, and a CVD method can be used as a formation method.

[0057] As shown in FIG. 6(G), the third insulating film 303 of the hard mask is removed by chemical mechanical polishing (CMP). This process exposes the top surface of the second insulating film 302. The conductive material 23 that was present in the openings of the hard mask is also removed. Next, the second insulating film 302 is peeled off. Wet etching can be used to peel off the second insulating film 302 made of silicon nitride. An example of an etchant is phosphoric acid (H3PO4). Next, the first insulating film 301 is removed. Wet etching can be used to remove the first insulating film 301 made of silicon dioxide. An example of an etchant is hydrofluoric acid (HF).

[0058] 6(H), an insulating region 15 is formed on the surface of the silicon substrate by a known method, thereby forming an isolation structure 20B.

[0059] 7 is an enlarged view showing a cross-sectional configuration of an isolation structure according to a comparative example. In an isolation structure 120 according to the comparative example, the trench 21 has a forward tapered shape throughout its depth. The gradient angle θ of the side surface 21b of the trench 21 with respect to the depth direction is constant throughout the trench 21 in its depth direction. A first width W1, which is the width W of the trench 21 at the surface 14a of the epitaxial semiconductor layer 14, is wider than a second width W2, which is the width W of the trench 21 at the tip 21a of the trench 21 in the depth direction. The isolation structure 120 does not have a sinker region, but may have a sinker region.

[0060] The second width W2, which is the bottom dimension, is set to a dimension necessary to ensure contact between the conductive material 23 and the semiconductor substrate 11. Once the bottom dimension is determined, the first width W1, which is the top dimension, is determined by the thickness of the insulating film 22, the taper angle, and the depth of the trench 21 (the total length of the trench 21 in the depth direction). In the isolation structure 120, the trench 21 has a forward tapered shape throughout its depth direction, so the first width W1, which is the top dimension, tends to be large. As an example, when the second width W2 is 0.8 μm, the thickness of the insulating film 22 is 0.5 μm, the depth of the trench 21 is 28.6 μm, and the slope angle θ is 1°, the first width W1 is 1.8 μm.

[0061] The only way to reduce the top dimension of a forward tapered shape is to reduce the taper angle or shallow the depth of the trench 21. In the trench 21, an electric field concentrates at the point where the boundary between the buried semiconductor layer 13 and the epitaxial semiconductor layer 12 meets the side surface 21b. To improve the breakdown voltage by forming a sinker region, the sinker region must be formed up to the electric field concentration point of the trench 21. However, if the taper angle is reduced, it becomes difficult for N-type impurities to penetrate deep into the trench 21 when forming the sinker region by ion implantation, making it difficult to improve the breakdown voltage. If the taper angle is reduced, the embedding ability of the conductive material 23 when embedding the trench 21 is reduced. Because the depth of the trench 21 needs to be deeper than the buried semiconductor layer 13, there is a limit to how shallow the depth of the trench 21 can be.

[0062] In contrast, in the isolation structure 20, at least a portion of the trench 21 has an inverted tapered shape rather than a forward tapered shape. This allows the first width W1, which is the top dimension of the trench 21, to be reduced. This increases the integration density of the semiconductor device 1. For example, if the minimum width W of the trench 21 is 0.8 μm, the thickness of the insulating film 22 is 0.5 μm, the depth of the first trench portion 25 (the total length of the first trench portion 25 in the depth direction) is 15 μm, and the first gradient angle θ1 is 1°, the first width W1 is 15.52 μm. In other words, even if the bottom dimension, the thickness of the insulating film 22, and the depth of the trench 21 are the same, the isolation structure 20 allows the top dimension of the trench 21 to be reduced by approximately 14%.

[0063] In the isolation structure 20, the first trench portion 25 near the surface 14a of the epitaxial semiconductor layer 14 has a forward tapered shape, which facilitates ion implantation. Therefore, the sinker region 24 can be formed up to the electric field concentration point by ion implantation, thereby improving the breakdown voltage. Furthermore, because the first trench portion 25 has a forward tapered shape, filling defects such as overhangs are less likely to occur when the conductive material 23 is filled inside the trench 21.

[0064] In the isolation structure 20, the top dimension of the trench 21 is determined not by the bottom dimension but by the taper angle and depth of the first trench portion 25, with the minimum value of the width W at the tip 25a of the first trench portion 25 as the reference. In order to reduce the top dimension, it is not necessary to make the taper angle smaller than necessary. This makes it easier to improve the breakdown voltage.

[0065] The forward tapered first trench portion 25 extends from the surface 14a of the epitaxial semiconductor layer 14 to a position where it penetrates the buried semiconductor layer 13. The tip 25a of the first trench portion 25 is located in the epitaxial semiconductor layer 12. Therefore, it is even easier to form the sinker region 24 by ion implantation up to the above-mentioned electric field concentration point, thereby improving the breakdown voltage.

[0066] (Variation) The following description of the modified examples of the isolation structure 20 will focus on the differences from the isolation structure 20. Description of the commonalities with the isolation structure 20 will be omitted as appropriate.

[0067] 8 is an enlarged view showing a cross-sectional configuration of an isolation structure according to a first modification. In an isolation structure 20A according to the first modification, a first trench portion 25 does not penetrate the buried semiconductor layer 13. The first trench portion 25 extends from a surface 14a of the epitaxial semiconductor layer 14 to a position just before the buried semiconductor layer 13. An end 25a of the first trench portion 25 is located in the epitaxial semiconductor layer 14. The second trench portion 26 extends from the end 25a of the first trench portion 25, penetrating the buried semiconductor layer 13 and the epitaxial semiconductor layer 12.

[0068] In the isolation structure 20A, at least a portion of the trench 21 has an inverse tapered shape rather than a forward tapered shape. This allows the first width W1, which is the top dimension of the trench 21, to be reduced, thereby increasing the integration density of the semiconductor device 1. The first trench portion 25 has a forward tapered shape, which facilitates ion implantation. When a conductive material is embedded inside the trench 21, embedding defects such as overhangs are less likely to occur. The second trench portion 26 has an inverse tapered shape, which allows the second width W2 to be wider. This ensures contact between the conductive material 23 and the semiconductor substrate 11.

[0069] In the isolation structure 20A, the top dimension of the trench 21 is determined not by the bottom dimension but by the taper angle and depth of the first trench portion 25, with the minimum value of the width W at the tip 25a of the first trench portion 25 as the reference. In order to reduce the top dimension, it is not necessary to make the taper angle smaller than necessary. This makes it easier to improve the breakdown voltage.

[0070] In the isolation structure 20A, instead of the first trench portion having a forward tapered shape, a second trench portion 26 having an inverse tapered shape penetrates the buried semiconductor layer 13. In the trench 21, an electric field is formed from the tip 21a toward the surface 14a of the epitaxial semiconductor layer 14. In this case, the second trench portion 26 located at the electric field concentration point has an inverse tapered shape, which alleviates the electric field concentration and improves the breakdown voltage.

[0071] 9 is an enlarged view showing a cross-sectional configuration of an isolation structure according to a second modification. In an isolation structure 20B according to the second modification, a first trench portion 25 has a forward tapered shape, and a second trench portion has a straight shape. The first gradient angle θ1 is a positive value, and the second gradient angle θ2 is 0°. The width W at an end 25a of the first trench portion 25 is equal to a second width W2, which is the bottom dimension.

[0072] In the isolation structure 20B, at least a portion of the trench 21 has a straight shape rather than a forward tapered shape. This allows the first width W1, which is the top dimension of the trench 21, to be reduced, thereby increasing the integration density of the semiconductor device 1. The first trench portion 25 has a forward tapered shape, which facilitates ion implantation. When the conductive material 23 is embedded inside the trench 21, embedding defects such as overhangs are less likely to occur. The second trench portion 26 has a reverse tapered shape, which allows the second width W2 to be wider. This ensures contact between the conductive material 23 and the semiconductor substrate 11.

[0073] In the isolation structure 20B, the top dimension of the trench 21 is determined by the taper angle and depth of the first trench portion 25, with the second width W2 as the reference. In order to reduce the top dimension, it is not necessary to make the taper angle smaller than necessary. This makes it easier to improve the breakdown voltage.

[0074] In the isolation structure 20B, the forward tapered first trench portion 25 also extends from the surface 14a of the epitaxial semiconductor layer 14 to a position where it penetrates the buried semiconductor layer 13. The tip 25a of the first trench portion 25 is located in the epitaxial semiconductor layer 12. Therefore, it is even easier to form the sinker region 24 up to the above-mentioned electric field concentration point by ion implantation, thereby improving the breakdown voltage.

[0075] 10 is an enlarged view showing a cross-sectional configuration of an isolation structure according to a third modification. In an isolation structure 20C according to the third modification, the first trench portion 25 has a forward tapered shape, and the second trench portion has a straight shape. The first gradient angle θ1 is a positive value, and the second gradient angle θ2 is 0°. The width W at the tip 25a of the first trench portion 25 is equal to the second width W2, which is the bottom dimension.

[0076] The first trench portion 25 does not penetrate the buried semiconductor layer 13. The first trench portion 25 extends from the surface 14a of the epitaxial semiconductor layer 14 to a position just before the buried semiconductor layer 13. An end 25a of the first trench portion 25 is located in the epitaxial semiconductor layer 14. The second trench portion 26 extends from the end 25a of the first trench portion 25 to penetrate the buried semiconductor layer 13 and the epitaxial semiconductor layer 12.

[0077] In the isolation structure 20C, at least a portion of the trench 21 has a straight shape rather than a forward tapered shape. This allows the first width W1, which is the top dimension of the trench 21, to be reduced, thereby increasing the integration density of the semiconductor device 1. The first trench portion 25 has a forward tapered shape, which facilitates ion implantation. When the conductive material 23 is embedded inside the trench 21, embedding defects such as overhangs are less likely to occur. The second trench portion 26 has a reverse tapered shape, which allows the second width W2 to be wider. This ensures contact between the conductive material 23 and the semiconductor substrate 11.

[0078] In the isolation structure 20C, the top dimension of the trench 21 is determined by the taper angle and depth of the first trench portion 25, with the second width W2 as the reference. In order to reduce the top dimension, it is not necessary to make the taper angle smaller than necessary. This makes it easier to improve the breakdown voltage.

[0079] As long as the first gradient angle θ1 and the second gradient angle θ2 are different from each other, both the first trench portion 25 and the second trench portion 26 may have an inverse tapered shape.

[0080] In the isolation structures 20, 20A, 20B, and 20C, the trench 21 has a first trench portion 25 and a second trench portion 26 that are continuously aligned in the depth direction, but may further have other trench portions. For example, a third trench portion may be provided between the first trench portion 25 and the surface 14a. A third trench portion may be provided between the second trench portion 26 and the tip 21a. A third trench portion may be provided between the first trench portion 25 and the second trench portion 26. The first trench portion 25 and the second trench portion 26 do not have to be continuously aligned in the depth direction.

[0081] The first gradient angle θ1 and the second gradient angle θ2 may be equal to each other as long as the gradient angle θ varies between the first trench portion 25 and the second trench portion 26. For example, if the gradient angle of a third trench portion provided between the first trench portion 25 and the second trench portion 26 is different from the first gradient angle θ1 and the second gradient angle θ2, the gradient angle θ varies between the first trench portion 25 and the second trench portion 26.

[0082] In the above-described embodiments, one or more elements of one embodiment may be combined with one or more elements of another embodiment.

[0083] Below, examples of features extracted from the description of this specification and the drawings are shown.

[0084] [A1] (Figures 2 to 4) A semiconductor substrate (11), a buried semiconductor layer (13) provided on the semiconductor substrate; a first epitaxial semiconductor layer (14) provided on the buried semiconductor layer; a device (50) disposed within the first epitaxial semiconductor layer; an isolation structure (20) surrounding the device; Equipped with The isolation structure includes: a trench (21) extending from the surface (14a) of the first epitaxial semiconductor layer to a position penetrating the buried semiconductor layer (13); an insulating film (22) covering the side surface of the trench; a conductive region (23) provided in the trench so as to be surrounded by the insulating film; and The trench has a first trench portion (25) and a second trench portion (26) aligned in a depth direction of the trench, At least one of the first trench portion and the second trench portion has a straight shape with a constant width (W) or an inverse tapered shape with a width that increases along the depth direction, The slope angle (θ) of the side surface with respect to the depth direction varies between the first trench portion and the second trench portion. Semiconductor device (1).

[0085] [A2] the first trench portion has a forward tapered shape in which the width narrows along the depth direction, The second trench portion has a straight shape with a constant width. The semiconductor device according to [A1].

[0086] [A3] the first trench portion has a forward tapered shape in which the width narrows along the depth direction, The second trench portion has an inverse tapered shape in which the width increases along the depth direction. The semiconductor device according to [A1].

[0087] [A4] the first trench portion extends from the surface of the first epitaxial semiconductor layer to a position just before the buried semiconductor layer; The semiconductor device according to any one of [A1] to [A3].

[0088] [A5] The tip (25a) of the first trench portion is located in the first epitaxial semiconductor layer. The semiconductor device according to [A4].

[0089] [A6] the first trench portion extends from the surface of the first epitaxial semiconductor layer to a position penetrating the buried semiconductor layer; The semiconductor device according to any one of [A1] to [A3].

[0090] [A7] Further comprising a second epitaxial semiconductor layer (12) provided between the semiconductor substrate and the buried semiconductor layer, an end of the first trench portion is located in the second epitaxial semiconductor layer; The semiconductor device according to [A6].

[0091] [A8] the isolation structure further includes a sinker region (24) provided along the side surface of the trench and having an impurity concentration higher than an impurity concentration of the first epitaxial semiconductor layer. The semiconductor device according to any one of [A1] to [A7].

[0092] [A9] the sinker region extends from the surface of the first epitaxial semiconductor layer to a position penetrating the buried semiconductor layer; The semiconductor device according to [A8].

[0093] [A10] Further comprising a second epitaxial semiconductor layer (12) provided between the semiconductor substrate and the buried semiconductor layer, a tip of the sinker region is located in the second epitaxial semiconductor layer; The semiconductor device according to [A9].

[0094] [A11] the side surface of the trench is curved between the first trench portion and the second trench portion; The semiconductor device according to any one of [A1] to [A10].

[0095] [A12] the first trench portion and the second trench portion are continuously aligned in the depth direction; The semiconductor device according to any one of [A1] to [A11].

[0096] [A13] the trench extends from the surface of the first epitaxial semiconductor layer to the semiconductor substrate; The semiconductor device according to any one of [A1] to [A12]. [Explanation of symbols]

[0097] 1...Semiconductor device 3...First main surface 4...Second main surface 5A…1st side 5B…Second side 5C…Third side 5D…Fourth side 10...Device area 11...Semiconductor substrate 12...Epitaxial semiconductor layer (second epitaxial semiconductor layer) 12a...tip 13...Buried semiconductor layer 14...Epitaxial semiconductor layer (first epitaxial semiconductor layer) 14a…Surface 15...Isolation area 151...First outer insulation area 152...First inner insulating region 153...Second inner insulating region 154…Second outer insulation area 20, 20A, 20B, 20C...Isolation structure 21...Trench 21a...tip 21b...side 22...Insulating film 23...Conductive material (conductive region) 24...Sinker area 24a...tip 25...First trench section 25a...tip 26...Second trench section 50…devices 51...Semiconductor well region 521...First drain region 522...Second drain region 53...Body area 54...Source region 551...first insulating film 552...Second insulating film 561...First gate electrode 562...Second gate electrode 57...Buried semiconductor layer 120...Isolation structure 301...first insulating film 302...Second insulating film 303...Third insulating film 304...First resist material 305...First opening 306...Concave on the surface 307...Deep recessed bottom E: Bias potential application terminal W…width W1…1st width W2...Second width θ...gradient angle θ1...First gradient angle θ2: Second gradient angle

Claims

1. a semiconductor substrate; a buried semiconductor layer provided on the semiconductor substrate; a first epitaxial semiconductor layer provided on the buried semiconductor layer; a device disposed within the first epitaxial semiconductor layer; an isolation structure surrounding the device; Equipped with The isolation structure includes: a trench extending from a surface of the first epitaxial semiconductor layer to a position penetrating the buried semiconductor layer; an insulating film covering a side surface of the trench; a conductive region provided in the trench so as to be surrounded by the insulating film; and the trench has a first trench portion and a second trench portion aligned in a depth direction of the trench, At least one of the first trench portion and the second trench portion has a straight shape with a constant width or an inverse tapered shape with a width that increases along the depth direction, a gradient angle of the side surface with respect to the depth direction varies between the first trench portion and the second trench portion; Semiconductor device.

2. the first trench portion has a forward tapered shape in which the width narrows along the depth direction, The second trench portion has a straight shape with a constant width. The semiconductor device according to claim 1 .

3. the first trench portion has a forward tapered shape in which the width narrows along the depth direction, The second trench portion has an inverse tapered shape in which the width increases along the depth direction. The semiconductor device according to claim 1 .

4. the first trench portion extends from the surface of the first epitaxial semiconductor layer to a position just before the buried semiconductor layer; 4. The semiconductor device according to claim 2 or 3.

5. an end of the first trench portion is located in the first epitaxial semiconductor layer; The semiconductor device according to claim 4 .

6. the first trench portion extends from the surface of the first epitaxial semiconductor layer to a position penetrating the buried semiconductor layer; 4. The semiconductor device according to claim 2 or 3.

7. a second epitaxial semiconductor layer provided between the semiconductor substrate and the buried semiconductor layer; an end of the first trench portion is located in the second epitaxial semiconductor layer; The semiconductor device according to claim 6.

8. the isolation structure further includes a sinker region provided along the side surface of the trench and having an impurity concentration higher than an impurity concentration of the first epitaxial semiconductor layer. The semiconductor device according to any one of claims 1 to 3.

9. the sinker region extends from the surface of the first epitaxial semiconductor layer to a position penetrating the buried semiconductor layer; The semiconductor device according to claim 8 .

10. a second epitaxial semiconductor layer provided between the semiconductor substrate and the buried semiconductor layer; a tip of the sinker region is located in the second epitaxial semiconductor layer; The semiconductor device according to claim 9 .

11. the side surface of the trench is curved between the first trench portion and the second trench portion; The semiconductor device according to any one of claims 1 to 3.

12. the first trench portion and the second trench portion are continuously aligned in the depth direction; The semiconductor device according to any one of claims 1 to 3.

13. the trench extends from the surface of the first epitaxial semiconductor layer to the semiconductor substrate; The semiconductor device according to any one of claims 1 to 3.

Images