Semiconductor device

Abstract

To provide a semiconductor device capable of reducing gate capacitance.SOLUTION: A semiconductor device according to an embodiment includes a first electrode, a second electrode, a semiconductor layer having a first surface and a second surface opposite to the second electrode, a gate electrode including a first portion and a second portion extending in a first direction in the semiconductor layer, a field plate electrode provided in the semiconductor layer between the gate electrode and the second surface and electrically connected to the first electrode, and a second portion provided between the first portion and the second portion in the semiconductor layer. A conductive layer electrically isolated from the first electrode, and a field plate insulating layer provided between the field plate electrode and the semiconductor layer, wherein a first distance in the first direction between an end portion in the first direction of a first surface of the field plate insulating layer and the conductive layer is smaller than a second distance in the first direction from the end portion to the gate electrode.SELECTED DRAWING: Figure 3

Description

[Technical Field]

[0001] FIELD An embodiment of the present invention relates to a semiconductor device. [Background technology]

[0002] Vertical transistors, in which the gate electrode is buried in a trench, are used to miniaturize transistors or improve their performance. In vertical transistors, there is a trade-off between drain-source breakdown voltage (hereinafter simply referred to as "breakdown voltage") and on-resistance. In other words, increasing the impurity concentration in the drift region to reduce on-resistance reduces the breakdown voltage. Conversely, decreasing the impurity concentration in the drift region to improve breakdown voltage increases the on-resistance.

[0003] One structure that improves the tradeoff between breakdown voltage and on-resistance is the provision of a field plate electrode in the trench of a vertical transistor. By changing the electric field distribution in the drift region with the field plate electrode, it is possible to increase the impurity concentration in the drift region while maintaining the breakdown voltage. Therefore, it is possible to reduce the on-resistance while maintaining the breakdown voltage.

[0004] The provision of a field plate electrode increases the capacitance between the gate electrode and the field plate electrode, which may increase the gate capacitance. To achieve faster transistors, it is desirable to reduce the gate capacitance. [Prior art documents] [Patent documents]

[0005] [Patent Document 1] JP 2013-115225 A Summary of the Invention [Problem to be solved by the invention]

[0006] An object of the present invention is to provide a semiconductor device capable of reducing gate capacitance. [Means for solving the problem]

[0007] The semiconductor device of the embodiment includes a first electrode, a second electrode, a semiconductor layer provided between the first electrode and the second electrode and having a first surface facing the first electrode and a second surface facing the second electrode, the semiconductor layer including: a first semiconductor region of a first conductivity type electrically connected to the second electrode; a second semiconductor region of a second conductivity type provided between the first semiconductor region and the first surface; and a third semiconductor region of the first conductivity type provided between the second semiconductor region and the first surface and electrically connected to the first electrode; a gate electrode provided in the semiconductor layer and including a first portion extending in a first direction parallel to the first surface and a second portion positioned relative to the first portion in a second direction parallel to the first surface and perpendicular to the first direction; a field plate electrode provided between the first portion and the second portion and electrically connected to the first electrode; a conductive layer provided in the semiconductor layer, between the first portion and the second portion, and electrically isolated from the first electrode; a gate insulating layer provided between the gate electrode and the semiconductor layer; a field plate insulating layer provided between the field plate electrode and the semiconductor layer; a first insulating layer provided between the conductive layer and the field plate electrode; a second insulating layer provided between the first portion and the conductive layer; and a third insulating layer provided between the second portion and the conductive layer, wherein a first distance in the first direction between an end of the field plate insulating layer in the first direction on the first surface and the conductive layer is smaller than a second distance in the first direction between the end and the gate electrode. [Brief explanation of the drawings]

[0008] [Figure 1] 1 is a schematic diagram of a semiconductor device according to a first embodiment. [Figure 2]FIG. 1 is a schematic cross-sectional view of a portion of a semiconductor device according to a first embodiment. [Figure 3] FIG. 2 is a schematic top view of a part of the semiconductor device according to the first embodiment. [Figure 4] FIG. 1 is a schematic cross-sectional view of a portion of a semiconductor device according to a first embodiment. [Figure 5] FIG. 1 is a schematic cross-sectional view of a portion of a semiconductor device according to a first embodiment. [Figure 6] FIG. 1 is a schematic cross-sectional view of a portion of a semiconductor device according to a first embodiment. [Figure 7] FIG. 1 is a schematic cross-sectional view of a portion of a semiconductor device according to a first embodiment. [Figure 8] FIG. 1 is a schematic cross-sectional view of a portion of a semiconductor device according to a first embodiment. [Figure 9] FIG. 10 is a schematic cross-sectional view of a portion of a semiconductor device according to a first comparative embodiment. [Figure 10] FIG. 10 is a schematic cross-sectional view of a portion of a semiconductor device according to a second comparative embodiment. [Figure 11] FIG. 4 is a schematic cross-sectional view of a part of a semiconductor device according to a first modified example of the first embodiment. [Figure 12] FIG. 10 is a schematic cross-sectional view of a part of a semiconductor device according to a second modified example of the first embodiment. [Figure 13] FIG. 10 is a schematic cross-sectional view of a part of a semiconductor device according to a third modified example of the first embodiment. [Figure 14] FIG. 10 is a schematic cross-sectional view of a part of a semiconductor device according to a second embodiment. [Figure 15] FIG. 10 is a schematic top view of a part of a semiconductor device according to a second embodiment. [Figure 16] FIG. 10 is a schematic cross-sectional view of a part of a semiconductor device according to a second embodiment. [Figure 17] FIG. 10 is a schematic cross-sectional view of a part of a semiconductor device according to a first modified example of the second embodiment. [Figure 18] FIG. 10 is a schematic top view of a part of a semiconductor device according to a first modified example of the second embodiment. [Figure 19] FIG. 10 is a schematic cross-sectional view of a part of a semiconductor device according to a first modified example of the second embodiment. [Figure 20] FIG. 10 is a schematic cross-sectional view of a part of a semiconductor device according to a first modified example of the second embodiment. [Figure 21]FIG. 10 is a schematic cross-sectional view of a part of a semiconductor device according to a second modification of the second embodiment. [Figure 22] FIG. 10 is a schematic top view of a part of a semiconductor device according to a second modification of the second embodiment. [Figure 23] FIG. 10 is a schematic cross-sectional view of a part of a semiconductor device according to a second modification of the second embodiment. [Figure 24] FIG. 10 is a schematic cross-sectional view of a part of a semiconductor device according to a second modification of the second embodiment. [Figure 25] FIG. 10 is a schematic cross-sectional view of a part of a semiconductor device according to a second modification of the second embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0009] Hereinafter, an embodiment of the present invention will be described with reference to the drawings. In the following description, the same or similar components will be designated by the same reference numerals, and the description of components that have already been described will be omitted as appropriate.

[0010] In this specification, n + shape, n shape, n - When there is a notation with form, n + shape, n shape, n - This means that the n-type impurity concentration decreases in the order of the p + shape, p shape, p - If there is a form notation, p + shape, p shape, p - This means that the p-type impurity concentration decreases in the order of the type.

[0011] The impurity concentration of a semiconductor device can be measured by, for example, secondary ion mass spectrometry (SIMS). The relative level of the impurity concentration of a semiconductor device can also be determined from the level of the carrier concentration determined by, for example, scanning capacitance microscopy (SCM). Distances such as the width and depth of an impurity region of a semiconductor device can be determined by, for example, SIMS. Distances such as the width and depth of an impurity region of a semiconductor device can also be determined from, for example, an SCM image.

[0012] Qualitative and quantitative analysis of the chemical composition of the components constituting the semiconductor device herein can be performed by, for example, SIMS, energy dispersive X-ray spectroscopy (EDX), or Rutherford backscattering spectroscopy (RBS). Furthermore, for example, a scanning electron microscope (SEM) or a transmission electron microscope (TEM) can be used to measure the thickness of the components constituting the semiconductor device, the distance between the components, and the like.

[0013] (First embodiment) The semiconductor device of the first embodiment includes a first electrode, a second electrode, and a semiconductor layer provided between the first electrode and the second electrode and having a first surface facing the first electrode and a second surface facing the second electrode, the semiconductor layer including a first semiconductor region of a first conductivity type electrically connected to the second electrode, a second semiconductor region of a second conductivity type provided between the first semiconductor region and the first surface, and a third semiconductor region of the first conductivity type provided between the second semiconductor region and the first surface and electrically connected to the first electrode; a first portion provided in the semiconductor layer and extending in a first direction parallel to the first surface, and a second portion parallel to the first surface and perpendicular to the first direction with respect to the first portion; the field plate insulating layer is provided between the field plate electrode and the semiconductor layer, a first insulating layer is provided between the conductive layer and the field plate electrode, a second insulating layer is provided between the first portion and the conductive layer, and a third insulating layer is provided between the second portion and the conductive layer, wherein a first distance in the first direction between an end of the field plate insulating layer in the first direction on the first surface of the field plate insulating layer and the conductive layer is smaller than a second distance in the first direction between the end and the gate electrode.

[0014] In the following, an example will be described in which the first conductivity type is n-type and the second conductivity type is p-type, and the semiconductor device is an n-channel Metal Oxide Semiconductor Field Effect Transistor (MOSFET) that uses electrons as carriers.

[0015] The semiconductor device of the first embodiment is a MOSFET 100. The MOSFET 100 is a vertical trench gate MOSFET in which a gate electrode and a field plate electrode are provided in a trench.

[0016] In this specification, a trench refers to a groove-type or recessed structure that the semiconductor layer itself has, and a component other than the semiconductor layer can be provided inside the trench. The trench is a part of the semiconductor layer.

[0017] 1(a) and 1(b) are schematic diagrams of a semiconductor device according to a first embodiment. Fig. 1(a) shows the front surface side of a MOSFET 100. Fig. 1(b) shows the back surface side of the MOSFET 100.

[0018] As shown in FIG. 1(a), on the surface side of the MOSFET 100, a source electrode 10, a source electrode wiring 10x, a gate electrode pad 12, and a gate electrode wiring 12x are provided.

[0019] The source electrode wiring 10x is physically and electrically connected to the source electrode 10. The source electrode wiring 10x extends in a second direction.

[0020] The gate electrode wiring 12x is physically and electrically connected to the gate electrode pad 12. The gate electrode wiring 12x extends in a second direction. The gate electrode wiring 12x is provided between the source electrode wiring 10x and the source electrode 10 in the first direction.

[0021] As shown in FIG. 1(b), a drain electrode 20 is provided on the back surface side of the MOSFET 100.

[0022] A plurality of transistors are provided below the source electrode 10. The gate electrode pad 12 and the gate electrode wiring 12x are electrically connected to the gate electrodes of the transistors. A gate voltage is applied to the gate electrode pad 12 to control the switching operation of the transistors.

[0023] Fig. 2 is a schematic cross-sectional view of a part of the semiconductor device of the first embodiment. Fig. 2 is a cross-sectional view taken along line AA' in Fig. 1(a). Fig. 2 is a cross-sectional view taken along line AA' in Fig. 3.

[0024] Fig. 3 is a schematic top view of a portion of the semiconductor device of the first embodiment. Fig. 3 is a top view of the portion indicated by the dotted line in Fig. 1(a). Fig. 3 is a top view including a portion corresponding to Fig. 2. Fig. 3 is a view of a position corresponding to the first face F1 of the semiconductor layer 30. Fig. 3 is a view excluding components above the first face F1.

[0025] 4, 5, 6, 7, and 8 are schematic cross-sectional views of a portion of the semiconductor device of the first embodiment. FIG. 4 is a BB' cross-section of FIGS. 1(a) and 3. FIG. 5 is a CC' cross-section of FIGS. 1(a) and 3. FIG. 6 is a DD' cross-section of FIGS. 1(a) and 3. FIG. 7 is an EE' cross-section of FIG. 3. FIG. 8 is an FF' cross-section of FIG. 3.

[0026] The MOSFET 100 includes a source electrode 10 (first electrode), a drain electrode 20 (second electrode), a semiconductor layer 30, a gate electrode 40, a gate insulating layer 45, a field plate electrode 50, a field plate insulating layer 55, a conductive layer 60, a first interelectrode insulating layer 71 (first insulating layer), a second interelectrode insulating layer 72 (second insulating layer), a third interelectrode insulating layer 73 (third insulating layer), and an interlayer insulating layer 80.

[0027] The source electrode 10 includes a source contact plug 10a, the source electrode wiring 10x includes a field plate contact plug 10xa, and the gate electrode wiring 12x includes a gate contact plug 12xa.

[0028] The semiconductor layer 30 has trenches 31, n + shaped drain region 33, n - a p-type drift region 34 (first semiconductor region), a p-type body region 35 (second semiconductor region), and an n-type + The source region 36 (third semiconductor region) is of a crystalline form.

[0029] The gate electrode 40 includes a first portion 40a, a second portion 40b, and a third portion 40c.

[0030] The semiconductor layer 30 is provided between the source electrode 10 and the drain electrode 20. The semiconductor layer 30 has a first surface ("F1" in FIG. 2) and a second surface ("F2" in FIG. 2). The second surface F2 faces the first surface F1.

[0031] The first face F1 faces the source electrode 10. The second face F2 faces the drain electrode 20.

[0032] The first direction and the second direction are parallel to the first face F1. The second direction is perpendicular to the first direction. The third direction is perpendicular to the first face F1. The third direction is perpendicular to the first direction and the second direction.

[0033] Hereinafter, the term "depth" refers to the depth based on the first plane F1, that is, the distance in the third direction based on the first plane F1.

[0034] The semiconductor layer 30 is, for example, single-crystal silicon (Si). When the semiconductor layer 30 is single-crystal silicon, the surface of the semiconductor layer 30 is, for example, a plane inclined at an angle of 0 to 8 degrees with respect to the (100) plane.

[0035] n + A drain region 33 having a shape is provided in the semiconductor layer 30. The drain region 33 is in contact with the second face F2. The drain region 33 is in contact with the drain electrode 20. The drain region 33 is electrically connected to the drain electrode 20.

[0036] The drain region 33 contains n-type impurities. The n-type impurities are, for example, phosphorus (P) or arsenic (As). The concentration of the n-type impurities is, for example, 1×10 18 cm -3 More than 1×10 21 cm -3 The following is the result.

[0037] n -A drift region 34 having a shape similar to that of the first face F1 is provided in the semiconductor layer 30. The drift region 34 is provided between the drain region 33 and the first face F1. The drift region 34 is provided on the drain region 33. The drift region 34 functions as a current path when the MOSFET 100 is in an on-state.

[0038] The drift region 34 contains n-type impurities. The n-type impurities are, for example, phosphorus (P) or arsenic (As). The n-type impurity concentration is, for example, 1×10 15 cm -3 More than 1×10 18 cm -3 The following is the result.

[0039] The thickness of the drift region 34 in the third direction is, for example, not less than 5 μm and not more than 15 μm.

[0040] A p-type body region 35 is provided in the semiconductor layer 30. The body region 35 is provided between the drift region 34 and the first face F1.

[0041] The body region 35 is provided between two adjacent trenches 31.

[0042] The body region 35 is in contact with, for example, the source electrode 10. The body region 35 is electrically connected to, for example, the source electrode 10. The body region 35 is electrically connected to the source electrode 10 using, for example, a source contact plug 10a, as shown in FIG. 2 . The source contact plug 10a is in contact with the body region 35.

[0043] When the MOSFET 100 is turned on, an inversion layer channel is formed in the body region 35 facing the gate electrode 40 .

[0044] The body region 35 contains p-type impurities. The p-type impurities are, for example, boron (B). The p-type impurity concentration is, for example, 1×10 16 cm -3 More than 1×10 20 cm -3 The following is the result.

[0045] n + A source region 36 having a shape similar to that of the body region 35 is provided in the semiconductor layer 30. The source region 36 is provided between the body region 35 and the first face F1.

[0046] The source region 36 is in contact with the first face F1. The source region 36 is in contact with the source electrode 10. The source region 36 is electrically connected to the source electrode 10. The source region 36 is electrically connected to the source electrode 10 using a source contact plug 10a, for example, as shown in FIG. 2. The source contact plug 10a is in contact with the source electrode 10.

[0047] The source region 36 is provided between two adjacent trenches 31.

[0048] The source region 36 contains n-type impurities. The n-type impurities are, for example, phosphorus (P) or arsenic (As). The n-type impurity concentration is, for example, 1×10 19 cm -3 More than 1×10 21 cm -3 The following is the result.

[0049] The trench 31 is provided in the semiconductor layer 30. The trench 31 is located on the first face F1 side of the semiconductor layer 30. The trench 31 is a groove formed in the semiconductor layer 30.

[0050] 3, the trench 31 extends in a first direction. The plurality of trenches 31 are repeatedly arranged in a second direction. For example, the plurality of trenches 31 are repeatedly arranged at a constant pitch in the second direction.

[0051] The trench 31 penetrates the body region 35 and reaches the drift region 34. The depth of the trench 31 is, for example, not less than 1 μm and not more than 5 μm. The width of the trench 31 in the second direction is, for example, not less than 0.3 μm and not more than 1 μm.

[0052] The gate electrode 40 is provided in the semiconductor layer 30. The gate electrode 40 is provided between one part of the semiconductor layer 30 and another part of the semiconductor layer 30. The gate electrode 40 is provided in the trench 31. The gate electrode 40 includes a first portion 40a, a second portion 40b, and a third portion 40c.

[0053] 2, the second portion 40b is located in the second direction relative to the first portion 40a. The second portion 40b is spaced apart from the first portion 40a in the second direction within the trench 31.

[0054] 4, the third portion 40c connects the first portion 40a and the second portion 40b and extends in the second direction.

[0055] The gate electrode 40 is electrically connected to the gate electrode wiring 12x using a gate contact plug 12xa, for example, as shown in Fig. 4. The gate contact plug 12xa is in contact with the third portion 40c.

[0056] The gate electrode 40 is a conductor and is made of, for example, polycrystalline silicon containing n-type impurities or p-type impurities.

[0057] The gate insulating layer 45 is provided between the gate electrode 40 and the semiconductor layer 30. The gate insulating layer 45 is provided between the gate electrode 40 and the body region 35. The gate insulating layer 45 is provided between the gate electrode 40 and the drift region 34. The gate insulating layer 45 is provided between the gate electrode 40 and the source region 36. The gate insulating layer 45 is made of, for example, silicon oxide.

[0058] The field plate electrode 50 is provided in the semiconductor layer 30. The field plate electrode 50 is provided between one part of the semiconductor layer 30 and another part of the semiconductor layer 30. The field plate electrode 50 is provided in the trench 31. The field plate electrode 50 is provided between the gate electrode 40 and the second face F2. The distance in the third direction between the second face F2 and the field plate electrode 50 is smaller than the distance in the third direction between the second face F2 and the gate electrode 40. The field plate electrode 50 extends in the first direction.

[0059] The field plate electrode 50 has the function of changing the electric field distribution in the drift region 34 when the MOSFET 100 is in an off state, thereby improving the breakdown voltage of the MOSFET 100.

[0060] 6, the field plate electrode 50 is electrically connected to the source electrode wiring 10x using a field plate contact plug 10xa. The field plate electrode 50 is electrically connected to the source electrode 10. The field plate contact plug 10xa is in contact with the field plate electrode 50. The field plate electrode 50 is connected to the source electrode wiring 10x, for example, in a region where there is no trench directly below.

[0061] The field plate electrode 50 is a conductor and is made of, for example, polycrystalline silicon containing n-type impurities or p-type impurities.

[0062] The field plate insulating layer 55 is provided between the field plate electrode 50 and the semiconductor layer 30. The field plate insulating layer 55 is provided between the field plate electrode 50 and the drift region 34. The field plate insulating layer 55 is made of, for example, silicon oxide.

[0063] The thickness in the second direction of field plate insulating layer 55 is, for example, thicker than the thickness in the second direction of gate insulating layer 45. The thickness in the second direction of field plate insulating layer 55 is, for example, 3 to 30 times the thickness in the second direction of gate insulating layer 45.

[0064] The conductive layer 60 is provided in the semiconductor layer 30. The conductive layer 60 is provided between one portion of the semiconductor layer 30 and another portion of the semiconductor layer 30. The conductive layer 60 is provided in the trench 31. The conductive layer 60 is provided between the first portion 40a and the second portion 40b of the gate electrode 40. The conductive layer 60 is spaced apart from the gate electrode 40. The conductive layer 60 is spaced apart from the field plate electrode 50. The field plate electrode 50 is provided between the conductive layer 60 and the second face F2.

[0065] The conductive layer 60 is electrically isolated from the source electrode 10. The conductive layer 60 is electrically isolated from the gate electrode 40. Note that being electrically isolated means that there is no electrical short circuit.

[0066] The conductive layer 60 is floating, that is, the conductive layer 60 is not fixed to any potential.

[0067] The first interelectrode insulating layer 71 is provided between the conductive layer 60 and the field plate electrode 50. The first interelectrode insulating layer 71 is provided, for example, between the gate electrode 40 and the field plate electrode 50. The first interelectrode insulating layer 71 is made of, for example, silicon oxide.

[0068] The thickness in the third direction of first inter-electrode insulating layer 71 between conductive layer 60 and field plate electrode 50 is, for example, thicker than the thickness in the second direction of gate insulating layer 45. The thickness in the third direction of first inter-electrode insulating layer 71 between conductive layer 60 and field plate electrode 50 is, for example, two to five times the thickness in the second direction of gate insulating layer 45.

[0069] The second inter-electrode insulating layer 72 is provided between the first portion 40a of the gate electrode 40 and the conductive layer 60. The second inter-electrode insulating layer 72 is, for example, silicon oxide.

[0070] The third interelectrode insulating layer 73 is provided between the second portion 40b of the gate electrode 40 and the conductive layer 60. The third interelectrode insulating layer 73 is, for example, silicon oxide.

[0071] The interlayer insulating layer 80 is provided between the gate electrode 40 and the source electrode 10. The interlayer insulating layer 80 has a function of electrically isolating the gate electrode 40 and the source electrode 10. The interlayer insulating layer 80 is made of, for example, silicon oxide.

[0072] The source electrode 10 is provided on the first face F1 side of the semiconductor layer 30. The source electrode 10 is provided above the first face F1 of the semiconductor layer 30.

[0073] The source electrode 10 is electrically connected to the source region 36 and the body region 35. The source electrode 10 contacts the source region 36 and the body region 35, for example.

[0074] The source electrode 10 is a region to which, for example, a bonding wire is connected when the MOSFET 100 is mounted.

[0075] The source electrode 10 is made of metal and has, for example, a laminated structure of titanium (Ti) and aluminum (Al).

[0076] The source electrode wiring 10x is physically and electrically connected to the source electrode 10. The source electrode 10 and the field plate electrode 50 are electrically connected using the source electrode wiring 10x.

[0077] The source electrode wiring 10x is made of metal. The source electrode wiring 10x has, for example, a laminated structure of titanium (Ti) and aluminum (Al). The material of the source electrode wiring 10x is, for example, the same as the material of the source electrode 10.

[0078] The drain electrode 20 is provided on the second face F2 side of the semiconductor layer 30. The drain electrode 20 is provided on the second face F2 of the semiconductor layer 30. The drain electrode 20 is electrically connected to the drain region 33. The drain electrode 20 contacts the drain region 33.

[0079] The drain electrode 20 is made of metal and has a laminated structure of a material selected from, for example, titanium (Ti), aluminum (Al), nickel (Ni), copper (Cu), silver (Ag), and gold (Au).

[0080] The gate electrode pad 12 is provided on the first face F1 side of the semiconductor layer 30. The gate electrode pad 12 is provided above the first face F1 of the semiconductor layer 30.

[0081] The gate electrode pad 12 is electrically connected to the gate electrode 40. When the MOSFET 100 is mounted, the gate electrode pad 12 is a region to which, for example, a bonding wire is connected.

[0082] The gate electrode pad 12 is made of metal. The gate electrode pad 12 has a laminated structure of, for example, titanium (Ti) and aluminum (Al). The material of the gate electrode pad 12 is the same as the material of the source electrode 10, for example.

[0083] The gate electrode wiring 12x is physically and electrically connected to the gate electrode 40. The gate electrode pad 12 and the gate electrode 40 are electrically connected using the gate electrode wiring 12x.

[0084] The gate electrode wiring 12x is made of a metal. The gate electrode wiring 12x has, for example, a laminated structure of titanium (Ti) and aluminum (Al). The material of the gate electrode wiring 12x is, for example, the same as the material of the source electrode 10 and the material of the gate electrode pad 12.

[0085] As shown in FIGS. 3 and 7 , the distance in the first direction between the end in the first direction of the field plate insulating layer 55 on the first face F1 (Ex in FIGS. 3 and 7 ) and the conductive layer 60 is a first distance d1. In other words, the distance in the first direction between the end in the first direction of the trench 31 (Ex in FIGS. 3 and 7 ) and the conductive layer 60 is a first distance d1. Furthermore, as shown in FIGS. 3 and 8 , the distance in the first direction between the end in the first direction of the field plate insulating layer 55 on the first face F1 (Ex in FIGS. 3 and 7 ) and the gate electrode 40 is a second distance d2. In other words, the distance in the first direction between the end in the first direction of the trench 31 (Ex in FIGS. 3 and 8 ) and the gate electrode 40 is a second distance d2.

[0086] The first distance d1 is smaller than the second distance d2, or in other words, the second distance d2 is larger than the first distance d1.

[0087] The difference between the second distance d2 and the first distance d1 is, for example, larger than the depth in the third direction of field plate insulating layer 55. The difference between the second distance d2 and the first distance d1 is, for example, not more than 50 times the depth in the third direction of field plate insulating layer 55. The difference between the second distance d2 and the first distance d1 is, for example, not less than 10 μm and not more than 100 μm.

[0088] The difference between the second distance d2 and the first distance d1 is, for example, larger than the depth in the third direction of the trench 31. The difference between the second distance d2 and the first distance d1 is, for example, 50 times or less the depth in the third direction of the trench 31. The difference between the second distance d2 and the first distance d1 is, for example, 10 μm or more and 100 μm or less.

[0089] The structure inside the trench 31 of the MOSFET 100 of the first embodiment is manufactured by repeatedly forming an insulating film and filling a conductive film in the trench 31. A mask material is used when removing the conductive film or the insulating film. By appropriately determining the position of the end of the mask material near the end Ex of the trench 31 in the first direction, it is possible to make the first distance d1 smaller than the second distance d2.

[0090] For example, the position of the edge of the first mask material when etching the conductive film that forms the field plate electrode 50 is defined as the first position. The position of the edge of the conductive layer 60 in the first direction is determined by the first position. Furthermore, the position of the edge of the second mask material when etching the insulator film that becomes the field plate insulating layer 55 after the conductive layer 60 is formed is defined as the second position. The position of the edge of the gate electrode 40 in the first direction is determined by the second position. By positioning the first position closer to the edge Ex of the trench 31 in the first direction than the second position, it is possible to make the first distance d1 smaller than the second distance d2.

[0091] Next, the operation and effects of the semiconductor device of the first embodiment will be described.

[0092] 9 is a schematic cross-sectional view of a part of a semiconductor device of a first comparative embodiment, which corresponds to FIG. 2 of the first embodiment.

[0093] The semiconductor device of the first comparative embodiment is a MOSFET 901. The MOSFET 901 differs from the MOSFET 100 of the first embodiment in that the MOSFET 901 does not include the conductive layer 60 and has a field plate electrode 50 provided between the first portion 40a and the second portion 40b of the gate electrode 40.

[0094] In the MOSFET 901 of the first comparative example, the gate electrode 40 faces, in the second direction, the field plate electrode 50 electrically connected to the source electrode 10. The capacitance between the gate electrode 40 and the field plate electrode 50 facing each other in the second direction is the gate-source capacitance.

[0095] In the MOSFET 901 of the first comparative example, there is a concern that the capacitance between the gate and source becomes large, which may hinder the speedup of the transistor.

[0096] In the MOSFET 100 of the first embodiment, the gate electrode 40 faces the conductive layer 60 in the second direction. The conductive layer 60 is not electrically connected to the source electrode 10 and is floating. Therefore, the gate-source capacitance of the MOSFET 100 is reduced compared to the MOSFET 901 of the first comparative embodiment. This reduces the gate capacitance of the MOSFET 100, enabling the MOSFET 100 to operate at a higher speed.

[0097] 10 is a schematic cross-sectional view of a portion of a semiconductor device of a second comparative embodiment, which corresponds to FIG. 3 of the first embodiment.

[0098] The semiconductor device of the second comparative embodiment is a MOSFET 902. As shown in Fig. 10, the MOSFET 902 differs from the MOSFET 100 of the first embodiment in that the first distance d1 is equal to the second distance d2.

[0099] In MOSFET 902, gate electrode 40 is adjacent to field plate electrode 50 electrically connected to source electrode 10 near end Ex of trench 31 in the first direction. The capacitance between gate electrode 40 and field plate electrode 50 is gate-source capacitance.

[0100] In the MOSFET 902 of the second comparative example, there is a concern that the capacitance between the gate and source becomes large, which may hinder the speedup of the transistor.

[0101] In the MOSFET 100 of the first embodiment, the first distance d1 is smaller than the second distance d2; in other words, the second distance d2 is larger than the first distance d1. Therefore, in the MOSFET 100, the distance between the gate electrode 40 and the field plate electrode 50 in a plane parallel to the first surface near the end Ex of the trench 31 in the first direction is larger than that in the MOSFET 902 of the second comparative embodiment. Therefore, the gate-source capacitance of the MOSFET 100 is reduced compared to that of the MOSFET 902 of the second comparative embodiment. This reduces the gate capacitance of the MOSFET 100, enabling the MOSFET 100 to operate at a higher speed.

[0102] As described above, the MOSFET 100 of the first embodiment reduces the gate capacitance and enables the MOSFET to operate at a higher speed.

[0103] From the viewpoint of reducing the gate-source capacitance, the difference between the second distance d2 and the first distance d1 is preferably greater than the depth of field plate insulating layer 55, more preferably at least twice the depth of field plate insulating layer 55, and even more preferably at least five times the depth of field plate insulating layer 55.

[0104] From the viewpoint of reducing the gate-source capacitance, the difference between the second distance d2 and the first distance d1 is preferably greater than the depth of the trench 31, more preferably at least twice the depth of the trench 31, and even more preferably at least five times the depth of the trench 31.

[0105] From the viewpoint of reducing the gate-source capacitance, the difference between the second distance d2 and the first distance d1 is preferably 10 μm or more, more preferably 20 μm or more, and even more preferably 30 μm or more.

[0106] From the viewpoint of preventing the conductive layer 60 from being fixed to the source potential due to coupling with the field plate electrode 50, the thickness in the third direction of the first interelectrode insulating layer 71 between the conductive layer 60 and the field plate electrode 50 is preferably greater than the thickness in the second direction of the gate insulating layer 45. The thickness in the third direction of the first interelectrode insulating layer 71 between the conductive layer 60 and the field plate electrode 50 is more preferably at least two times the thickness in the second direction of the gate insulating layer 45, and even more preferably at least three times the thickness.

[0107] (First Modification) The semiconductor device of the first variant of the first embodiment differs from the semiconductor device of the first embodiment in that, at the end of the conductive layer in the first direction, the angle between the interface between the conductive layer and the first insulating layer and the first surface is 60 degrees or less.

[0108] Fig. 11 is a schematic cross-sectional view of a part of a semiconductor device according to a first modification of the first embodiment, and corresponds to Fig. 7 of the first embodiment.

[0109] 11 , in the MOSFET 101, at an end portion in a first direction of the conductive layer 60, the angle (θ in FIG. 11 ) between the interface between the conductive layer 60 and the first interelectrode insulating layer 71 and the first plane F1 is 60 degrees or less. The angle θ between the interface between the conductive layer 60 and the first interelectrode insulating layer 71 and the first plane F1 is, for example, not less than 20 degrees and not more than 60 degrees.

[0110] According to MOSFET 101 of the first modification of the first embodiment, the gate capacitance is reduced and the speed of the MOSFET can be increased, as in the first embodiment. Furthermore, in MOSFET 101 of the first modification of the first embodiment, when first interelectrode insulating layer 71 is formed by vapor phase growth, the gradient of the base is gentle, which improves the uniformity of the film thickness of first interelectrode insulating layer 71, for example.

[0111] (Second Modification) The semiconductor device of the second modification of the first embodiment differs from the semiconductor device of the first embodiment in that the gate electrode does not include the third portion.

[0112] Fig. 12 is a schematic cross-sectional view of a part of a semiconductor device according to a second modification of the first embodiment, and corresponds to Fig. 4 of the first embodiment.

[0113] The semiconductor device according to the second modification of the first embodiment is a MOSFET 102. As shown in FIG. 12, in the MOSFET 102, the gate electrode 40 does not include the third portion 40c. As shown in FIG. 12, the gate contact plug 12xa is directly connected to the first portion 40a and the second portion 40b. The gate contact plug 12xa contacts the first portion 40a and the second portion 40b.

[0114] According to the MOSFET 102 of the second modification of the first embodiment, the gate capacitance is reduced, and the speed of the MOSFET can be increased, similarly to the first embodiment.

[0115] (Third Modification) The semiconductor device of the third modified example of the first embodiment differs from the semiconductor device of the first embodiment in that the conductive layer is electrically connected to the gate electrode.

[0116] Fig. 13 is a schematic cross-sectional view of a part of a semiconductor device according to a third modification of the first embodiment, and corresponds to Fig. 4 of the first embodiment.

[0117] The semiconductor device according to the third modification of the first embodiment is a MOSFET 103. In the MOSFET 103, as shown in FIG. 13 , the gate contact plug 12xa is directly connected to the first portion 40a and the second portion 40b as well as to the conductive layer 60. The conductive layer 60 is electrically connected to the gate electrode wiring 12x and to the gate electrode 40.

[0118] Since the gate electrode 40 and the conductive layer 60 have the same potential, even if the gate electrode 40 and the conductive layer 60 face each other in the second direction, the capacitance between the gate electrode 40 and the conductive layer 60 does not become gate capacitance, and therefore an increase in the gate capacitance is suppressed.

[0119] Also in the MOSFET 103, similarly to the MOSFET 100 of the first embodiment, the second distance d2 is larger than the first distance d1. Therefore, the distance between the gate electrode 40 and the field plate electrode 50 in a plane parallel to the first plane is large near the end Ex of the trench 31 in the first direction. Therefore, similarly to the MOSFET 100 of the first embodiment, the gate-source capacitance of the MOSFET 103 is reduced. This reduces the gate capacitance of the MOSFET 103, enabling the MOSFET 103 to operate at a higher speed.

[0120] In MOSFET 103, conductive layer 60 has the same potential as gate electrode 40, and therefore the capacitance between conductive layer 60 and field plate electrode 50 becomes the gate-source capacitance. The gate-source capacitance of MOSFET 103 can be reduced by, for example, increasing the thickness of first interelectrode insulating layer 71.

[0121] According to the MOSFET 103 of the third modification of the first embodiment, the gate capacitance is reduced, and the speed of the MOSFET can be increased, similarly to the first embodiment.

[0122] As described above, according to the first embodiment and the modified example, a semiconductor device with reduced gate capacitance can be realized.

[0123] (Second embodiment) The semiconductor device of the second embodiment differs from the semiconductor device of the first embodiment in that the field plate electrode is electrically connected to the source electrode wiring on the conductive layer side of the end of the field plate insulating layer in the first direction on the first surface. Hereinafter, description of content that overlaps with the first embodiment may be omitted.

[0124] The semiconductor device of the second embodiment is a MOSFET 200. The MOSFET 200 is a vertical trench gate MOSFET in which a gate electrode and a field plate electrode are provided in a trench.

[0125] As with the MOSFET 100 of the first embodiment, the MOSFET 200 has a source electrode 10, a source electrode wiring 10x, a gate electrode pad 12, and a gate electrode wiring 12x provided on the front surface side thereof.

[0126] Fig. 14 is a schematic cross-sectional view of a part of the semiconductor device of the second embodiment. Fig. 14 is a cross-section taken along line GG' in Fig. 15. Fig. 14 is a view corresponding to Fig. 7 of the first embodiment.

[0127] Fig. 15 is a schematic top view of a part of the semiconductor device of the second embodiment, which corresponds to Fig. 3 of the first embodiment.

[0128] Fig. 16 is a schematic cross-sectional view of a part of the semiconductor device of the second embodiment. Fig. 16 is a cross-section taken along line HH' in Fig. 15. Fig. 16 is a view corresponding to Fig. 8 of the first embodiment.

[0129] The MOSFET 200 includes a source electrode 10 (first electrode), a drain electrode 20 (second electrode), a semiconductor layer 30, a gate electrode 40, a gate insulating layer 45, a field plate electrode 50, a field plate insulating layer 55, a conductive layer 60, a first interelectrode insulating layer 71 (first insulating layer), a second interelectrode insulating layer 72 (second insulating layer), a third interelectrode insulating layer 73 (third insulating layer), and an interlayer insulating layer 80.

[0130] The source electrode 10 includes a source contact plug 10a, the source electrode wiring 10x includes a field plate contact plug 10xa, and the gate electrode wiring 12x includes a gate contact plug 12xa.

[0131] The semiconductor layer 30 has trenches 31, n + shaped drain region 33, n - a p-type drift region 34 (first semiconductor region), a p-type body region 35 (second semiconductor region), and an n-type + The source region 36 (third semiconductor region) is of a crystalline form.

[0132] The gate electrode 40 includes a first portion 40a and a second portion 40b.

[0133] The top surfaces of the gate electrode 40, field plate electrode 50, and conductive layer 60 of the MOSFET 200 are substantially on a plane parallel to the first plane F1. The top surfaces of the gate electrode 40, field plate electrode 50, and conductive layer 60 of the MOSFET 200 are substantially in the same plane as the first plane F1.

[0134] 14, the field plate electrode 50 is connected to the source electrode wiring 10x on the conductive layer 60 side of the end (Ex in FIG. 14) in the first direction of the first face F1 of the field plate insulating layer 55. In other words, the field plate electrode 50 is connected to the source electrode wiring 10x directly above the trench 31. The field plate electrode 50 is electrically connected to the source electrode wiring 10x using a field plate contact plug 10xa. The field plate contact plug 10xa is in contact with the field plate electrode 50.

[0135] The gate electrode 40 of the MOSFET 200 is electrically connected to the gate electrode wiring 12x using a gate contact plug 12xa. The gate contact plug 12xa is directly connected to the first portion 40a and the second portion 40b, as shown in FIG. 16. The gate contact plug 12xa contacts the first portion 40a and the second portion 40b.

[0136] The MOSFET 200 can be manufactured, for example, by embedding the field plate electrode 50, the conductive layer 60, and the gate electrode 40 in the trench 31, and then planarizing the surfaces of each electrode using a chemical mechanical polishing method (CMP method) or the like.

[0137] As with the first embodiment, the MOSFET 200 of the second embodiment reduces gate capacitance, enabling a faster MOSFET. Furthermore, the MOSFET 200 of the second embodiment allows, for example, the field plate contact plug 10xa and the gate contact plug 12xa to have the same opening depth when they are formed. This allows the field plate contact plug 10xa and the gate contact plug 12xa to be easily formed.

[0138] (First Modification) The semiconductor device of the first modified example of the second embodiment differs from the semiconductor device of the second embodiment in that the conductive layer is electrically connected to the gate electrode.

[0139] Fig. 17 is a schematic cross-sectional view of a part of a semiconductor device according to a first modified example of the second embodiment. Fig. 17 is a cross-section taken along line II' in Fig. 18. Fig. 17 is a view corresponding to Fig. 14 of the second embodiment.

[0140] Fig. 18 is a schematic top view of a part of a semiconductor device according to a first modified example of the second embodiment, and corresponds to Fig. 15 of the second embodiment.

[0141] Fig. 19 is a schematic cross-sectional view of a part of a semiconductor device according to a first modified example of the second embodiment. Fig. 19 is a cross-section taken along line JJ' in Fig. 18. Fig. 19 is a view corresponding to Fig. 16 of the second embodiment.

[0142] 20 is a schematic cross-sectional view of a part of a semiconductor device according to a first modification of the second embodiment, taken along the line KK' in FIG.

[0143] The semiconductor device of the first modified example of the second embodiment is a MOSFET 201. In the MOSFET 201, as shown in FIG. 20 , the gate contact plug 12xa is directly connected to the conductive layer 60 in addition to the first portion 40a and the second portion 40b. The conductive layer 60 is electrically connected to the gate electrode wiring 12x and electrically connected to the gate electrode 40. The conductive layer 60 is connected to the gate electrode wiring 12x using the same gate contact plug 12xa as the gate electrode 40.

[0144] Since the gate electrode 40 and the conductive layer 60 have the same potential, even if the gate electrode 40 and the conductive layer 60 face each other in the second direction, the gate capacitance does not increase.

[0145] Also in the MOSFET 201, similar to the MOSFET 200 of the second embodiment, the second distance d2 is larger than the first distance d1. Therefore, the distance between the gate electrode 40 and the field plate electrode 50 in a plane parallel to the first plane is large near the end Ex of the trench 31 in the first direction. Therefore, similar to the MOSFET 200 of the second embodiment, the gate-source capacitance of the MOSFET 201 is reduced. This reduces the gate capacitance of the MOSFET 201, enabling the MOSFET 201 to operate at a higher speed.

[0146] In MOSFET 201, conductive layer 60 has the same potential as gate electrode 40, and therefore the capacitance between conductive layer 60 and field plate electrode 50 becomes the gate-source capacitance. The gate-source capacitance of MOSFET 201 can be reduced by, for example, increasing the thickness of first interelectrode insulating layer 71.

[0147] According to the MOSFET 201 of the first modification of the second embodiment, the gate capacitance is reduced, and the speed of the MOSFET can be increased, similarly to the second embodiment.

[0148] (Second Modification) The semiconductor device of the second modified example of the second embodiment differs from the semiconductor device of the second modified example of the second embodiment in that the conductive layer is connected to the gate electrode wiring using a gate contact plug that is different from the gate electrode.

[0149] Fig. 21 is a schematic cross-sectional view of a part of a semiconductor device according to a second modification of the second embodiment. Fig. 21 is a cross-section taken along line LL' in Fig. 22. Fig. 21 is a view corresponding to Fig. 17 of the first modification of the second embodiment.

[0150] Fig. 22 is a schematic top view of a part of a semiconductor device according to a second modification of the second embodiment, and corresponds to Fig. 18 of the first modification of the second embodiment.

[0151] Fig. 23 is a schematic cross-sectional view of a part of a semiconductor device according to a second modified example of the second embodiment. Fig. 23 is a cross-section taken along line MM' in Fig. 22. Fig. 23 is a view corresponding to Fig. 19 of the first modified example of the second embodiment.

[0152] Fig. 24 is a schematic cross-sectional view of a part of a semiconductor device according to a second modification of the second embodiment. Fig. 24 is a cross-section taken along line NN' in Fig. 22. Fig. 24 is a view corresponding to Fig. 20 of the first modification of the second embodiment.

[0153] 25 is a schematic cross-sectional view of a part of a semiconductor device according to a second modification of the second embodiment, taken along line OO' in FIG.

[0154] The semiconductor device of the second modification of the second embodiment is a MOSFET 202. As shown in FIG. 24, in the MOSFET 202, the gate contact plug 12xa is directly connected to the first portion 40a and the second portion 40b. Also, as shown in FIG. 25, in the MOSFET 202, the gate contact plug 12xa is directly connected to the conductive layer 60. The conductive layer 60 is connected to the gate electrode wiring 12x using the gate contact plug 12xa that is different from the gate electrode 40.

[0155] According to the MOSFET 202 of the second modification of the second embodiment, the gate capacitance is reduced, and the speed of the MOSFET can be increased, similarly to the second embodiment.

[0156] In the embodiment, the semiconductor layer is made of single crystal silicon, but the semiconductor layer is not limited to single crystal silicon. For example, the semiconductor layer may be made of other single crystal semiconductors such as single crystal silicon carbide.

[0157] In the embodiment, the first conductivity type is n-type and the second conductivity type is p-type, but it is also possible to configure the first conductivity type as p-type and the second conductivity type as n-type.

[0158] Although several embodiments of the present invention have been described, these embodiments are presented as examples and are not intended to limit the scope of the invention. These novel embodiments may be embodied in various other forms, and various omissions, substitutions, and modifications may be made without departing from the spirit of the invention. For example, components of one embodiment may be replaced or changed with components of another embodiment. These embodiments and modifications thereof are included within the scope and spirit of the invention, and are also included in the scope of the invention and its equivalents as defined in the claims. [Explanation of symbols]

[0159] 10 source electrode (first electrode) 10x source electrode wires 12 Gate electrode pad 12x gate electrode wiring 20 Drain electrode (second electrode) 30 Semiconductor layer 31 Trench 34 drift region (first semiconductor region) 35 Body region (second semiconductor region) 36 source region (third semiconductor region) 40 gate electrode 40a First Part 40b Second part 40c Third Part 45 Gate insulating layer 50 Field plate electrode 55 Field plate insulating layer 60 Conductive layer 71 First inter-electrode insulating layer (first insulating layer) 72 Second inter-electrode insulating layer (second insulating layer) 73 Third inter-electrode insulating layer (third insulating layer) 100 MOSFET (semiconductor device) 200 MOSFET (semiconductor device) Ex end F1 First Side F2 Second side d1 First distance d2 Second distance θ angle

Claims

1. a first electrode; a second electrode; and a semiconductor layer provided between the first electrode and the second electrode, the semiconductor layer having a first surface facing the first electrode and a second surface facing the second electrode, a first semiconductor region of a first conductivity type electrically connected to the second electrode; a second semiconductor region of a second conductivity type provided between the first semiconductor region and the first surface; a third semiconductor region of the first conductivity type provided between the second semiconductor region and the first surface and electrically connected to the first electrode; a semiconductor layer comprising: a gate electrode provided in the semiconductor layer, the gate electrode including a first portion extending in a first direction parallel to the first surface, and a second portion positioned relative to the first portion in a second direction parallel to the first surface and perpendicular to the first direction; a field plate electrode provided in the semiconductor layer, between the gate electrode and the second surface, and electrically connected to the first electrode; a conductive layer provided in the semiconductor layer, between the first portion and the second portion, and electrically isolated from the first electrode; a gate insulating layer provided between the gate electrode and the semiconductor layer; a field plate insulating layer provided between the field plate electrode and the semiconductor layer; a first insulating layer provided between the conductive layer and the field plate electrode; a second insulating layer provided between the first portion and the conductive layer; a third insulating layer provided between the second portion and the conductive layer; Equipped with a first distance in the first direction between an end of the field plate insulating layer in the first direction on the first surface and the conductive layer is smaller than a second distance in the first direction between the end and the gate electrode.

2. 2. The semiconductor device according to claim 1, wherein said conductive layer is electrically isolated from said gate electrode.

3. 2. The semiconductor device according to claim 1, wherein said conductive layer is floating.

4. 2. The semiconductor device according to claim 1, wherein said conductive layer is electrically connected to said gate electrode.

5. 2. The semiconductor device according to claim 1, wherein the difference between said second distance and said first distance is greater than the depth of said field plate insulating layer.

6. 2. The semiconductor device according to claim 1, wherein the difference between said second distance and said first distance is 10 [mu]m or more.

7. 2. The semiconductor device according to claim 1, wherein a thickness of said first insulating layer between said conductive layer and said field plate electrode in a third direction perpendicular to said first direction and said second direction is greater than a thickness of said gate insulating layer in said second direction.

8. 2. The semiconductor device according to claim 1, wherein a thickness of said first insulating layer between said conductive layer and said field plate electrode in a third direction perpendicular to said first direction and said second direction is at least twice a thickness of said gate insulating layer in said second direction.

9. 2. The semiconductor device according to claim 1, wherein an angle between an interface between said conductive layer and said first insulating layer and said first surface at an end of said conductive layer in said first direction is 60 degrees or less.

10. a gate electrode pad provided on the first surface side of the semiconductor layer; a gate electrode wiring provided on the first surface side of the semiconductor layer, extending in the second direction, connected to the gate electrode pad, and connected to the gate electrode; a source electrode wiring provided on the first surface side of the semiconductor layer, extending in the second direction, connected to the first electrode, and connected to the field plate electrode; 2. The semiconductor device according to claim 1, wherein said gate electrode wiring is provided between said source electrode wiring and said first electrode in said first direction.

11. a gate electrode pad provided on the first surface side of the semiconductor layer; a gate electrode wiring provided on the first surface side of the semiconductor layer and connected to the gate electrode pad, the gate electrode further includes a third portion extending in the second direction and connecting the first portion and the second portion; 2. The semiconductor device according to claim 1, wherein said gate electrode is connected to said gate electrode wiring immediately above said third portion.

12. a source electrode wiring provided on the first surface side of the semiconductor layer and connected to the first electrode, 2. The semiconductor device according to claim 1, wherein said field plate electrode is connected to said source electrode wiring on a side closer to said conductive layer than said end portion.

Images