Method of manufacturing semiconductor device

Abstract

To provide a method of manufacturing a semiconductor device capable of appropriately etching a workpiece.SOLUTION: According to one embodiment, a method of manufacturing a semiconductor device includes alternately switching between supplying a first gas not containing halogen onto a processing object in which a recess is formed without supplying a high-frequency voltage and forming a surface layer containing a component of the first gas on a surface of the processing object in a state where the processing object is cooled, and supplying a second gas containing halogen onto the processing object while supplying a high-frequency voltage and etching the processing object using plasma generated from the second gas to process the recess.SELECTED DRAWING: Figure 2

Description

[Technical Field]

[0001] FIELD An embodiment of the present invention relates to a method for manufacturing a semiconductor device. [Background technology]

[0002] When manufacturing semiconductor devices such as three-dimensional semiconductor memories, recesses are sometimes formed in the workpiece by etching. When forming the recesses, the sidewalls of the recesses are sometimes protected with a protective film. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Patent Publication No. 2021-19185 Summary of the Invention [Problem to be solved by the invention]

[0004] A method for manufacturing a semiconductor device that can appropriately etch an object to be processed is provided. [Means for solving the problem]

[0005] According to one embodiment, a method for manufacturing a semiconductor device includes alternating between supplying a first gas that does not contain a halogen onto a workpiece having a recess formed therein without supplying a high-frequency voltage, and forming a surface layer containing components of the first gas on the surface of the workpiece while the workpiece is cooled, and supplying a second gas that contains a halogen onto the workpiece while supplying a high-frequency voltage, and etching the workpiece to form a recess using plasma generated from the second gas. [Brief explanation of the drawings]

[0006] [Figure 1] 1 is a diagram showing an example of the configuration of a semiconductor manufacturing apparatus that can be used in the semiconductor device manufacturing method according to the first embodiment. [Figure 2]3 is a flowchart showing a method for manufacturing the semiconductor device according to the first embodiment. [Figure 3] 2A to 2C are cross-sectional views illustrating a method for manufacturing the semiconductor device according to the first embodiment. [Figure 4] 4 is a time chart showing the method for manufacturing the semiconductor device according to the first embodiment. [Figure 5] 5A to 5C are diagrams showing examples of a first gas and a second gas in the method for manufacturing a semiconductor device according to the first embodiment. [Figure 6] 4A to 4C are cross-sectional views showing the method for manufacturing the semiconductor device according to the first embodiment, following FIG. 3. [Figure 7] 7A to 7C are cross-sectional views showing the method for manufacturing the semiconductor device according to the first embodiment, following FIG. 6. [Figure 8] 8A to 8C are cross-sectional views showing the method for manufacturing the semiconductor device according to the first embodiment, following FIG. 7. [Figure 9] 10 is a flowchart showing a method for manufacturing a semiconductor device according to a second embodiment. [Figure 10] 10 is a time chart showing a method for manufacturing a semiconductor device according to a second embodiment. [Figure 11] 5A to 5C are cross-sectional views illustrating a method for manufacturing a semiconductor device according to a second embodiment. [Figure 12] 12A to 12C are cross-sectional views showing the method for manufacturing the semiconductor device according to the second embodiment, following FIG. 11. [Figure 13] 10 is a flowchart showing a method for manufacturing a semiconductor device according to a third embodiment. [Figure 14] 10 is a time chart showing a method for manufacturing a semiconductor device according to a third embodiment. [Figure 15] 10A to 10C are cross-sectional views showing a method for manufacturing a semiconductor device according to a third embodiment. [Figure 16] 16A to 16C are cross-sectional views showing the method for manufacturing the semiconductor device according to the third embodiment, following FIG. 15. [Figure 17] 10A to 10C are cross-sectional views showing a method for manufacturing a semiconductor device according to a fourth embodiment. [Figure 18]18A to 18C are cross-sectional views showing the method for manufacturing the semiconductor device according to the fourth embodiment, following FIG. 17. DETAILED DESCRIPTION OF THE INVENTION

[0007] Hereinafter, embodiments will be described with reference to the drawings. To facilitate understanding of the description, the same components in the drawings will be denoted by the same reference numerals as much as possible, and duplicated descriptions will be omitted.

[0008] (First embodiment) Fig. 1 is a diagram showing an example of the configuration of a semiconductor manufacturing apparatus 1 that can be used in the semiconductor device manufacturing method according to the first embodiment. As shown in Fig. 1, the semiconductor manufacturing apparatus 1 includes a processing chamber 2 (i.e., a chamber), a lower electrode 3, an upper electrode 4, a gas supply unit 5, a gas exhaust unit 6, a cooling device 7, a power supply unit 8, and a control circuit 9.

[0009] The processing chamber 2 is a space in which the workpiece 10 can be etched by sputtering using plasma (i.e., plasma etching). In the processing chamber 2, holes (i.e., recesses) are formed in the workpiece 10 by etching. The holes can also be called openings. The processing chamber 2 may have a door (gate) for loading and unloading the workpiece 10.

[0010] The lower electrode 3 functions as a mounting table for placing the workpiece 10. The lower electrode 3 has a surface 3a which is a mounting surface for the workpiece 10. The semiconductor manufacturing apparatus 1 may have an electrostatic chuck for holding the workpiece 10 on the surface 3a.

[0011] The upper electrode 4 has a surface 4a and an opening 4b for introducing a gas into the processing chamber 2 through the upper electrode 4. The opening 4b has a plurality of inlets on the surface 4a.

[0012] The gas supply unit 5 includes a gas supply source 51 such as a cylinder cabinet, and a mass flow controller 52. The gas supply unit 5 supplies gas from the gas supply source 51 to the processing chamber 2.

[0013] The gas supply source 51 contains a first gas, a second gas, and a third gas, which are each contained in a container such as a gas cylinder.

[0014] The first gas is a gas used to form a surface layer on the surface of the workpiece 10. The first gas is a gas that does not contain a halogen. For example, the first gas is a gas that does not contain fluorine as a halogen. The first gas is, for example, an inorganic gas that does not contain a halogen. The inorganic gas that does not contain a halogen is, for example, water vapor or hydrogen peroxide. The first gas may be an organic gas that does not contain a halogen, such as an organic solvent gas. The organic gas that does not contain a halogen is, for example, at least one compound represented by the general formula R—OH, R—CHO, R—COOH, R—NO, R—NH, R—OCO—R, R—CN, R—O—R, or CxHy (x and y are integers). Specifically, the organic gas that does not contain a halogen is CH 14 O2 (butyl propionate), C3H4O (acrolein: 2-propenal), C3H3N (acrylonitrile: propenenitrile), C7H 10 O3 (allyl acetoacetate), C3H6O (allyl alcohol: 2-propen-1-ol), C8H 14 (Allylcyclopentane), C7H8O (Anisole methoxybenzene), C8H 12 (1,4-cyclooctadiene), CH 12 (cis,cis-1,5-cyclooctadiene), CH 10 (1,3,5-cyclooctatriene), and CH 18 O(dibutyl ether).

[0015] The second gas is a gas used to etch the workpiece 10 on which a surface layer is formed. The second gas is a gas containing a halogen. The second gas is, for example, a gas containing fluorine as the halogen. The second gas is a gas having a lower condensation temperature than the first gas. That is, the first gas is a gas having a higher condensation temperature than the second gas. The second gas is, for example, a fluoride gas represented by the composition formula CxHyFz (where C represents carbon, H represents hydrogen, F represents fluorine, x represents an integer equal to or greater than 0, y represents an integer equal to or greater than 0, and z represents an integer equal to or greater than 1). The second gas may be HF gas. The second gas may further include a fluoride gas of a type different from the composition formula CxHyFz, such as SiF4 and PF3.

[0016] The third gas is a gas used in etching to remove a surface layer formed on the bottom surface of the hole in the object 10. The third gas is, for example, a rare gas such as Ar gas.

[0017] The mass flow controller 52 adjusts the flow rates of the first gas, the second gas, and the third gas introduced from the gas supply source 51 into the processing chamber 2, respectively.

[0018] The gas exhaust unit 6 has a valve 61, a turbo molecular pump 62, and a dry pump 63. The gas exhaust unit 6 reduces the pressure inside the processing chamber 2. The gas exhaust unit 6 is capable of reducing the pressure inside the processing chamber 2 to a vacuum state. The gas exhaust unit 6 also exhausts gas from inside the processing chamber 2.

[0019] The cooling device 7 includes a chiller 71 and a refrigerant pipe 72 provided inside the lower electrode 3. The chiller 71 cools the workpiece 10 on the lower electrode 3 by circulating a refrigerant through the refrigerant pipe 72. The power supply unit 8 includes a power supply 81 that supplies an AC voltage and a matching circuit 82 such as a matching box. The power supply unit 8 matches the impedance between the processing chamber 2 and the power supply 81 using the matching circuit 82, and supplies a radio frequency (RF) voltage to the processing chamber 2. The radio frequency voltage is, for example, an AC voltage having a frequency of 200 kHz or more and 200 MHz or less.

[0020] The control circuit 9 controls the mass flow controller 52, the power supply 81, the gas discharge unit 6, and the cooling device 7. The control circuit 9 is configured with hardware such as a processor, for example. In this case, a program for executing the processing of the control circuit 9 may be stored in a recording medium such as a memory, and the control circuit 9 may execute the processing by reading and executing the program stored in the recording medium.

[0021] Next, a method for manufacturing a semiconductor device according to the first embodiment, to which the semiconductor manufacturing apparatus 1 configured as above is applied, will be described.

[0022] FIG. 2 is a flowchart showing a method for manufacturing a semiconductor device according to the first embodiment. FIG. 3 is a cross-sectional view showing the method for manufacturing a semiconductor device according to the first embodiment. Specifically, FIG. 3 shows a part of an XZ cross section including an X axis along the surface of the substrate 101 and a Z axis along the thickness direction of the substrate 101, which is perpendicular to the X axis. FIG. 4 is a time chart showing the method for manufacturing a semiconductor device according to the first embodiment. FIG. 5 is a diagram showing an example of a first gas and a second gas in the method for manufacturing a semiconductor device according to the first embodiment. FIG. 6 is a cross-sectional view showing the method for manufacturing a semiconductor device according to the first embodiment, following FIG. 3.

[0023] 2, first, the object 10 is prepared (step S1). Specifically, the object 10 having the configuration shown in FIG.

[0024] 3, the object 10 includes a substrate 101, an underlayer 102 provided on the substrate 101, stacked films 103 and 104 having first layers 103 and second layers 104 alternately stacked on the underlayer 102, and a mask layer 106 provided on the stacked films 103 and 104. The mask layer 106 is provided with an opening H1 penetrating the mask layer 106 and having a sidewall H1A and a bottom surface H1B.

[0025] The substrate 101 may be, for example, a semiconductor substrate such as a silicon substrate or a silicon carbide substrate, an insulating substrate such as a glass substrate, a quartz substrate or a sapphire substrate, or a compound semiconductor substrate such as a GaAs substrate.

[0026] The base layer 102 may be, for example, an insulating film such as a silicon oxide film or a silicon nitride film, or a conductive layer between insulating films. The base layer 102 is not necessarily provided. If the base layer 102 is not provided, the first layer 103 or the second layer 104 is formed on the substrate 101.

[0027] 3, the first layer 103 is a sacrificial layer. The sacrificial layer is a region where a conductive layer will later be formed. That is, the sacrificial layer is a layer that is removed from between the second layers 104 by wet etching using a chemical solution such as phosphoric acid to be replaced with a conductive layer. The first layer 103 may be, for example, a silicon nitride film.

[0028] The second layer 104 may be, for example, a silicon oxide film.

[0029] The mask layer 106 functions as a mask for etching the object 10. The mask layer 106 is, for example, a carbon film formed by chemical vapor deposition (CVD).

[0030] After preparing the workpiece 10, a first etching (not shown) using the mask layer 106 is performed to form a hole H2 in the workpiece 10, the hole H2 continuing downward (in the -Z direction) from the opening H1 (FIG. 6). Note that the hole H2 shown in FIG. 6 is the hole H2 after processing has progressed through multiple etchings. When the hole H2 is first formed by the first etching, the hole H2 is shallow. After the hole H2 is formed, as shown in FIG. 2, a surface layer 11 is formed on the workpiece 10 in which the hole H2 has been formed (step S2, FIG. 6(a)). Note that the surface layer 11 may also be formed on the inner surface (e.g., sidewall H1A) of the mask layer 106 before or during the first etching to form the hole H2.

[0031] As shown in FIG. 4, in the step of forming the surface layer 11 (step S2), the control circuit 9 controls the mass flow controller 52 to introduce the first gas into the processing chamber 2 (first gas: ON). Also, in the step of forming the surface layer 11 (step S2), the control circuit 9 does not cause the power source 81 to supply a high-frequency voltage to the processing chamber 2 (RF: OFF). Also, the control circuit 9 controls the cooling device 7 to cool the workpiece 10 to a temperature not higher than the condensation temperature of the first gas and not lower than the condensation temperature of the second gas. Alternatively, the control circuit 9 may cool the workpiece 10 to a temperature not higher than the triple point temperature of the first gas and not lower than the triple point temperature of the second gas. Alternatively, the control circuit 9 may cool the workpiece 10 to a temperature not higher than the melting point of the first gas and not lower than the melting point of the second gas. For example, the control circuit 9 may cool the workpiece 10 to a temperature between −20° C. and −130° C. Such cooling of the object 10 continues in the etching step (step S4) after the step of forming the surface layer 11 (step S2). Therefore, in the first embodiment, the etching of the object 10 is performed in a cooled state of the object 10. Furthermore, the control circuit 9 controls the gas exhaust unit 6 to control the pressure in the processing chamber 2 to be higher than that during etching of the object 10 (pressure: High).

[0032] Through such control by the control circuit 9, a halogen-free first gas is supplied onto the workpiece 10 without supplying a high-frequency voltage, and a surface layer 11 containing components of the first gas is formed on the surface of the workpiece 10 after the workpiece 10 is cooled. More specifically, the surface layer 11 is preferably formed on the surface of the workpiece 10 after the workpiece 10 is cooled to a temperature below the condensation temperature of the first gas and above the condensation temperature of the second gas. More specifically, the surface layer 11 is preferably formed on the surface of the workpiece 10 under a pressure higher than that used during etching of the workpiece 10. As shown in FIG. 5 , when the first gas is water vapor (HO), the condensation temperature is, for example, −50°C, and when the second gas is hydrogen fluoride (HF), the condensation temperature is, for example, −80°C. In this case, the surface layer 11 is preferably formed on the surface of the workpiece 10 after the workpiece 10 is cooled to a temperature between −80°C and −50°C. Figure 5 is based on a description in the Journal of Vacuum Science & Technology A (February 27, 2023, Condensation temperatures of gases relevant for semiconductor etching. Values ​​from Ref. 146., p. 14, FIG. 17).

[0033] The step of forming the surface layer 11 (step S2) will be described in more detail. As shown in FIG. 6, the etching of the object 10 is performed so as to increase the depth of the hole H2 formed in the object 10 by repeating the etching. FIG. 6(a) shows a step of forming the surface layer 11 in the hole H2 after the etching of the object 10 has been repeated multiple times compared to FIG. 3. In FIG. 6(a), the mask layer 106 on the stacked films 103 and 104 is not shown. As shown in FIG. 6(a), the surface layer 11 includes a surface layer 11a formed on the side wall H2A of the hole H2. Also, as shown in FIG. 6(a), the surface layer 11 includes a surface layer 11b formed on the bottom surface H2B of the hole H2. That is, in the step of forming the surface layer 11 (step S2), the surface layer 11 is formed on both the side wall H2A and the bottom surface H2B of the hole H2.

[0034] The surface layer 11a formed on the sidewall H2A of the hole H2 protects the sidewall H2A during etching and can suppress bowing due to side etching. In contrast, the surface layer 11b formed on the bottom surface H2B of the hole H2 inhibits etching of the bottom surface H2B. To prevent the surface layer 11b formed on the bottom surface H2B of the hole H2 from inhibiting etching, as shown in FIG. 2, after the surface layer 11 is formed, the surface layer 11b formed on the bottom surface H2B of the hole H2 is removed (step S3).

[0035] 4, in the step of removing the surface layer 11b (step S3), the control circuit 9 controls the mass flow controller 52 to introduce a third gas into the processing chamber 2 instead of the first gas (first gas: OFF) (third gas: ON). The control circuit 9 also controls the power supply 81 to supply a high-frequency voltage to the processing chamber 2 (RF: ON). The control circuit 9 also controls the gas exhaust unit 6 to control the pressure in the processing chamber 2 to be lower than the pressure when the surface layer 11 is formed (pressure: Low).

[0036] Under such control by the control circuit 9, a third gas is supplied while a high-frequency voltage is supplied onto the workpiece 10, and the surface layer 11b formed on the bottom surface H2B of the hole H2 is removed by etching using plasma generated from the third gas (FIG. 6(b)). When the surface layer 11b formed on the bottom surface H2B of the hole H2 is removed, the sidewall H2A of the hole H2 is protected by the surface layer 11a formed on the sidewall H2A.

[0037] After the surface layer 11b formed on the bottom surface H2B of the hole H2 is removed, the workpiece 10 is etched (step S4) as shown in FIG. 2. By etching the workpiece 10, the hole H2 formed in the workpiece 10 is processed. The etching of the workpiece 10 is performed on the bottom surface H2B of the hole H2 while the sidewall H2A of the hole H2 is protected by the surface layer 11a formed on the sidewall H2A. As shown in FIG. 4, in the etching step of the workpiece 10 (step S4), the control circuit 9 controls the mass flow controller 52 to introduce the second gas into the processing chamber 2 instead of the third gas (third gas: OFF) (second gas: ON). The control circuit 9 also controls the power source 81 to continue supplying a high-frequency voltage to the processing chamber 2 (RF: ON). The control circuit 9 also maintains the pressure in the processing chamber 2 lower than that used when the surface layer 11 was formed (pressure: Low).

[0038] By such control by control circuit 9, a high-frequency voltage is supplied onto workpiece 10 while a second gas is supplied, and workpiece 10 is etched using plasma generated from the second gas.

[0039] FIG. 7 is a cross-sectional view illustrating the method for manufacturing a semiconductor device according to the first embodiment, subsequent to FIG. 6. In the example illustrated in FIG. 7, the workpiece 10 is etched by an etchant E (e.g., ions or radicals) in plasma generated from the second gas. As illustrated in FIG. 7, in the etching process of the workpiece 10, the sidewall H2A of the hole H2 is protected by the surface layer 11a. That is, instead of etching the sidewall H2A of the hole H2, the surface layer 11a on the sidewall H2A is etched. Meanwhile, the surface layer 11b on the bottom surface H2B of the hole H2 is removed in the removal process (step S3). Therefore, etching in the hole H2 progresses in the depth direction (−Z direction) of the hole H2 while suppressing side etching (i.e., bowing). Note that in the example illustrated in FIG. 7(a), one etching of the workpiece 10 removes one layer of the first layer 103 compared to the state before etching (see FIG. 6). In practice, a plurality of layers of the first layer 103 and the second layer 104 may be removed by etching the workpiece 10 once.

[0040] After etching the object 10, the formation of the surface layer 11 is repeated as shown in FIG. 7(b).

[0041] 2, the formation of the surface layer 11 (step S2), the removal of the surface layer 11b formed on the bottom surface H2B of the hole H2 (step S3), and the etching of the workpiece 10 (step S4) are sequentially repeated until the aspect ratio of the hole H2 reaches a desired value or more. The aspect ratio of the hole H2 is the ratio of the dimension of the hole H2 in the Z direction (i.e., height) to the dimension of the hole H2 in the X direction (i.e., width). Increasing the aspect ratio of the hole H2 to a desired value or more may be achieved by performing the processes from step S2 to step S4 a preset number of times.

[0042] After the aspect ratio of the hole H2 reaches a desired value or more, a memory layer is formed in the hole H2 (i.e., the memory hole) as shown in FIG. 2 (step S5). FIG. 8 is a cross-sectional view showing the method for manufacturing the semiconductor device according to the first embodiment, subsequent to FIG. 7. In the memory layer formation process (step S5), a memory film 109 including a block insulating film 193, a charge storage layer 192, and a tunnel insulating film 191, a semiconductor channel layer 108, and a core insulating film 107 are formed in this order in the hole H2. The core insulating film 107, the semiconductor channel layer 108, and the memory film 109 function as a memory layer that constitutes a memory cell.

[0043] The core insulating film 107 may be, for example, a silicon oxide film. The semiconductor channel layer 108 may be, for example, a polysilicon layer. The tunnel insulating film 191 may be, for example, a stacked film having a silicon oxide film and a silicon oxynitride film. The charge storage layer 192 may be, for example, a silicon nitride film. The block insulating film 193 may be, for example, a silicon oxide film.

[0044] After forming the memory film 109, the first layer 103 is removed by wet etching to form a cavity between the first layer 103 and the second layer 104. After forming the cavity, a plurality of conductive films are stacked in the cavity to form a conductive layer 110. The conductive layer 110 functions as, for example, a gate electrode (word line). Furthermore, contact plugs, wiring, interlayer insulating films, etc. are formed on the substrate 101. This allows the semiconductor device to be manufactured.

[0045] As described above, the semiconductor device manufacturing method according to the first embodiment includes alternately switching between supplying a halogen-free first gas onto a workpiece 10 having a hole H2 (i.e., a recess) formed therein without supplying a high-frequency voltage, and forming a surface layer 11 containing components of the first gas on the surface of the workpiece 10 while the workpiece 10 is cooled, and supplying a halogen-containing second gas onto the workpiece 10 while supplying a high-frequency voltage, and etching the workpiece 10 with plasma generated from the second gas to form the hole H2. In other words, the semiconductor device manufacturing method according to the first embodiment includes alternately switching between supplying a halogen-free second gas onto the workpiece 10 while supplying a high-frequency voltage, and etching the workpiece 10 with plasma generated from the second gas to form the hole H2, and supplying a halogen-free first gas onto the workpiece 10 having a hole H2 formed therein without supplying a high-frequency voltage, and forming a surface layer 11 containing components of the first gas on the surface of the workpiece 10. That is, in the method for manufacturing the semiconductor device according to the first embodiment, the formation of the surface layer 11 and the processing of the hole H2 by etching are alternately switched.

[0046] Here, when the workpiece 10 is etched while cooled by the cooling device 7 as described above (i.e., cryogenic etching), the etching rate can be improved. However, when the workpiece 10 is etched while cooled, it may be difficult to form a protective film that protects the sidewall H2A due to a chemical reaction of the etching gas. If it is difficult to form a protective film due to a chemical reaction of the etching gas, it is difficult to protect the sidewall H2A with the protective film. The difficulty in protecting the sidewall H2A makes it difficult to suppress bowing.

[0047] In contrast, according to the first embodiment, the surface layer 11 can be formed before etching, and the surface layer 11a formed on the sidewall H2A can appropriately protect the sidewall H2A. Therefore, even if the workpiece 10 is cooled to improve the etching rate, the sidewall H2A can be protected and bowing can be suppressed. Furthermore, by using a halogen-free gas as the first gas used to form the surface layer 11, it is possible to reduce the influence on film formation conditions, such as changes in etching conditions caused by residual gas from the first gas. Furthermore, if a halogen-containing gas is used as the first gas to form the surface layer 11, bowing may occur when ions in the first gas collide with the sidewall H2A due to a reaction between the workpiece 10 to be protected and excess halogen contained in the first gas. Therefore, forming the surface layer 11 using a halogen-free first gas makes it possible to effectively suppress bowing.

[0048] In the first embodiment, the first gas preferably has a higher condensation temperature than the second gas, which makes it possible to easily form the surface layer 11.

[0049] In the first embodiment, the surface layer 11 is preferably formed in a state where the object 10 is cooled to a temperature equal to or lower than the condensation temperature of the first gas. This allows the surface layer 11 to be formed quickly, thereby improving the etching rate.

[0050] In the first embodiment, the surface layer 11 is preferably formed in a state in which the object 10 is cooled to a temperature equal to or higher than the condensation temperature of the second gas. This effectively prevents the second gas from solidifying during etching after the formation of the surface layer 11, thereby further improving the etching rate.

[0051] In the first embodiment, the surface layer 11 is preferably formed under a pressure higher than that used when etching the object 10. This shortens the mean free path of particles in the first gas, thereby reducing the surface layer 11b formed on the bottom surface H2B of the hole H2, thereby further improving the etching rate. In the first embodiment, the surface layer 11b on the bottom surface H2B of the hole H2 is removed in the removal step (step S3), so pressure control is not required.

[0052] In the first embodiment, the first gas is preferably an inorganic gas that does not contain halogen. The inorganic gas is preferably water vapor or hydrogen peroxide. This allows the surface layer 11 to be formed quickly and appropriately.

[0053] In the first embodiment, the second gas preferably contains a fluoride gas, which allows the object 10 to be appropriately etched.

[0054] In the first embodiment, it is preferable that the etching of the object 10 is performed so as to increase the depth of the hole H2 as the etching is repeated, and the surface layer 11 is formed on the sidewall H2A of the hole H2. This allows the bottom surface H2B of the hole H2 to be etched at a high etching rate while the sidewall H2A of the hole H2 is appropriately protected.

[0055] Moreover, in the first embodiment, it is preferable to further include removing the surface layer 11b formed on the bottom surface H2B of the hole H2 between the formation of the surface layer 11 and the etching of the object 10. This makes it possible to remove the surface layer 11b on the bottom surface H2B, which inhibits etching, and therefore further improve the etching rate.

[0056] In the first embodiment, the surface layer 11b formed on the bottom surface H2B of the hole H2 is preferably removed by etching using plasma generated from the third gas, thereby making it possible to appropriately remove the surface layer 11b on the bottom surface H2B of the hole H2.

[0057] (Second embodiment) Next, a second embodiment in which the surface layer 11 is formed except for the bottom surface H2B of the hole H2 will be described, focusing on the differences from the above-described embodiment.

[0058] Fig. 9 is a flowchart showing a method for manufacturing a semiconductor device according to the second embodiment, Fig. 10 is a time chart showing a method for manufacturing a semiconductor device according to the second embodiment, and Fig. 11 is a cross-sectional view showing a method for manufacturing a semiconductor device according to the second embodiment.

[0059] 2, an example has been described in which the surface layer 11 is formed on the sidewall H2A and bottom surface H2B of the hole H2, and then the surface layer 11b formed on the bottom surface H2B is removed. In contrast, in the examples shown in FIGS. 9 to 11, the surface layer 11 is formed on the sidewall H2A of the hole H2, excluding the bottom surface H2B of the hole H2. That is, in the examples shown in FIGS. 9 to 11, the surface layer 11 is formed under conditions that prevent the surface layer 11b from being formed on the bottom surface H2B of the hole H2 (step S2 in FIGS. 9 and 10).

[0060] For example, the control circuit 9 controls the gas exhaust unit 6 so that the pressure in the processing chamber 2 is higher than in the first embodiment, thereby preventing the formation of the surface layer 11b on the bottom surface H2B of the hole H2. When the pressure in the processing chamber 2 is higher, the mean free path of particles in the first gas becomes shorter. When the mean free path becomes shorter, the number of particles in the first gas that reach the bottom surface H2B of the hole H2 decreases, thereby preventing the formation of the surface layer 11b on the bottom surface H2B. In addition to increasing the pressure in the processing chamber 2, the control circuit 9 may also prevent the formation of the surface layer 11b on the bottom surface H2B of the hole H2 by, for example, adjusting the flow rate of the first gas.

[0061] 9 to 11, a step of removing the surface layer 11b formed on the bottom surface H2B of the hole H2 is not required. Therefore, in the examples shown in FIGS. 9 to 11, etching is performed (step S4 in FIGS. 9 and 10, FIG. 11(b)) immediately after the formation of the surface layer 11 (step S2 in FIGS. 9 and 10, FIG. 11(a)).

[0062] Fig. 12 is a cross-sectional view showing the method for manufacturing a semiconductor device according to the second embodiment, subsequent to Fig. 11. After etching the object 10, as shown in Fig. 12, formation of the surface layer 11 excluding the bottom surface H2B of the hole H2 is repeated for the object 10 with the increased depth of the hole H2.

[0063] As described above, in the second embodiment, the surface layer 11 is formed on the sidewall H2A of the hole H2 except for the bottom surface H2B of the hole H2. This makes it possible to omit the step of removing the surface layer 11b on the bottom surface H2B, thereby further improving the etching rate.

[0064] (Third embodiment) Next, a third embodiment in which the surface layer 11b on the bottom surface H2B of the hole H2 is used as an etchant will be described, focusing on the differences from the above-mentioned embodiments. Fig. 13 is a flowchart showing a method for manufacturing a semiconductor device according to the third embodiment. Fig. 14 is a time chart showing a method for manufacturing a semiconductor device according to the third embodiment. Fig. 15 is a cross-sectional view showing a method for manufacturing a semiconductor device according to the third embodiment.

[0065] 2, the surface layer 11b formed on the bottom surface H2B of the hole H2 functions as an etching inhibitor layer, and therefore the surface layer 11b on the bottom surface H2B is removed. In contrast, in the examples shown in FIGS. 13 to 15, the etching of the workpiece 10 is performed while the surface layer 11a formed on the sidewall H2A of the hole H2 protects the sidewall H2A, and the surface layer 11b formed on the bottom surface H2B of the hole H2 promotes etching. That is, in the examples shown in FIGS. 13 to 15, the surface layer 11a on the sidewall H2A of the hole H2 is used as a protective film, and the surface layer 11b on the bottom surface H2B of the hole H2 is used as an etchant.

[0066] Specifically, in the examples shown in FIGS. 13 to 15, after the surface layer 11 is formed to a desired thickness (step S2 in FIGS. 13 and 14, and FIG. 15(a)), the surface layer 11b on the bottom surface H2B of the hole H2 is not removed. Instead of removing the surface layer 11b on the bottom surface H2B of the hole H2, the object 10 is etched in a state in which the components of the first gas are added to the second gas (step S40 in FIGS. 13 and 14, and FIG. 15(b)). Note that achieving the desired thickness of the surface layer 11 may be achieved by supplying the first gas at a preset flow rate for a preset time.

[0067] More specifically, as shown in FIG. 14, the control circuit 9 controls the mass flow controller 52 to continuously supply the first gas during both the period for forming the surface layer 11 and the period for etching the workpiece 10. Also, as shown in FIG. 15, after the surface layer 11 is formed, including the bottom surface H2B of the hole H2 (FIG. 15(a)), the process proceeds to etching while leaving the surface layer 11b on the bottom surface H2B (FIG. 15(b)). Also, as shown in FIG. 14, in the step of forming the surface layer 11 (step S2), the control circuit 9 preferably controls the cooling device 7 so that the workpiece 10 is cooled to a temperature lower than the triple point temperature T1 of the first gas and the triple point temperature T2 of the second gas. Also, in the etching step (step S40), the control circuit 9 preferably controls the cooling device 7 so that the workpiece 10 is cooled to the temperature of the triple point T2 of the second gas. When the first gas is HO, the triple point temperature T1 is −50° C. at a pressure of 4 Pa. When the second gas is HF, the temperature T2 of the triple point is −80° C. at a pressure of 4 Pa.

[0068] For example, when the thickness of the surface layer 11b formed on the bottom surface H2B of the hole H2 is sufficiently thinner than the thickness of the surface layer 11a formed on the side wall H2A of the hole H2, the surface layer 11b can function as an etchant rather than an inhibitory layer. For example, the control circuit 9 can adjust the thickness of the surface layer 11b by adjusting the pressure in the processing chamber 2 and the supply amount of the first gas so that the thickness of the surface layer 11b remains at a thickness that allows the surface layer 11b to function as an etchant.

[0069] Fig. 16 is a cross-sectional view showing the method for manufacturing a semiconductor device according to the third embodiment, following Fig. 15. After the object 10 is etched, as shown in Fig. 16, formation of the surface layer 11 is repeated on the object 10 with the hole H2 having an increased depth.

[0070] According to the third embodiment, the surface layer 11a formed on the side wall H2A of the hole H2 functions as a protective film, and the surface layer 11b formed on the bottom surface H2B of the hole H2 functions as an etchant, thereby further improving the etching rate while protecting the side wall H2A.

[0071] (Fourth embodiment) Next, a fourth embodiment in which sidewall H2A is protected by a reaction product produced by etching will be described, focusing on the differences from the above-described embodiments. Fig. 17 is a cross-sectional view showing a method for manufacturing a semiconductor device according to the fourth embodiment. Fig. 18 is a cross-sectional view showing the method for manufacturing a semiconductor device according to the fourth embodiment, subsequent to Fig. 17.

[0072] In the example shown in FIGS. 17 and 18, during the etching of the workpiece 10, a second surface layer 12 containing a reaction product P (FIG. 17(a)) generated by etching is formed on the sidewall H2A of the hole H2 (FIG. 17(b)). After the second surface layer 12 is formed, a surface layer 11 is formed on the sidewall H2A and bottom surface H2B of the hole H2 (FIG. 18(a)). After the surface layer 11 is formed, etching is repeated (FIG. 18(b)).

[0073] According to the fourth embodiment, the side wall H2A is protected by the surface layer 11 and the second surface layer 12, so that bowing can be more effectively suppressed.

[0074] In the above-described embodiment, the laminated films 103 and 104 are exemplified as the object 10. The object 10 is not limited to the laminated films 103 and 104, and may be, for example, a silicon film or a carbon film. Furthermore, in the above-described embodiment, the memory hole H2 is exemplified as the recess. The recess is not limited to the memory hole, and may be, for example, a via hole for embedding a via plug.

[0075] Although several embodiments have been described above, these embodiments are presented only as examples and are not intended to limit the scope of the invention. The novel wafers and methods described herein may be embodied in various other forms. Furthermore, various omissions, substitutions, and modifications may be made to the wafers and methods described herein without departing from the spirit of the invention. The appended claims and their equivalents are intended to cover such forms and modifications that fall within the scope and spirit of the invention. [Explanation of symbols]

[0076] 10 workpiece, 11 surface layer, H2 hole, H2A side wall, H2B bottom surface

Claims

1. supplying a first gas not containing a halogen onto a processing object having a recess formed therein without supplying a high frequency voltage, and forming a surface layer containing a component of the first gas on the surface of the processing object while the processing object is cooled; supplying a second gas containing the halogen onto the object while supplying the high-frequency voltage, and etching the object using plasma generated from the second gas to process the recessed portion; and (c) alternately switching between the above.

2. 2. The method for manufacturing a semiconductor device according to claim 1, wherein said first gas has a higher condensation temperature than said second gas.

3. The method for manufacturing a semiconductor device according to claim 2 , wherein the surface layer is formed in a state where the object is cooled to a temperature equal to or lower than a condensation temperature of the first gas.

4. The method for manufacturing a semiconductor device according to claim 3 , wherein the surface layer is formed in a state where the object is cooled to a temperature equal to or higher than a condensation temperature of the second gas.

5. The method for manufacturing a semiconductor device according to claim 1 , wherein the surface layer is formed under a pressure higher than that when the object is etched.

6. 2. The method for manufacturing a semiconductor device according to claim 1, wherein said first gas is an inorganic gas that does not contain said halogen.

7. 7. The method for manufacturing a semiconductor device according to claim 6, wherein the inorganic gas is water vapor or hydrogen peroxide.

8. 2. The method for manufacturing a semiconductor device according to claim 1, wherein the first gas is an organic gas that does not contain the halogen.

9. 2. The method for manufacturing a semiconductor device according to claim 1, wherein the second gas includes a fluoride gas.

10. The method for manufacturing a semiconductor device according to claim 1 , wherein the surface layer is formed on a side wall of the recess.

11. The method for manufacturing a semiconductor device according to claim 10 , wherein the surface layer is also formed on the bottom surface of the recess.

12. 12. The method for manufacturing a semiconductor device according to claim 11, further comprising removing the surface layer formed on a bottom surface of the recess between forming the surface layer and etching the object.

13. The method for manufacturing a semiconductor device according to claim 12, wherein the surface layer formed on the bottom surface of the recess is removed by etching using plasma generated from a third gas.

14. The method for manufacturing a semiconductor device according to claim 10 , wherein the surface layer is formed on the sidewall of the recess except for the bottom surface of the recess.

15. 12. The method for manufacturing a semiconductor device according to claim 11, wherein the etching of the object to be processed is performed while the sidewalls of the recess are protected by the surface layer formed on the sidewalls of the recess and while the etching is promoted by the surface layer formed on the bottom surface of the recess.

16. 16. The method for manufacturing a semiconductor device according to claim 15, wherein the etching of the object is performed in a state in which a component of the first gas is added to the second gas.

17. 17. The method for manufacturing a semiconductor device according to claim 16, wherein the first gas is supplied continuously both during a period in which the surface layer is formed and during a period in which the object is etched.

18. 11. The method for manufacturing a semiconductor device according to claim 10, wherein etching the object includes forming a second surface layer containing a reaction product produced by the etching on a side wall of the recess.

Images