Display device

Abstract

To provide a display device capable of improving display quality by outputting light to a plurality of regions with different luminance in a display region divided into the plurality of regions.SOLUTION: The display device includes a base layer including a display area in which a plurality of pixels are disposed and a non-display area disposed around the display area, a first power line electrically connected to the plurality of pixels, and a second power line electrically connected to the plurality of pixels. The display area may be divided into a plurality of areas, and the second power line may include a second first power line configured to apply the first voltage to a first pixel disposed in a first area of the plurality of areas and a second second power line configured to apply the second voltage to a second pixel disposed in a second area of the plurality of areas. The first voltage has a voltage level different from that of the second voltage during a first period, and the first voltage has the same voltage level as that of the second voltage during a second period other than the first period.SELECTED DRAWING: Figure 5

Description

[Technical Field]

[0001] The present invention relates to a display device, and more particularly to a display device with improved display quality in the display area. [Background technology]

[0002] Generally, electronic devices that provide images to users, such as smartphones, digital cameras, laptops, navigation systems, and smart televisions, include a display device for displaying the images. The display device generates an image and provides the generated image to the user through a display screen.

[0003] The display device includes a plurality of pixels for generating an image, a scan driving circuit for applying scan signals to the pixels, a data driving unit for applying data voltages to the pixels, and an emission driving unit for applying emission signals to the pixels. The pixels receive the data voltages in response to the scan signals, and display an image by emitting light of a brightness corresponding to the data voltages in response to the emission signals.

[0004] A pixel can display moving and still images. When a pixel displays moving images, it can receive continuously updated images. When a pixel displays still images, it can maintain the image it was initially provided with and subsequently receive no images. [Prior art documents] [Patent documents]

[0005] [Patent Document 1] International Publication WO2012 / 052886 [Patent Document 2] Korean Patent No. 10-2449048 (KR10-2449048B) Summary of the Invention [Problem to be solved by the invention]

[0006] An object of the present invention is to provide a display device capable of improving display quality by outputting light with different luminance to a plurality of regions in a display area divided into a plurality of regions. [Means for solving the problem]

[0007] A display device according to an embodiment of the present invention includes a base layer including a display area in which a plurality of pixels are arranged and a non-display area arranged around the display area, a first power line electrically connected to the plurality of pixels, and a second power line electrically connected to the plurality of pixels. The display area is divided into a plurality of regions, and the second power line includes a 2-1 power line applying a first voltage to a first pixel arranged in a first region among the plurality of regions, and a 2-2 power line applying a second voltage to a second pixel arranged in a second region among the plurality of regions. During a first period, the first voltage has a voltage level different from that of the second voltage, and during a second period excluding the first period, the first voltage has a voltage level equal to that of the second voltage.

[0008] Each of the plurality of pixels may include a pixel driving unit disposed on the base layer and including a transistor, and a light-emitting element disposed on the transistor, the light-emitting element including a first electrode, an intermediate layer disposed on the first electrode, and a second electrode disposed on the intermediate layer, wherein the first power line is electrically connected to the transistor, and the second power line is electrically connected to the second electrode.

[0009] A display device according to an embodiment of the present invention may further include a separator that divides the display area into the plurality of regions and has an obtuse taper angle, and the second electrode may include a 2-1 electrode and a 2-2 electrode electrically separated by the separator, the 2-1 electrode being disposed in the first region and the 2-2 electrode being disposed in the second region.

[0010] The 2-1 electrode may be electrically connected to the 2-1 power line, and the 2-2 electrode may be electrically connected to the 2-2 power line.

[0011] A first connection portion may be defined in the second region, where the second-2 power line and the second-2 electrode are connected to each other.

[0012] The first connection portion may include a first layer, a second layer disposed on the first layer, and a third layer disposed on the second layer, and a side surface of the third layer may protrude outward from a side surface of the second layer, and the 2-2 electrode may be in contact with the side surface of the second layer.

[0013] A tip portion may be defined by the side surface of the third layer, and the 2-2 electrode may be partially cut by the tip portion.

[0014] The 2-2 power supply line may include the first connection portion, and the 2-2 electrode may be in contact with the 2-2 power supply line.

[0015] The display device according to an exemplary embodiment of the present invention may further include a connection line disposed on a layer different from the second power line and electrically connected to the second power line through a contact hole.

[0016] The connecting wire may include the first connection portion, and the 2-2 electrode may be in contact with the connecting wire.

[0017] A second connection portion may be defined in the first region, where the 2-1 power line and the 2-1 electrode are connected to each other.

[0018] The 2-1 power supply line may be disposed in the first region.

[0019] A display device according to one embodiment of the present invention may further include a pixel-defining film having an opening defined therein that exposes at least a portion of the first electrode, and the separator may be disposed on the pixel-defining film.

[0020] The second power line may further include a second-third power line that applies a third voltage to first pixels arranged in a third region among the plurality of regions, and the first voltage may have a voltage level different from a voltage level of the third voltage during the first period.

[0021] The second region and the third region may be spaced apart from each other with the first region interposed therebetween.

[0022] The second voltage and the third voltage may each have a voltage level lower than a voltage level of the first voltage.

[0023] A plurality of 2-2 power lines may be provided, and the 2-2 power lines may be electrically connected to each of the second pixels.

[0024] The second-2 power line may extend in a first direction and be disposed in the display area.

[0025] During the first period, the first voltage may have a voltage level higher than a voltage level of the second voltage.

[0026] The first power supply line may apply a first power supply voltage to the pixel, and the first power supply voltage may have a voltage level higher than each of the first voltage and the second voltage.

[0027] A display device according to an embodiment of the present invention may further include a pad unit disposed in the non-display area, the pad unit including a first voltage pad for receiving the first power supply voltage and a second voltage pad for receiving each of the first voltage and the second voltage, the first voltage pad being electrically connected to a first power supply line and the second voltage pad being connected to the second power supply line.

[0028] The second voltage pads may include a 2-1 voltage pad that applies the first voltage to the 2-1 power line and a 2-2 voltage pad that applies the second voltage to the 2-2 power line.

[0029] A display device according to an embodiment of the present invention includes: (1) a base layer including a first region and a second region surrounded by the first region; (2) a driving element layer disposed on the base layer and including a pixel driving unit; (3) a light-emitting element disposed on the driving element layer and including a first electrode, an intermediate layer disposed on the first electrode, and a second electrode disposed on the intermediate layer; (4) a first power line electrically connected to the first electrode; and (5) a second power line electrically connected to the second electrode. The second electrode includes a 2-1 electrode disposed in the first region and electrically connected to a 2-1 power line of the second power line, and a 2-2 electrode disposed in the second region and electrically connected to a 2-2 power line of the second power line. A first connection part connecting the 2-2 power line and the 2-2 electrode may be disposed in the second region.

[0030] The first connection portion may include a first layer, a second layer disposed on the first layer, and a third layer disposed on the second layer, and a side surface of the third layer may protrude outward from a side surface of the second layer, and the 2-2 electrode may be in contact with the side surface of the second layer.

[0031] A tip portion may be defined by the side surface of the third layer, and the 2-2 electrode may be partially interrupted by the tip portion.

[0032] The 2-1 power supply line may apply a first voltage to the 2-1 electrode, and the 2-2 power supply line may apply a second voltage to the 2-2 electrode.

[0033] During a first period, the first voltage may have a voltage level different from that of the second voltage, and during a second period excluding the first period, the first voltage may have a voltage level equal to that of the second voltage.

[0034] During the first section, The first voltage may have a voltage level higher than a voltage level of the second voltage.

[0035] A second connection portion where the 2-1 power line and the 2-1 electrode are connected to each other may be defined in the first region.

[0036] The 2-1 power supply line may be disposed in the first region.

[0037] The base layer may further include a third region spaced apart from the second region with the first region interposed therebetween.

[0038] The second electrode may further include a 2-3 electrode disposed in the third region, and a third connection portion may be defined in the third region, where the 2-3 power line of the second power line and the 2-3 electrode are connected to each other.

[0039] The display device according to an embodiment of the present invention may further include a separator that separates the first region from the second region and has an obtuse taper angle, and the 2-1 electrode and the 2-2 electrode may be electrically separated by the separator. [Effects of the Invention]

[0040] The display area may include a first area and a second area separated by a separator. A first voltage applied to a first pixel disposed in the first area may be different from a second voltage applied to a second pixel disposed in the second area. As a result, the first area and the second area may display images with different luminances in the same light-emitting period, thereby providing a display panel with improved display quality.

[0041] Furthermore, since it is only necessary to adjust the voltage level of the second voltage to increase the brightness of the second region, the second voltage can be tailored to have a voltage level required for the second pixel, thereby reducing power consumption. [Brief explanation of the drawings]

[0042] [Figure 1A] 1 is a perspective view of a display device according to an embodiment of the present invention; [Figure 1B] 1 is an exploded perspective view of a display device according to an embodiment of the present invention; [Figure 2] 1 is a simplified cross-sectional view of a display module according to one embodiment of the present invention; [Figure 3] 1 is a block diagram of a display device according to an embodiment of the present invention; [Figure 4A] 4 is a diagram (1) showing an equivalent circuit of one of the pixels shown in FIG. 3. [Figure 4B] 4 is a diagram (2) showing an equivalent circuit of one of the pixels shown in FIG. 3. [Figure 5] 2 is a plan view of a display panel and a driving circuit unit according to an embodiment of the present invention; [Figure 6] FIG. 6 is an enlarged view of the AA′ region shown in FIG. 5. [Figure 7] 7 is a cross-sectional view of the display module of the present invention taken along line II' in FIG. 6. [Figure 8A] FIG. 8 is an enlarged view of a region BB′ shown in FIG. 7. [Figure 8B] FIG. 8 is an enlarged view of a CC′ region shown in FIG. 7. [Figure 9] 1 is a cross-sectional view of a display module according to an embodiment of the present invention; [Figure 10A] 6 is a graph showing a voltage applied to a first pixel arranged in a first region shown in FIG. 5; [Figure 10B] 6 is a graph showing a voltage applied to a second pixel arranged in a second region shown in FIG. 5; [Figure 11A] 10 is a plan view of a display panel and a driving circuit unit according to another embodiment of the present invention; [Figure 11B] FIG. 11B is an enlarged view of the DD′ region shown in FIG. 11A. [Figure 11C] 11C is a cross-sectional view of a display device according to another embodiment of the present invention, corresponding to line II-II' shown in FIG. 11B. [Figure 12A] FIG. 1 is a plan view (1) of a display panel according to another embodiment of the present invention. [Figure 12B]FIG. 10 is a plan view (2) of a display panel according to another embodiment of the present invention. [Figure 12C] FIG. 3 is a plan view (3) of a display panel according to another embodiment of the present invention. DETAILED DESCRIPTION OF THE INVENTION

[0043] Because the present invention can be modified in various ways and can have various forms, specific embodiments are shown by way of example in the drawings and described in detail herein, but it should be understood that this is not intended to limit the invention to the particular disclosed form, and that the invention encompasses all modifications, equivalents, and alternatives falling within the spirit and technical scope of the invention.

[0044] In this specification, when a certain component (or region, layer, portion, etc.) is described as being "on," "coupled," or "bonded" to another component, it means that it can be directly disposed / coupled / bonded to the other component, or that a third component can be disposed therebetween.

[0045] The same reference numerals refer to the same elements, and in the drawings, thickness, proportions, and dimensions of elements are exaggerated for the purpose of efficiently explaining the technical contents.

[0046] "And / or" includes all combinations of one or more that the associated constructs may define.

[0047] Terms such as "first," "second," etc. may be used to describe various components, but the components should not be limited by these terms. These terms are used only to distinguish one component from another. For example, a first component may be referred to as a "second component," and similarly, a second component may be referred to as a "first component" without departing from the scope of the present invention. A singular expression includes a plural expression unless the context clearly dictates otherwise.

[0048] Furthermore, terms such as "under," "below," "on," and "above" are used to describe the relationship between components shown in the drawings. These terms are relative concepts and are described based on the directions shown in the drawings.

[0049] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. Furthermore, terms, such as terms defined in commonly used dictionaries, should be interpreted to have a meaning consistent with the meaning in the context of the relevant art, and are expressly defined herein unless they are interpreted as idealized or overly formal.

[0050] It should be understood that the use of terms such as "comprise" or "have" is intended to specify the presence of a stated feature, number, step, operation, component, part, or combination thereof, but does not preclude the possible presence or addition of one or more other features, numbers, steps, operations, components, parts, or combinations thereof.

[0051] Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

[0052] FIG. 1A is a perspective view of a display device according to an embodiment of the present invention, and FIG. 1B is an exploded perspective view of the display device according to an embodiment of the present invention.

[0053] 1A and 1B, the display device DD may be a device that is activated in response to an electrical signal. The display device DD may include various embodiments. For example, the display device DD may include a tablet, a laptop, a computer, a television, etc. In this embodiment, the display device DD is exemplarily illustrated as a smartphone.

[0054] The display device DD can display an image IM on a display surface FS parallel to each of the first direction DR1 and the second direction DR2 in a third direction DR3. The display surface FS on which the image IM is displayed may correspond to the front surface of the display device DD, or the front surface FS of the window WM. Hereinafter, the display surface, front surface, and front surface of the display device DD and the front surface of the window WM will be referred to by the same reference symbol FS. The image IM can include a static image as well as a dynamic image. In FIG. 1A, a clock window and an application icon are illustrated as examples of the image IM.

[0055] In this embodiment, the front (or upper) and back (or lower) surfaces of each component are defined based on the direction in which the image IM is displayed. The front and back surfaces are opposed to each other in a third direction DR3, and the normal directions of the front and back surfaces may be parallel to the third direction DR3. However, the directions indicated by the first to third directions DR1, DR2, and DR3 are relative concepts and may be converted to other directions.

[0056] The display device DD may include a window WM, a display module DM, a driving circuit unit DC, and a housing HU. In this embodiment, the window WM and the housing HU may be combined to form the exterior of the display device DD. Although not shown, the display device DD may further include an electronic module.

[0057] The window WM may include an optically transparent insulating material. For example, the window WM may include glass or plastic. The window WM may have a multi-layer (laminate) structure or a single-layer structure. For example, the window WM may include multiple plastic films bonded together with an adhesive, or a glass substrate and a plastic film bonded together with an adhesive.

[0058] The window WM may be divided into a transmissive area TA and a bezel area BZA on a plane. In this specification, the term "on a plane" may refer to a view from a third direction DR3. Also, the term "thickness direction" may refer to the third direction DR3.

[0059] The transmissive area TA may be an optically transparent area. The bezel area BZA may be an area having a relatively low light transmittance compared to the transmissive area TA. The bezel area BZA may define the shape of the transmissive area TA. The bezel area BZA may be adjacent to and surround the transmissive area TA.

[0060] The bezel area BZA may have a predetermined color. The bezel area BZA may cover the non-display area NDA of the display module DM to block the non-display area NDA from being viewed from the outside. However, this is illustrated as an example, and the bezel area BZA may be omitted in a window WM according to an embodiment of the present invention.

[0061] The display module DM may be disposed below the window WM. In this specification, "below" may refer to the direction opposite to the direction in which the display module DM provides an image. The display module DM may display an image IM and sense a user input TC. The display module DM includes a front surface including a display area DA and a non-display area NDA. The display area DA may also be referred to as an active area because it is an area that is activated in response to an electrical signal.

[0062] In this embodiment, the display area DA may be an area where an image IM is displayed and a user input TC is sensed. The transparent area TA may overlap the display area DA. For example, the transparent area TA may overlap the front surface of or at least a portion of the display area DA. Thus, a user can view the image IM or provide a user input TC through the transparent area TA.

[0063] The non-display area NDA may be an area covered by the bezel area BZA. The non-display area NDA is adjacent to the display area DA. The non-display area NDA may surround the display area DA. A drive circuit, drive wiring, etc. for driving the display area DA may be arranged in the non-display area NDA.

[0064] In this embodiment, the display module DM is assembled in a flat state with the display area DA and non-display area NDA facing the window WM. However, this is shown as an example, and a portion of the non-display area NDA may be curved. In this case, a portion of the non-display area NDA may face the rear surface of the display device DD, thereby reducing the area of ​​the bezel area BZA on the front surface of the display device DD. Alternatively, the display module DM may be assembled with a portion of the display area DA also curved. Alternatively, the non-display area NDA may be omitted in the display module DM according to an embodiment of the present invention.

[0065] The display area DA of the display module DM may include multiple areas. For example, the display area DA of the display module DM may include a first area AA1 and a second area AA2. The second area AA2 may be surrounded by the first area AA1. Although not shown, the display area DA may further include a third area spaced apart from the second area AA2. The first area AA1 and the second area AA2 will be described in detail below.

[0066] The driving circuit unit DC may be electrically connected to the display module DM and may include a main circuit board MB and a flexible film CF.

[0067] The flexible film CF is electrically connected to the display module DM. The flexible film CF may be connected to pads PD of the display module DM arranged in the non-display area NDA. The flexible film CF provides electrical signals to the display module DM for driving the display module DM. The electrical signals may be generated by the flexible film CF or the main circuit board MB.

[0068] The main circuit board MB can include various drive circuits for driving the display module DM, connectors for power supply, and the like.

[0069] The housing HU is coupled to the window WM, and the housing HU is coupled to the window WM to provide an interior space in which the display module DM can be accommodated.

[0070] The housing HU may include a material having a relatively high rigidity. For example, the housing HU may include a plurality of frames and / or plates made of glass, plastic, or metal, or a combination thereof. The housing HU may stably protect the components of the display device DD accommodated in its internal space from external impact.

[0071] FIG. 2 is a simplified cross-sectional view of a display module according to one embodiment of the present invention.

[0072] 2, the display module DM may include a display panel DP and a sensing layer ISL. The display panel DP may include a base layer BL, a driving element layer DDL, a light emitting element layer LDL, and an encapsulation layer TFE.

[0073] The base layer BL may be a flexible substrate that allows bending, folding, rolling, etc. The base layer BL may be a glass substrate, a metal substrate, a polymer substrate, etc. However, embodiments of the present invention are not limited thereto, and the base layer BL may be an inorganic layer, an organic layer, or a composite material layer. The base layer BL has substantially the same shape as the display panel DP.

[0074] The base layer BL may have a multi-layer structure. For example, the base layer BL may include a first synthetic resin layer, a second synthetic resin layer, and an inorganic layer disposed therebetween. Each of the first and second synthetic resin layers may include a polyimide-based resin, but is not particularly limited thereto.

[0075] The driving element layer DDL may be disposed on the base layer BL. The driving element layer DDL may include a plurality of insulating layers, a plurality of semiconductor patterns, a plurality of conductive patterns, signal lines, etc. The driving element layer DDL may include a pixel driving circuit. Hereinafter, unless otherwise specified, if structure A and structure B are disposed on the same layer, it is interpreted as being formed by the same process, containing the same material, or having the same layered structure. A conductive pattern or semiconductor pattern disposed on the same layer may be interpreted as described above.

[0076] The light-emitting element layer LDL may be disposed on the driving element layer DDL. The light-emitting element layer LDL may include a light-emitting element. For example, the light-emitting element may include an organic light-emitting material, an inorganic light-emitting material, an organic-inorganic light-emitting material, a quantum dot, a quantum rod, a micro LED, or a nano LED.

[0077] The encapsulating layer TFE may be disposed on the light-emitting element layer LDL. The encapsulating layer TFE can protect the light-emitting element layer LDL, i.e., the light-emitting element, from foreign substances such as moisture, oxygen, and dust particles. The encapsulating layer TFE may include at least one encapsulating inorganic layer. The encapsulating layer TFE may include a stacked structure of a first encapsulating inorganic layer / an encapsulating organic layer / a second encapsulating inorganic layer.

[0078] The sensing layer ISL may be disposed directly on the display panel DP. The sensing layer ISL may sense user input, for example, by an electromagnetic induction method or an electrostatic capacitance method. The display panel DP and the sensing layer ISL may be formed through a continuous process. Here, "directly disposed" may mean that no third component is disposed between the sensing layer ISL and the display panel DP. For example, a separate adhesive layer may not be disposed between the sensing layer ISL and the display panel DP.

[0079] FIG. 3 is a block diagram of a display device according to an embodiment of the present invention.

[0080] 3, the display device DD may include a display panel DP, a drive controller 100, a data drive circuit 200, a scan drive circuit SDC, an emission drive circuit EDC, and a voltage generator 300. The drive controller 100 may be defined as a timing controller.

[0081] The display panel DP may include a plurality of scan lines GIL1 to GILn, GCL1 to GCLn, GWL1 to GWLn, GBL1 to GBLn, a plurality of light emitting lines EML1 to EMLn, a plurality of data lines DL1 to DLm, and a plurality of pixels PX, where n and m may be natural numbers.

[0082] The planar area of ​​the display panel DP may include a display area DA and a non-display area NDA surrounding the display area DA. The pixels PX may be arranged in the display area DA. The pixels PX may be electrically connected to the scan lines GIL1 to GILn, GCL1 to GCLn, GWL1 to GWLn, GBL1 to GBLn, the light emitting lines EML1 to EMLn, and the data lines DL1 to DLm, respectively.

[0083] Each pixel PX may be electrically connected to four corresponding scan lines and one corresponding light-emitting line. For example, a pixel in the jth row may be connected to the jth scan lines GILj, GCLj, GWLj, and GBLj and the jth light-emitting line EMLj. j may be a natural number greater than 1 and less than n.

[0084] The scan lines GIL1 to GILn, GCL1 to GCLn, GWL1 to GWLn, and GBL1 to GBLn may include a plurality of initialization scan lines GIL1 to GILn, a plurality of compensation scan lines GCL1 to GCLn, a plurality of write scan lines GWL1 to GWLn, and a plurality of bias scan lines GBL1 to GBLn.

[0085] Each of the pixels PX may be connected to a corresponding one of the initialization scan lines GIL1 to GILn, a corresponding one of the compensation scan lines GCL1 to GCLn, a corresponding one of the write scan lines GWL1 to GWLn, and a corresponding one of the bias scan lines GBL1 to GBLn.

[0086] The scan driving circuit SDC may be disposed on a first side of the display panel DP. Scan lines GIL1 to GILn, GCL1 to GCLn, GWL1 to GWLn, and GBL1 to GBLn may extend from the scan driving circuit SDC in a first direction DR1.

[0087] The light emitting driving circuit EDC may be disposed on a second side of the display panel DP. The light emitting lines EML1 to EMLn may extend from the light emitting driving circuit EDC in a direction opposite to the first direction DR2.

[0088] 3, the scan drive circuit SDC and the emission drive circuit EDC are arranged opposite each other with the pixel PX in between, but the present invention is not limited to this. For example, the scan drive circuit SDC and the emission drive circuit EDC may be arranged adjacent to each other on either the first side or the second side of the display panel DP. In other embodiments, the scan drive circuit SDC and the emission drive circuit EDC may be configured as a single circuit.

[0089] The scan lines GIL1 to GILn, GCL1 to GCLn, GWL1 to GWLn, GBL1 to GBLn and the light emitting lines EML1 to EMLn may be arranged spaced apart from each other in the second direction DR2. The data lines DL1 to DLm may extend from the data driving circuit 200 in a direction opposite to the second direction DR2 and be arranged spaced apart from each other in the first direction DR1.

[0090] The drive controller 100 can receive the image signal RGB, the control signal CTRL, and the mode signal MFD_EN. The drive controller 100 can generate an image data signal DS by converting the data format of the image signal RGB so that it conforms to the interface specifications with the data drive circuit 200. The drive controller 100 can output a scan control signal SCS, a data control signal DCS, and a light emission control signal ECS in response to the control signal CTRL.

[0091] The data driving circuit 200 can receive a data control signal DCS and an image data signal DS from the driving controller 100. The data driving circuit 200 can convert the image data signal DS into a data signal and output the converted data signal. The data signal can be defined as an analog voltage corresponding to the gray level of the image data signal DS. The data signal can be applied to the pixels PX through the data lines DL1 to DLm.

[0092] The voltage generator 300 generates voltages necessary for the operation of the display panel DP. The voltage generator 300 generates a first power supply voltage ELVDD, a first voltage ELVSS1, a second voltage ELVSS2, a first initialization voltage VINT, and a second initialization voltage AINT. The first power supply voltage ELVDD, the second power supply voltage ELVSS, the first initialization voltage VINT, and the second initialization voltage AINT may be applied to the pixels PX.

[0093] The scan driving circuit SDC can receive a scan control signal SCS from the driving controller 100. The scan driving circuit SDC can output scan signals to the scan lines GIL1 to GILn, GCL1 to GCLn, GWL1 to GWLn, and GBL1 to GBLn in response to the scan control signal SCS. The scan signals can be applied to the pixels PX through the scan lines GIL1 to GILn, GCL1 to GCLn, GWL1 to GWLn, and GBL1 to GBLn.

[0094] The light emitting drive circuit EDC can receive a light emitting control signal ECS from the drive controller 100. The light emitting drive circuit EDC can output a light emitting signal to the light emitting lines EML1 to EMLn in response to the light emitting control signal ECS. The light emitting signal can be applied to the pixels PX through the light emitting lines EML1 to EMLn.

[0095] 4A and 4B are diagrams showing an equivalent circuit of one of the pixels shown in FIG.

[0096] For example, FIG. 4A illustrates a first pixel PXab connected to the a-th data line DLa, the b-th scan lines GWLb, GCLb, GILb, and GBLb, and the b-th light-emitting line EMLb. FIG. 4B illustrates a second pixel PXcd connected to the c-th data line DLc, the d-th scan lines GWLd, GCLd, GILd, and GBLd, and the d-th light-emitting line EMLd. a and c may each be a natural number less than m, and b and d may each be a natural number less than n. The first pixel PXab may be disposed in the first area AA1 shown in FIG. 1B, and the second pixel PXcd may be disposed in the second area AA2. The first pixel PXab and the second pixel PXcd are described in the same manner, except that the first voltage ELVSS1 is applied to the first pixel PXab and the second voltage ELVSS2 is applied to the second pixel PXcd.

[0097] 4A, the first pixel PXab may include a first pixel circuit PC1 and a first light emitting element OLED1 connected to the first pixel circuit PC1. The first pixel circuit PC1 may drive the first light emitting element OLED1.

[0098] The first pixel circuit PC1 may include a plurality of transistors T1 to T8 and a capacitor CST. The transistors T1 to T8 and the capacitor CST may control the amount of current flowing to the first light emitting element OLED1. The first light emitting element OLED1 may generate light having a predetermined brightness according to the amount of current received.

[0099] The bth write scan line GWLb may receive the bth write scan signal GWb, the bth compensation scan line GCLb may receive the bth compensation scan signal GCb, the bth initialization scan line GILb may receive the bth initialization scan signal GIb, the bth bias scan line GBLb may receive the bth bias scan signal GBb, and the bth light-emitting line EMLb may receive the bth light-emitting signal EMb.

[0100] The first pixel PXab may be connected to the a-th data line DLa, the b-th write scan line GWLb, the b-th compensation scan line GCLb, the b-th initialization scan line GILb, the b-th bias scan line GBLb, the b-th emission line EMLb, the first initialization line VIL1, the second initialization line VIL2, the bias line VBL, the first power supply line PL1, and the second-1st power supply line PL2-1.

[0101] The first initialization line VIL1 receives the first initialization voltage VINT, the second initialization line VIL2 receives the second initialization voltage AINT, the bias line VBL receives the bias voltage VBIAS, the first power supply line PL1 receives the first power supply voltage ELVDD, and the second-1st power supply line PL2-1 receives the first voltage ELVSS1.

[0102] Each of the transistors T1 to T8 may include a source electrode, a drain electrode, and a gate electrode. Each of the transistors T1 to T8 may include an input electrode (or source electrode), an output electrode (or drain electrode), and a control electrode (or gate electrode). For convenience, one of the input electrode and the output electrode may be referred to as a first electrode and the other may be referred to as a second electrode in this specification. The transistors T1 to T8 may include first to eighth transistors T1 to T8. The first, second, and fifth to eighth transistors T1, T2, T5 to T8 may be PMOS transistors. The third and fourth transistors T3 and T4 may be NMOS transistors.

[0103] The first transistor T1 may be defined as a driving switching transistor, the second transistor TT2 may be defined as a switching transistor, the third transistor T3 may be defined as a compensation transistor, the fourth transistor T4 and the seventh transistor T7 may be defined as initialization transistors, the fifth transistor T5 and the sixth transistor T6 may be defined as light-emitting control transistors, and the eighth transistor T8 may be defined as a bias transistor.

[0104] The first light emitting element OLED1 may be defined as an organic light emitting element. The first light emitting element OLED1 may include a first anode (first-1 electrode) AE1 and a first cathode (or second-1 electrode) CE1. The first anode AE1 may receive a first power supply voltage ELVDD through the sixth, first, and fifth transistors T6, T1, and T5. The first power supply voltage ELVDD may be applied to the first pixel circuit PC1 through a first power supply line PL1.

[0105] The first cathode CE1 may receive a first voltage ELVSS1 having a level lower than the first power supply voltage ELVDD, and the first voltage ELVSS1 may be applied to the first pixel circuit PC1 through a second-1 power supply line PL2-1.

[0106] The first transistor T1 may be disposed between the fifth transistor T5 and the sixth transistor T6 and may be connected to the fifth transistor T5 and the sixth transistor T6. The first transistor T1 may be connected to the first power line PL1 through the fifth transistor T5 and to the first anode AE1 through the sixth transistor T6.

[0107] The first transistor T1 may include a first electrode connected to the first power line PL1 through the fifth transistor T5, a second electrode connected to the first anode AE1 through the sixth transistor T6, and a control electrode connected to the first node N1.

[0108] A first electrode of the first transistor T1 may be connected to the fifth transistor T5, and a second electrode of the first transistor T1 may be connected to the sixth transistor T6. The first transistor T1 may control the amount of current flowing through the first light emitting element OLED1 in response to a voltage of a first node N1 applied to a control electrode of the first transistor T1.

[0109] The second transistor TT2 may be disposed between the first transistor T1 and the a-th data line DLa and may be connected to the first transistor T1 and the a-th data line DLa, and may include a first electrode connected to the a-th data line DLa, a second electrode connected to the first electrode of the first transistor T1, and a control electrode connected to the b-th write scan line GWLb.

[0110] The second transistor TT2 is turned on in response to the b-th write scan signal GWb received through the b-th write scan line GWLb to electrically connect the a-th data line DLa to the first electrode of the first transistor T1, and performs a switching operation to provide the data voltage VD (corresponding to the data signal described above) received through the a-th data line DLa to the first electrode of the first transistor T1.

[0111] The third transistor T3 may be connected to the second electrode of the first transistor T1 and the first node N1, and may include a first electrode connected to the second electrode of the first transistor T1, a second electrode connected to the first node N1, and a control electrode connected to the b-th compensation scan line GCLb.

[0112] The third transistor T3 may be turned on in response to the b-th compensation scan signal GCb received through the b-th compensation scan line GCLb to electrically connect the second electrode of the first transistor T1 to the control electrode of the first transistor T1. When the third transistor T3 is turned on, the first transistor T1 and the third transistor T3 may be connected in a diode configuration.

[0113] The fourth transistor T4 may be connected to the first node N1. The fourth transistor T4 may include a first electrode connected to the first node N1, a second electrode connected to the first initialization line VIL1, and a control electrode connected to the b-th initialization scan line GILb. The fourth transistor T4 may be turned on in response to the b-th initialization scan signal GIb received through the b-th initialization scan line GILb to provide the first initialization voltage VINT received through the first initialization line VIL1 to the first node N1.

[0114] The fifth transistor T5 may include a first electrode connected to the first power line PL1, a second electrode connected to the first electrode of the first transistor T1, and a control electrode connected to the b-th light-emitting line EMLb.

[0115] The sixth transistor T6 may include a first electrode connected to the second electrode of the first transistor T1, a second electrode connected to the first anode AE1, and a control electrode connected to the b-th light emitting line EMLb.

[0116] The fifth transistor T5 and the sixth transistor T6 may be turned on by the b-th light-emitting signal EMb received through the b-th light-emitting line EMLb. The turned-on fifth transistor T5 and the sixth transistor T6 provide the first power supply voltage ELVDD to the first light-emitting element OLED1, allowing a driving current to flow through the first light-emitting element OLED1. As a result, the first light-emitting element OLED1 can emit light.

[0117] The seventh transistor T7 may include a first electrode connected to the first anode AE1, a second electrode connected to the second initialization line VIL2, and a control electrode connected to the b-th bias scan line GBLb. The seventh transistor T7 may be turned on in response to the b-th bias scan signal GBb received through the b-th bias scan line GBLb to provide the second initialization voltage AINT received through the second initialization line VIL2 to the first anode AE1 of the first light emitting element OLED1.

[0118] In another embodiment of the present invention, the seventh transistor T7 may be omitted. In another embodiment of the present invention, the second initialization voltage AINT may have a different level from the first initialization voltage VINT, but is not limited thereto, and may have the same level as the first initialization voltage VINT.

[0119] The seventh transistor T7 can improve the black display capability of the first pixel PXab. When the seventh transistor T7 is turned on, a parasitic capacitor (not shown) of the first light emitting element OLED1 can be discharged. Therefore, when black luminance is realized, the first light emitting element OLED1 does not emit light due to leakage current of the first transistor T1, and therefore the black display capability can be improved.

[0120] The capacitor CST may include a first electrode coupled to the first power line PL1 and a second electrode coupled to the first node N1. When the fifth transistor T5 and the sixth transistor T6 are turned on, the amount of current flowing through the first transistor T1 may be determined according to the voltage stored in the capacitor CST.

[0121] The eighth transistor T8 may include a first electrode connected to the bias line VBL, a second electrode connected to the first electrode of the first transistor T1, and a control electrode connected to the bth bias scan line GBLb.

[0122] The eighth transistor T8 is turned on by the b-th bias scan signal GBb to provide the bias voltage VBIAS to the first electrode of the first transistor T1.

[0123] 4B, the second pixel PXcd may include a second pixel circuit PC2 and a second light-emitting element OLED2 connected to the second pixel circuit PC2. The second pixel circuit PC2 may drive the second light-emitting element OLED2. The second pixel circuit PC2 may include a plurality of transistors T1 to T8 and a capacitor CST. The transistors T1 to T8 and the capacitor CST may control the amount of current flowing through the second light-emitting element OLED2. The second light-emitting element OLED2 may generate light having a predetermined brightness in accordance with the amount of current received.

[0124] In particular, the second cathode (or 2-2 electrode) CE2 of the second light emitting element OLED2, unlike the first cathode CE1 of the first light emitting element OLED1, is connected to the 2-2 power line PL2-2 and may receive the second voltage ELVSS2. As an example of the present invention, the second voltage ELVSS2 may have a voltage level lower than the first voltage ELVSS1.

[0125] Therefore, the second light emitting element OLED2 can emit light in response to a voltage corresponding to the difference between the signal transmitted through the sixth transistor T6 and the second voltage ELVSS2. That is, even if a signal having the same magnitude as the signal input to the second anode AE2 of the first light emitting element OLED1 is transmitted to the second anode AE2 of the second light emitting element OLED2, the driving current of the second light emitting element OLED2 increases by the difference between the second voltage ELVSS2 and the first voltage ELVSS1. Therefore, under the same input signal, the second light emitting element OLED2 can output light with higher brightness than the first light emitting element OLED1.

[0126] In addition, as will be described later, according to one embodiment of the present invention, the 2-1 electrode CE1 (see FIG. 6) and the 2-2 electrode CE2 (see FIG. 6) may be separated, and the first voltage ELVSS1 received by the first light emitting element OLED1 through the 2-1 power supply line PL2-1 and the second voltage ELVSS2 received by the second light emitting element OLED2 through the 2-2 power supply line PL2-2 may be different from each other.

[0127] FIG. 5 is a plan view of a display panel and a driving circuit unit according to an embodiment of the present invention.

[0128] 5, the display panel DP may be divided into a plurality of regions. A first region AA1 and a second region AA2 may be defined in the display panel DP. That is, the display region DA may include the first region AA1 and the second region AA2. The first region AA1 and the second region AA2 may be separated by a separator SPR.

[0129] The first region AA1 and the second region AA2 may be adjacent to each other. The second region AA2 may have a rectangular shape, and at least one side defining the second region AA2 may be adjacent to the first region AA1. The second region AA2 may be surrounded by the first region AA1. While FIG. 5 illustrates an example in which the display region DA includes only the first region AA1 and the second region AA2 of the second region AA2, the present invention is not limited thereto. That is, as an example of the present invention, the display region DA may further include a third region divided into the first and second regions A1 and A2 by a separator SPR. When viewed in a plan view, the second region AA2 may be defined toward the top of the display panel DP.

[0130] The pixels PX may be arranged in a first direction DR1 and a second direction DR2. The pixels PX may include a plurality of pixel rows extending in the first direction DR1 and arranged in the second direction DR2, and a plurality of pixel columns extending in the second direction DR2 and arranged in the first direction DR1.

[0131] The pixel PX may include a first pixel PX1 and a second pixel PX2. The first pixel PX1 may be disposed in the first area AA1, and the second pixel PX2 may be disposed in the second area AA2. The first pixel PX1 and the second pixel PX2 may each be a pixel that generates light. The number of first pixels PX1 and the number of second pixels PX2 within the same area may be different. For example, the number of second pixels PX2 may be smaller than the number of first pixels PX1. The first and second pixels PX1 and PX2 may have substantially the same configuration.

[0132] The pad section PDA may include a first pad PD1 and a second pad PD2. The pad section PDA may be a portion to which the flexible film CF is connected. The pad section PDA may include various pads such as a data pad (not shown) or an input pad (not shown), but in the present invention, only pads PD1 and PD2 associated with voltages provided to the pixels PX are illustrated.

[0133] The pad unit PDA may overlap the non-display area NDA. The pad unit PDA may be disposed adjacent to the lower end of the display panel DP. However, the arrangement of the pad unit PDA is not limited thereto and may be disposed in various positions.

[0134] The first pad PD1 is disposed in the non-display area NDA and can receive a first power supply voltage ELVDD. The first pad PD1 is electrically connected to the pixel PX and can provide the first power supply voltage ELVDD to the 1-1 electrode AE1 (see FIG. 7) of the pixel PX. The second pad PD2 is disposed in the non-display area NDA and can receive first and second voltages ELVSS1 and ELVSS2 that are different from the first power supply voltage ELVDD. The second pad PD2 can include a 2-1 pad PD2-1 that receives the first voltage ELVSS1 and a 2-2 pad PD2-2 that receives the second voltage ELVSS2. The 2-1 pad PD2-1 is electrically connected to the first pixel PX1 and provides a first voltage ELVSS1 to the 2-1 electrode CE1 (see FIG. 6) of the first pixel PX1, and the 2-2 pad PD2-2 is electrically connected to the second pixel PX2 and provides a second voltage ELVSS2 to the 2-2 electrode CE2 (see FIG. 6) of the second pixel PX2.

[0135] The display panel DP may include first power lines PL1 and second power lines PL2. The first power line PL1 may overlap the display area DA and extend along a first direction DR1 or a second direction DR2. The first power line PL1 may cross the display area DA in the first direction DR1 or the second direction DR2. A plurality of first power lines PL1 may be provided. The first power lines PL1 may extend along the second direction DR2 and be arranged along the first direction DR1, or may extend along the first direction DR1 and be arranged along the second direction DR2. One first power line PL1 may be arranged for each pixel column extended in the second direction DR2, and one first power line PL1 may be arranged for each pixel row extended in the first direction DR1.

[0136] The first power lines PL1 may be electrically connected to the first pad PD1. Each of the first power lines PL1 may be electrically connected to a pixel PX. One of the first power lines PL1 may be electrically connected to a pixel PX constituting a pixel column extended in the second direction DR2. Each of the first power lines PL1 may be electrically connected to each of the first and second pixels PX1 and PX2. Each of the first power lines PL1 may be electrically connected to the 1-1 electrodes AE1 (see FIG. 7) of the first and second pixels PX1 and PX2 to supply a first power voltage ELVDD.

[0137] The second power supply P line PL2 may include a 2-1 power supply line PL2-1 and a 2-2 power supply line PL2-2. The 2-1 power supply line PL2-1 may overlap the non-display area NDA. The 2-1 power supply line PL2-1 may be arranged to surround three sides of the display area DA. Specifically, the 2-1 power supply line PL2-1 may be arranged to surround three sides of the first area AA. The 2-1 power supply line PL2-1 may be electrically connected to the first pixel PX1. The 2-1 power supply line PL2-1 may be electrically connected to the 2-1 electrode CE1 (see FIG. 6) of the first pixel PX1 and may supply the first voltage ELVSS1.

[0138] The second-2 power line PL2-2 may overlap the display area DA. The second-2 power line PL2-2 may extend along the second direction DR2. The second-2 power line PL2-2 may overlap the first area AA1 and the second area AA2. Specifically, the second-2 power line PL2-2 may cross the first area AA1 and extend to a specific position in the second area AA2. A plurality of second-2 power lines PL2-2 may be provided. The second-2 power lines PL2-2 may extend along the second direction DR2 and be arranged in the first direction DR1. Although FIG. 5 illustrates two second-2 power lines PL2-2, the number of second-2 power lines PL2-2 is not limited thereto, and may be three or more. The second-2 power line PL2-2 may be electrically connected to the second pixel PX2. The second-second power line PL2-2 is electrically connected to the second-second electrode CE2 (see FIG. 6) of the second pixel PX2 and may supply the second voltage ELVSS2. Specifically, the second-second power line PL2-2 may supply the second voltage ELVSS2 to the second-second electrode CE2 (see FIG. 6) through a connection part CP. A plurality of connection parts CP may be provided. In FIG. 5, the number of connection parts CP is illustrated as two, the same as the number of the second-second power lines PL2-2, but is not limited thereto and may be three or more depending on the number of the second-second power lines PL2-2.

[0139] The voltage generator 300 may be disposed on the main circuit board MB. The voltage generator 300 may generate a first power supply voltage ELVDD, a first voltage ELVSS1, and a second voltage ELVSS2. The pad unit PDA may be electrically connected to the voltage generator 300. The voltage generator 300 may be electrically connected to a first power supply line PL1 and a second power supply line PL2 through the pad unit PDA. The voltage generator 300 may apply the first power supply voltage ELVDD to the first pad PD1, the first voltage ELVSS1 to the second-1 pad PD2-1, and the second voltage ELVSS2 to the second-2 pad PD2-2. As a result, the voltage generator 300 can supply the first power supply voltage ELVDD to the 1-1 electrodes AE1 of the first and second pixels PX1 and PX2, supply the first voltage ELVSS1 to the 2-1 electrode CE1 of the first pixel PX1, and supply the second voltage ELVSS2 to the 2-2 electrode CE2 of the second pixel PX2.

[0140] FIG. 6 is an enlarged view of the area AA′ shown in FIG.

[0141] 6 illustrates a display panel DP including a plurality of light emitting units UT, a separator SPR, second electrodes CE1 and CE2 separated from each other by the separator SPR, and a second-second power line PL2-2. The first-second electrode AE2 (see FIG. 7) will be described later.

[0142] In this embodiment, one light emitting unit UT among the plurality of light emitting units UT may include three light emitting portions EP1, EP2, and EP3. The light emitting units UT may be arranged in a first direction DR1 and a second direction DR2. However, this is merely an example, and the number and arrangement of the light emitting units UT may be variously designed and are not limited to any one embodiment.

[0143] Each of the light-emitting portions EP1, EP2, and EP3 may correspond to a light-emitting opening OP-PDL (see FIG. 7) described below. That is, each of the light-emitting portions EP1, EP2, and EP3 is an area where light is emitted by the above-described light-emitting element (e.g., the second light-emitting element OLED2 shown in FIG. 4B), and may correspond to a unit that configures an image displayed on the display panel DP. More specifically, each of the light-emitting portions EP1, EP2, and EP3 may correspond to an area defined by a light-emitting opening OP-PDL (see FIG. 7) described below, particularly an area defined by the bottom surface of the light-emitting opening OP-PDL.

[0144] The light-emitting units EP1, EP2, and EP3 may include a first light-emitting unit EP1, a second light-emitting unit EP2, and a third light-emitting unit EP3. The first light-emitting unit EP1, the second light-emitting unit EP2, and the third light-emitting unit EP3 may emit light of different colors. Therefore, the light-emitting elements constituting the first light-emitting unit EP1, the second light-emitting unit EP2, and the third light-emitting unit EP3 may emit light of different colors. For example, the first light-emitting unit EP1 may emit red light, the second light-emitting unit EP2 may emit green light, and the third light-emitting unit EP3 may emit blue light, but the color combination is not limited thereto. Furthermore, at least two of the light-emitting units EP1, EP2, and EP3 may emit light of the same color. For example, all of the first to third light-emitting units EP1, EP2, and EP3 may emit blue light, or all may emit white light.

[0145] Meanwhile, unlike the illustrated embodiment, the third light-emitting unit EP3 among the light-emitting units EP1, EP2, and EP3 may include two sub-light-emitting units spaced apart from each other in the second direction DR2, or at least one of the other light-emitting units EP1 and EP2 may include spaced-apart sub-light-emitting units, and the present invention is not limited to any one embodiment.

[0146] The second electrodes CE1 and CE2 may include a 2-1 electrode CE1 disposed in the first region AA1 and a 2-2 electrode CE2 disposed in the second region AA2. The first region AA1 and the second region AA2 may be separated by a separator SPR. The 2-1 electrode CE1 and the 2-2 electrode CE2 may be electrically isolated from each other by the separator SPR. The 2-1 electrode CE1 and the 2-2 electrode CE2 may be commonly deposited using an open mask as a common electrode.

[0147] The second-second power line PL2-2 may be disposed overlapping the first area AA1 and the second area AA2. A plurality of second-second power lines PL2-2 may be provided, and only one of the plurality of second-second power lines PL2-2 is illustrated in FIG. 6. The second-second power line PL2-2 may be electrically connected to the second-second electrode CE2. The second-second power line PL2-2 may apply a second voltage ELVSS2 (see FIG. 5) to the second-second electrode CE2.

[0148] The second-second power line PL2-2 may include a connection portion (or a first connection portion) CP. The connection portion CP may be provided on one side of the second-second power line PL2-2. The connection portion CP will be described in detail below.

[0149] Figure 7 is a cross-sectional view of a display module of the present invention taken along line I-I' in Figure 6. Figure 8A is an enlarged view of a region BB' in Figure 7. Figure 8B is an enlarged view of a region CC' in Figure 7.

[0150] 7, a display panel DP according to an embodiment may include a base layer BL, a driving element layer DDL, a light-emitting element layer LDL, an encapsulation layer TFE, and a sensing layer ISL. The driving element layer DDL may include a plurality of insulating layers 10, 20, 30, 40, and 50 disposed on the base layer BL, and a plurality of conductive patterns and semiconductor patterns disposed between the insulating layers. The conductive patterns and semiconductor patterns may form a second pixel circuit PC2 between the insulating layers. For ease of explanation, FIG. 7 exemplarily illustrates a cross section of a region in which one of the plurality of light-emitting units disposed in the second region AA2 illustrated in FIG. 6 is disposed.

[0151] The base layer BL may be a member that provides a base surface on which the second pixel circuit PC2 is disposed. The base layer BL may be a rigid substrate or a flexible substrate that allows bending, folding, rolling, etc. The base layer BL may be a glass substrate, a metal substrate, a polymer substrate, etc. However, embodiments of the present invention are not limited thereto, and the base layer BL may be an inorganic layer, an organic layer, or a composite material layer.

[0152] The base layer BL may have a multi-layer structure. The base layer BL may include a first polymer resin layer, a silicon oxide (SiOx) layer disposed on the first polymer resin layer, an amorphous silicon (a-Si) layer disposed on the silicon oxide layer, and a second polymer resin layer disposed on the amorphous silicon layer. The silicon oxide layer and the amorphous silicon layer may be referred to as a base barrier layer.

[0153] The polymer resin layer may include a polyimide-based resin. The polymer resin layer may also include at least one of an acrylate-based resin, a methacrylate-based resin, a polyisoprene-based resin, a vinyl-based resin, an epoxy-based resin, a urethane-based resin, a cellulose-based resin, a siloxane-based resin, a polyamide-based resin, and a perylene-based resin. In this specification, a "-based" resin refers to a resin containing a functional group of "-based."

[0154] Each of the insulating layer, conductive layer, and semiconductor layer disposed on the base layer BL may be formed by coating, deposition, etc. Then, the insulating layer, semiconductor layer, and conductive layer may be selectively patterned through multiple photolithography processes to form holes in the insulating layer, or semiconductor patterns, conductive patterns, signal lines, etc.

[0155] The driving element layer DDL may include first to fifth insulating layers 10, 20, 30, 40, and 50 and a second pixel circuit PC2, which are sequentially stacked on a base layer BL. Figure 7 illustrates one transistor TR and two capacitors C1 and C2 in the second pixel circuit PC2. Meanwhile, although not shown, other transistors constituting the second pixel circuit PC2 may have the same structure as the transistor TR illustrated in Figure 7. However, this is merely an example, and the other transistors constituting the second pixel circuit PC2 may have a different structure from the transistor TR, and the present invention is not limited to any one embodiment.

[0156] A first insulating layer 10 may be disposed on the base layer BL. The first insulating layer 10 may be an inorganic layer and / or an organic layer and may have a single-layer or multi-layer structure. The first insulating layer 10 may include at least one of aluminum oxide, titanium oxide, silicon oxide, silicon nitride, silicon oxynitride, zirconium oxide, and hafnium oxide. In this embodiment, the first insulating layer 10 is illustrated as a single-layer silicon oxide layer. Meanwhile, insulating layers, which will be described later, may be inorganic layers and / or organic layers and may have a single-layer or multi-layer structure. The inorganic layer may include at least one of the above-mentioned materials, but is not limited thereto.

[0157] Meanwhile, the first insulating layer 10 may cover the lower conductive layer BCL. That is, the display panel may further include a lower conductive layer BCL disposed overlapping the transistor TR. The lower conductive layer BCL may block the transistor TR from being affected by an electric potential due to polarization of the base layer BL. The lower conductive layer BCL may also block light incident on the transistor TR from below. At least one of an inorganic barrier layer and a buffer layer may be further disposed between the lower conductive layer BCL and the base layer BL.

[0158] The lower conductive layer BCL may include a reflective metal, such as titanium (Ti), molybdenum (Mo), a molybdenum-containing alloy, aluminum (Al), an aluminum-containing alloy, aluminum nitride (AlN), tungsten (W), tungsten nitride (WN), and copper (Cu).

[0159] In this embodiment, the lower conductive layer BCL may be connected to the source of the transistor TR through a source electrode pattern W1. In this case, the lower conductive layer BCL may be synchronized with the source of the transistor TR. However, this is merely an example, and the lower conductive layer BCL may be connected to the gate of the transistor TR and synchronized with the gate. Alternatively, the lower conductive layer BCL may be connected to another electrode and independently receive a constant voltage or a pulse signal. Alternatively, the lower conductive layer BCL may be isolated from other conductive patterns. The lower conductive layer BCL according to an embodiment of the present invention may be provided in various forms and is not limited to any one embodiment.

[0160] A transistor TR may be disposed on the first insulating layer 10. The transistor TR may include a semiconductor pattern SP and a gate electrode GE. The semiconductor pattern SP may be disposed on the first insulating layer 10. The semiconductor pattern SP may include an oxide semiconductor. For example, the oxide semiconductor may include a transparent conductive oxide (TCO) such as indium tin oxide (ITO), indium zinc oxide (IZO), indium gallium zinc oxide (IGZO), zinc oxide (ZnO), or indium oxide (In2O3). However, without being limited thereto, the semiconductor pattern may include amorphous silicon, low-temperature polycrystalline silicon, or polycrystalline silicon.

[0161] The semiconductor pattern SP may include a source region SR, a drain region DR, and a channel region CHR, which are divided according to the degree of conductivity. The channel region CR may be a portion overlapping the gate electrode GE in a plan view. The source region SR and the drain region DR may be portions separated by the channel region CR. If the semiconductor pattern SP is an oxide semiconductor, each of the source region SR and the drain region DR may be a reduced region. Therefore, the source region SR and the drain region DR have a relatively higher reduced metal content than the channel region CR. Alternatively, if the semiconductor pattern SP is polycrystalline silicon, each of the source region SR and the drain region DR may be a highly doped region.

[0162] The source region SR and the drain region DR may have a relatively high conductivity compared to the channel region CR. The source region SR may correspond to the source electrode of the transistor TR, and the drain region DR may correspond to the drain electrode of the transistor TR. As shown in FIG. 7, a separate source electrode pattern W1 and a drain electrode pattern W2 may be further provided, connected to the source region SR and the drain region DR, respectively. Specifically, the separate source electrode pattern W1 and the drain electrode pattern W2 may each be integrally formed with one of the lines constituting the second pixel circuit PC2, and are not limited to any one embodiment.

[0163] The second insulating layer 20 may overlap a plurality of pixels and cover the semiconductor pattern SP. The second insulating layer 20 may be an inorganic and / or organic layer and may have a single-layer or multi-layer structure. The second insulating layer 20 may include at least one of aluminum oxide, titanium oxide, silicon oxide, silicon nitride, silicon oxynitride, zirconium oxide, and hafnium oxide. In this embodiment, the second insulating layer 20 may be a single silicon oxide layer.

[0164] The gate electrode GE may be disposed on the second insulating layer 20. The gate electrode GE may correspond to the gate of the transistor TR. The gate electrode GE may also be disposed above the semiconductor pattern SP. However, this is merely an example, and the gate electrode GE may also be disposed below the semiconductor pattern SP, and is not limited to any one embodiment.

[0165] The gate electrode GE may include, but is not limited to, titanium (Ti), silver (Ag), molybdenum (Mo), aluminum (Al), aluminum nitride (AlN), tungsten (W), tungsten nitride (WN), copper (Cu), or alloys thereof.

[0166] A third insulating layer 30 may be disposed on the gate electrode GE. The third insulating layer 30 may be an inorganic layer and / or an organic layer and may have a single-layer or multi-layer structure. The fourth insulating layer 40 may include at least one of aluminum oxide, titanium oxide, silicon oxide, silicon nitride, silicon oxynitride, zirconium oxide, and hafnium oxide.

[0167] Among the plurality of conductive patterns W1, W2, CPE1, CPE2, and CPE3, the first capacitor electrode CPE1 and the second capacitor electrode CPE2 constitute a first capacitor C1. The first capacitor electrode CPE1 and the second capacitor electrode CPE2 may be spaced apart by a first insulating layer 10 and a second insulating layer 20.

[0168] In an embodiment of the present invention, the first capacitor electrode CPE1 and the lower conductive layer BCL may have an integral shape, and the second capacitor electrode CPE2 and the gate electrode GE may have an integral shape.

[0169] A third capacitor electrode CPE3 may be disposed on the third insulating layer 30. The third capacitor electrode CPE3 may be spaced apart from the second capacitor electrode CPE2 via the third insulating layer 30 and may overlap on a plane. The third capacitor electrode CPE3 may form a second capacitor C2 together with the second capacitor electrode CPE2.

[0170] A fourth insulating layer 40 may be disposed on the third insulating layer 30 and / or the third capacitor electrode CPE3. The fourth insulating layer 40 may be an inorganic layer and / or an organic layer and may have a single-layer or multi-layer structure. The fourth insulating layer 40 may include at least one of aluminum oxide, titanium oxide, silicon oxide, silicon nitride, silicon oxynitride, zirconium oxide, and hafnium oxide.

[0171] A source electrode pattern W1 and a drain electrode pattern W2 may be disposed on the fourth insulating layer 40. The source electrode pattern W1 may be connected to a source region SR of the transistor TR through a first contact hole CNT1, and the source region SR of the source electrode pattern W1 and the semiconductor pattern SP may function as the source of the transistor TR. The drain electrode pattern W2 may be connected to a drain region DR of the transistor TR through a second contact hole CNT2, and the drain electrode pattern W2 and the drain region DR of the semiconductor pattern SP may function as the drain of the transistor TR. A fifth insulating layer 50 may be disposed on the source electrode pattern W1 and the drain electrode pattern W2.

[0172] A second-second power line PL2-2 may be disposed on the fifth insulating layer 50. The second-second power line PL2-2 may be electrically connected to the second light emitting element OLED2. The second-second power line PL2-2 may have a three-layer structure. Specifically, the second-second power line PL2-2 may include a first layer L1, a second layer L2, and a third layer L3 sequentially stacked along a third direction DR3. This will be described in detail later.

[0173] A sixth insulating layer 60 may be disposed on the second-second power line PL2-2. The sixth insulating layer 60 may be disposed on the fifth insulating layer 50 to cover the second-second power line PL2-2. Each of the fifth insulating layer 50 and the sixth insulating layer 60 may be an organic layer. For example, each of the fifth insulating layer 50 and the sixth insulating layer 60 may include a general-purpose polymer such as BCB (benzocyclobutene), polyimide, HMDSO (hexamethyl disiloxane), polymethylmethacrylate (PMMA), or polystyrene (PS), a polymer derivative having a phenolic group, an acrylic polymer, an imide polymer, an aryl ether polymer, an amide polymer, a fluorine-based polymer, a p-xylene-based polymer, a vinyl alcohol-based polymer, or a blend thereof.

[0174] The sixth insulating layer 60 may have a first opening OP1 exposing at least a portion of the second-second power line PL2-2. The second-second power line PL2-2 may be electrically connected to the second light emitting element OLED2 through the portion exposed from the sixth insulating layer 60. This will be described in detail later. Meanwhile, in the display panel DP according to an embodiment of the present invention, the sixth insulating layer 60 may be omitted or a plurality of sixth insulating layers 60 may be provided, and the display panel DP is not limited to any one embodiment.

[0175] A light-emitting element layer LDL may be disposed on the sixth insulating layer 60. The light-emitting element layer LDL may include a pixel-defining layer PDL, a second light-emitting element OLED2, and a separator SPR. The pixel-defining layer PDL may be an organic layer. For example, the pixel-defining layer PDL may include common polymers such as BCB (benzocyclobutene), polyimide, HMDSO (hexamethyl disiloxane), polymethylmethacrylate (PMMA), and polystyrene (PS), polymer derivatives having a phenolic group, acrylic polymers, imide polymers, aryl ether polymers, amide polymers, fluorine-based polymers, p-xylene-based polymers, vinyl alcohol-based polymers, and blends thereof.

[0176] In one embodiment, the pixel defining (defining) film PDL may have a light absorbing property, for example, a black color. That is, the pixel defining (defining) film PDL may include a black component (black coloring agent). The black component may include a black dye or a black pigment. The black component may include carbon black, a metal such as chromium, or an oxide thereof. The pixel defining (defining) film PDL may correspond to a light-blocking pattern having a light-blocking property.

[0177] An opening OP-PDL (hereinafter referred to as a light-emitting opening) exposing at least a portion of a first-second electrode AE2 (described later) may be defined in the pixel definition (defining) layer PDL. A plurality of light-emitting openings OP-PDL may be provided, each corresponding to each light-emitting element. All components of the second light-emitting element OLED2 may be arranged to overlap in the light-emitting opening OP-PDL, and the light-emitting opening OP-PDL may be a region where light emitted by the second light-emitting element OLED2 is substantially displayed. Accordingly, the shape of the third light-emitting portion EP3 among the above-described light-emitting portions EP1, EP2, and EP3 (see FIG. 6) may substantially correspond to the shape of the light-emitting opening OP-PDL on a plane.

[0178] The second light-emitting element OLED2 may include a first-second electrode AE2, a second intermediate layer IML2, and a second-second electrode CE2. The first-second electrode AE2 may be a semi-transmissive, transmissive, or reflective electrode. According to an embodiment of the present invention, the first-second electrode AE2 may include a reflective layer made of silver (Ag), magnesium (Mg), aluminum (Al), platinum (Pt), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), or a compound thereof, and a transparent or semi-transparent electrode layer formed on the reflective layer. The transparent or semi-transparent electrode layer may include at least one selected from the group consisting of indium tin oxide (ITO), indium zinc oxide (IZO), indium gallium zinc oxide (IGZO), zinc oxide (ZnO), indium oxide (In2O3), and aluminum-doped zinc oxide (AZO). For example, the first-second electrode AE2 may include a laminated structure of ITO / Ag / ITO.

[0179] In this embodiment, the first-2 electrode AE2 may be an anode of the second light emitting element OLED2. That is, the first-2 electrode AE2 may be connected to the transistor TR through a third contact hole CNT3 formed through the fifth insulating layer 50 and the sixth insulating layer 60. Specifically, the first-2 electrode AE2 may be connected to the source of the transistor TR through a source electrode pattern W1 connected to the third contact hole CNT3.

[0180] The second intermediate layer IML2 may be disposed between the first-second electrode AE2 and the second-second electrode CE2. The second intermediate layer IML2 may include an emitting layer EML and a functional layer FNL. The second light-emitting element OLED2 may include the second intermediate layer IML2 having various structures and is not limited to any one embodiment. For example, the functional layer FNL may be provided as a plurality of layers, or as two or more layers separated by the emitting layer EML. Alternatively, in one embodiment, the functional layer FNL may be omitted.

[0181] The emission layer EML may include an organic light-emitting material. The emission layer EML may also include an inorganic light-emitting material or may be provided as a mixed layer of an organic light-emitting material and an inorganic light-emitting material. In this embodiment, the emission layer EML may emit any one of blue, red, and green light. However, this is not limited thereto, and the emission layers EML disposed in all of the emission units EP1, EP2, and EP3 (see FIG. 6) may include an emission material that displays the same color. In this case, the emission layer EML may emit blue light or white light. Furthermore, while FIG. 7 illustrates an embodiment in which the emission layer EML and the functional layer FNL have different shapes, this is not limited thereto, and the emission layer EML and the functional layer FNL may be disposed in the same shape on a plane.

[0182] The functional layer FNL may be disposed between the first-second electrode AE2 and the second-second electrode CE2. Specifically, the functional layer FNL may be disposed between the first-second electrode AE2 and the emitting layer EML, or between the second-second electrode CE2 and the emitting layer EML. Alternatively, the functional layer FNL may be disposed both between the first-second electrode AE2 and the emitting layer EML and between the second-second electrode CE2 and the emitting layer EML. In this embodiment, the emitting layer EML is illustrated as being inserted within the functional layer FNL. However, this is merely an example, and the functional layer FNL may include a layer disposed between the emitting layer EML and the first-second electrode AE2 and / or a layer disposed between the emitting layer EML and the second-second electrode CE2. A plurality of each of these may be provided, and this is not limited to any one embodiment.

[0183] The functional layer FNL can control charge transfer between the first-second electrode AE2 and the second-second electrode CE2. The functional layer FNL can include a hole injection / transport material and / or an electron injection / transport material. The functional layer FNL can include at least one of an electron blocking layer, a hole transport layer, a hole injection layer, a hole blocking layer, an electron transport layer, an electron injection layer, and a charge generation layer.

[0184] The 2-2 electrode CE2 may be disposed on the second intermediate layer IML2. As described above, the 2-2 electrode CE2 may be connected to the connection portion CP and electrically coupled to the 2-2 power line PL2-2. As described above, the 2-2 power line PL2-2 may include the connection portion CP. The connection portion CP may be defined in an area exposed from the sixth insulating layer 60 and may be a portion to which the 2-2 electrode CE2 is connected. Here, a tip portion TP may be defined in the connection portion CP.

[0185] The connection portion CP of the second-2 power line PL2-2 will be described in more detail with reference to FIGS. 7 and 8A. As shown in FIGS. 7 and 8A, the second-2 power line PL2-2 may have a three-layer structure. Specifically, the second-2 power line PL2-2 may include a first layer L1, a second layer L2, and a third layer L3 that are sequentially stacked along the third direction DR3. The second layer L2 may include a different material from the first layer L1. The second layer L2 may also include a different material from the third layer L3. The second layer L2 may have a relatively greater thickness than the first layer L1. The second layer L2 may also have a relatively greater thickness than the third layer L3. The second layer L2 may include a highly conductive material. In one embodiment, the second layer L2 may include aluminum (Al).

[0186] Meanwhile, the first layer L1 may include a material having a lower etching rate (easier to be etched) than the second layer L2. That is, the first layer L1 and the second layer L2 may be composed of materials having a high etching selectivity relative to each other. In one embodiment, the first layer L1 may include titanium (Ti), and the second layer L2 may include aluminum (Al). In this case, the side surface L1_W of the first layer L1 may be defined outward from the side surface L2_W of the second layer L2. That is, the connection portion CP of the second-second power line PL2-2 may have a shape in which the side surface L1_W of the first layer L1 protrudes outward from the side surface L2_W of the second layer L2. That is, the connection portion CP of the second-second power line PL2-2 may have a shape in which the side surface L2_W of the second layer L2 is recessed inward from the side surface L1_W of the first layer L1.

[0187] The third layer L3 may include a material having a lower etching rate (is less easily etched) than the second layer L2. That is, the third layer L3 and the second layer L2 may be made of materials having a high etching selectivity relative to each other. In one embodiment, the third layer L3 may include titanium (Ti), and the second layer L2 may include aluminum (Al). In this case, the side surface L3_W of the third layer L3 may be defined outward from the side surface L2_W of the second layer L2. That is, the connection portion CP of the second-second power line PL2-2 may have a shape in which the side surface L3_W of the third layer L3 protrudes outward from the side surface L2_W of the second layer L2. That is, the connection portion CP of the second-second power line PL2-2 may have an undercut shape or an overhang structure, and a tip portion TP of the connection portion CP may be defined by the protruding portion of the third layer L3 compared to the second layer L2.

[0188] The sixth insulating layer 60 and the pixel defining layer PDL may expose at least a portion of the tip portion TP and at least a portion of the second side surface L2_W. Specifically, a first opening OP1 exposing one side of the second-2 power line PL2-2 may be defined in the sixth insulating layer 60, and a second opening OP2 overlapping the first opening OP1 may be defined in the pixel defining layer PDL. The plane area of ​​the second opening OP2 may be larger than that of the first opening OP1. However, the present invention is not limited thereto. As long as at least a portion of the tip portion TP and at least a portion of the second side surface L2_W can be exposed, the plane area of ​​the second opening OP2 may be smaller than or equal to that of the first opening OP1.

[0189] A second intermediate layer IML2 may be disposed on the pixel defining layer PDL. The second intermediate layer IML2 may also be disposed on a portion of the sixth insulating layer 60 exposed by the second opening OP2 of the pixel defining layer PDL. The second intermediate layer IML2 may also be disposed on a portion of the second-2 power line PL2-2 exposed by the first opening OP1 of the sixth insulating layer 60. As shown in FIG. 8A , the second intermediate layer IML2 may include one end IN1 disposed along the top surface of the fifth insulating layer 50 and the other end IN2 disposed along the top surface of the chip portion TP. That is, in cross section, the second intermediate layer IML2 may have a shape that is partially disconnected from the chip portion TP in a region where the connection portion CP is defined. However, when viewed in a plan view, the second intermediate layer IML2 may have an integral shape that is entirely connected within a second area AA2 (see Figure 6) defined by a closed line by the separator SPR, like the 2-2 electrode CE2.

[0190] A 2-2 electrode CE2 may be disposed on the second intermediate layer IML2. The 2-2 electrode CE2 may also be disposed on a portion of the sixth insulating layer 60 exposed by the second opening OP2 in the pixel defining layer PDL. The 2-2 electrode CE2 may also be disposed on a portion of the 2-2 power line PL2-2 exposed by the first opening OP1 in the sixth insulating layer 60. As shown in FIG. 8A , the 2-2 electrode CE2 may include one end EN1 of the 2-2 electrode CE2 disposed along the upper surface of the fifth insulating layer 50 and the other end EN2 disposed along the upper surface of the tip portion TP. That is, in cross section, the 2-2 electrode CE2 may have a shape that is partially disconnected from the tip portion TP in the region where the connection portion CP is defined. However, when viewed from above, the 2-2 electrode CE2 may have an integral shape that is entirely connected within a second area AA2 (see FIG. 6) that is defined by the separator SPR as a closed curve.

[0191] Meanwhile, one end EN1 of the 2-2 electrode CE2 may be disposed along the side surface of the second layer L2 and may be in contact with the side surface L2_W of the second layer L2. Specifically, due to the difference in deposition angle between the 2-2 electrode CE2 and the second intermediate layer IML2, the 2-2 electrode CE2 may be formed to be in contact with the side surface L2_W of the second layer L2 exposed from the second intermediate layer IML2 by the tip portion TP. That is, the 2-2 electrode CE2 may be connected to the 2-2 power line PL2-2 without a separate patterning process for the second intermediate layer IML2, and therefore the second light emitting element OLED2 may be electrically connected to the 2-2 power line PL2-2.

[0192] In addition, in this embodiment, the other end IN2 of the second intermediate layer IML2 and the other end EN2 of the 2-2 electrode CE2 are illustrated as covering the side L3_W of the third layer L3, but this is shown as an example, and at least a portion of the side L3_W of the third layer L3 may be exposed from the other end IN2 of the second intermediate layer IML2 and / or the other end EN2 of the 2-2 electrode CE2.

[0193] Meanwhile, as described above, the display panel DP may include a separator SPR. The separator SPR may be disposed on the pixel definition layer PDL. In one embodiment, the second electrode CE and the intermediate layer IML may be formed by common deposition on a plurality of pixels through an open mask. Here, the second electrode CE may be divided into a 2-1 electrode CE1 and a 2-2 electrode CE2 by the separator SPR, and the intermediate layer IML may be divided into a first intermediate layer IML1 and a second intermediate layer IML2 by the separator SPR. As described above, the separator SPR may have a closed line shape corresponding to the second area AA2, and therefore the 2-2 electrode CE2 and the second intermediate layer IML2 may have a divided shape corresponding to the second area AA2. That is, the 2-1 electrode CE1 and the 2-2 electrode CE2 may be electrically independent from each other, and the first intermediate layer IML1 and the second intermediate layer IML2 may be electrically independent from each other.

[0194] The separator SPR will be described in more detail with reference to Figures 7 and 8B. As shown in Figure 8B, the separator SPR may have a tapered shape. That is, the angle θ (hereinafter referred to as the taper angle) formed by the side surface SPR_W of the separator SPR with respect to the upper surface of the pixel defining layer PDL may be an obtuse angle. However, this is merely an example, and the taper angle θ may be set in various ways as long as the separator SPR can electrically disconnect the 2-1 electrode CE1 and the 2-2 electrode CE2. The separator SPR may also have a structure similar to that of the tip portion TP, and is not limited to any one embodiment.

[0195] In one embodiment, the separator SPR may include an insulating material, and in particular, may include an organic insulating material. The separator SPR may include an inorganic insulating material, or may be configured with multiple layers (laminated) of organic and inorganic insulating materials, and may include a conductive material depending on the embodiment. That is, the separator SPR is not particularly limited in terms of the type of material as long as it can electrically disconnect the 2-1 electrode CE1 and the 2-2 electrode CE2 from each other.

[0196] A dummy layer UP may be disposed on the separator SPR. The dummy layer UP may include a first dummy layer UP1 disposed on the separator SPR and a second dummy layer UP2 disposed on the first dummy layer UP1. The first dummy layer UP1 may be formed in the same process as the intermediate layer IML and may include the same material as the second electrode CE. The second dummy layer UP2 may be formed in the same process as the second electrode CE and may include the same material as the second electrode CE. That is, the first dummy layer UP1 and the second dummy layer UP2 may be formed simultaneously during the formation of the intermediate layer IML and the second electrode CE. In another embodiment, the display panel DP may not include the dummy layer UP.

[0197] 8B, in one embodiment, the 2-2 electrode CE2 may include a first end EN1a, and the second dummy layer UP2 may include a second end EN2a. The first end EN1a may be spaced apart from the separator SPR and positioned on the pixel defining layer PDL, and the second end EN2a may be spaced apart from the first end EN1a and positioned on the side surface SPR_W of the separator SPR. Although FIG. 10B illustrates the first end EN1a as being spaced apart from the side surface SPR_W of the separator SPR by a predetermined distance, the present invention is not limited thereto. If the first end EN1a is electrically disconnected from the second end EN2a, the first end EN1a may also contact the side surface SPR_W of the separator SPR. Furthermore, even if the first end EN1a and the second end EN2a are connected and not distinguishable from each other, if the thickness of the portion formed along the side SPR_W of the separator SPR is thin and the electrical resistance is high, if the 2-1 electrode CE1 and the 2-2 electrode CE2 are electrically disconnected from each other, the 2-1 electrode CE1 and the 2-2 electrode CE2 can be considered to be separated from each other by the separator SPR.

[0198] Referring again to FIG. 7, an encapsulating layer TFE may be disposed on the light-emitting element layer LDL. The encapsulating layer TFE may cover the second light-emitting element OLED2 and the separator SPR. The encapsulating layer TFE may include a first inorganic layer IL1, an organic layer OL, and a second inorganic layer IL2, which are sequentially stacked. However, without being limited thereto, the encapsulating layer TFE may further include multiple inorganic layers and organic layers. The encapsulating layer TFE may also be a glass substrate.

[0199] The first and second inorganic layers IL1 and IL2 protect the second light emitting element OLED2 from moisture and oxygen outside the display panel DP, and the organic layer OL protects the second light emitting element OLED2 from foreign substances such as particles remaining during the formation of the first inorganic layer IL1. The first and second inorganic layers IL1 and IL2 may include a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, an aluminum oxide layer, or the like. The organic layer OL may include an acrylic organic layer, and the type of material is not limited to any one of them.

[0200] The sensing layer ISL can sense an external input. In this embodiment, the sensing layer ISL can be formed on the encapsulation layer TFE through a continuous process. In this case, the sensing layer ISL can be expressed as being directly disposed on the encapsulation layer TFE. "Directly disposed" can mean that no other components are disposed between the sensing layer ISL and the encapsulation layer TFE. That is, a separate adhesive member does not need to be disposed between the sensing layer ISL and the encapsulation layer TFE. However, this is merely an example, and in the display panel DP according to an embodiment of the present invention, the sensing layer ISL can be formed separately and then coupled to the display panel DP through an adhesive member, and is not limited to any one embodiment.

[0201] The sensing layer ISL may include a plurality of conductive layers and a plurality of insulating layers. The plurality of conductive layers may include a first sensing conductive layer MTL1 and a second sensing conductive layer MTL2, and the plurality of insulating layers may include first to third sensing insulating layers 71, 72, and 73. However, this is merely an example, and the number of conductive layers and insulating layers is not limited to any one embodiment.

[0202] Each of the first to third insulating layers 71, 72, and 73 may have a single-layer structure or a multi-layer structure stacked along the third direction DR3. The first to third sensing insulating layers 71, 72, and 73 may include an inorganic film. The inorganic film may include at least one of aluminum oxide, titanium oxide, silicon oxide, silicon nitride, silicon oxynitride, zirconium oxide, and hafnium oxide. The first to third sensing insulating layers 71, 72, and 73 may include an organic film. The organic film may include at least one of acrylic resin, methacrylic resin, polyisoprene, vinyl resin, epoxy resin, urethane resin, cellulose resin, siloxane resin, polyimide resin, polyamide resin, and perylene resin.

[0203] The first sensing conductive layer MTL1 may be disposed between the first sensing insulating layer 71 and the second sensing insulating layer 72, and the second sensing conductive layer MTL2 may be disposed between the second sensing insulating layer 72 and the third sensing insulating layer 73. A portion of the second sensing conductive layer MTL2 may be connected to the first sensing conductive layer MTL1 through a contact hole CNT formed in the second sensing insulating layer 72. Each of the first sensing conductive layer MTL1 and the second sensing conductive layer MTL2 may have a single-layer structure or a multi-layer structure stacked along the third direction DR3.

[0204] The single-layer sensing conductive layer may include a metal layer or a transparent conductive layer. The metal layer may include molybdenum, silver, titanium, copper, aluminum, or an alloy thereof. The transparent conductive layer may include a transparent conductive oxide such as indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), or indium zinc tin oxide (IZTO). Alternatively, the transparent conductive layer may include a conductive polymer such as PEDOT, a metal nanowire, graphene, or the like.

[0205] The multi-layered sensing conductive layer can include a metal layer, such as a titanium (Ti) / aluminum (Al) / titanium (Ti) three-layer structure, or the multi-layered conductive layer can include at least one metal layer and at least one transparent conductive layer.

[0206] The first sensing conductive layer MTL1 and the second sensing conductive layer MTL2 may constitute a sensor that senses an external input in the sensing layer ISL. The sensor may be driven in a capacitive manner, such as a mutual capacitance (mutual-capacitance) or a self-capacitance (self-capacitance) manner. However, this is merely an example, and the sensor may be driven in a resistive manner, an ultrasonic manner, or an infrared manner in addition to the capacitive manner, and is not limited to any one embodiment.

[0207] Each of the first and second sensing conductive layers MTL1 and MTL2 may include a transparent conductive oxide or may have a metal mesh shape formed of an opaque conductive material. The first and second sensing conductive layers MTL1 and MTL2 may have various materials and shapes as long as the visibility of the image displayed by the display panel DP is not reduced, and are not limited to any one embodiment.

[0208] 9 is a cross-sectional view of a display module according to an embodiment of the present invention. Hereinafter, any description that overlaps with the above description will be omitted.

[0209] 9, the display module DMa of the present invention may include a connecting wire CN electrically connected to the second-second power line PL2-2a. The connecting wire CN may be disposed on a different layer from the second-second power line PL2-2a. For example, the second-second power line PL2-2a may be disposed on the fourth insulating layer 40, and the connecting wire CN may be disposed on the fifth insulating layer 50. The connecting wire CN may be electrically connected to the second-second power line PL2-2a through a fourth contact hole CNT4 formed through the fifth insulating layer 50.

[0210] The connecting wire CN may have a three-layer structure. Specifically, the connecting wire CN may include a first layer L1a, a second layer L2a, and a third layer L3a that are sequentially stacked along the third direction DR3. The second layer L2a may include a different material from the first layer L1a. Also, the second layer L2a may include a different material from the third layer L3a. The second layer L2a may have a relatively thicker thickness than the first layer L1a. Also, the second layer L2a may have a relatively thicker thickness than the third layer L3a. The second layer L2a may include a highly conductive material. In one embodiment, the second layer L2a may include aluminum (Al).

[0211] According to an embodiment of the present invention, the connecting wire CN may include a connection portion CPa. The connection portion CPa may have a shape in which a side surface L2_W (see FIG. 8A) of the second layer L2a is recessed inward from a side surface L1_W (see FIG. 8A) of the first layer L1a. That is, the connection portion CPa may have an undercut shape or an overhang structure, and a tip portion TP of the connection portion CPa may be defined by a portion of the third layer L3a that protrudes from the second layer L2a.

[0212] The connecting wire CN may be in contact with the 2-2 electrode CE2. Specifically, one end EN1 (see FIG. 8A) of the 2-2 electrode CE2 may be disposed along a side surface of the second layer L2 and may be in contact with a side surface L2_W of the second layer L2. As a result, the 2-2 electrode CE2 may be connected to the connecting wire CN, and the 2-2 electrode CE2 may be connected to a 2-2 power line PL2-2a electrically connected to the connecting wire CN.

[0213] Figure 10A is a graph showing a voltage applied to a first pixel arranged in the first region shown in Figure 5. Figure 10B is a graph showing a voltage applied to a second pixel arranged in the second region shown in Figure 5. Figures 10A and 10B are graphs showing voltages applied to the first pixel and the second pixel during each light-emitting period.

[0214] 4A and 10A, during the light-emitting period, the first light-emitting element OLED1 may emit light in response to a voltage corresponding to the difference between the signal transmitted through the sixth transistor T6 and the first voltage ELVSS1. The signal transmitted through the sixth transistor T6 may be defined as a transmission signal SG. That is, the brightness of the first light-emitting element OLED1 may be determined in response to the difference between the voltage level of the transmission signal SG and the voltage level of the first voltage ELVSS1. The greater the difference between the transmission signal SG and the first voltage ELVSS1, the greater the brightness of the first light-emitting element OLED1.

[0215] For ease of explanation, the level of the transfer signal SG is shown as being constant during the first and second sections A1 and A2, but the present invention is not limited thereto. That is, the level of the transfer signal SG may vary depending on the data signal DS (see FIG. 3).

[0216] 10A, the difference between the voltage level of the transmission signal SG and the voltage level V1 of the first voltage ELVSS1 may be the same between the first section A1 and the second section A2. That is, the voltage level V1 of the first voltage ELVSS1 may be constant between the first section A1 and the second section A2. As a result, since the voltage level of the transmission signal SG is constant between the first section A1 and the second section A2, the brightness of the first light emitting element OLED1 may be constant. However, the present invention is not limited thereto. As the voltage level of the transmission signal SG changes between the first section A1 and the second section A2, the brightness of the first light emitting element OLED1 may be continuously varied between the first section A1 and the second section A2.

[0217] 4B and 10B, during the light emitting period, the second light emitting element OLED2 may emit light in response to a voltage corresponding to the difference between the signal transmitted through the sixth transistor T6 and the second voltage ELVSS2. That is, the brightness of the second light emitting element OLED2 may be determined in response to the difference between the voltage level of the transmission signal SG and the voltage level of the second voltage ELVSS2, and the greater the difference between the transmission signal SG and the second voltage ELVSS2, the greater the brightness of the second light emitting element OLED2.

[0218] 10B, the voltage level V3 of the second voltage ELVSS2 during the first interval A1 may be different from the voltage level V2 of the second voltage ELVSS2 during the second interval A2. For example, the voltage level V2 of the second voltage ELVSS2 during the second interval A2 may be lower than the voltage level V3 of the second voltage ELVSS2 during the first interval A1. As a result, because the voltage level of the transfer signal SG is constant, the luminance of the second light-emitting element OLED2 during the first interval A1 is higher than the luminance of the second light-emitting element OLED2 during the second interval A2.

[0219] 10A and 10B, the voltage level V1 of the first voltage ELVSS1 may be equal to the voltage level V2 of the second voltage ELVSS2 during the second section A2. Furthermore, the voltage level V1 of the first voltage ELVSS1 during the first section A1 and the voltage level V3 of the second voltage ELVSS2 during the first section A1 may be different from each other. For example, the voltage level V1 of the first voltage ELVSS1 during the first section A1 may be greater than the voltage level V3 of the second voltage ELVSS2 during the first section A1. That is, the difference M1 between the voltage level of the transmission signal SG during the first section A1 and the voltage level V1 of the first voltage ELVSS1 may be less than the difference M2 between the voltage level of the transmission signal SG during the first section A1 and the voltage level V3 of the second voltage ELVSS2. As a result, the luminance of the second light emitting element OLED2 in the first section A1 may be greater than the luminance of the first light emitting element OLED1, and the luminance of the second light emitting element OLED2 in the second section A2 excluding the first section A1 may be the same as the luminance of the first light emitting element OLED1.

[0220] 5, 10A, and 10B, the first pixel PX1 disposed in the first area AA1 emits light having a brightness corresponding to the difference M1 between the voltage level of the transfer signal SG and the voltage level V1 of the first voltage ELVSS1 during the first interval A1, and the second pixel PX2 disposed in the second area AA2 emits light having a brightness corresponding to the difference M2 between the voltage level of the transfer signal SG and the voltage level V3 of the second voltage ELVSS2 during the first interval A1. That is, an image can be displayed at a different brightness in a specific area (e.g., the second area AA2) of the display area DA than in other areas (e.g., the first area AA1), thereby providing a display panel DP with improved display quality. Furthermore, because only the voltage level of the second voltage ELVSS2 needs to be adjusted to enhance the brightness of the second area AA2, the second voltage ELVSS2 can be precisely adjusted and provided to the second pixel PX2, thereby reducing power consumption.

[0221] Figure 11A is a plan view of a display panel and a driving circuit unit according to another embodiment of the present invention. Figure 11B is an enlarged view of a region DD' shown in Figure 11A. Figure 11C is a cross-sectional view of a display module according to another embodiment of the present invention, taken along line II-II' shown in Figure 11B. Descriptions that overlap with those previously described will be omitted.

[0222] 11A, the display panel DPb may include a first power line PL1 and a second power P line PL2a. The second power P line PL2a may include a second-first power line PL2-1a and a second-second power line PL2-2. The second-first power line PL2-1a and the second-second power line PL2-2 may each overlap the display area DA. The second-first power line PL2-1a and the second-second power line PL2-2 may each extend along a second direction DR2.

[0223] The second-1 power line PL2-1a may overlap the first area AA1. The second-1 power line PL2-1a may be electrically connected to the first pixel PX1. The second-1 power line PL2-1a may be electrically connected to the second-1 electrode CE1 (see FIG. 11B) of the first pixel PX1 and supply the first voltage ELVSS1. Specifically, the second-1 power line PL2-1a may supply the first voltage ELVSS1 to the second-1 electrode CE1 through the second connection part CP2. The second-2 power line PL2-2 may be electrically connected to the second pixel PX2. The second-2 power line PL2-2 may be electrically connected to the second-2 electrode CE2 (see FIG. 11B) of the second pixel PX2 and supply the second voltage ELVSS2. Specifically, the 2-2 power supply line PL2-2 may supply the second voltage ELVSS2 to the 2-2 electrode CE2 through the first connection part CP1.

[0224] A plurality of second-1 power supply lines PL2-1a and a plurality of second-2 power supply lines PL2-2 may be provided. The second-1 power supply lines PL2-1a and the second-2 power supply lines PL2-2 may each extend along the second direction DR2 and be arranged in the first direction DR1. Although FIG. 11A illustrates two second-1 power supply lines PL2-1a, the number of second-1 power supply lines PL2-1a is not limited thereto and may be three or more. A plurality of first connection parts CP1 and a plurality of second connection parts CP2 may each be provided.

[0225] 11A and 11B, the 2-1 electrode CE1 may be commonly disposed over the entire first region AA1. That is, the 2-1 electrode CE1 may be commonly deposited as a common electrode using an open mask. The 2-1 power line PL2-1a may include a second connection portion CP2. The second connection portion CP2 may be provided on one side of the 2-1 power line PL2-1a.

[0226] 11C, the second-1 power supply line PL2-1a may be disposed on the fifth insulating layer 50. The second-1 power supply line PL2-1a may have a three-layer structure. Specifically, the second-1 power supply line PL2-1a may include a first layer L1b, a second layer L2b, and a third layer L3b that are sequentially stacked along the third direction DR3. The second-1 power supply line PL2-1a may have the same structure as the second-2 power supply line PL2-2 shown in FIG. 7.

[0227] The 2-1 power line PL2-1a may include a second connection portion CP2. The second connection portion CP2 may have a shape in which a side surface L2_W (see FIG. 8A) of the second layer L2b is recessed inward from a side surface L1_W (see FIG. 8A) of the first layer L1b. That is, the second connection portion CP2 may have an undercut shape or an overhang structure, and a tip portion TP of the second connection portion CP2 may be defined by a portion of the third layer L3b that protrudes from the second layer L2b.

[0228] The 2-1 power supply line PL2-1a may be in contact with the 2-1 electrode CE1. Specifically, one end of the 2-1 electrode CE1 may be disposed along the side surface L2_W of the second layer L2b and may be in contact with the side surface L2_W of the second layer L2b. As a result, the 2-1 electrode CE1 may be connected to the 2-1 power supply line PL2-1a, and the 2-1 electrode CE1 may be connected to the 2-1 power supply line PL2-1a.

[0229] 11A to 11C, the second-1 power line PL2-1a is not disposed in the non-display area NDA but may be disposed in the first area AA1 in the display area DA. The second-1 power line PL2-1a may supply the first voltage ELVSS1 to the second-1 electrode CE1 through the second connection part CP2. By disposing the second-1 power line PL2-1a in the display area DA, the area occupied by the second-1 power line PL2-1a in the non-display area NDA may be reduced, and as a result, the area of ​​dead space in the display panel DPb may be reduced.

[0230] Furthermore, compared to a structure in which the 2-1 power supply line PL2-1a is disposed in the non-display area NDA and supplies the first voltage ELVSS1 to the 2-1 electrode CE1, it is possible to prevent the voltage drop IR-DROP phenomenon that occurs due to the longer current path applied to the 2-1 electrode CE1 disposed in the center of the display panel DP, and to prevent a deterioration in the display quality of the display device DD (see FIG. 1).

[0231] 12A to 12C are plan views of a display panel according to another embodiment of the present invention.

[0232] 12A, the display panel DPc of the present invention may include a display area DA and a non-display area NDA. The display area DA may include a first area AA1a, a second area AA2a, and a third area AA3. The first area AA1a, the second area AA2a, and the third area AA3 may be separated from each other by separators SPR1 and SPR2. For example, the first area AA1a and the second area AA2a may be separated from each other by the first separator SPR1, and the first area AA1a and the third area AA3 may be separated from each other by the second separator SPR2. The second area AA2a and the third area AA3 may be spaced apart from each other in the second direction DR2 via the first area AA1a. That is, the second area AA2a and the third area AA3 may each be surrounded by the first area AA1a.

[0233] Pixels PX (see FIG. 5) may be arranged in the display area DA. Although not shown, among the pixels PX, a first pixel PX1 may be arranged in the first area AA1a, a second pixel PX2 may be arranged in the first area AA2a, and a third pixel PX3 may be arranged in the third area AA3.

[0234] The second power P line PL2b may include a second-first power line PL2-1b, a second-second power line PL2-2b, and a second-third power line PL2-3. The second-first power line PL2-1b, the second-second power line PL2-2b, and the second-third power line PL2-3 may each overlap the display area DA. The second-first power line PL2-1b, the second-second power line PL2-2b, and the second-third power line PL2-3 may each extend along the second direction DR2.

[0235] The second-1 power line PL2-1b may be electrically connected to the first pixel PX1 arranged in the first area AA1a. The second-1 power line PL2-1b may supply a first voltage ELVSS1a to the first pixel PX1 through a first connection part CP1a. The second-2 power line PL2-2b may be electrically connected to the second pixel PX2 arranged in the second area AA2a. The second-2 power line PL2-2b may supply a second voltage ELVSS2a to the second pixel PX2 through a second connection part CP2a. The second-3 power line PL2-3 may be electrically connected to the third pixel PX3 arranged in the third area AA3. The second-3 power line PL2-3 may supply a third voltage ELVSS3 to the third pixel PX3 through a third connection part CP3.

[0236] The first voltage ELVSS1a, the second voltage ELVSS2a, and the third voltage ELVSS3 may be supplied to the pixel PX independently. That is, the first pixel PX1 arranged in the first area AA1a, the second pixel PX2 arranged in the second area AA2a, and the third pixel PX3 arranged in the third area AA3 may each emit light of different luminances for the same gray level during the same light-emitting period. As an example, the second voltage ELVSS2a and the third voltage ELVSS3 may each be lower than the first voltage ELVSS1a during the same light-emitting period (e.g., the first area A1 shown in FIG. 10B). Therefore, during the same light-emitting period, the second pixel arranged in the second area AA2a and the third pixel arranged in the third area AA3 may each emit light of higher luminance than the first pixel arranged in the first area AA1a. Furthermore, by inserting a test unit for detecting voltage drop in each of the 2-1 power line PL2-1b, the 2-2 power line PL2-2b, and the 2-3 power line PL2-3, it is possible to detect in advance the voltage drop phenomenon of the first to third pixels arranged in each of the first area AA1a, the second area AA2a, and the third area AA3, thereby preventing a deterioration in the display quality of the display panel DPc.

[0237] 12B and 12C, the second power supply P line PL2b and the connecting parts CP1a, CP2a, CP3, etc. are omitted from FIG. 12A, but the same explanation as for FIG. 12A can be applied.

[0238] 12B, the display panel DPd of the present invention may include a display area DA and a non-display area NDA. The display area DA may include first to ninth areas AA1b to AA9b. The first to ninth areas AA1b to AA9b may be separated from each other by separators SPRa. The first to ninth areas AA1b to AA9b may have the same shape. The first to ninth areas AA1b to AA9b may be arranged in a lattice pattern. However, the first to ninth areas AA1b to AA9b may be arranged in various ways without being limited to the arrangement shown in FIG. 12B.

[0239] The second power line PL2 (see FIG. 5) may include power lines 2-1 to 2-9 that apply different voltages to the first to ninth pixels arranged in the first to ninth areas AA1b to AA9b, respectively, so that the first to ninth pixels can emit light of different luminances for the same gray level.

[0240] 12C, the display panel DPe of the present invention may include a display area DA and a non-display area NDA. The display area DA may include first to fourth areas AA1c to AA4c. The first to fourth areas AA1c to AA4c may be separated from each other by separators SPR1a, SPR2a, and SPR3. For example, the first area AA1c and the second area AA2c may be separated from each other by the first separator SPR1a, the second area AA2c and the third area AA3c may be separated from each other by the second separator SPR2a, and the third area AA3c and the fourth area AA4c may be separated from each other by the third separator SPR3. The first to fourth areas AA1c to AA4c may be arranged diagonally with respect to the first direction DR1 and the second direction DR2.

[0241] The second power line PL2 (see FIG. 5) may include power lines 2-1 to 2-4 that apply different voltages to the first to fourth pixels arranged in the first to fourth regions AA1c to AA4c, respectively, so that the first to fourth pixels can emit light of different luminances for the same gray level.

[0242] Although the present invention has been described above with reference to preferred embodiments, it will be understood by those skilled in the art or those with ordinary knowledge in the art that various modifications and changes can be made to the present invention without departing from the spirit and scope of the present invention as defined in the claims below. Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification, but should be determined by the claims.

[0243] According to a preferred specific embodiment, the following is true:

[0244] The background and issues of this case are as follows (i) to (v).

[0245] (i) When using smartphones, smartwatches, tablet PCs, etc. outdoors on sunny days, they are sometimes switched to High Brightness Mode (HBM) so that the characters and figures on the screen can be read.

[0246] (ii) However, since the high brightness mode (HBM) has problems such as increased power consumption and heat generation, it is possible to designate only specific areas as high brightness mode (HBM) areas where the high brightness mode (HBM) is possible.

[0247] (iii) On the other hand, it is also possible to display a still image in some areas and update it as needed, while displaying a moving image in other areas. In this case, the display area for the still image may be set as a high brightness mode (HBM) area.

[0248] (vi) Patent Document 1 (WO2012052886) discloses that in a display panel in which light-emitting display elements (OLEDs) are arranged, first brightness control regions (50, 50') and second brightness control regions (51, 51') are set in the display region, and the drive current and brightness in the first brightness control regions (50, 50') are made larger than those in the second brightness control regions (51, 51'). This addresses the problem of brightness reduction due to attenuation of the drive voltage when the display panel becomes larger and the drive voltage lines become longer. (Figure 2 of Patent Document 1)

[0249] (v) On the other hand, Patent Document 2 (KR10-2449048B) discloses that the partition wall (300) surrounding the display area separates the organic light-emitting layer (350) from the periphery, thereby preventing leakage current from the organic light-emitting layer (350). (Figure 3 of Patent Document 2)

[0250] In a specific embodiment of the present application, the following A1 to A4 and the like may be employed, and at least one of the following A5 to A10 may be employed.

[0251] In the A1 high brightness mode (HBM) enabled region (second region AA2), a driving current and a driving voltage are supplied to the light emitting element (OLED2) through a driving voltage line (second-second power supply line PL2-2) separate from that in the non-high brightness mode region (first region AA1).

[0252] A1-1 Such a drive voltage line (2-2 power supply line PL2-2) for the high brightness mode (HBM) possible area (second area AA2) is arranged to extend within the display area (DA), and in particular, to extend within the non-high brightness mode area (first area AA1). (Figs. 5-6 of the present application, etc.)

[0253] The drive voltage line (2-2 power supply line PL2-2) for the A2 high brightness mode (HBM) possible region (second region AA2) supplies power to the common electrode (second electrode CE2) in the high brightness mode (HBM) region (second region AA2). That is, the supply voltage (second voltage ELVSS2) to the common electrode (second electrode; second cathode CE2) in the high brightness mode (HBM) region (second region AA2) can be set so that the difference with the voltage level of the pixel electrode (first electrode; first cathode CE1) is greater than the supply voltage (first voltage ELVSS1) to the common electrode (first electrode CE1) in the non-high brightness mode region (first region AA1). (Figures 10A and 10B of the present application)

[0254] A3 In the first section (A1), high brightness is achieved by lowering the power supply voltage (second voltage ELVSS2) to the common electrode (second electrode; second cathode CE2) in the high brightness mode (HBM) possible area (second area AA2).

[0255] A3-1 As shown in FIG. 10B of the present application, the power supply voltage (second voltage ELVSS2) can be gradually reduced, maintained at a constant voltage, and then gradually increased back to the original level.

[0256] A3-2 In the second section (A2) other than the first section (A1), the supply voltage (first voltage ELVSS1) (V1 in FIG. 10A) to the common electrode (first electrode CE1) in the non-high brightness mode area (first area AA1) and the supply voltage (second voltage ELVSS2) (V2 in FIG. 10B) to the common electrode (second electrode; second cathode CE2) in the high brightness mode (HBM) area (second area AA2) may be the same. (Figures 10A and 10B of the present application)

[0257] A3-3 By alternately, particularly periodically repeating the first section (A1) in which high brightness mode (HBM) is realized in the high brightness mode (HBM) possible area (second area AA2) and the second section (A2) in which high brightness mode is not realized, it is possible to improve visibility in the high brightness mode (HBM) possible area (second area AA2) while suppressing an increase in power consumption.

[0258] A4 The common electrode (second electrode; second cathode CE2) in the high brightness mode (HBM) enabled area (second area AA2) and the common electrode (first electrode; first cathode CE1) in the non-high brightness mode area (first area AA1) are separated by a partition wall (separator SPR).

[0259] A4-1 The partition (separator SPR) is formed on the pixel defining film (PDL) that forms the pixel aperture (light-emitting aperture OP-PDL), and both side surfaces are inversely tapered or overhanging.

[0260] A4-2 When the light-emitting layers (IML1, IML2) and the common electrode layers (CE1, CE2) covering them are formed by isotropic film formation such as vapor deposition, discontinuities occur at the lower ends of the inversely tapered side surfaces.

[0261] A4-3 The angle (taper angle θ) formed between the lower end of the side surface (SPR_W) of the partition wall (separator SPR) and the bottom surface of the partition wall (separator SPR) (the flat upper surface of the pixel defining layer (PDL)) is at least 90°, 100°, or 110°, and may be, for example, less than 150°, less than 140°, or less than 130°.

[0262] A4-4 The inorganic insulating layer (first inorganic layer IL1) covering the common electrode layer (layer of second electrodes CE1, CE2) contacts at least one of the partition wall (separator SPR) and the upper surface of the pixel defining layer (PDL) at the lower end of the side surface (SPR_W) of the partition wall (separator SPR). (Figs. 8B and 7 of the present application)

[0263] A5 The driving voltage line (2-2 power supply line PL2-2) for the common electrode (second electrode; second cathode CE2) in the high brightness mode (HBM) region (second region AA2) is formed on the first planarization layer (fifth insulating layer 50 as an organic layer) at the upper end of the backplane (driving element layer DDL) including the pixel circuit, and is covered by the second planarization layer (sixth insulating layer 60 as an organic layer).

[0264] A5-1 A pixel electrode (first-second electrode AE2) and a pixel defining film (PDL) are formed on the second planarizing layer (sixth insulating layer 60).

[0265] A5-2 The light-emitting layers (IML1, IML2) and the common electrode layers (CE1, CE2) covering them entirely cover the pixel defining film (PDL) and its openings (light-emitting opening OP-PDL and first and second openings OP1 and OP2 for the connection portion CP).

[0266] A5-3 A connection part (CP) that is electrically connected to the common electrode (second electrode; second cathode CE2) of the high brightness mode (HBM) area (second area AA2) is provided at the tip of the driving voltage line (second-2 power supply line PL2-2) for the high brightness mode (HBM) area (second area AA2).

[0267] A5-4 The connection part (CP) is formed by an opening (first opening OP1) that penetrates the second planarization layer (sixth insulating layer 60) and an opening (second opening OP2) that is provided inside the first opening OP1 and penetrates the first planarization layer (fifth insulating layer 50). (Figs. 7 and 8A, and Figs. 5 to 6 of the present application)

[0268] At the A6 connection portion (CP), the side end surface of the common electrode (CE2) for the high brightness mode possible area and the side end surface of the driving voltage line (2-2 power supply line PL2-2) for the high brightness mode are in direct contact at the bottom of the opening (second opening OP2) that penetrates the first planarization layer (fifth insulating layer 50).

[0269] A6-1 At the bottom of the opening (second opening OP2) that penetrates the first planarization layer (fifth insulating layer 50), the upper surface of the driving voltage line (2-2 power supply line PL2-2) for the high-brightness mode possible region and the common electrode (second electrode; second cathode CE2) for the high-brightness mode possible region sandwich the light-emitting layer (second intermediate layer IML2) from above and below, and further conductivity is achieved via this light-emitting layer (second intermediate layer IML2).

[0270] A6-2 The driving voltage line (second-second power supply line PL2-2) for the high-brightness mode area consists of a three-layer film consisting of a thick metal layer (L2) that has high conductivity and is susceptible to wet etching, and thin metal layers (L1, L3) above and below it that are resistant to wet etching.

[0271] A6-3 This three-layer film is, for example, a three-layer film (Ti / Al / Ti) in which an aluminum layer is sandwiched between titanium layers from above and below.

[0272] A6-4 By wet etching the driving voltage line (second-second power supply line PL2-2) for the high brightness mode area, which is made of such a three-layer film, the thick metal layer in the middle (L2) is recessed, and the thin metal layer above (L1) protrudes like a shelf to form a "chip part (TP)."

[0273] A6-5 The common electrode (CE2) for the high-brightness mode enabled area is interrupted at the "chip portion (TP)". However, the top surface of the "chip portion (TP)" and the common electrode (CE2) above it may be in further electrical contact via the light-emitting layer (second intermediate layer IML2). Also, the top surface of the lower thin metal layer (L1) and the common electrode (CE2) above it may be in further electrical contact via the light-emitting layer (second intermediate layer IML2). (Figures 7 and 8A of the present application)

[0274] A7 The driving voltage line (2-2 power supply line PL2-2) for the high brightness mode possible area can also be formed from a "connecting wiring (CN)" whose tip portion is made of a three-layer film placed on the first planarization layer (fifth insulating layer 50) as described above and forms a tip portion (TP), and a metal wiring (PL2-2a) covered by the first planarization layer (fifth insulating layer 50). (Figure 9 of the present application)

[0275] A8 The driving voltage line (second-first power supply line PL2-1) for the common electrode (CE1) in the non-high brightness region (first region AA1) and its connection portion (CP1) with the common electrode (CE1) can be formed in the same manner as the driving voltage line (second-second power supply line PL2-2) for the high brightness mode possible region and its connection portion (CP2) with the common electrode (CE2). Also, like the driving voltage line (second-second power supply line PL2-2) for the high brightness mode possible region, it can be arranged to extend within the display region (DA). (Figs. 11A to 11C of the present application)

[0276] A9 In addition to the non-high brightness area (first area AA1a), multiple high brightness mode possible areas (second to third areas AA2a, AA3) can be set, and different common electrode drive voltages (ELVSS1a, ELVSS2a, ELVSS3) can be applied to each of them. (Figure 12A of the present application)

[0277] A10 The display screen and common electrode can be divided into multiple regions by using lattice-shaped or diagonal separators (separators SPR). (Figs. 12B-12C of the present application) [Explanation of symbols]

[0278] BL Base Layer CNT contact hole CP connection DA display area DDL driving element layer LDL light emitting element layer NDA Hidden Area PDL Pixel Defined Membrane PL1, PL2, PL2-1, PL2-2 power lines PX pixels SPR Separator TP tip part

Claims

1. a base layer including a display area in which a plurality of pixels are arranged and a non-display area arranged around the display area; a first power line electrically connected to the plurality of pixels; a second power line electrically connected to the plurality of pixels; The display area is divided into a plurality of areas, The second power supply line is a second-1 power supply line that applies a first voltage to a first pixel arranged in a first region among the plurality of regions; a second-2 power line that applies a second voltage to second pixels arranged in a second region among the plurality of regions; During a first interval, the first voltage has a voltage level different from a voltage level of the second voltage; The display device, wherein the first voltage has the same voltage level as the second voltage during a second period excluding the first period.

2. Each of the plurality of pixels is a pixel driving unit disposed on the base layer and including a transistor; a light-emitting element disposed on the transistor, the light-emitting element including a first electrode, an intermediate layer disposed on the first electrode, and a second electrode disposed on the intermediate layer; the first power supply line is electrically connected to the transistor; The display device of claim 1 , wherein the second power line is electrically connected to the second electrode.

3. The display area is divided into the plurality of areas, and the separator has an obtuse tapered angle. the second electrode includes a 2-1 electrode and a 2-2 electrode electrically separated by the separator; 3. The display device according to claim 2, wherein the 2-1 electrode is disposed in the first region, and the 2-2 electrode is disposed in the second region.

4. The 2-1 electrode is electrically connected to the 2-1 power line, 4. The display device of claim 3, wherein the second-2 electrode is electrically connected to the second-2 power line.

5. 5. The display device according to claim 4, wherein a first connection portion where the second-2 power supply line and the second-2 electrode are connected to each other is defined in the second region.

6. the first connection portion includes a first layer, a second layer disposed on the first layer, and a third layer disposed on the second layer; 6. The display device of claim 5, wherein a side surface of the third layer protrudes outward from a side surface of the second layer, and the second-2 electrode is in contact with the side surface of the second layer.

7. a tip portion is defined by the side surface of the third layer; 7. The display device according to claim 6, wherein the second-2 electrode is partially interrupted by the tip portion.

8. 6. The display device of claim 5, wherein the second-2 power supply line includes the first connection portion, and the second-2 electrode is in contact with the second-2 power supply line.

9. 6. The display device of claim 5, further comprising a connection line disposed on a layer different from the second-second power line and electrically connected to the second-second power line through a contact hole.

10. 10. The display device of claim 9, wherein the connecting wire includes the first connection portion, and the 2-2 electrode contacts the connecting wire.

11. 5. The display device according to claim 4, wherein a second connection portion where the 2-1 power supply line and the 2-1 electrode are connected to each other is defined in the first region.

12. 12. The display device according to claim 11, wherein the 2-1 power supply line is arranged in the first region.

13. a pixel defining film having an opening defined therein that exposes at least a portion of the first electrode; The display device according to claim 3 , wherein the separator is disposed on the pixel defining film.

14. The second power supply line is a second-third power line configured to apply a third voltage to first pixels disposed in a third region among the plurality of regions; The display device of claim 1 , wherein the first voltage has a voltage level different from a voltage level of the third voltage during the first period.

15. The display device of claim 14 , wherein the second region and the third region are spaced apart from each other with the first region interposed therebetween.

16. The display device of claim 14 , wherein each of the second voltage and the third voltage has a voltage level lower than a voltage level of the first voltage.

17. 2. The display device of claim 1, wherein a plurality of second-2 power lines are provided, and the second-2 power lines are electrically connected to the second pixels, respectively.

18. 18. The display device of claim 17, wherein the second-2 power line extends in a first direction and is disposed in the display area.

19. The display device of claim 1 , wherein the first voltage has a voltage level higher than a voltage level of the second voltage during the first period.

20. 2. The display device of claim 1, wherein the first power supply line applies a first power supply voltage to the pixel, the first power supply voltage having a voltage level higher than each of the first voltage and the second voltage.

21. a pad unit disposed in the non-display area and including a first voltage pad receiving the first power supply voltage and a second voltage pad receiving each of the first voltage and the second voltage; the first voltage pad is electrically connected to a first power line; The display device of claim 20, wherein the second voltage pad is connected to the second power line.

22. The second voltage pad is a second-1 voltage pad for applying the first voltage to the second-1 power supply line; 22. The display device of claim 21, further comprising: a second-2 voltage pad for applying the second voltage to the second-2 power supply line.

23. a base layer including a first region and a second region surrounded by the first region; a driving element layer disposed on the base layer and including a pixel driving unit; a light-emitting element disposed on the driving element layer, the light-emitting element including a first electrode, an intermediate layer disposed on the first electrode, and a second electrode disposed on the intermediate layer; a first power line electrically connected to the first electrode; a second power supply line electrically connected to the second electrode, The second electrode is a second-1 electrode disposed in the first region and electrically connected to a second-1 power line of the second power line; a second-2 electrode disposed in the second region and electrically connected to a second-2 power line of the second power line; A display device in which a first connection portion where the second-2 power supply line and the second-2 electrode are connected is disposed in the second region.

24. the first connection portion includes a first layer, a second layer disposed on the first layer, and a third layer disposed on the second layer; 24. The display device of claim 23, wherein a side surface of the third layer protrudes outward from a side surface of the second layer, and the second-2 electrode is in contact with the side surface of the second layer.

25. a tip portion is defined by the side surface of the third layer; 25. The display device according to claim 24, wherein the 2-2 electrode is partially cut off by the tip portion.

26. the 2-1 power supply line applies a first voltage to the 2-1 electrode; 24. The display device of claim 23, wherein the second-2 power supply line applies a second voltage to the second-2 electrode.

27. During a first interval, the first voltage has a voltage level different from a voltage level of the second voltage; 27. The display device of claim 26, wherein the first voltage has the same voltage level as the second voltage during the second period excluding the first period.

28. 28. The display device of claim 27, wherein during the first period, the first voltage has a voltage level higher than a voltage level of the second voltage.

29. 24. The display device of claim 23, wherein a second connection portion is defined in the first region, where the 2-1 power supply line and the 2-1 electrode are connected to each other.

30. 30. The display device of claim 29, wherein the 2-1 power supply line is arranged in the first region.

31. The display device of claim 23 , wherein the base layer further includes a third region spaced apart from the second region with the first region interposed therebetween.

32. The second electrode is further including a second-third electrode disposed in the third region; 32. The display device of claim 31, wherein a third connection portion is defined in the third region, where a second-third power line of the second power line and the second-third electrode are connected to each other.

33. The separator further comprises a separator that separates the first region from the second region and has an obtuse taper angle, 24. The display device according to claim 23, wherein the 2-1 electrode and the 2-2 electrode are electrically separated by the separator.

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