Image pickup device

Abstract

To provide an imaging element and an imaging apparatus capable of suppressing streaking.SOLUTION: An imaging element includes a photoelectric conversion unit that converts light into electric charge, a transfer unit that transfers the electric charge of the photoelectric conversion unit, a discharge unit that discharges the electric charge of the photoelectric conversion unit, a first control line that is connected to the transfer unit and to which a first control signal for supplying a first potential to the transfer unit is output, and a second control line that is connected to the discharge unit and to which a second control signal for supplying a second potential higher than the first potential to the discharge unit is output.SELECTED DRAWING: Figure 2

Description

[Technical Field]

[0001] The present invention relates to an imaging device. [Background technology]

[0002] BACKGROUND ART Conventionally, a solid-state imaging device including an imaging element using a MOS transistor has been known (Patent Document 1). [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Laid-Open No. 2005-65184 Summary of the Invention

[0004] In a conventional solid-state imaging device with an image sensor using MOS transistors, the charge equivalent to the capacitance of the photodiode is transferred to the floating diffusion, causing the potential of the vertical signal line to fluctuate excessively relative to the input range of the analog-to-digital converter. As a result, in a conventional solid-state imaging device with an image sensor using MOS transistors, the current value of the current source decreases compared to normal operation, causing changes in the ground potential and power supply potential, and worsening streaking.

[0005] One aspect of the present invention is an imaging element comprising a photoelectric conversion unit that converts light into electric charges, a transfer unit that transfers the electric charges of the photoelectric conversion unit, a discharge unit that discharges the electric charges of the photoelectric conversion unit, a first control line connected to the transfer unit and outputting a first control signal that supplies a first potential to the transfer unit, and a second control line connected to the discharge unit and outputting a second control signal that supplies a second potential higher than the first potential to the discharge unit.

[0006] One aspect of the present invention is an imaging device including the imaging element described above.

[0007] One aspect of the present invention is a semiconductor module comprising: a first layer having the above-mentioned imaging device in which unit cells, each of which is a set of a predetermined number of the imaging elements, are arranged two-dimensionally; and a second layer having the first control line and the second control line. [Brief explanation of the drawings]

[0008] [Figure 1] 1 is a diagram showing a circuit of an image sensor 1 according to an embodiment. [Figure 2] 2 is a diagram showing a pixel PX and a pixel control circuit PC according to the embodiment. FIG. [Figure 3] 10A and 10B are diagrams illustrating a state in which the amount of signal charge accumulated in the photodiode PD according to the embodiment is adjusted. [Figure 4] 10 is a diagram showing a state in which a dark current occurs on the side of the discharge transistor TX2 according to the embodiment. FIG. [Figure 5] 10 is a timing chart for explaining when the potential V_TX2 of the discharge transistor TX2 according to the embodiment is adjusted. [Figure 6] 10 is a timing chart in which the potential adjustment end time according to the modified example of the embodiment is after time T4 and before time T5. [Figure 7] 10 is a timing chart in a case where the potential adjustment start time is a time before time T1 when the select transistor SEL is turned on according to a modification of the embodiment. [Figure 8] 1 is a side view of a semiconductor module M according to an embodiment. [Figure 9] 1 is a front view of a semiconductor module M according to an embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0009] Hereinafter, the embodiments will be described in detail with reference to the drawings. 1 is a diagram showing an example of a circuit of an image sensor 1 according to this embodiment. The image sensor 1 is a CMOS solid-state image sensor.

[0010] The image sensor 1 includes a pixel section 2, a vertical scanning circuit 3, a horizontal scanning circuit 4, vertical signal lines VL, and an ADC. The pixel section 2 is made up of a plurality of pixels PX arranged two-dimensionally. The vertical signal lines VL are provided corresponding to each column of pixels PX, and pixel signals of the pixels PX in the corresponding column are supplied to the vertical signal lines VL. The ADC performs A / D (analog / digital) conversion on the signals output from the vertical signal lines VL.

[0011] In the example shown in Fig. 1, the number of pixels PX is 6 x 4 (6 rows, 4 columns), but the number is not limited to this. Also, in Fig. 1, pixels PX designated by the symbol Gr are pixels that sense Gr (green), pixels PX designated by the symbol R are pixels that sense R (red), and pixels PX designated by the symbol B are pixels that sense B (blue). In this way, pixels that sense Gr (green), pixels that sense R (red), and pixels that sense B (blue) are arranged alternately in the pixel section 2.

[0012] (Explanation of pixel circuit) 2 is a diagram showing an example of a pixel PX and a pixel control circuit PC. The pixel PX includes a photodiode PD, a transfer transistor TX1, a drain transistor TX2, a floating diffusion FD, a reset transistor RST, an amplification transistor SF, a selection transistor SEL, and a current source VDD.

[0013] The photodiode PD converts light into an electric charge. The transfer transistor TX1 transfers the electric charge of the photodiode PD from the photodiode PD to the floating diffusion FD. The drain transistor TX2 drains the electric charge of the photodiode PD. The floating diffusion FD receives the electric charge of the photodiode PD via the transfer transistor TX1 and converts the electric charge into a voltage. The reset transistor RST resets the electric potential of the floating diffusion FD. The amplification transistor SF outputs a signal corresponding to the electric potential of the floating diffusion FD. The selection transistor SEL supplies a signal corresponding to the electric potential of the floating diffusion FD to the vertical signal line VL. The current source VDD is a power supply potential.The transfer transistor TX1, the drain transistor TX2, the reset transistor RST, the amplification transistor SF, and the selection transistor SEL provided in the pixel PX are all NMOS transistors.

[0014] The gates of the transfer transistor TX1 and the drain transistor TX2 are commonly connected for each row, and control signals for controlling the transfer transistor TX1 and the drain transistor TX2 are supplied to these gates from the vertical scanning circuit 3 (see FIG. 1). A first control line L1 is connected to the transfer transistor TX1 and outputs a first control signal ΦTX1 that supplies a first potential to the transfer transistor TX1. A second control line L2 is connected to the drain transistor TX2 and outputs a second control signal ΦTX2 that supplies a second potential higher than the first potential to the drain transistor TX2.

[0015] The pixel control circuit PC is a circuit for controlling the pixels PX. The pixel control circuit PC is included in the vertical scanning circuit 3. The pixel control circuit PC includes a transfer section driver D1, a discharge section driver D2, a transfer section power supply VTX_H, a transfer section negative power supply VTX_L1, and a discharge section negative power supply VTX_L2. The transfer section driver D1 outputs a first control signal ΦTX1 to the transfer transistor TX1 via a first control line L1. The discharge section driver D2 outputs a second control signal ΦTX2 to the discharge transistor TX2 via a second control line L2.

[0016] The transfer unit power supply VTX_H is a power supply common to the transfer unit driver D1 and the discharge unit driver D2. Meanwhile, the transfer unit negative power supply VTX_L1 is the power supply for the transfer unit driver D1, and the discharge unit negative power supply VTX_L2 is the power supply for the discharge unit driver D2. In the pixel control circuit PC, the transfer unit driver D1 and the discharge unit driver D2 each have their own negative power supplies, the transfer unit negative power supply VTX_L1 and the discharge unit negative power supply VTX_L2. Therefore, in the pixel PX, the potential of the transfer unit driver D1 and the potential of the discharge unit driver D2 can be made different from each other. In other words, in the pixel PX, the voltage on the negative power supply side of the discharge transistor TX2 is variable.

[0017] In the pixel PX, the voltage on the negative power supply side of the drain transistor TX2 is variable, so the potential V_TX2 of the drain transistor TX2 is also variable. In the pixel PX, the second control line L2 is connected to the drain transistor TX2, and a second control signal ΦTX2 is output to supply a second potential to the drain transistor TX2. Because the potential V_TX2 of the drain transistor TX2 is variable, the second potential can be made higher than the first potential supplied to the transfer transistor TX1 by the first control signal ΦTX1.

[0018] The gates of the reset transistors RST are commonly connected for each row, and a control signal ΦRST for controlling the reset transistors RST is supplied to this gate from the vertical scanning circuit 3 (see FIG. 1). The gates of the select transistors SEL are commonly connected for each row, and a control signal ΦSEL for controlling the select transistors SEL is supplied to this gate from the vertical scanning circuit 3.

[0019] The photodiode PD of each pixel PX generates signal charge according to the amount of incident light (subject light). The transfer transistor TX1 of each pixel PX is turned on during a high-level period of the first control signal ΦTX1, and transfers the charge in the photodiode PD to the floating diffusion FD. The discharge transistor TX2 of each pixel PX is turned on during a low-level period of the first control signal ΦTX1, and discharges the signal charge accumulated in the photodiode PD. The reset transistor RST is turned on during the high level period of the control signal ΦRST (the period of the potential of the current source VDD), and resets the floating diffusion FD.

[0020] The amplifier transistor SF has a drain connected to a current source VDD, a gate connected to a floating diffusion FD, and a source connected to the drain of the select transistor SEL, the source of which is connected to a vertical signal line VL. The constant current source TD supplies a current to the vertical signal line VL when the select transistor SEL of the pixel PX corresponding to the vertical signal line VL is turned on.

[0021] The amplification transistor SF of each pixel PX outputs a voltage to the vertical signal line VL via the selection transistor SEL according to the voltage value of the floating diffusion FD. The selection transistor SEL is turned on during a high-level period of the control signal ΦSEL, connecting the source of the amplification transistor SF to the vertical signal line VL.

[0022] 3 shows a state in which the amount of signal charge accumulated in the photodiode PD is adjusted by adjusting the potential V_TX2 of the drain transistor TX2. The potential V1 schematically represents the respective potentials of the current source VDD, the drain transistor TX2, the photodiode PD, the transfer transistor TX1, and the floating diffusion FD in this state.

[0023] When the drain transistor TX2 is turned on, the potential V_TX2 of the drain transistor TX2 changes from potential V_A, which is the same as the potential V_TX1 of the transfer transistor TX1, which is off, to potential V_B, which is higher than potential V_A. As a result, part of the signal charge accumulated in the photodiode PD is discharged to the current source VDD, and the amount of signal charge accumulated in the photodiode PD is adjusted. In the image sensor 1, the amplitude of the potential of the vertical signal line VL is limited by the circuit of the pixel PX.

[0024] The control for adjusting the potential V_TX2 of the discharge transistor TX2 is performed based on feedback from a user or a sensor. When the feedback from the user or a sensor is acquired, the discharge section driver D2 outputs a second control signal ΦTX2, which supplies a second potential, from the second control line L2 to the discharge transistor TX2. The value of the second potential is determined based on, for example, the gain of the ADC. The value of the second potential is set in advance, for example, when the pixel PX is manufactured. The value of the second potential may be specified by feedback from a user or a sensor.

[0025] (Explanation of when to adjust the potential of the discharge transistor) When capturing an image of a low-brightness subject, the potential V_TX1 is adjusted so that dark current does not occur on the transfer transistor TX1 side. Meanwhile, as described above, in the pixel PX, the potential V_TX2 of the discharge transistor TX2 is adjusted. Therefore, when capturing an image of a low-brightness subject, the potential V_TX2 on the discharge transistor TX2 side may deviate from the optimal value for suppressing the generation of dark current, resulting in the generation of dark current. Figure 4 shows a state in which dark current occurs on the discharge transistor TX2 side due to the adjustment of the potential V_TX2. In the following, a case will be described in which the timing for adjusting the potential V_TX2 of the drain transistor TX2 is set or selected in order to suppress the generation of dark current.

[0026] FIG. 5 is a timing chart for explaining the timing at which the potential V_TX2 of the drain transistor TX2 according to this embodiment is adjusted. At time T1, the control signal ΦSEL goes to high level, turning on the selection transistor SEL. At time T2, the second control signal ΦTX2 goes high, turning on the drain transistor TX2. Also at time T2, the control signal ΦRST goes low, turning off the reset transistor RST. In response to these, the signal charge accumulated in the photodiode PD is drained, and the floating diffusion FD is reset. When the floating diffusion FD is reset, the voltage of the vertical signal line VL rises compared to before the floating diffusion FD was reset.

[0027] At time T3, the second control signal ΦTX2 goes low, turning off the drain transistor TX2. When the drain transistor TX2 turns off, signal charges are accumulated in the photodiode PD. At time T4, the first control signal ΦTX1 goes high, turning on the transfer transistor TX1. When the transfer transistor TX1 turns on, the signal charge accumulated in the photodiode PD starts to be transferred to the floating diffusion FD. As a result, the voltage of the vertical signal line VL starts to decrease.

[0028] At time T5, the first control signal ΦTX1 goes low, turning off the transfer transistor TX1. When the transfer transistor TX1 turns off, the transfer of signal charge from the photodiode PD to the floating diffusion FD ends. The length of the period ET0 from time T3 to time T5 corresponds to the exposure time. The potential difference V0 on the vertical signal line VL before the transfer transistor TX1 turns on and after it turns off is detected as luminance. The ADC then stores the potential difference V0 at a node, and then performs A / D conversion by comparing the value obtained by changing the voltage stored at the node with the voltage value of the dark signal previously read using a comparator.

[0029] At time T31, the second control signal ΦTX2 goes high, turning on the drain transistor TX2. The level of the second control signal ΦTX2 that goes high at time T31 is lower than the level of the second control signal ΦTX2 that goes high at time T2. As a result, the drain transistor TX2 is supplied with a potential V_B, which is higher than the potential V_A during the period from time T2 to time T3, via the second control line L2. The potential V_A during the period from time T2 to time T3 is the potential when the transfer transistor TX1 is in the on state. At time T32, the second control signal ΦTX2 goes low, turning off the drain transistor TX2. The length of the period from time T31 to time T32, during which the potential V_TX2 of the drain transistor TX2 goes to the potential V_A, is, for example, approximately 1.0 μs. In the following description, time T31 may be referred to as the potential adjustment start time, and time T32 as the potential adjustment end time.

[0030] The potential adjustment start time is the time immediately before time T4 when the signal charge accumulated in the photodiode PD starts to be transferred to the floating diffusion FD. Therefore, the potential V_TX2 of the drain transistor TX2 is maintained at the potential V_A until the time immediately before time T4 when the transfer of the signal charge starts. Maintaining the potential V_TX2 at the potential V_A means that the potential V_TX2 is maintained at the optimal potential value for suppressing the generation of dark current. Therefore, the potential V_TX2 of the drain transistor TX2 is maintained at the optimal potential value for suppressing the generation of dark current until the time immediately before time T4 when the transfer of the signal charge starts. Here, the time immediately before time T4 refers to any time included in the period from a time a predetermined time before time T4 to time T4. The drain transistor TX2 is turned off at time T32, which is before time T4.

[0031] In the present embodiment, an example has been described in which the potential adjustment start time at which the discharge transistor TX2 is supplied with the potential V_TX2 higher than the potential V_A by the second control signal ΦTX2 is immediately before the time T4 at which the transfer of signal charges starts, but this is not limiting. The potential adjustment start time may be any time after the discharge transistor TX2 is supplied with the potential V_A by the second control signal ΦTX2 and before the supply of the potential V_A to the transfer transistor TX1 by the first control signal ΦTX1 is completed.

[0032] For example, a potential V_B higher than the potential V_A may be supplied to the drain transistor TX2 by the second control signal ΦTX2 during a period between time T3 when the supply of the potential V_A to the drain transistor TX2 by the second control signal ΦTX2 is completed and time T4 when the supply of the first potential to the transfer transistor TX1 by the first control signal ΦTX1 is started, that is, during a period between time T4 and an intermediate period between time T3 and time T4. In other words, the potential adjustment start period may be a period between time T4 and an intermediate period between time T3 when the photodiode PD is reset and time T4 when the transfer of signal charges is started.

[0033] The time T32, which is the time when the potential adjustment ends, may be a time after the time T4 when the transfer of signal charges begins and a time before the time T5 when the supply of the potential V_A to the transfer transistor TX1 by the first control signal ΦTX1 is completed. 6 shows a timing chart in which the potential adjustment ends after time T4 and before time T5. In FIG. 6, time T31a is the potential adjustment start time and time T32a is the potential adjustment end time. In FIG. 6, the period in which the potential V_TX2 of the discharge transistor TX2 becomes the potential V_B overlaps with the period in which the signal charge is being transferred.

[0034] The potential adjustment start time may be a time after the ADC reads the dark signal and before time T5 when the ADC performs A / D conversion.

[0035] The potential adjustment start time may be a time before time T1 when the select transistor SEL is turned on. If the potential adjustment start time is a time before time T1, the signal charge accumulated in the photodiode PD is discharged before time T1 when the select transistor SEL is turned on. 7 shows a timing chart in which the potential adjustment starts before time T1 when the select transistor SEL turns on. In FIG. 7, the period from time T2b to time T3b is the period in which the photodiode PD and the floating diffusion FD are reset. In FIG. 7, the period from time T31b to time T32b is the period in which the potential V_TX2 of the discharge transistor TX2 becomes the potential V_B. The select transistor SEL turns on at time T1b. Time T1b is later than time T32b. In FIG. 7, the reset transistor RST turns on at time T6b, which is later than time T1b when the select transistor SEL turns on.

[0036] In the image sensor 1, a row from which a pixel signal is to be read out is sequentially selected as a selected row from among rows each consisting of a plurality of pixels PX (see FIG. 1) arranged in a matrix. The potential adjustment may start at a time before the row including the pixel PX having the drain transistor TX2 whose potential VTX_2 is to be adjusted is selected as the selected row.

[0037] As described above, in pixel PX, after the discharge transistor TX2 is supplied with a potential V_A by the second control signal ΦTX2 and before the supply of the first potential to the transfer transistor TX1 by the first control signal ΦTX1 is completed, the discharge transistor TX2 is supplied with a potential V_B higher than the potential V_A by the second control signal ΦTX2.

[0038] (Explanation of the structure of a semiconductor module equipped with a solid-state imaging device) 8 and 9 are diagrams showing an example of the configuration of a semiconductor module M according to this embodiment. Fig. 8 is a side view of the semiconductor module M, and Fig. 9 is a front view of the semiconductor module M. The imaging element 1 is used, for example, by being included in a semiconductor module M. The semiconductor module M is configured, for example, by stacking three layers of chips. The three layers of chips are a MOS image sensor chip IS, a signal processing chip DSP, and a logic circuit chip LC. The semiconductor module M includes the MOS image sensor chip IS, the signal processing chip DSP, and the logic circuit chip LC. The MOS image sensor chip IS includes the imaging element 1 in which unit cells, each of which includes a predetermined number of pixels PX, are arranged two-dimensionally. As described above, the imaging element 1 includes the pixels PX. The signal processing chip DSP includes a pixel control circuit PC, an ADC, and a constant current source TD. As described above, the pixel control circuit PC includes a first control line L1 and a second control line L2. The logic circuit chip LC performs various logical operations based on the image signal from the imaging element 1.

[0039] As described above, the potential V_B is the value of the potential V_TX2 of the drain transistor TX2 during the period when the charge of the photodiode PD is drained.

[0040] The embodiments of the present invention have been described above, but the correspondence between the present invention and the above embodiments will now be supplemented with a description. In the above embodiment, the imaging device of the present invention corresponds to the imaging element 1, and the imaging element corresponds to the pixel PX. Furthermore, the photoelectric conversion unit of the present invention corresponds to the photodiode PD, the transfer unit of the present invention corresponds to the transfer transistor TX1, the discharge unit of the present invention corresponds to the discharge transistor TX2, the first control line of the present invention corresponds to the first control line L1, and the second control line of the present invention corresponds to the second control line L2. Furthermore, the first potential and the third potential of the present invention correspond to the potential V_A, the first control signal of the present invention corresponds to the first control signal ΦTX1, the second potential and the fourth potential of the present invention correspond to the potential V_B, and the second control signal of the present invention corresponds to the second control signal ΦTX2. Furthermore, the first period of the present invention corresponds to time T3, and the second period of the present invention corresponds to time T4. The semiconductor module in the present invention corresponds to the semiconductor module M. The first layer in the present invention corresponds to the MOS image sensor chip IS, and the second layer corresponds to the signal processing chip DSP.

[0041] (1) In the above embodiment, the pixel PX includes a photodiode PD that converts light into an electric charge, a transfer transistor TX1 that transfers the electric charge of the photodiode PD, a discharge transistor TX2 that discharges the electric charge of the photodiode PD, a first control line L1 that is connected to the transfer transistor TX1 and outputs a first control signal ΦTX1 that supplies a potential V_A to the transfer transistor TX1, and a second control line L2 that is connected to the discharge transistor TX2 and outputs a second control signal ΦTX2 that supplies a potential V_B that is higher than the potential V_A to the discharge transistor TX2.

[0042] In a pixel PX configured as described above, the charge in the photodiode PD can be discharged by supplying the drain transistor TX2 with a potential V_B higher than the potential V_A supplied to the transfer transistor TX1, thereby preventing excessive fluctuations in the potential of the vertical signal line VL. The drain of the drain transistor TX2 functions as an overflow drain, which is equivalent to providing the pixel PX with an overflow drain. Note that in the pixel PX, as an example, the potential V_TX2 of the drain transistor TX2 is adjusted based on the gain of the ADC. In the pixel PX, streaking can be prevented by preventing excessive fluctuations in the potential of the vertical signal line VL.

[0043] Here, conventionally, the transfer unit power supply and the transfer unit negative power supply are power supplies common to the transfer unit driver and the discharge unit driver, and therefore, it has not been possible to adjust the value of the potential supplied to the discharge transistor to a value different from the value of the potential supplied to the transfer transistor. In addition, conventionally, a CLIP circuit is used to limit the amplitude of the potential of the vertical signal line and suppress streaking. In contrast, the pixel PX of the above embodiment can limit the amplitude of the potential of the vertical signal line, eliminating the need for an additional circuit such as a CLIP circuit. The pixel PX can occupy a smaller area on the chip than conventional pixels, increasing the degree of freedom in chip design.

[0044] (2) Also, in the above embodiment, after the potential V_A is supplied to the discharge transistor TX2 by the second control signal ΦTX2 and before the supply of the potential V_A to the transfer transistor TX1 by the first control signal ΦTX1 is completed, the pixel PX supplies the discharge transistor TX2 with a potential V_B higher than the potential V_A by the second control signal ΦTX2.

[0045] In the pixel PX having such a configuration, even if supplying the discharge transistor TX2 with a potential V_B higher than the potential V_A supplied to the transfer transistor TX1 causes the potential V_TX2 of the discharge transistor TX2 to shift from the optimal value of the potential for suppressing dark current, thereby causing dark current to occur, the potential V_TX2 can be adjusted to a time before the transfer of signal charge to the floating diffusion FD is completed, thereby shortening the period during which the potential V_TX2 deviates from the optimal value of the potential for suppressing dark current. In other words, in the pixel PX, the period during which dark current may occur can be made shorter than the length of the period from time T2 to time T5, thereby suppressing the occurrence of dark current.

[0046] (3) In addition, in the above embodiment, pixel PX receives a potential V_B higher than the potential V_A from the discharge transistor TX2 by the second control signal ΦTX2 during a period between time T3 when the supply of potential V_A to the discharge transistor TX2 is completed by the second control signal ΦTX2 and time T4 when the supply of potential V_A to the transfer transistor TX1 is initiated by the first control signal ΦTX1, and during a period between time T3 and time T4 and time T4.

[0047] In the pixel PX having such a configuration, even if the potential V_TX2 of the discharge transistor TX2 deviates from the optimal value for suppressing dark current and dark current is generated, the time when the potential V_TX2 is adjusted can be set to a time before the transfer of signal charge to the floating diffusion FD is completed, and the period during which the potential V_TX2 deviates from the optimal value for suppressing dark current can be made shorter than the period between time T4 and the midpoint between time T3 and time T4. In other words, in the pixel PX, the period during which dark current can be generated can be made shorter than the period between time T4 and the midpoint between time T3 and time T4, and therefore the generation of dark current can be suppressed.

[0048] (4) In the above embodiment, the image sensor 1 includes pixels PX. In the image sensor 1 configured as described above, it is possible to prevent the potential of the vertical signal line VL from fluctuating excessively.

[0049] (5) In addition, in the above embodiment, the semiconductor module M includes a MOS image sensor chip IS having an imaging element 1 in which unit cells, each of which has a predetermined number of pixels PX, are arranged two-dimensionally, and a signal processing chip DSP having a first control line L1 and a second control line L2. In the semiconductor module M having such a configuration, the area of ​​the MOS image sensor chip IS is the area of ​​a predetermined number of pixels PX, so that the size can be made compact.

[0050] One embodiment of the present invention has been described in detail above with reference to the drawings, but the specific configuration is not limited to that described above, and various design changes and the like are possible within the scope that does not deviate from the gist of the present invention. [Explanation of symbols]

[0051] 1. Image sensor PX pixels PD photodiode TX1 transfer transistor TX2 Emission Transistor L1 First control line L2 Second control line ΦTX1 First control signal ΦTX2 Second control signal M Semiconductor Module IS MOS image sensor chip DSP signal processing chip

Claims

[Claim 1] a photoelectric conversion unit that converts light into an electric charge; a transfer unit that transfers charges from the photoelectric conversion unit; a discharge unit that discharges the charge of the photoelectric conversion unit; a first control line connected to the transfer unit and outputting a first control signal that supplies a first potential to the transfer unit; a second control line connected to the discharge section, through which a second control signal is output to supply a second potential higher than the first potential to the discharge section; An imaging element comprising:

Images