Wafer inspection apparatus and method for inspecting electrical characteristics of wafer

Abstract

To provide a wafer inspection device and an inspection method of electric characteristics capable of achieving both time reduction of electric characteristic inspection on one wafer and suppression of creeping discharge.SOLUTION: A wafer inspection device 100 includes a wafer chuck 30 for holding a wafer W, and a whole surface probe card 50 having a top plate part 51, a whole surface probe needle 54 electrically connected to the wafer W, and a frame-shaped pressure holding seal 55. A wafer inspection device 100 is closed by a wafer chuck 30, a pressure holding seal 55 and a top plate part 51 to form an internal space 60 in which a wafer is arranged, and includes a pressurization path 43 as a pressurization part for pressurizing the internal space 60. The method of inspecting the electrical characteristics of the wafer W includes attaching the overall probe card 50 to the wafer chuck 30 to form the internal space 60 in which the wafer W is disposed, and inspecting the electrical characteristics of the wafer W via the overall probe card 50 in a state where the internal space 60 is pressurized.SELECTED DRAWING: Figure 3

Description

[Technical Field]

[0001] The present disclosure relates to a wafer inspection apparatus that inspects the electrical characteristics of a plurality of semiconductor chips formed on a wafer, and a method for inspecting the electrical characteristics of a wafer. [Background technology]

[0002] It has been known that when a wafer on which multiple semiconductor chips are formed is subjected to an electrical characteristic test, if a voltage higher than a predetermined level is applied, creeping discharge occurs at the edge of the semiconductor chip. In particular, creeping discharge is likely to occur in the case of semiconductor chips formed with power devices, since a high voltage must be applied during the electrical characteristic test. When creeping discharge occurs, discharge marks from the test remain on the semiconductor chip, resulting in the semiconductor chip being deemed a defective product. Furthermore, when creeping discharge occurs, the measured voltage oscillates, causing the measured value to become unstable, resulting in an abnormal measurement value and resulting in the product being deemed a defective product.

[0003] Therefore, a wafer inspection device capable of suppressing the occurrence of creeping discharge due to the application of high voltage has been proposed, for example, as described in Patent Document 1. The wafer inspection device described in Patent Document 1 includes a stage on which a wafer is placed and a probe card arranged above the stage, and the probe card is formed with a pressure wall extending toward the stage and having an opening, and a probe arranged within the opening. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] Japanese Patent Publication No. 2022-70357 Summary of the Invention [Problem to be solved by the invention]

[0005] When electrical characteristics of a semiconductor chip are inspected, the wafer inspection device described above can suppress the occurrence of creeping discharge by enclosing the semiconductor chip with a pressure wall and applying a predetermined pressure.

[0006] However, this wafer inspection device is configured to perform electrical characteristic tests on each of the multiple semiconductor chips on a wafer, so testing one wafer requires a pressure application process and an inspection process for each semiconductor chip, which takes time.

[0007] In view of the above, the present disclosure aims to provide a wafer inspection device and a method for inspecting the electrical characteristics of a wafer that can reduce the time required to inspect the electrical characteristics of a single wafer having multiple semiconductor chips while suppressing creeping discharge in the semiconductor chips. [Means for solving the problem]

[0008] According to one aspect of the present disclosure, a wafer inspection apparatus is a wafer inspection apparatus used to inspect electrical characteristics of a plurality of semiconductor chips formed on a wafer, the wafer inspection apparatus comprising: a wafer chuck (30) for holding a wafer; a full-surface probe card (50) having a top plate portion (51) covering the entire area of ​​the wafer, full-surface probe needles (54) formed on a lower surface (51b) of the top plate portion facing the wafer and electrically connected to each electrode pad of a plurality of semiconductor chips, and a frame-shaped pressure-retaining seal (55) attached to the lower surface of the top plate portion and in close contact with the outer side of the wafer of the wafer chuck; The wafer chuck is closed by a wafer chuck, a pressure-retaining seal, and a top plate, and includes a pressurizing section (43) for pressurizing an internal space (60) in which the wafer is placed.

[0009] This wafer inspection device holds a wafer on a wafer chuck, and then attaches a frame-shaped pressure-retaining seal, a top plate covering the wafer, and a full-surface probe card with full-surface probe needles to the wafer chuck, thereby forming an internal space that encloses the entire wafer.The wafer inspection device also has a pressurizing unit that pressurizes the internal space, making it possible to inspect the electrical characteristics of multiple semiconductor chips via the full-surface probe needles while pressurizing the entire wafer.As a result, the wafer inspection device only requires a single pressurizing process when inspecting the electrical characteristics of all multiple semiconductor chips on a single wafer, thereby reducing inspection time and suppressing the occurrence of creeping discharge.

[0010] According to one aspect of the present disclosure, a method for inspecting electrical characteristics of a wafer is a method for inspecting electrical characteristics of a wafer including a plurality of semiconductor chips, the method comprising: The wafer is held by a wafer chuck (30), a full-surface probe card (50) having full-surface probe needles (54) electrically connected to the electrode pads of the plurality of semiconductor chips and a frame-shaped pressure-retaining seal (55) larger than the outer diameter of the wafer, attached to the wafer chuck, and sealing the space in which the wafer is placed to form an internal space (60); The internal space is pressurized to a certain pressure to place the entire wafer under a pressurized atmosphere. In a pressurized atmosphere, the electrical characteristics of a plurality of semiconductor chips are inspected via a full-surface probe card.

[0011] In this wafer electrical characteristics inspection method, a wafer is held on a wafer chuck, and a frame-shaped pressure-retaining seal, a top plate covering the wafer, and a full-surface probe card having full-surface probe needles are attached to the wafer chuck to form an internal space enclosing the entire wafer. This inspection method then pressurizes the internal space at a constant pressure, and inspects the electrical characteristics of multiple semiconductor chips via the full-surface probe needles while keeping the entire wafer in a pressurized environment. This wafer electrical characteristics inspection method thus performs only one pressurization step per wafer to inspect multiple semiconductor chips, thereby shortening the time required to inspect the electrical characteristics of a single wafer and suppressing the occurrence of creeping discharge.

[0012] The reference symbols in parentheses attached to each component indicate an example of the correspondence between the component and the specific components described in the embodiments described below. [Brief explanation of the drawings]

[0013] [Figure 1] 1 is a cross-sectional view of a wafer inspection apparatus according to an embodiment, showing a state before a full surface probe card is mounted on a wafer chuck. [Figure 2] 10 is an explanatory diagram of an internal space formed when the full surface probe card is attached to a wafer chuck. FIG. [Figure 3] 1 is a cross-sectional view of the wafer inspection apparatus according to the embodiment, showing a state after a full surface probe card has been mounted on a wafer chuck. [Figure 4] FIG. 2 is a diagram showing the top side of a full-surface probe card. [Figure 5] FIG. 10 is a view showing the underside of a full-surface probe card. [Figure 6] 10A and 10B are diagrams showing an example of alignment between a full surface probe card and a wafer chuck according to a first modified example. [Figure 7] FIG. 10 is a cross-sectional view showing an example of the structure of a full-surface probe needle according to a second modified example. [Figure 8] FIG. 10 is a cross-sectional view showing an example of the structure of a full surface probe card and a wafer chuck according to a third modified example. [Figure 9] FIG. 11 is a cross-sectional view showing an example of a holding mechanism between a full surface probe card and a wafer chuck according to a fourth modified example. [Figure 10] 13A and 13B are diagrams showing examples of contact between probes for individual pieces and electrodes of chip pieces according to a fifth modified example. [Figure 11] FIG. 13 is a cross-sectional view showing an example of the structure of a chip piece electrode and a piece probe according to a sixth modified example. DETAILED DESCRIPTION OF THE INVENTION

[0014] Hereinafter, embodiments of the present disclosure will be described with reference to the accompanying drawings. In the following embodiments, identical or equivalent parts will be denoted by the same reference numerals.

[0015] (Embodiment) A wafer inspection apparatus 100 according to an embodiment will now be described. The wafer inspection apparatus 100 is suitable for use in inspecting the electrical characteristics of a wafer W having a plurality of semiconductor chips on which power devices such as power MOSFETs are formed, but can also be used to inspect a wafer W on which semiconductor devices other than power devices are formed. MOSFET is an abbreviation for Metal Oxide Semiconductor Field Effect Transistor. In this specification, a case in which power devices are formed on a wafer W and a high voltage equal to or higher than a predetermined level is applied in inspecting the electrical characteristics will be described as a representative example, but the use of the wafer inspection apparatus 100 is not limited to this.

[0016] [Basic configuration] 1, the wafer inspection apparatus 100 includes a wafer stage operating unit 10, a base unit 20, a wafer chuck 30, a full surface probe card 50, an individual piece probe 70, and a prober head 80. As shown in FIG. 2, the wafer inspection apparatus 100 holds the wafer W on the wafer chuck 30 and attaches the full surface probe card 50 to the wafer chuck 30, thereby forming a closed internal space 60 in which the wafer W is placed. By pressurizing the internal space 60, the wafer inspection apparatus 100 can inspect the electrical characteristics of multiple semiconductor chips formed on the wafer W via the full surface probe card 50 while placing the entire wafer W in a pressurized environment.

[0017] The wafer stage operating unit 10 is a moving stage that moves the base 20, wafer chuck 30, and full-surface probe card 50. The wafer stage operating unit 10 moves and rotates the attached base 20, wafer chuck 30, and full-surface probe card 50, for example, in the X-axis direction, Y-axis direction, Z-axis direction, and θ-direction. The X-axis direction and Y-axis direction are, for example, two orthogonal axial directions in a plane along the surface 30a of the wafer chuck 30 on which the wafer W is held. The Z-axis direction is a direction orthogonal to the XY plane to which the X-axis and Y-axis directions belong, and can also be said to be a direction along the thickness direction of the wafer chuck 30. The θ-direction is a rotation direction around the Z-axis direction.

[0018] The wafer stage operation unit 10 is used to move the full surface probe card 50 when bringing the full surface probe card 50 into contact with the individual piece probes 70 and inspecting the electrical characteristics of the wafer W. The wafer stage operation unit 10 is composed of, for example, three movement mechanisms corresponding to the X-axis, Y-axis, and Z-axis directions and a rotation mechanism in the θ direction, and has multiple known drive mechanisms such as a mechanical drive mechanism having a motor and a ball screw. The wafer stage operation unit 10 has a working area in the Z-axis direction that is at least equal to the height of the full surface probe card 50.

[0019] The base 20 is detachably attached to, for example, the wafer stage operating unit 10, and serves as the base of the wafer chuck 30. In the base 20, together with the wafer chuck 30, a first vacuum path 41, a second vacuum path 42, and a pressurization path 43 are formed.

[0020] The wafer chuck 30 is, for example, detachably attached to the base 20 and holds the wafer W on the surface 30a by vacuum suction. The wafer chuck 30 has a plurality of first suction ports 31 formed on the surface 30a and communicating with a first vacuum path 41. The first suction ports 31 suction-fix the wafer W. The wafer chuck 30 has a plurality of second suction ports 32 formed on the outer side of the first vacuum path 41 and communicating with a second vacuum path 42. The second suction ports 32 suction-hold a pressure-retaining seal 55 (described later). The wafer chuck 30 has a pressure port 33 formed between the first suction ports 31 and the second suction ports 32 and communicating with a pressurization path 43. A predetermined gas can be injected into the internal space 60 through the pressure port 33 to create a pressurized atmosphere in the internal space 60. The wafer chuck 30 is configured to have a known heating / cooling device (not shown) installed inside so that the wafer temperature can be controlled when inspecting the electrical characteristics of semiconductor chips formed on the wafer W, and to maintain the wafer temperature constant at a predetermined temperature during inspection.

[0021] 1, the first vacuum path 41 is a plurality of through holes formed integrally in the base 20 and the wafer chuck 30. For example, one end of the first vacuum path 41 communicates with the first suction port 31 of the wafer chuck 30, and the other end communicates with the outer periphery of the base 20, and is connected to a vacuum source (not shown) through a pipe 21 connected to the base 20. This allows the wafer inspection device 100 to vacuum-suck the wafer W via the first suction port 31 by drawing a vacuum through the first vacuum path 41, as shown in FIG.

[0022] The second vacuum path 42 is, for example, a plurality of through holes formed independently of the first vacuum path 41 and integrally formed in the base 20 and the wafer chuck 30. For example, one end of the second vacuum path 42 is connected to the second suction port 32 of the wafer chuck 30, and the other end is connected to the outer periphery of the base 20, and is connected to a vacuum source (not shown) through a pipe 22 connected to the base 20 side. As a result, by drawing a vacuum through the second vacuum path 42, it is possible to vacuum-suck the entire surface probe card 50 via the second suction port 32.

[0023] The pressurization path 43 is a plurality of through-holes formed integrally in the base 20 and the wafer chuck 30, independent of the vacuum paths 41 and 42, and serves as a pressurization unit for pressurizing the internal space 60. For example, one end of the pressurization path 43 is connected to the pressurization port 33 of the wafer chuck 30, and the other end is connected to the outer periphery of the base 20. The pressurization path 43 is connected to a gas supply source (not shown) through a pipe 23 connected to the base 20. By supplying gas to the internal space 60 through the pressurization path 43, the internal space 60 can be pressurized, and ultimately the entire wafer W held by suction can be pressurized. The wafer inspection device 100 creates a pressurized environment by, for example, supplying a predetermined amount of gas to the internal space 60 through the pressurization path 43 and then closing a solenoid valve (not shown) provided on the pipe 23 to stop the gas supply. The wafer inspection device 100 then performs an electrical characteristic inspection of the wafer W while maintaining a constant pressure pressurized environment in which the gas supplied within the internal space 60 is stationary. The pressure port 33 is formed inside the area directly below the pressure retention seal 55 of the full-surface probe card 50, i.e., between the first suction port 31 and the second suction port 32. The pressure when pressurizing the internal space 60 by the pressure path 43 is determined so as to be a voltage at which no spark voltage is generated, based on Paschen's law, which determines the spark voltage as a function of the product of the air pressure and the distance between the electrodes, for example.

[0024] As shown in FIG. 1 , the full-surface probe card 50 includes a top plate 51 that covers the wafer W and a frame-shaped pressure-retaining seal 55 attached to the top plate 51. When attached to the wafer chuck 30, the full-surface probe card 50 closes the area where the wafer W is placed, forming an internal space 60. The full-surface probe card 50 contacts each electrode pad of each semiconductor chip across the entire wafer W held by the wafer chuck 30 while contacting the probe needles 71 of the chip probes 70 on the side opposite the wafer chuck 30, thereby enabling electrical characteristic testing. The full-surface probe card 50 is configured to appropriately change the patterns of chip chip electrodes 52 and full-surface probe needles 54 (described later) depending on the size, arrangement, pattern, etc., of the multiple semiconductor chips formed on the wafer W. The full-surface probe card 50 is manufactured, for example, using known wafer burn-in materials and a known manufacturing method.

[0025] When the top plate 51 is attached to the wafer chuck 30, the surface exposed to the outside is the upper surface 51a. As shown in FIG. 4, for example, the upper surface 51a is provided with a plurality of chip piece electrodes 52 and a plurality of slits 53 separating adjacent chip piece electrodes 52. The surface of the top plate 51 opposite the upper surface 51a, which faces the wafer chuck 30, is the lower surface 51b. As shown in FIG. 5, for example, the lower surface 51b is provided with full-surface probe needles 54 connected to the electrodes of each semiconductor chip on the wafer W. The top plate 51 is a plate-like member whose main portion is made of an insulating material such as glass epoxy resin. The top plate 51 preferably has a circular planar shape similar to that of the wafer W, but is not limited to this shape. The top plate 51 need only cover all of the first suction port 31, the second suction port 32, and the pressure port 33 of the wafer chuck 30. The top plate 51 may have other planar shapes, such as an ellipse or a polygon, and its shape, size, etc. may be modified as appropriate.

[0026] 4 and 5, a plurality of alignment marks AM for aligning with the wafer chuck 30 are formed on the upper surface 51a and the lower surface 51b of the top plate portion 51. The alignment marks AM are provided to bring the full surface probe needles 54 into contact with each electrode pad on the wafer W with high precision, but the number of alignment marks AM may be one.

[0027] 4, the chip piece electrodes 52 are formed in a pattern corresponding to the electrode pads of the semiconductor chips formed on the wafer W, and a plurality of chip piece electrodes 52 are formed on the upper surface 51a of the top plate portion 51. The chip piece electrodes 52 are electrically connected to full surface probe needles 54 formed on the lower surface 51b. The chip piece electrodes 52 are configured, for example, in a printed pattern that matches the electrode pattern of the semiconductor chips on the wafer W, but are not limited to this and may have other structures such as pin-on probes, wire probes, and MEMS probes. MEMS is an abbreviation for Micro Electro Mechanical Systems.

[0028] As shown in FIG. 4 , for example, a plurality of slits 53 are formed around each of the plurality of chip piece electrodes 52 along the four outer edges thereof in a top view. The slits 53 are, for example, through-grooves provided to separate adjacent chip piece electrodes 52 and suppress creeping discharge during electrical characteristic testing. Forming the slits 53 can shorten the distance between the chip piece electrodes 52. For example, when applying a voltage of 2000 V at 1 atmosphere, if the slits 53 are not provided, a creeping distance of approximately 7 mm is required to suppress creeping discharge. However, by providing the slits 53, this is treated as a clearance distance, and a minimum clearance distance of 1 mm can be achieved.

[0029] The full-surface probe needles 54 are pin-shaped, as shown in FIGS. 1 and 5, and contact the electrode pads of each semiconductor chip on the wafer W, enabling voltage application to each semiconductor chip. The full-surface probe needles 54 are configured to make point contact with the electrodes of the wafer W, such as pin-shaped probes, wire probes, or MEMS probes. The height difference between the full-surface probe needles 54 and the pressure-retaining seal 55 is adjusted so that a specified overdrive amount is achieved when the full-surface probe needles 54 contact the electrode pads of each semiconductor chip on the wafer W held by the wafer chuck 30. The height here refers to the amount of protrusion from the lower surface 51b. The overdrive amount is the distance the tip of the full-surface probe needle 54 moves from the position where it contacts the electrode pad on the wafer W when the full-surface probe card 50 is attached to the wafer chuck 30 to the position of the tip when the wafer chuck 30 is completely attached. For example, when the pressure retaining seal 55 is attached to the same surface 30a of the wafer chuck 30 as the wafer W, the full surface probe needles 54 are made smaller in height than the pressure retaining seal 55 within a predetermined range.

[0030] The pressure-retaining seal 55 is, for example, a frame-shaped member attached to the surface 30a of the wafer chuck 30 outside the holding area for holding the wafer W. The pressure-retaining seal 55 is suction-held by the second suction ports 32 of the wafer chuck 30 in a tight contact state. The pressure-retaining seal 55 is made of any material and has a thickness greater than or equal to a predetermined value so as to have sufficient rigidity to prevent deformation due to pressure, thereby maintaining a pressurized environment when the internal space 60 is pressurized. For example, the pressure-retaining seal 55 is bonded to the underside 51b of the top plate 51 with an adhesive (not shown) or is integral with the top plate 51 to maintain airtightness to prevent pressure leakage when the internal space 60 is pressurized. For example, when electrical characteristic testing is performed on the wafer W at a constant high or low temperature, the pressure-retaining seal 55 is made of any material that can withstand the temperature. The height of the pressure-retaining seal 55 from the underside 51b of the top plate 51 is greater than that of the full-surface probe needles 54 to prevent the full-surface probe needles 54 from coming into contact with objects other than the wafer W during transport of the full-surface probe card 50.

[0031] The individual piece probe 70 has, for example, probe needles 71 corresponding to the chip piece electrodes 52 of the full surface probe card 50. The individual piece probe 70 is connected to a measuring instrument for electrical characteristic testing (not shown), and by bringing the probe needles 71 into contact with the chip piece electrodes 52 of the full surface probe card 50, it is possible to test the electrical characteristics of the wafer W held on the wafer chuck 30. The probe needles 71 may be of any configuration as long as they are electrically connected to the chip piece electrodes 52 and can test the electrical characteristics, such as a cantilever probe, a pin-on probe, a wire probe, or an MEMS probe. The arrangement of the probe needles 71 of the individual piece probe 70 is appropriately changed depending on the pattern of the chip piece electrodes 52 of the full surface probe card 50.

[0032] The prober head 80 is a support member that supports the individual probes 70. The prober head 80 is disposed opposite the upper surface 51a of the full-surface probe card 50, with the individual probes 70 detachably attached thereto, for example.

[0033] The above is the basic configuration of the wafer inspection device 100 of this embodiment.

[0034] [Electrical property inspection] Next, the flow of inspection of the electrical characteristics of the wafer W by the wafer inspection device 100 will be described.

[0035] The wafer inspection device 100 has, for example, a first loader unit (not shown) for transporting the wafer W, a second loader unit (not shown) for transporting the full surface probe card 50, and a wafer aligner (not shown) for determining the orientation of the wafer W. The wafer inspection device 100 also has, for example, an imaging unit (not shown) for capturing images of the wafer W, the full surface probe card 50, etc.

[0036] First, the wafer inspection apparatus 100 uses a first loader unit to remove the wafer W from a wafer carrier (not shown), and uses a wafer aligner to determine the orientation of the wafer W using a notch or orientation flat formed on the wafer W as a marker. Next, the wafer inspection apparatus 100 aligns the wafer W by, for example, placing the wafer W on the surface 30a of the wafer chuck 30 and analyzing image data obtained by capturing an image of the wafer W with an imaging unit using a known image authentication technique. The wafer inspection apparatus 100 then records position information (X, Y, θ) of the wafer W on a recording medium (not shown), and then performs vacuum suction using the first vacuum path 41 to suction-hold the wafer W on the wafer chuck 30. The position information (X, Y, θ) refers to, for example, the position in the X-axis direction, the position in the Y-axis direction, and the rotational state in the θ direction.

[0037] Next, the wafer inspection apparatus 100 uses a second loader unit to retrieve the full-surface probe card 50 stored in a storage unit (not shown), for example. The storage unit is, for example, a part of the wafer inspection apparatus 100. Next, the wafer inspection apparatus 100 acquires position information (X, Y, θ) of the full-surface probe card 50, for example, by capturing and analyzing the alignment marks AM of the full-surface probe card 50 with an imaging unit. Then, the wafer inspection apparatus 100 aligns the full-surface probe card 50 based on the position information (X, Y, θ) of the wafer W and the position information (X, Y, θ) of the full-surface probe card 50, and places the full-surface probe card 50 on the wafer chuck 30. Thereafter, the wafer inspection apparatus 100 draws a vacuum using, for example, the second vacuum path 42, suction-fixes the pressure-retaining seal 55 of the full-surface probe card 50 to the wafer chuck 30, and forms an internal space 60 in which the wafer W is placed. Through these steps, the full surface probe needles 54 of the full surface probe card 50 are brought into contact with the electrode pads of the plurality of semiconductor chips on the wafer W with high precision.

[0038] Next, the wafer inspection apparatus 100, for example, operates the wafer stage operating unit 10 to move the wafer chuck 30 to which the full-surface probe card 50 is attached in the Z-axis direction, thereby bringing the chip electrodes 52 of the full-surface probe card 50 into contact with the individual piece probes 70. The wafer inspection apparatus 100 then supplies a predetermined gas, such as air, from the pressurizing path 43 to the internal space 60, creating a pressurized atmosphere at a predetermined constant pressure (e.g., but not limited to, 5 atmospheres). Since the pressure-retaining seal 55 has a predetermined or higher rigidity, deformation and pressure fluctuations due to pressurization of the internal space 60 are suppressed, thereby maintaining a constant pressurized environment. The pressure in this pressurizing step is appropriately set to a pressure that can suppress creeping discharge depending on the type of semiconductor device formed on the wafer W and the voltage applied in the inspection step. The pressurizing step of the internal space 60 may be performed before the step of contacting the full-surface probe card 50 with the individual piece probes 70.

[0039] Next, the wafer inspection apparatus 100 applies a predetermined voltage and current from a measuring device (not shown) to the semiconductor chips on the wafer W via the individual piece probe 70 and the full surface probe card 50, thereby inspecting the electrical characteristics. This places the wafer W in a pressurized environment when inspecting the electrical characteristics of the wafer W on which power semiconductor devices are formed, thereby preventing creeping discharge caused by the application of a high voltage. If necessary, the wafer inspection apparatus 100 may pre-control the temperature of the wafer W to a high temperature of 100°C or higher or a low temperature of 0°C or lower using a heating / cooling device (not shown) in the wafer chuck 30, and inspect the electrical characteristics at a constant temperature and pressure.

[0040] Then, while maintaining the internal space 60 pressurized at a constant pressure, the wafer inspection apparatus 100 operates the wafer stage operating unit 10, brings the chip probes 70 into contact with the other chip electrodes 52, and performs electrical characteristic tests on the other semiconductor chips in the same manner as described above. The wafer inspection apparatus 100 repeats this process to perform electrical characteristic tests on all of the semiconductor chips on one wafer W. As a result, electrical characteristic tests on one wafer W require only one pressurizing step followed by multiple inspection steps, significantly reducing the time required compared to conventional inspection apparatuses that require a pressurizing step for each semiconductor chip.

[0041] For example, if one wafer W has 100 semiconductor chips and the time required for the pressure application step in a conventional inspection device is 20 seconds, then the pressure application step alone will take 20 x 100 = 2000 seconds to inspect the electrical characteristics of one wafer W. In contrast, with wafer inspection device 100, the pressure application step is performed only once in the electrical characteristics inspection of one wafer W. Therefore, even if the time required for this pressure application step is 60 seconds, this reduces the time by 1940 seconds, thereby improving the throughput of the equipment.

[0042] Then, the wafer inspection apparatus 100, for example, releases the vacuum suction of the pressure retention seal 55 via the second vacuum path 42, and then temporarily removes the full surface probe card 50 via the second loader unit. Subsequently, the wafer inspection apparatus 100, for example, releases the vacuum suction of the wafer W via the first vacuum path 41, transports the inspected wafer W via the first loader unit, and recovers the wafer W into the wafer carrier. Thereafter, for a new wafer W, the series of steps including the wafer alignment step and transport step, the full surface probe card 50 alignment step and transport step, the internal space 60 pressurization step, and the electrical characteristic inspection step are repeated.

[0043] The above is the basic flow of the inspection of the electrical characteristics of the wafer W by the wafer inspection apparatus 100.

[0044] In the above description, the internal space 60 enclosed by the wafer chuck 30 and the full-surface probe card 50 is pressurized, and electrical characteristic testing is performed on the entire wafer W in a pressurized environment. However, it is of course possible to perform electrical characteristic testing without pressurizing the internal space 60. For example, the wafer inspection apparatus 100 can perform electrical characteristic testing without pressurizing the internal space 60, leaving it at 1 atmosphere, or by connecting the pressurization path 43 to a vacuum source and reducing the pressure in the internal space 60. Furthermore, by creating an inert gas atmosphere in the internal space, the apparatus can also be used to test the electrical characteristics of devices that are susceptible to oxidation at high temperatures. In this way, the wafer inspection apparatus 100 can perform electrical characteristic testing by controlling the internal space 60 to various pressure environments, such as pressurized, atmospheric pressure, reduced pressure, or an inert gas atmosphere, or to different atmospheric gas environments, depending on the type of semiconductor device formed on the wafer W.

[0045] In the wafer inspection apparatus 100 according to this embodiment, an internal space 60 is formed that encloses the entire wafer W by attaching to the wafer chuck 30 a full surface probe card 50 having a frame-shaped pressure-retaining seal 55 and a top plate portion 51 that covers the wafer W. The wafer inspection apparatus 100 applies pressure to the internal space 60 through a pressure path 43, and is able to inspect the electrical characteristics of multiple semiconductor chips via the full surface probe needles 54 while the entire wafer W is pressurized. Therefore, the wafer inspection apparatus 100 requires only one pressurization step when inspecting the electrical characteristics of all of the multiple semiconductor chips on a single wafer W, thereby reducing the inspection time and suppressing the occurrence of creeping discharge.

[0046] Furthermore, since the wafer inspection device 100 is structured so that the full-surface probe needles 54 of the full-surface probe card 50 contact the electrode pads of each semiconductor chip on the wafer W, it is possible to inspect the electrical characteristics of the entire area from the center to the outermost periphery of the wafer W.

[0047] Furthermore, the wafer inspection device 100 is configured to be able to inspect electrical characteristics by bringing the piece probes 70 into contact with the chip piece electrodes 52 while the entire area of ​​the wafer W remains covered with the full-surface probe card 50. In other words, the wafer inspection device 100 is configured without a structure that operates directly above the wafer W exposed to the outside, and therefore has the effect of suppressing adhesion of particles to the wafer W.

[0048] Furthermore, when testing electrical characteristics, wafer inspection device 100 only needs to pressurize or depressurize internal space 60, allowing wafer stage operating unit 10 to be placed in an atmospheric environment. In other words, wafer inspection device 100 does not need to place the entire facility in a pressurized or depressurized environment, resulting in a configuration that reduces facility costs.

[0049] (First Modification) The wafer inspection apparatus 100 only needs to be able to align the wafer chuck 30 and the full surface probe card 50, and the full surface probe card 50 does not need to have alignment marks AM. The wafer inspection apparatus 100 may be configured, for example as shown in Fig. 6, in which positioning pins 34 are provided on the wafer chuck 30 and positioning holes 551 corresponding to the positioning pins 34 are provided on the pressure retaining seal 55. Conversely, the wafer inspection apparatus 100 may be configured such that positioning pins are provided on the pressure retaining seal 55 side and corresponding positioning holes are provided on the wafer chuck 30.

[0050] Furthermore, the wafer inspection apparatus 100 may be configured such that the full surface probe card 50 is held by the second loader unit and is aligned when being mounted on the wafer chuck 30 before being transported to the wafer chuck 30. For example, the full surface probe card 50 may be aligned in advance using an alignment mark or the like, and then the full surface probe card 50 may be transported by the second loader unit while its orientation is fixed, and then mounted on the wafer chuck 30.

[0051] (Second Modification) In the wafer inspection apparatus 100, instead of a structure in which the full surface probe needles 54 make point contact with the electrode pads of the wafer W like pins, the full surface probe needles 54 may have a structure in which they make surface contact with the electrode pads, as shown in Fig. 7. In this way, the full surface probe needles 54 may be configured to be able to make contact with the electrode pads of the wafer W, and the shape, size, height, arrangement, number, etc. of the full surface probe needles 54 may be changed as appropriate.

[0052] (Third Modification) 8, the wafer inspection apparatus 100 may be configured such that a step portion 35 is provided on the wafer chuck 30, and the pressure retaining seal 55 is held at a position lower than the wafer W. In this case, the wafer chuck 30 has, for example, the step portion 35 facing the base 20 outside the area that suction-holds the wafer W, and the second suction port 32 is formed closer to the base 20 than the first suction port 31, and is configured to suction-hold the pressure retaining seal 55.

[0053] Furthermore, the pressure retaining seal 55 may be held at a position on the wafer chuck 30 that is higher than the position at which the wafer W is placed. Here, a position higher than the position at which the wafer W is placed means a position farther from the base 20 than the wafer W, and conversely, a lower position means a position closer to the base 20 than the wafer W.

[0054] As a result, in addition to the effects of the above embodiment, the wafer inspection apparatus 100 can suppress contact between the full surface probe needles 54 and other components during transportation, etc., thereby more reliably protecting the full surface probe needles 54. Furthermore, the wafer inspection apparatus 100 can easily control the pressing force and overdrive amount when the full surface probe needles 54 come into contact with the wafer W.

[0055] (Fourth Modification) 9, the wafer inspection apparatus 100 may have a configuration in which the base 20 and wafer chuck 30 do not have the second vacuum path 42, and the wafer chuck 30 and full-surface probe card 50 are provided with mechanical holding mechanisms. The wafer inspection apparatus 100 may have a configuration in which, for example, the pressure retaining seal 55 has a mounting portion 552 on its outer periphery, and the wafer chuck 30 has a mechanically operable holding portion 36. The holding portion 36 is configured to, for example, fit into and hold the mounting portion 552 of the pressure retaining seal 55, and mechanically maintain a tight contact state between the pressure retaining seal 55 and the wafer chuck 30 so that the pressurized state can be maintained even when the internal space 60 is pressurized.

[0056] In this way, the wafer inspection device 100 only needs to be configured to maintain a constant pressure when the internal space 60 is pressurized and to be able to hold the full-surface probe card 50 on the wafer chuck 30, and the fixing structure of the full-surface probe card 50 on the wafer chuck 30 can be modified as appropriate.

[0057] (Fifth Modification) The wafer inspection device 100 may be configured to perform electrical characteristic testing on multiple semiconductor chips on the wafer W one by one using the probe needles 71 of the chip probe 70, or may be configured to perform electrical characteristic testing on multiple semiconductor chips that are not adjacent to each other at once. For example, as shown in Fig. 10, the chip probe 70 is configured to have multiple probe needles 71 that can apply voltage simultaneously to multiple chip electrodes 52 that are arranged at a distance greater than the pattern distance at which creeping discharge occurs when a predetermined voltage is applied to the semiconductor chip at 1 atmosphere.

[0058] For example, the multiple probe needles 71 are configured to contact two chip piece electrodes 52 spaced apart by a distance d1 in the X-axis direction and two chip piece electrodes 52 spaced apart by a distance d2 in the Y-axis direction, for a total of four chip piece electrodes 52. In this case, for example, the linear distance d3 between the chip piece electrodes 52 on the diagonal of the rectangle formed by the four chip piece electrodes 52 is, like the distances d1 and d2, a distance that exceeds the distance at which creeping discharge occurs. This makes it possible to inspect the electrical characteristics of some of the multiple semiconductor chips on the wafer W via the multiple chip piece electrodes 52 in a single inspection process, further shortening the time required for the inspection process.

[0059] When the individual piece probe 70 is configured as a multi-chip measurement probe in this way, the full-surface probe card 50 may be configured without the slits 53 separating the multiple chip piece electrodes 52. Also, while Fig. 10 shows a representative example in which the probe needles 71 are in contact with four chip piece electrodes 52, the present invention is not limited to this example, and the number and arrangement of the probe needles 71 may be changed as appropriate.

[0060] According to this modification, in addition to the same effects as the above embodiment, the wafer inspection device 100 also has the effect of reducing the number of electrical characteristic inspection processes required for one wafer W, as the individual piece probe 70 is a multi-chip measurement probe, thereby shortening the inspection time.

[0061] (Sixth Modification) 11 , the wafer inspection device 100 may be configured such that the chip piece electrodes 52 of the full-surface probe card 50 are pin-shaped such as pin-pin probes, and the piece probes 70 have electrode pads 72 instead of probe needles 71. Even in this case, the wafer inspection device 100 can inspect the electrical characteristics of the wafer W by bringing the chip piece electrodes 52 into contact with the electrode pads 72 of the piece probes 70.

[0062] The wafer inspection apparatus 100 according to the first to sixth modified examples described above also provides the same effects as those of the above embodiment. For ease of understanding, only some of the relevant components of the wafer inspection apparatus 100 are shown in Figures 6 to 10, and other components are omitted.

[0063] (Other embodiments) Although the present disclosure has been described with reference to the embodiments, it is understood that the present disclosure is not limited to the embodiments or structures. The present disclosure also encompasses various modifications and modifications within the scope of equivalents. In addition, various combinations and forms, as well as other combinations and forms including only one element, more than one, or less than one, are also within the scope and spirit of the present disclosure.

[0064] It goes without saying that in each of the above embodiments, the elements constituting the embodiments are not necessarily essential unless they are specifically stated as essential or are clearly considered essential in principle. Furthermore, in each of the above embodiments, when numerical values ​​such as the number, values, amounts, and ranges of the components of the embodiments are mentioned, they are not limited to the specific numbers unless they are specifically stated as essential or are clearly limited to a specific number in principle. Furthermore, in each of the above embodiments, when the shapes, positional relationships, etc. of the components are mentioned, they are not limited to the shapes, positional relationships, etc., unless they are specifically stated or are clearly limited to a specific shape, positional relationship, etc. in principle. [Explanation of symbols]

[0065] 30...wafer chuck, 41...first vacuum path, 42...second vacuum path, 43...pressure path, 50...full surface probe card, 51...top plate portion, 51a...upper surface (of top plate portion), 51b...lower surface (of top plate portion), 52...chip individual electrode, 54...full surface probe needle, 55...pressure retention seal, 60...internal space, 70...individual probe

Claims

1. A wafer inspection device used to inspect electrical characteristics of a plurality of semiconductor chips formed on a wafer, comprising: a wafer chuck (30) for holding the wafer; a full-surface probe card (50) including a top plate portion (51) covering the entire area of ​​the wafer, full-surface probe needles (54) formed on a lower surface (51b) of the top plate portion facing the wafer and electrically connected to each electrode pad of the plurality of semiconductor chips, and a frame-shaped pressure-retaining seal (55) attached to the lower surface of the top plate portion and in close contact with the outer side of the wafer of the wafer chuck, The wafer inspection device is provided with a pressure section (43) for pressurizing an internal space (60) in which the wafer is placed, the internal space (60) being closed by the wafer chuck, the pressure-retaining seal, and the top plate section.

2. 2. The wafer inspection device of claim 1, wherein the surface of the top plate portion opposite the lower surface is an upper surface (51a), and the full surface probe card has a plurality of chip piece electrodes (52) on the upper surface that correspond to each electrode pad of the plurality of semiconductor chips, are electrically independent, and are electrically connected to the full surface probe needles.

3. 3. The wafer inspection device according to claim 2, further comprising a chip probe (70) connected to at least one of the plurality of chip electrodes and used to inspect electrical characteristics of the semiconductor chip.

4. 4. The wafer inspection device according to claim 1, wherein the wafer chuck has a first vacuum path (41) for suction-holding the wafer, a second vacuum path (42) for suction-holding the pressure-retaining seal, and a pressure path (43) communicating with the internal space and constituting the pressure section.

5. A method for inspecting electrical characteristics of a wafer having a plurality of semiconductor chips, comprising: The wafer is held by a wafer chuck (30); a full-surface probe card (50) having full-surface probe needles (54) electrically connected to the electrode pads of the plurality of semiconductor chips and a frame-shaped pressure-retaining seal (55) larger than the outer diameter of the wafer, attached to the wafer chuck, and sealing the space in which the wafer is placed to form an internal space (60); The internal space is pressurized at a constant pressure to place the entire wafer under a pressurized atmosphere; a wafer electrical characteristic inspection method, wherein electrical characteristics of the plurality of semiconductor chips are inspected via the full surface probe card in the pressurized atmosphere;

6. 6. The method for inspecting electrical characteristics of a wafer according to claim 5, wherein placing the entire wafer under a pressurized atmosphere is carried out by injecting a predetermined gas into the internal space through a pressurized path (43) formed in the wafer chuck and communicating with the internal space.

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