Semiconductor device

Abstract

To provide a semiconductor device which can be suitably manufactured.SOLUTION: The semiconductor device includes a plurality of conductive layers 110 stacked in a stacking direction, first and second conductor columns 120 and extending in the stacking direction and arranged in a first direction intersecting the stacking direction, an insulating column 131 extending in the stacking direction and provided between the first and second conductor columns, a semiconductor layer 130 formed along an outer peripheral surface of the insulating column, connected to the first and second conductor columns, and facing the plurality of conductive layers, and a memory film 140 provided between the plurality of conductive layers and the semiconductor layer. In a cross section intersecting the stacking direction, at least a part of an outer peripheral surface of the semiconductor layer is formed substantially along a shape of a circle, an ellipse, or an oval, and at least a part of the first conductor column and at least a part of the second conductor column are provided outside the shape of the circle, the ellipse, or the oval.SELECTED DRAWING: Figure 5

Description

[Technical Field]

[0001] The present embodiment relates to a semiconductor device. [Background technology]

[0002] 2. Description of the Related Art As semiconductor memory devices and the like become more highly integrated, studies are underway regarding three-dimensionalization of semiconductor memory devices and the like. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] US Patent Application Publication No. 2023 / 0106571 [Patent Document 2] Japanese Patent Publication No. 2023-016592 Summary of the Invention [Problem to be solved by the invention]

[0004] A semiconductor device that can be suitably manufactured is provided. [Means for solving the problem]

[0005] A semiconductor device according to one embodiment includes a plurality of conductive layers stacked in a stacking direction, first and second conductor columns extending in the stacking direction and aligned in a first direction intersecting the stacking direction, insulating columns extending in the stacking direction and provided between the first and second conductor columns, semiconductor layers formed along outer circumferential surfaces of the insulating columns, connected to the first and second conductor columns, and facing the plurality of conductive layers, and a memory film provided between the plurality of conductive layers and the semiconductor layer. In a cross section intersecting the stacking direction, at least a portion of the outer circumferential surface of the semiconductor layer is formed substantially along the shape of a circle, an ellipse, or an oval, and at least a portion of the first conductor column and at least a portion of the second conductor column are provided outside the shape of the circle, the ellipse, or the oval. [Brief explanation of the drawings]

[0006] [Figure 1]1 is a schematic circuit diagram showing a configuration of a semiconductor memory device according to a first embodiment. [Figure 2] FIG. 2 is a schematic plan view showing the configuration of the semiconductor memory device. [Figure 3] FIG. 2 is a schematic XY cross-sectional view showing the configuration of the semiconductor memory device. [Figure 4] FIG. 2 is a schematic plan view showing the configuration of the semiconductor memory device. [Figure 5] FIG. 2 is a schematic perspective view showing the configuration of the semiconductor memory device. [Figure 6] FIG. 2 is a schematic perspective view showing the configuration of the semiconductor memory device. [Figure 7] FIG. 2 is a schematic XY cross-sectional view showing the configuration of the semiconductor memory device. [Figure 8] FIG. 2 is a schematic XY cross-sectional view showing the configuration of the semiconductor memory device. [Figure 9] FIG. 2 is a schematic cross-sectional view showing the configuration of the semiconductor memory device. [Figure 10] 5A to 5C are schematic cross-sectional views for explaining a manufacturing method of the semiconductor memory device. [Figure 11] 5A to 5C are schematic cross-sectional views for explaining the manufacturing method. [Figure 12] 5A to 5C are schematic cross-sectional views for explaining the manufacturing method. [Figure 13] 5A to 5C are schematic cross-sectional views for explaining the manufacturing method. [Figure 14] 5A to 5C are schematic cross-sectional views for explaining the manufacturing method. [Figure 15] 5A to 5C are schematic cross-sectional views for explaining the manufacturing method. [Figure 16] 5A to 5C are schematic cross-sectional views for explaining the manufacturing method. [Figure 17] 5A to 5C are schematic cross-sectional views for explaining the manufacturing method. [Figure 18] 5A to 5C are schematic cross-sectional views for explaining the manufacturing method. [Figure 19] 5A to 5C are schematic cross-sectional views for explaining the manufacturing method. [Figure 20] 5A to 5C are schematic cross-sectional views for explaining the manufacturing method. [Figure 21] 5A to 5C are schematic cross-sectional views for explaining the manufacturing method. [Figure 22] 5A to 5C are schematic cross-sectional views for explaining the manufacturing method. [Figure 23] 5A to 5C are schematic cross-sectional views for explaining the manufacturing method. [Figure 24] 5A to 5C are schematic cross-sectional views for explaining the manufacturing method. [Figure 25] 5A to 5C are schematic cross-sectional views for explaining the manufacturing method. [Figure 26] 5A to 5C are schematic cross-sectional views for explaining the manufacturing method. [Figure 27] 5A to 5C are schematic cross-sectional views for explaining the manufacturing method. [Figure 28] 5A to 5C are schematic cross-sectional views for explaining the manufacturing method. [Figure 29] 5A to 5C are schematic cross-sectional views for explaining the manufacturing method. [Figure 30] FIG. 10 is a schematic cross-sectional view showing the configuration of a portion of a semiconductor memory device according to a second embodiment. [Figure 31] FIG. 10 is a schematic cross-sectional view showing the configuration of a portion of a semiconductor memory device according to a second embodiment. [Figure 32] FIG. 10 is a schematic cross-sectional view showing the configuration of a portion of a semiconductor memory device according to a second embodiment. [Figure 33] 5A to 5C are schematic cross-sectional views for explaining a manufacturing method of the semiconductor memory device. [Figure 34] 5A to 5C are schematic cross-sectional views for explaining the manufacturing method. [Figure 35] 5A to 5C are schematic cross-sectional views for explaining the manufacturing method. [Figure 36] 5A to 5C are schematic cross-sectional views for explaining the manufacturing method. [Figure 37] 5A to 5C are schematic cross-sectional views for explaining the manufacturing method. [Figure 38]5A to 5C are schematic cross-sectional views for explaining the manufacturing method. [Figure 39] 5A to 5C are schematic cross-sectional views for explaining the manufacturing method. [Figure 40] 5A to 5C are schematic cross-sectional views for explaining the manufacturing method. [Figure 41] 5A to 5C are schematic cross-sectional views for explaining the manufacturing method. [Figure 42] 5A to 5C are schematic cross-sectional views for explaining the manufacturing method. [Figure 43] 5A to 5C are schematic cross-sectional views for explaining the manufacturing method. [Figure 44] FIG. 10 is a schematic cross-sectional view showing a configuration of a portion of a semiconductor memory device according to a third embodiment. [Figure 45] FIG. 10 is a schematic cross-sectional view showing a configuration of a portion of a semiconductor memory device according to a third embodiment. [Figure 46] FIG. 10 is a schematic cross-sectional view showing a configuration of a portion of a semiconductor memory device according to a third embodiment. [Figure 47] FIG. 10 is a schematic cross-sectional view showing a configuration of a portion of a semiconductor memory device according to a fourth embodiment. [Figure 48] FIG. 10 is a schematic cross-sectional view showing a configuration of a portion of a semiconductor memory device according to a fourth embodiment. [Figure 49] FIG. 10 is a schematic cross-sectional view showing a configuration of a portion of a semiconductor memory device according to a fourth embodiment. [Figure 50] 5A to 5C are schematic cross-sectional views for explaining a manufacturing method of the semiconductor memory device. [Figure 51] 5A to 5C are schematic cross-sectional views for explaining the manufacturing method. [Figure 52] 5A to 5C are schematic cross-sectional views for explaining the manufacturing method. [Figure 53] 5A to 5C are schematic cross-sectional views for explaining the manufacturing method. [Figure 54] 5A to 5C are schematic cross-sectional views for explaining the manufacturing method. [Figure 55] 5A to 5C are schematic cross-sectional views for explaining the manufacturing method. [Figure 56] 5A to 5C are schematic cross-sectional views for explaining the manufacturing method. [Figure 57] 5A to 5C are schematic cross-sectional views for explaining the manufacturing method. [Figure 58] 5A to 5C are schematic cross-sectional views for explaining the manufacturing method. [Figure 59] 5A to 5C are schematic cross-sectional views for explaining the manufacturing method. [Figure 60] 5A to 5C are schematic cross-sectional views for explaining the manufacturing method. [Figure 61] 5A to 5C are schematic cross-sectional views for explaining the manufacturing method. [Figure 62] 5A to 5C are schematic cross-sectional views for explaining the manufacturing method. [Figure 63] 5A to 5C are schematic cross-sectional views for explaining the manufacturing method. [Figure 64] FIG. 10 is a schematic cross-sectional view showing the configuration of a portion of a semiconductor memory device according to a fifth embodiment. [Figure 65] FIG. 10 is a schematic cross-sectional view showing the configuration of a portion of a semiconductor memory device according to a fifth embodiment. [Figure 66] FIG. 10 is a schematic cross-sectional view showing the configuration of a portion of a semiconductor memory device according to a fifth embodiment. [Figure 67] 5A to 5C are schematic cross-sectional views for explaining a manufacturing method of the semiconductor memory device. [Figure 68] 5A to 5C are schematic cross-sectional views for explaining the manufacturing method. [Figure 69] 5A to 5C are schematic cross-sectional views for explaining the manufacturing method. [Figure 70] 5A to 5C are schematic cross-sectional views for explaining the manufacturing method. [Figure 71] 5A to 5C are schematic cross-sectional views for explaining the manufacturing method. [Figure 72] 5A to 5C are schematic cross-sectional views for explaining the manufacturing method. [Figure 73] 5A to 5C are schematic cross-sectional views for explaining the manufacturing method. [Figure 74]5A to 5C are schematic cross-sectional views for explaining the manufacturing method. [Figure 75] 5A to 5C are schematic cross-sectional views for explaining the manufacturing method. [Figure 76] 5A to 5C are schematic cross-sectional views for explaining the manufacturing method. [Figure 77] 5A to 5C are schematic cross-sectional views for explaining the manufacturing method. [Figure 78] 5A to 5C are schematic cross-sectional views for explaining the manufacturing method. [Figure 79] 5A to 5C are schematic cross-sectional views for explaining the manufacturing method. [Figure 80] 5A to 5C are schematic cross-sectional views for explaining the manufacturing method. [Figure 81] 5A to 5C are schematic cross-sectional views for explaining the manufacturing method. [Figure 82] FIG. 10 is a schematic cross-sectional view showing the configuration of a portion of a semiconductor memory device according to a sixth embodiment. [Figure 83] FIG. 10 is a schematic cross-sectional view showing the configuration of a portion of a semiconductor memory device according to a sixth embodiment. [Figure 84] FIG. 10 is a schematic cross-sectional view showing the configuration of a portion of a semiconductor memory device according to a sixth embodiment. [Figure 85] 5A to 5C are schematic cross-sectional views for explaining a manufacturing method of the semiconductor memory device. [Figure 86] 5A to 5C are schematic cross-sectional views for explaining the manufacturing method. [Figure 87] 5A to 5C are schematic cross-sectional views for explaining the manufacturing method. [Figure 88] 5A to 5C are schematic cross-sectional views for explaining the manufacturing method. [Figure 89] 5A to 5C are schematic cross-sectional views for explaining the manufacturing method. [Figure 90] 5A to 5C are schematic cross-sectional views for explaining the manufacturing method. [Figure 91] 5A to 5C are schematic cross-sectional views for explaining the manufacturing method. [Figure 92]5A to 5C are schematic cross-sectional views for explaining the manufacturing method. [Figure 93] 5A to 5C are schematic cross-sectional views for explaining the manufacturing method. [Figure 94] 5A to 5C are schematic cross-sectional views for explaining the manufacturing method. [Figure 95] 5A to 5C are schematic cross-sectional views for explaining the manufacturing method. [Figure 96] 5A to 5C are schematic cross-sectional views for explaining the manufacturing method. [Figure 97] 13A to 13C are schematic cross-sectional views for explaining a method for manufacturing a semiconductor memory device according to a seventh embodiment. [Figure 98] 5A to 5C are schematic cross-sectional views for explaining the manufacturing method. [Figure 99] 5A to 5C are schematic cross-sectional views for explaining the manufacturing method. [Figure 100] FIG. 13 is a schematic cross-sectional view for explaining a semiconductor memory device according to a seventh embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0007] Next, semiconductor devices according to embodiments will be described in detail with reference to the drawings. Note that the following embodiments are merely examples and are not intended to limit the present invention. Furthermore, the following drawings are schematic, and for the sake of convenience, some configurations may be omitted. Furthermore, parts common to multiple embodiments are given the same reference numerals, and descriptions thereof may be omitted.

[0008] Furthermore, in this specification, when a first component is said to be "electrically connected" to a second component, the first component may be directly connected to the second component, or the first component may be connected to the second component via wiring, a semiconductor member, a transistor, etc. For example, when three transistors are connected in series, the first transistor is "electrically connected" to the third transistor even if the second transistor is in the OFF state.

[0009] In this specification, a predetermined direction parallel to the surface of the substrate is called the X direction, a direction parallel to the surface of the substrate and perpendicular to the X direction is called the Y direction, and a direction perpendicular to the surface of the substrate is called the Z direction.

[0010] Furthermore, in this specification, expressions such as "upper" and "lower" are based on the substrate. For example, the direction away from the substrate along the Z direction is referred to as "up," and the direction approaching the substrate along the Z direction is referred to as "lower." Furthermore, when referring to a certain configuration, the lower surface or lower end refers to the surface or end of the configuration facing the substrate, and when referring to the upper surface or upper end, refers to the surface or end of the configuration facing away from the substrate. Furthermore, surfaces that intersect with the X or Y direction are referred to as side surfaces, etc.

[0011] In this specification, the direction intersecting the surface of the substrate may be referred to as the stacking direction. The direction along a predetermined plane intersecting the stacking direction may be referred to as the first direction, and the direction intersecting the first direction along this plane may be referred to as the second direction. The stacking direction may or may not coincide with the Z direction. The first and second directions may or may not correspond to either the X and Y directions, or the X' and Y' directions described below.

[0012] [First embodiment] [Circuit configuration] 1 is a schematic circuit diagram showing the configuration of a semiconductor memory device according to the first embodiment. The semiconductor memory device according to this embodiment includes a plurality of memory blocks BLK, a plurality of bit lines BL connected in common to the plurality of memory blocks BLK, a plurality of source lines SL connected in common to the plurality of memory blocks BLK, and a peripheral circuit PC connected to the plurality of memory blocks BLK, the plurality of bit lines BL, and the plurality of source lines SL.

[0013] Each of the memory blocks BLK includes a plurality of word lines WL and a plurality of memory pillars MP. Each of the memory pillars MP includes a local bit line LBL, a local source line LSL, and a plurality of memory cells MC connected in parallel between the local bit line LBL and the local source line LSL. Each of the word lines WL is commonly connected to all of the memory pillars MP in the memory block BLK.

[0014] The memory cells MC are field-effect transistors, each having a drain electrode connected to a local bit line LBL, a source electrode connected to a local source line LSL, and a control gate electrode connected to a word line WL. Each memory cell MC also has a charge storage film disposed between its channel region and the control gate electrode. The threshold voltage of each memory cell MC varies depending on the amount of charge in the charge storage film. Each memory cell MC stores one or more bits of user data.

[0015] Each memory block BLK is provided with a plurality of local bit lines LBL corresponding to the plurality of bit lines BL and a plurality of local source lines LSL corresponding to the plurality of source lines SL. The plurality of bit lines BL are connected in common to the corresponding local bit lines LBL in all memory blocks BLK. The plurality of source lines SL are connected in common to the corresponding local source lines LSL in all memory blocks BLK.

[0016] The peripheral circuit PC includes, for example, a voltage generation circuit that generates voltages used in read operations, write operations, erase operations, etc., a decode circuit that supplies voltages generated according to address data to each wiring, a sense amplifier that measures the voltage or current of the bit line BL to read user data stored in the memory cell MC and switches the voltage of the bit line BL according to the user data to be stored in the memory cell MC, and a sequencer that controls these circuits according to input command data to perform read operations, write operations, erase operations, etc.

[0017] For example, during a read operation, the peripheral circuit PC selects one memory block BLK and then selects one word line WL. It also supplies a read voltage to the selected word line WL and a non-select voltage to the unselected word lines WL. The read voltage is a voltage of a magnitude that turns the memory cell MC ON or OFF depending on the data stored in the memory cell MC. The non-select voltage is a voltage of a magnitude that turns the memory cell MC OFF regardless of the data stored in the memory cell MC.

[0018] Furthermore, the peripheral circuit PC supplies a voltage difference between the bit line BL and the source line SL during a read operation, for example. Accordingly, some of the memory cells MC connected to the selected word line WL are turned on, and current flows through the corresponding bit lines BL. Meanwhile, other memory cells MC connected to the selected word line WL are not turned on, and no current flows through the corresponding bit lines BL.

[0019] In addition, the peripheral circuit PC functions as a NOR flash memory that supplies a predetermined voltage to multiple word lines WL, multiple bit lines BL, and multiple source lines SL in one memory block BLK selected during an erase operation, thereby erasing all the data recorded in all memory cells MC in the selected memory block BLK at once.

[0020] 2 is a schematic plan view showing the configuration of a semiconductor memory device according to this embodiment. The semiconductor memory device according to this embodiment includes a semiconductor substrate 100 and a plurality of finger structures FS provided on the semiconductor substrate 100. In the illustrated example, these plurality of finger structures FS are aligned in the Y direction and extend in the X direction. In this embodiment, these plurality of finger structures FS each function as a memory block BLK (FIG. 1).

[0021] [structure] FIG. 3 is a schematic XY cross-sectional view showing the configuration of a semiconductor memory device according to this embodiment. FIG. 4 is a schematic plan view showing the configuration of a semiconductor memory device according to this embodiment. FIG. 4 illustrates a plan view of a region corresponding to FIG. 3. FIG. 4 illustrates bit lines BL, source lines SL, and the like. FIGS. 5 and 6 are schematic perspective views showing the configuration of a semiconductor memory device according to this embodiment. FIGS. 7 and 8 are schematic XY cross-sectional views showing the configuration of a semiconductor memory device according to this embodiment. FIGS. 7 and 8 are schematic views for explanation, showing only one memory pillar MP. FIG. 7 illustrates a cross-section at a height position corresponding to a conductive layer 110, which will be described later. FIG. 8 illustrates a cross-section at a height position corresponding to an insulating layer 101, which will be described later. FIG. 9 is a schematic cross-sectional view showing the configuration of a semiconductor memory device according to this embodiment. FIG. 9 illustrates a cross-section of the structure shown in FIG. 3 taken along line AA′ and viewed in the direction of the arrow.

[0022] 3 to 9, in addition to the X, Y, and Z directions, the X' and Y' directions are also shown. The X' and Y' directions are directions within the XY plane. The X' direction is a direction obtained by rotating the X direction by approximately 30° around the Z direction as an axis. The Y' direction is a direction obtained by rotating the Y direction by approximately 30° around the Z direction as an axis. The X' and Y' directions are perpendicular to each other.

[0023] 5, the finger structure FS includes a plurality of conductive layers 110 and insulating layers 101 arranged alternately in the Z direction, and a plurality of memory pillars MP extending in the Z direction through the plurality of conductive layers 110 and insulating layers 101. In addition, an inter-finger insulating member IFS is provided between two finger structures FS adjacent to each other in the Y direction.

[0024] The conductive layer 110 has a generally plate-like shape extending in the X direction. The conductive layer 110 may include a laminated film of a barrier conductive film such as titanium nitride (TiN) and a metal film such as tungsten (W). The conductive layer 110 may also include polycrystalline silicon containing impurities such as phosphorus (P) or boron (B). The conductive layer 110 functions as the word line WL described with reference to FIG. 1 and the control gate electrode of the memory cell MC. The insulating layer 101 includes silicon oxide (SiO2) or the like.

[0025] The memory pillars MP are arranged in two rows in the X direction in each finger structure FS, as shown in Fig. 3 for example. Each memory pillar MP includes a pair of conductor posts 120 and a semiconductor layer 130 connected to the pair of conductor posts 120, as shown in Fig. 5 for example. Furthermore, each memory pillar MP includes a gate insulating film 140 (memory film) provided between the conductive layer 110 and the semiconductor layer 130, as shown in Fig. 6 for example.

[0026] For example, as shown in FIG. 3 , a pair of conductor pillars 120 are spaced apart in the X′ direction in each memory pillar MP. The semiconductor layer 130 is provided between the pair of conductor pillars 120 and is in contact with the pair of conductor pillars 120. In the XY cross section shown in FIG. 3 , the inner and outer peripheral surfaces of the semiconductor layer 130 are formed approximately along a circle. The pair of conductor pillars 120 are provided outside these circles. The pair of conductor pillars 120 are formed in a substantially rectangular shape with two sides extending in the X′ direction. The length of the conductor pillars 120 in the Y′ direction is smaller than the diameter of the semiconductor layer 130. The surface of one conductor pillar 120 facing the other conductor pillar 120 in the X′ direction is in contact with the semiconductor layer 130. Similarly, the surface of the other conductor pillar 120 facing the one conductor pillar 120 in the X′ direction is in contact with the semiconductor layer 130.

[0027] 3, the gate insulating film 140 is formed along the outer peripheral surfaces of the pair of conductor posts 120 and the semiconductor layer 130. That is, of the outer peripheral surface of the semiconductor layer 130, the portions other than the contact surface with the conductor posts 120 are in contact with the gate insulating film 140. Also, of the outer peripheral surface of the conductor post 120, the portions other than the contact surface with the semiconductor layer 130 (the surface opposite to the other conductor posts 120 in the X' direction and both surfaces in the Y' direction) are in contact with the gate insulating film 140. The conductive layer 110 surrounds the pair of conductor posts 120 and the semiconductor layer 130 via the gate insulating film 140.

[0028] Each of the pair of conductor columns 120 is continuous in the Z direction within the range of the Z direction in which the plurality of conductive layers 110 are provided. Therefore, as shown in FIGS. 7 to 9, each of the pair of conductor columns 120 is provided at a height position corresponding to both the conductive layers 110 and the insulating layers 101.

[0029] 1, one of the pair of conductor pillars 120 functions as the local bit line LBL, and the other functions as the local source line LSL. The conductor pillar 120 has at least a lower resistivity than the semiconductor layer 130. The conductor pillar 120 may include a semiconductor pillar such as polycrystalline silicon containing impurities such as phosphorus (P) or boron (B), or may include a metal pillar, or may include both. Note that when the conductor pillar 120 includes a semiconductor pillar such as polycrystalline silicon containing impurities such as phosphorus (P) or boron (B), the semiconductor layer 130 does not include the impurity, or the concentration of the impurity contained in the semiconductor layer 130 is lower than the concentration of the impurity in the conductor pillar 120.

[0030] The semiconductor layer 130 is continuous in the Z direction within the range in which the plurality of conductive layers 110 are provided, and faces the plurality of conductive layers 110 arranged in the Z direction. Therefore, as shown in Figures 7 to 9, the semiconductor layer 130 is provided at a height position corresponding to both the conductive layer 110 and the insulating layer 101.

[0031] The semiconductor layer 130 includes, for example, polycrystalline silicon (Si) or the like. The semiconductor layer 130 has a substantially cylindrical shape, and an insulating pillar 131 made of silicon oxide (SiO2) or the like is provided in the center. The semiconductor layer 130 functions as a channel region of a plurality of memory cells MC aligned in the Z direction.

[0032] The gate insulating film 140 is divided in the Z direction in correspondence with the plurality of conductive layers 110 arranged in the Z direction. That is, as shown in Figures 7 and 9, the gate insulating film 140 is provided at a height position corresponding to the conductive layers 110, but as shown in Figures 8 and 9, the gate insulating film 140 is not provided at a height position corresponding to the insulating layer 101.

[0033] 6, the gate insulating film 140 includes a tunnel insulating film 141, a charge storage film 142, and block insulating films 143 and 144 stacked between the semiconductor layer 130 and the conductive layer 110. The tunnel insulating film 141 and the block insulating film 143 include, for example, silicon oxide (SiO2) or the like. The charge storage film 142 includes, for example, a film capable of storing charge, such as silicon nitride (SiN), and can hold an amount of charge corresponding to the data recorded in the memory cell MC. The block insulating film 144 includes, for example, a metal oxide film with a high dielectric constant, such as alumina (Al2O3). In the illustrated example, the block insulating films 144 and 143, the charge storage film 142, and the tunnel insulating film 141 are provided in this order on the upper and lower surfaces of the conductive layer 110 and on the surfaces facing the semiconductor layer 130 and the conductor post 120.

[0034] 4, above the multiple finger structures FS aligned in the Y direction, multiple bit lines BL and multiple source lines SL are provided, extending in the Y direction and alternately aligned in the X direction. Each of the multiple memory pillars MP is arranged such that one conductor post 120 overlaps one of the bit lines BL when viewed from the Z direction, and the other conductor post 120 overlaps one of the source lines SL when viewed from the Z direction. The bit line BL is connected to one of the conductor posts 120 via a contact electrode 121. The source line SL is connected to the other conductor post 120 via a contact electrode 122.

[0035] [Manufacturing method] Next, a method for manufacturing the semiconductor memory device according to the first embodiment will be described with reference to FIGS. 10 to 29. FIGS. 10 to 29 are schematic cross-sectional views for explaining the manufacturing method. FIGS. 11, 14, 17, 20, 23, 26, and 28 show cross sections corresponding to FIG. 7. FIGS. 12, 15, 18, 21, and 24 show cross sections corresponding to FIG. 8. FIGS. 10, 13, 16, 19, 22, 25, 27, and 29 show cross sections corresponding to FIG. 9.

[0036] In manufacturing the semiconductor memory device according to this embodiment, a plurality of insulating layers 101 and a plurality of sacrificial layers 110A are alternately formed, for example, as shown in Fig. 10. This step is performed by a method such as CVD (Chemical Vapor Deposition).

[0037] Next, as shown in FIGS. 11 to 13, for example, openings 120A are formed at positions corresponding to the conductor posts 120, and openings 130A are formed at positions corresponding to the semiconductor layer 130. In the examples of FIGS. 11 and 12, the openings 130A are formed approximately along a circle. The pair of openings 120A are provided outside this circle and are continuous with the opening 130A. The pair of openings 120A are formed in a substantially rectangular shape, and the length of the opening 120A in the Y' direction is smaller than the diameter of the opening 130A. The openings 120A and 130A extend in the Z direction and penetrate the multiple insulating layers 101 and the multiple sacrificial layers 110A. This process is performed by a method such as RIE (Reactive Ion Etching).

[0038] 14 to 16, a conductor layer 120B is formed inside the openings 120A and 130A. The conductor layer 120B is formed to a thickness that fills the opening 120A but does not fill the opening 130A. This step is performed by a method such as CVD.

[0039] 17 to 19, the conductor post 120 is formed. For example, the portion of the conductor layer 120B formed in the opening 120A is left, and the portion formed in the opening 130A is removed. This step is performed by, for example, wet etching or the like.

[0040] 20 to 22, the semiconductor layer 130 and the insulating pillar 131 are formed inside the opening 130A. This step is performed by a method such as CVD.

[0041] 23 to 25, grooves IFSA are formed in positions corresponding to the inter-finger insulating members IFS. The grooves IFSA extend in the Z and X directions, and separate the insulating layers 101 and the sacrificial layers 110A in the Y direction. This step is performed by a method such as RIE.

[0042] Next, the sacrificial layer 110A is removed through the grooves IFSA shown in Figures 26 and 27, for example, to form multiple voids 110B. This forms a hollow structure including multiple insulating layers 101 aligned in the Z direction and the conductor pillars 120, semiconductor layers 130, and insulating pillars 131 that support them. This process is performed by, for example, wet etching or another method.

[0043] 28 and 29, the gate insulating film 140 and the conductive layer 110 are formed in the gap 110B. This step is performed by, for example, a method such as CVD.

[0044] Thereafter, the inter-finger insulating members IFS, the bit lines BL, the source lines SL, etc. are formed, thereby completing the semiconductor memory device according to the first embodiment.

[0045] [effect] In the semiconductor memory device according to the first embodiment and each of the embodiments described below, the number of conductive layers 110 stacked in the Z direction can be increased by increasing the number of sacrificial layers 110A and insulating layers 101 in the process described with reference to Fig. 10. With such a configuration, a highly integrated NOR flash memory can be manufactured relatively easily.

[0046] As explained with reference to FIG. 1, the NOR flash memory includes a local bit line LBL, a local source line LSL, a plurality of memory cells MC connected in parallel between them, and a plurality of word lines WL connected to the gate electrodes of these memory cells MC.

[0047] To realize such a structure, it is conceivable to form holes, etc., as appropriate, corresponding to the local bit lines LBL, the local source lines LSL, the channel regions of the memory cells MC, etc. However, such a method requires precise positioning of these multiple holes, which increases the difficulty of manufacturing.

[0048] Therefore, for example, as explained with reference to Figures 11 to 13, the circular opening 130A and the substantially rectangular opening 120A are formed at the same time. Furthermore, the conductor post 120 is formed inside the opening 120A in the process explained with reference to Figures 14 to 19, and the semiconductor layer 130 is formed inside the opening 130A in the process explained with reference to Figures 20 to 22. According to such a method, it is not necessary to adjust the positional relationship between the local bit line LBL, the local source line LSL, and the channel regions of the memory cells MC, and it is possible to easily realize a semiconductor memory device.

[0049] [Second embodiment] [structure] Next, a semiconductor memory device according to a second embodiment will be described with reference to Figures 30 to 32. Figures 30 to 32 are schematic cross-sectional views showing the configuration of a portion of the semiconductor memory device according to the second embodiment, and show the configuration at positions corresponding to Figures 7 to 9, respectively. In the following description, parts that are the same as those in the semiconductor memory device according to the first embodiment are given the same reference numerals, and description thereof will be omitted.

[0050] The semiconductor memory device according to the second embodiment is basically configured in the same manner as the semiconductor memory device according to the first embodiment, except that the semiconductor memory device according to the second embodiment includes a semiconductor layer 230 instead of the semiconductor layer 130.

[0051] The semiconductor layer 230 is divided in the Z direction corresponding to the plurality of conductive layers 110 lined up in the Z direction. That is, as shown in Figures 30 and 32, the semiconductor layer 230 is provided at a height position corresponding to the conductive layer 110, but as shown in Figures 31 and 32, the semiconductor layer 230 is not provided at a height position corresponding to the insulating layer 101. Hereinafter, the portion of the semiconductor layer 230 divided in the Z direction will be referred to as a semiconductor portion 231.

[0052] Each of the semiconductor portions 231 faces a corresponding one of the conductive layers 110. The semiconductor portions 231 include, for example, polycrystalline silicon (Si). The multiple semiconductor portions 231 aligned in the Z direction are each separated in the Y' direction by a pair of conductor pillars 120, with an insulating pillar 131 provided between them. Each of the semiconductor portions 231 functions as a channel region of a memory cell MC.

[0053] For example, as shown in FIG. 30 , the insulating rod 131 is provided between a pair of conductive rods 120 and is in contact with the pair of conductive rods 120. In the XY cross section shown in FIG. 30 , the outer circumferential surface of the insulating rod 131 is formed approximately along a circle. The pair of conductive rods 120 are provided outside this circle. The length of the conductive rod 120 in the Y′ direction is smaller than the diameter of the circle along the outer circumferential surface of the insulating rod 131. The surface of one of the conductive rods 120 facing the other conductive rod 120 in the X′ direction is in contact with the insulating rod 131. Similarly, the surface of the other conductive rod 120 facing the one of the conductive rods 120 in the X′ direction is in contact with the insulating rod 131.

[0054] The semiconductor part 231 is formed along the outer peripheral surface of the insulating column 131, and is divided in the Y' direction by the pair of conductive columns 120, as described above. The outer peripheral surface of the semiconductor part 231 is formed roughly along a circle. The pair of conductive columns 120 are mainly provided outside this circle, but each also has a portion provided inside this circle. Of both surfaces in the Y' direction of the pair of conductive columns 120, contact portions with the semiconductor part 231 are provided near the contact surfaces with the insulating columns 131.

[0055] 30 , the gate insulating film 140 is formed along the outer peripheral surfaces of the pair of conductor posts 120 and the semiconductor part 231. That is, the outer peripheral surface of the semiconductor part 231 is in contact with the gate insulating film 140. Of the outer peripheral surfaces of the conductor post 120, parts other than the contact surface with the insulating post 131 and the contact surface with the semiconductor part 231 (the surface opposite to the other conductor post 120 in the X′ direction, and both surfaces in the Y′ direction other than the contact portion with the semiconductor part 231) are in contact with the gate insulating film 140. The conductive layer 110 surrounds the pair of conductor posts 120 and the semiconductor part 231 via the gate insulating film 140.

[0056] [Manufacturing method] Next, a method for manufacturing a semiconductor memory device according to the second embodiment will be described with reference to Figures 33 to 43. Figures 33 to 43 are schematic cross-sectional views for explaining the manufacturing method. Figures 33, 35, 38, and 41 show cross sections corresponding to Figure 30. Figures 36, 39, and 42 show cross sections corresponding to Figure 31. Figures 34, 37, 40, and 43 show cross sections corresponding to Figure 32.

[0057] In manufacturing the semiconductor memory device according to the second embodiment, for example, the steps described with reference to FIGS. 17 to 19 in the method for manufacturing the semiconductor memory device according to the first embodiment are carried out.

[0058] 33 and 34, a portion of the sacrificial layer 110A is removed inside the opening 130A to form a recess 230A. In this step, the conductor post 120 is not removed. Therefore, each of the multiple recesses 230A formed at each height position has two portions separated in the Y' direction by the conductor post 120. This step is performed by, for example, wet etching or the like.

[0059] 35 to 37, a semiconductor layer 230B is formed inside the opening 130A and the recess 230A. The semiconductor layer 230B is formed to a thickness that fills the recess 230A but does not fill the opening 130A. This step is performed by a method such as CVD, for example.

[0060] Next, as shown in FIGS. 38 to 40, the semiconductor layer 230 is formed. For example, of the semiconductor layer 230B, the portions formed in the recesses 230A are left, and the portions formed in the openings 130A are removed. This divides the semiconductor layer 230B into a plurality of semiconductor portions 231. This step is performed by, for example, wet etching or the like.

[0061] Next, as shown in Figures 41 to 43, for example, insulating pillars 131 are formed inside the openings 130A. This step is performed by a method such as CVD.

[0062] Thereafter, the steps described with reference to FIGS. 23 to 25 and subsequent steps are carried out to form the semiconductor memory device according to the second embodiment.

[0063] [effect] The semiconductor layer 130 according to the first embodiment is continuous in the Z direction within the range in which the plurality of conductive layers 110 are provided, and faces the plurality of conductive layers 110 arranged in the Z direction. In such a configuration, when a memory cell MC is accessed, there is a risk that disturbance may occur in another memory cell MC adjacent to the memory cell MC in the Z direction.

[0064] On the other hand, the semiconductor layer 230 according to the second embodiment is divided in the Z direction in accordance with the plurality of conductive layers 110 aligned in the Z direction. With this configuration, it is possible to suitably suppress the occurrence of the disturbance described above.

[0065] [Third embodiment] [structure] Next, a semiconductor memory device according to a third embodiment will be described with reference to Figures 44 to 46. Figures 44 to 46 are schematic cross-sectional views showing the configuration of a portion of the semiconductor memory device according to the third embodiment, and show the configuration at positions corresponding to Figures 7 to 9, respectively. In the following description, parts that are the same as those in the semiconductor memory device according to the first embodiment are given the same reference numerals, and description thereof will be omitted.

[0066] The semiconductor memory device according to the third embodiment is basically configured in the same manner as the semiconductor memory device according to the first embodiment, except that the semiconductor memory device according to the third embodiment includes a gate insulating film 340 instead of the gate insulating film 140.

[0067] The gate insulating film 340 is continuous in the Z direction within the range in which the plurality of conductive layers 110 are provided, and faces the plurality of conductive layers 110 arranged in the Z direction. Therefore, as shown in FIGS. 44 to 46, the gate insulating film 340 is provided at a height position corresponding to each of the conductive layers 110 and the insulating layer 101.

[0068] The gate insulating film 340 includes a tunnel insulating film 341, a charge storage film 342, and block insulating films 343 and 144 stacked between the semiconductor layer 130 and the conductive layer 110. The tunnel insulating film 341, the charge storage film 342, and the block insulating film 343 are basically configured in the same manner as the tunnel insulating film 141, the charge storage film 142, and the block insulating film 143. However, the tunnel insulating film 341, the charge storage film 342, and the block insulating film 343 are continuous in the Z direction within a range in the Z direction in which the multiple conductive layers 110 are provided. Therefore, the tunnel insulating film 341, the charge storage film 342, and the block insulating film 343 are provided at height positions corresponding to both the conductive layer 110 and the insulating layer 101, respectively.

[0069] [Manufacturing method] The semiconductor memory device according to the third embodiment is basically manufactured in the same manner as the semiconductor memory device according to the first embodiment.

[0070] However, when manufacturing the semiconductor memory device according to the third embodiment, after performing the steps described with reference to Figures 11 to 13 and before performing the steps described with reference to Figures 14 to 16, a block insulating film 343, a charge storage film 342, and a tunnel insulating film 341 are formed inside the openings 120A and 130A.

[0071] In addition, when manufacturing the semiconductor memory device according to the third embodiment, the tunnel insulating film 141, the charge storage film 142, and the block insulating film 143 are not formed in the steps described with reference to FIGS.

[0072] [Fourth embodiment] [structure] Next, a semiconductor memory device according to a fourth embodiment will be described with reference to Figures 47 to 49. Figures 47 to 49 are schematic cross-sectional views showing the configuration of a portion of the semiconductor memory device according to the fourth embodiment, and show the configuration at positions corresponding to Figures 44 to 46, respectively. In the following description, parts that are the same as those in the semiconductor memory device according to the third embodiment are given the same reference numerals, and description thereof will be omitted.

[0073] The semiconductor memory device according to the fourth embodiment is basically configured in the same manner as the semiconductor memory device according to the third embodiment, except that the semiconductor memory device according to the fourth embodiment includes a semiconductor layer 430 and a gate insulating film 440 instead of the semiconductor layer 130 and the gate insulating film 340.

[0074] The semiconductor layer 430 is divided in the Z direction corresponding to the plurality of conductive layers 110 lined up in the Z direction. That is, as shown in Figures 47 and 49, the semiconductor layer 430 is provided at a height position corresponding to the conductive layer 110, but as shown in Figures 48 and 49, the semiconductor layer 430 is not provided at a height position corresponding to the insulating layer 101. Hereinafter, the portion of the semiconductor layer 430 divided in the Z direction will be referred to as a semiconductor portion 431.

[0075] Each of the semiconductor portions 431 faces a corresponding one of the conductive layers 110. The semiconductor portions 431 include, for example, polycrystalline silicon (Si), etc. Each of the semiconductor portions 431 functions as a channel region of the memory cell MC.

[0076] The gate insulating film 440 includes a tunnel insulating film 441, a charge storage film 442, and block insulating films 443 and 144 stacked between the semiconductor layer 430 and the conductive layer 110. The tunnel insulating film 441, the charge storage film 442, and the block insulating film 443 are basically configured in the same manner as the tunnel insulating film 341, the charge storage film 342, and the block insulating film 343. However, the tunnel insulating film 441, the charge storage film 442, and the block insulating film 443 each include a plurality of protrusions that are aligned in the Z direction corresponding to the plurality of semiconductor portions 431 aligned in the Z direction and that protrude toward the conductive layer 110. That is, the tunnel insulating film 441, the charge storage film 442, and the block insulating film 443 are each formed along the unevenness that includes the plurality of semiconductor portions 431 aligned in the Z direction and the outer peripheral surfaces of the conductor pillars 120 or the outer peripheral surfaces of the insulating pillars 131.

[0077] For example, in the example of FIG. 47 , an insulating rod 131 is provided between a pair of conductive rods 120 and is in contact with the pair of conductive rods 120. In the XY cross section shown in FIG. 47 , the outer circumferential surface of the insulating rod 131 is formed approximately along a circle. The pair of conductive rods 120 are provided outside this circle. The length of the conductive rod 120 in the Y′ direction is smaller than the diameter of the circle along the outer circumferential surface of the insulating rod 131. The surface of one of the conductive rods 120 facing the other conductive rod 120 in the X′ direction is in contact with the insulating rod 131. Similarly, the surface of the other conductive rod 120 facing the one conductive rod 120 in the X′ direction is in contact with the insulating rod 131.

[0078] The semiconductor part 431 is formed along the outer peripheral surfaces of the pair of conductor columns 120 and the insulating columns 131 in the XY cross section shown in FIG. 47 . That is, the outer peripheral surface of the insulating column 131 other than the contact surface with the pair of conductor columns 120 is in contact with the semiconductor part 431. Furthermore, the outer peripheral surface of the conductor column 120 other than the contact surface with the insulating column 131 (the surface opposite to the other conductor columns 120 in the X′ direction and both surfaces in the Y′ direction) is in contact with the semiconductor part 431. The outer peripheral surface of the portion of the semiconductor part 431 provided on the outer peripheral surface of the insulating column 131 is formed approximately along a circle. The pair of conductor columns 120 are mainly provided outside this circle, but each also has a portion provided inside this circle. Furthermore, the gate insulating film 440 is formed along the outer peripheral surface of the semiconductor part 431. The conductive layer 110 surrounds the semiconductor part 431 via the gate insulating film 440.

[0079] [Manufacturing method] Next, a method for manufacturing a semiconductor memory device according to the fourth embodiment will be described with reference to Figures 50 to 63. Figures 50 to 63 are schematic cross-sectional views for explaining the manufacturing method. Figures 50, 52, 55, 58, and 61 show cross sections corresponding to Figure 47. Figures 53, 56, 59, and 62 show cross sections corresponding to Figure 48. Figures 51, 54, 57, 60, and 63 show cross sections corresponding to Figure 49.

[0080] In manufacturing the semiconductor memory device according to the fourth embodiment, for example, the steps described with reference to FIGS. 11 to 13 in the method for manufacturing the semiconductor memory device according to the first embodiment are carried out.

[0081] 50 and 51, a portion of the sacrificial layer 110A is removed inside the openings 120A and 130A to form a recess 430A. This step is performed by, for example, wet etching or the like.

[0082] Next, as shown in FIGS. 52 to 54, a block insulating film 443, a charge storage film 442, a tunnel insulating film 441, and a semiconductor layer 430B are formed inside the openings 120A and 130A and the recesses 430A. The block insulating film 443, the charge storage film 442, and the tunnel insulating film 441 have irregularities that correspond to the multiple recesses 430A aligned in the Z direction. The contact surface of the semiconductor layer 430B with the tunnel insulating film 441 is formed along the irregularities formed on the tunnel insulating film 441. On the other hand, the surface of the semiconductor layer 430B exposed to the openings 120A and 130A does not have such irregularities. The semiconductor layer 430B is formed to a thickness that does not fill the openings 120A and 130A. This process is performed by, for example, a method such as CVD.

[0083] Next, as shown in FIGS. 55 to 57, for example, the semiconductor layer 430 is formed. For example, of the semiconductor layer 430B, the portions formed in the recesses of the tunnel insulating film 441 are left, and the other portions are removed. This divides the semiconductor layer 430B into a plurality of semiconductor portions 431. This step is performed by, for example, a method such as wet etching.

[0084] Next, as shown in Figures 58 to 60, for example, a conductor layer 120B is formed inside the openings 120A and 130A. The conductor layer 120B is formed to a thickness that fills the opening 120A but does not fill the opening 130A. This step is performed by a method such as CVD.

[0085] Next, the conductor post 120 is formed as shown in Fig. 61 to Fig. 63. For example, of the conductor layer 120B, the portion formed in the opening 120A is left, and the portion formed in the opening 130A is removed. This step is performed by, for example, wet etching or the like.

[0086] Next, insulating pillars 131 are formed inside the openings 130A. This step is performed by a method such as CVD.

[0087] 23 to 25 and subsequent steps in the method for manufacturing the semiconductor memory device according to the first embodiment are then performed. However, in the steps described with reference to FIGS. 28 and 29, the tunnel insulating film 141, the charge storage film 142, and the block insulating film 143 are not formed. In this way, the semiconductor memory device according to the fourth embodiment is formed.

[0088] [effect] Similar to the semiconductor layer 230 according to the second embodiment, the semiconductor layer 430 according to the fourth embodiment is divided in the Z direction in correspondence with the plurality of conductive layers 110 aligned in the Z direction. With this configuration, it is possible to suitably suppress the occurrence of the disturbance described above.

[0089] [Fifth embodiment] [structure] Next, a semiconductor memory device according to a fifth embodiment will be described with reference to Figures 64 to 66. Figures 64 to 66 are schematic cross-sectional views showing the configuration of a portion of the semiconductor memory device according to the fifth embodiment, and show the configuration at positions corresponding to Figures 44 to 46, respectively. In the following description, parts that are the same as those in the semiconductor memory device according to the third embodiment are given the same reference numerals, and description thereof will be omitted.

[0090] The semiconductor memory device according to the fifth embodiment is basically configured in the same manner as the semiconductor memory device according to the third embodiment, except that the semiconductor memory device according to the fifth embodiment includes a gate insulating film 540 instead of the gate insulating film 340.

[0091] The gate insulating film 540 includes a tunnel insulating film 341 , a charge storage film 542 , and block insulating films 543 and 144 stacked between the semiconductor layer 130 and the conductive layer 110 .

[0092] The charge storage film 542 is divided in the Z direction corresponding to the plurality of conductive layers 110 lined up in the Z direction. That is, as shown in FIGS. 64 and 66, the charge storage film 542 is provided at a height position corresponding to the conductive layers 110, but as shown in FIGS. 65 and 66, the charge storage film 542 is not provided at a height position corresponding to the insulating layer 101. Hereinafter, the portion of the charge storage film 542 divided in the Z direction will be referred to as a charge storage portion 544.

[0093] Each charge storage portion 544 faces a corresponding conductive layer 110. The charge storage portion 544 includes, for example, polycrystalline silicon containing impurities such as phosphorus (P) or boron (B). Each charge storage portion 544 is a conductive floating gate and can hold an amount of charge corresponding to the data to be recorded in the memory cell MC.

[0094] The block insulating film 543 is basically configured in the same manner as the block insulating film 343. However, the block insulating film 543 includes a plurality of protrusions that are aligned in the Z direction in correspondence with the plurality of charge accumulation units 544 aligned in the Z direction and that protrude toward the conductive layer 110. That is, the block insulating film 543 is formed along the unevenness that includes the plurality of charge accumulation units 544 aligned in the Z direction and the outer peripheral surface of the tunnel insulating film 341.

[0095] The XY cross section shown in Fig. 64 is almost the same as the XY cross section described with reference to Fig. 7. However, in Fig. 64, a gate insulating film 540 is shown instead of the gate insulating film 140.

[0096] [Manufacturing method] Next, a method for manufacturing the semiconductor memory device according to the fifth embodiment will be described with reference to Figures 67 to 81. Figures 67 to 81 are schematic cross-sectional views for explaining the manufacturing method. Figures 67, 70, 73, 76, and 79 show cross sections corresponding to Figure 64. Figures 68, 71, 74, 77, and 80 show cross sections corresponding to Figure 65. Figures 69, 72, 75, 78, and 81 show cross sections corresponding to Figure 66.

[0097] In manufacturing the semiconductor memory device according to the fifth embodiment, for example, the steps up to the step described with reference to FIGS. 50 and 51 in the method for manufacturing the semiconductor memory device according to the fourth embodiment are carried out.

[0098] 67 to 69, a block insulating film 543 and a semiconductor layer 542A are formed inside the openings 120A, 130A and the recess 430A. The semiconductor layer 542A is formed to a thickness that fills the recess 430A but does not fill the openings 120A, 130A. This step is performed by a method such as CVD, for example.

[0099] Next, as shown in FIGS. 70 to 72, for example, a charge storage film 542 is formed. For example, of the semiconductor layer 542A, the portion formed in the recess 430A is left, and the portions formed in the openings 120A and 130A are removed. This divides the semiconductor layer 542A into a plurality of charge storage portions 544. This step is performed by, for example, wet etching or the like.

[0100] 73 to 75, a tunnel insulating film 341 and a conductor layer 120B are formed inside the openings 120A and 130A. The conductor layer 120B is formed to a thickness that fills the opening 120A but does not fill the opening 130A. This step is performed by a method such as CVD.

[0101] Next, the conductor post 120 is formed as shown in Figures 76 to 78. For example, of the conductor layer 120B, the portion formed in the opening 120A is left, and the portion formed in the opening 130A is removed. This step is performed by, for example, wet etching or the like.

[0102] Next, the semiconductor layer 130 and the insulating pillar 131 are formed inside the opening 130A. This process is performed by a method such as CVD.

[0103] 23 to 25 and subsequent steps in the method for manufacturing the semiconductor memory device according to the first embodiment are then performed. However, in the steps described with reference to FIGS. 28 and 29, the tunnel insulating film 141, the charge storage film 142, and the block insulating film 143 are not formed. In this way, the semiconductor memory device according to the fifth embodiment is formed.

[0104] [effect] The charge storage film 142 according to the first embodiment and the charge storage film 342 according to the third embodiment are continuous in the Z direction within a range in the Z direction in which the plurality of conductive layers 110 are provided. On the other hand, the charge storage film 542 according to the fifth embodiment is divided in the Z direction in correspondence with the plurality of conductive layers 110 arranged in the Z direction. With this configuration, a conductive floating gate can be used as the charge storage portion 544 of the memory cell MC.

[0105] [Sixth embodiment] [structure] Next, a semiconductor memory device according to a sixth embodiment will be described with reference to Figures 82 to 84. Figures 82 to 84 are schematic cross-sectional views showing the configuration of a portion of the semiconductor memory device according to the sixth embodiment, and show the configuration at positions corresponding to Figures 64 to 66, respectively. In the following description, parts that are the same as those in the semiconductor memory device according to the fifth embodiment are given the same reference numerals, and description thereof will be omitted.

[0106] The semiconductor memory device according to the sixth embodiment is basically configured in the same manner as the semiconductor memory device according to the fifth embodiment, except that the semiconductor memory device according to the sixth embodiment includes a semiconductor layer 430 and a gate insulating film 640 instead of the semiconductor layer 130 and the gate insulating film 540.

[0107] The gate insulating film 640 is basically configured in the same manner as the gate insulating film 540. However, the gate insulating film 640 includes a tunnel insulating film 441 and a block insulating film 643 instead of the tunnel insulating film 341 and the block insulating film 543.

[0108] The block insulating film 643 is basically configured in the same manner as the block insulating film 543. However, the block insulating film 643 is formed along the unevenness including the plurality of charge accumulation units 544 aligned in the Z direction and the outer peripheral surface of the tunnel insulating film 441.

[0109] The XY cross section shown in Fig. 82 is almost the same as the XY cross section described with reference to Fig. 47. However, in Fig. 82, a gate insulating film 640 is shown instead of the gate insulating film 440.

[0110] [Manufacturing method] Next, a method for manufacturing the semiconductor memory device according to the sixth embodiment will be described with reference to FIGS. 85 to 96. FIGS. 85 to 96 are schematic cross-sectional views for explaining the manufacturing method. FIGS. 85, 88, 91, and 94 show cross sections corresponding to FIG. 82. FIGS. 86, 89, 92, and 95 show cross sections corresponding to FIG. 83. FIGS. 87, 90, 93, and 96 show cross sections corresponding to FIG. 84.

[0111] In manufacturing the semiconductor memory device according to the sixth embodiment, for example, the steps up to the step described with reference to FIGS. 50 and 51 in the method for manufacturing the semiconductor memory device according to the fourth embodiment are carried out.

[0112] 85 to 87, a block insulating film 643 and a semiconductor layer 542A are formed inside the openings 120A, 130A and the recess 430A. The semiconductor layer 542A is formed to a thickness that fills the recess 430A but does not fill the openings 120A, 130A. This step is performed by a method such as CVD, for example.

[0113] Next, as shown in FIGS. 88 to 90, a portion of the semiconductor layer 542A is removed inside the opening 130A to form the charge storage film 542 and also form the recess 431A. The recess 431A is formed by removing a portion of the semiconductor layer 542A that is formed in the recess 430A (FIGS. 50 and 51) and leaving another portion of the portion that is formed in the recess 430A. The recess 431A is formed by the upper surface of the portion of the block insulating film 643 that is formed on the upper surface of the insulating layer 101, the lower surface of the portion that is formed on the lower surface of the insulating layer 101, and the exposed surfaces of the charge storage unit 544 in the openings 120A and 130A. This step is performed by, for example, wet etching or the like.

[0114] Next, as shown in FIGS. 91 to 93, a tunnel insulating film 441 and a semiconductor layer 430B are formed inside the openings 120A, 130A and the recesses 431A. The tunnel insulating film 441 has irregularities that correspond to the multiple recesses 431A aligned in the Z direction. The contact surface of the semiconductor layer 430B with the tunnel insulating film 441 is formed along the irregularities formed on the tunnel insulating film 441. On the other hand, the surfaces of the semiconductor layer 430B exposed to the openings 120A, 130A do not have such irregularities. The semiconductor layer 430B is formed to a thickness that does not fill the openings 120A, 130A. This process is performed by a method such as CVD, for example.

[0115] Next, as shown in FIGS. 94 to 96, for example, the semiconductor layer 430 is formed. For example, of the semiconductor layer 430B, the portion formed in the recess of the tunnel insulating film 441 that is aligned with the recess 431A is left, and the other portion is removed. This divides the semiconductor layer 430B into a plurality of semiconductor portions 431. This step is performed by, for example, a method such as wet etching.

[0116] Thereafter, for example, the steps from the step described with reference to Figures 58 to 60 onwards in the method for manufacturing the semiconductor memory device according to the fourth embodiment are carried out, thereby forming the semiconductor memory device according to the sixth embodiment.

[0117] [effect] Similar to the semiconductor layer 430 according to the fourth embodiment, the semiconductor layer 430 according to the sixth embodiment is divided in the Z direction in accordance with the plurality of conductive layers 110 arranged in the Z direction. With this configuration, it is possible to suitably suppress the occurrence of the disturbance described above.

[0118] [Modifications of the First to Sixth Embodiments] The configurations of the semiconductor memory devices according to the first to sixth embodiments have been described above. However, the configurations shown above are merely examples, and the specific configurations can be adjusted as appropriate.

[0119] For example, in the first to sixth embodiments, the inner and outer peripheral surfaces of the semiconductor layer 130, etc., are formed substantially along a circle in the XY cross section, or include a portion formed substantially along a circle. However, the inner and outer peripheral surfaces of the semiconductor layer 130, etc., may be formed substantially along an elliptical or oval shape instead of a circle, or may include a portion formed substantially along an elliptical or oval shape.

[0120] Furthermore, for example, the gate insulating film (memory film) according to the first to sixth embodiments may include a ferroelectric film or the like instead of the charge storage film 142 or the like.

[0121] The ferroelectric film described in this specification may contain, for example, orthorhombic hafnium oxide. The hafnium oxide contained in the ferroelectric film may be mainly orthorhombic. More specifically, the hafnium oxide contained in the ferroelectric film may be mainly orthorhombic III (space group Pbc21, space group number 29). The proportion of orthorhombic crystals among the hafnium oxide crystals contained in the ferroelectric film may be the largest. The orthorhombic crystal is also called an orthorhombic crystal.

[0122] Furthermore, the ferroelectric film described in this specification may contain at least one additive element selected from the group consisting of silicon (Si), zirconium (Zr), aluminum (Al), yttrium (Y), strontium (Sr), lanthanum (La), samarium (Sm), gadolinium (Gd), terbium (Tb), dysprosium (Dy), holmium (Ho), erbium (Er), ytterbium (Yb), lutetium (Lu), and barium (Ba).

[0123] From the viewpoint of imparting ferroelectricity to hafnium oxide, the concentration of the additive element is preferably 0.1 atomic % or more and 60 atomic % or less. The appropriate range of the concentration of the additive element for imparting ferroelectricity to hafnium oxide varies depending on the type of additive element. For example, when the additive element is silicon (Si), the appropriate range of the concentration of the additive element for imparting ferroelectricity is 3 atomic % or more and 7 atomic % or less. For example, when the additive element is barium (Ba), the appropriate range of the concentration of the additive element for imparting ferroelectricity is 0.1 atomic % or more and 3 atomic % or less. For example, when the additive element is zirconium (Zr), the appropriate range of the concentration of the additive element for imparting ferroelectricity is 10 atomic % or more and 60 atomic % or less.

[0124] Furthermore, for example, in the semiconductor memory device according to the first embodiment, as explained with reference to FIG. 7 etc., the semiconductor layer 130 is provided between a pair of conductor posts 120. Furthermore, the surface of one conductor post 120 facing the other conductor post 120 in the X' direction and the surface of the other conductor post 120 facing the one conductor post 120 in the X' direction are in contact with the semiconductor layer 130. Such a structure is realized by forming the semiconductor layer 130 after forming the conductor posts 120, as explained with reference to FIGS. 14 to 22, for example. The same applies to the semiconductor memory device according to the third embodiment (FIG. 44) and the semiconductor memory device according to the fifth embodiment (FIG. 64).

[0125] On the other hand, in the semiconductor memory device according to the second embodiment, as described with reference to Fig. 30, the semiconductor section 231 is formed along the outer circumferential surface of the insulating pillar 131 and is divided in the Y' direction via a pair of conductive pillars 120. This type of structure is realized, for example, as described with reference to Figs. 33 to 40, by removing a part of the sacrificial layer 110A after forming the conductive pillars 120, and by forming the semiconductor layer 230B and then removing a part of the semiconductor layer 230B to divide the semiconductor layer 230B in the Z direction.

[0126] Furthermore, in the semiconductor memory device according to the fourth embodiment, as explained with reference to Fig. 47, the semiconductor section 431 is formed along the outer peripheral surfaces of a pair of conductor posts 120 and insulating posts 131. Such a structure is realized, for example, by forming the conductor posts 120 after forming the semiconductor section 431, as explained with reference to Figs. 52 to 63. The same applies to the semiconductor memory device according to the sixth embodiment (Fig. 82).

[0127] Here, for example, in the first, second, third, and fifth embodiments, the conductor pillar 120 may be formed after the semiconductor layer 130 and the like are formed. When such a method is adopted in the first to third embodiments, the memory pillar MP will have an XY cross section as described with reference to FIG. 47 at a height position corresponding to the conductive layer 110. Furthermore, when such a method is adopted in the fifth embodiment, the memory pillar MP will have an XY cross section as described with reference to FIG. 82 at a height position corresponding to the conductive layer 110.

[0128] [Seventh embodiment] In the first to sixth embodiments and their modified examples, the openings 120A and 130A are formed in the process described with reference to Figures 11 to 13. This process assumes that, for example, patterning is performed using a mask having a pattern for the openings 120A and 130A, and the openings 120A and 130A are simultaneously formed by RIE or the like.

[0129] However, depending on the RIE conditions, if the openings 120A and 130A are formed simultaneously, the corners at the boundary between the openings 120A and 130A may be rounded, and the openings 120A and 130A may not be formed properly.

[0130] Therefore, in this embodiment, the openings 120A and 130A are formed separately, which allows the openings 120A and 130A to be formed in a suitable manner.

[0131] 97 to 99 are schematic cross-sectional views illustrating a method for manufacturing a semiconductor memory device according to the seventh embodiment, each showing a cross section corresponding to FIG.

[0132] In the method for manufacturing the semiconductor memory device according to the seventh embodiment, the steps up to the step described with reference to FIG. 10 in the method for manufacturing the semiconductor memory device according to the first embodiment are carried out.

[0133] Next, for example, as shown in Fig. 97, opening 720A is formed. Opening 720A is formed in a substantially rectangular shape extending in the X' direction when viewed from the Z direction. One end and the other end of opening 720A in the X' direction each constitute opening 120A. This process is performed by, for example, RIE or the like.

[0134] 98, a sacrificial layer 720B made of silicon (Si), silicon oxide (SiO2) doped with impurities such as phosphorus (P) or boron (B), silicon nitride (Si3N4), or the like is formed inside the opening 720A. This process is performed by a method such as CVD.

[0135] Next, an opening 130A is formed as shown in Fig. 99. This step is performed by, for example, RIE or the like.

[0136] Next, the sacrificial layer 720B is removed through the opening 130A, thereby forming the structure shown in FIGS.

[0137] Thereafter, the steps in the method for manufacturing the semiconductor memory device according to the first embodiment that follow the steps described with reference to Figures 14 to 16 are carried out, thereby forming the semiconductor memory device according to the first embodiment.

[0138] 97 to 99, opening 720A is formed, sacrificial layer 720B is formed inside opening 720A, and then opening 130A is formed. However, for example, opening 130A may be formed, a sacrificial layer may be formed inside opening 130A, and then opening 720A may be formed.

[0139] The manufacturing method according to the seventh embodiment is applicable to any of the first to sixth embodiments and their modified examples.

[0140] 100 is a schematic cross-sectional view for explaining the semiconductor memory device according to the seventh embodiment, which shows a cross section corresponding to FIG.

[0141] When the manufacturing method according to the seventh embodiment is employed, the center of the circle inscribed in the opening 130A may not coincide with the center positions in the X' direction and the Y' direction of the rectangle circumscribing the opening 720A. As a result, for example, as shown in Fig. 100, the centers of the circles corresponding to the inner and outer peripheral surfaces of the semiconductor layer 130 etc. do not coincide with the center positions in the X' direction and the Y' direction of the rectangle circumscribing the pair of conductor posts 120.

[0142] Here, as described above, in order to realize a NOR flash memory including local bit lines LBL and local source lines LSL extending in the Z direction, a plurality of memory cells MC connected in parallel between them, and a plurality of word lines WL connected to the gate electrodes of these memory cells MC, it is possible to consider, for example, forming holes or the like appropriately corresponding to the local bit lines LBL, the local source lines LSL, the channel regions of the memory cells MC, etc. However, such a method requires precise positioning of these holes, which increases the difficulty of manufacturing.

[0143] For example, the holes corresponding to the local bit line LBL and the holes corresponding to the local source line LSL must both be in contact with the holes corresponding to the channel regions of the memory cells MC, while the holes corresponding to the local bit line LBL and the holes corresponding to the local source line LSL must not be in contact with each other.

[0144] Here, in the seventh embodiment, the positioning of the opening 720A and the opening 130A is also performed. However, the opening 720A and the opening 130A only need to overlap each other so that the opening 120A is formed on both sides of the opening 130A in the X' direction, and this allows for relatively easy positioning. Furthermore, as described above, the manufacturing method according to this embodiment makes it possible to preferably form the openings 120A and 130A, respectively. Therefore, the manufacturing method according to this embodiment makes it easy to realize a semiconductor memory device.

[0145] [Eighth embodiment] In the above embodiments and modifications, the case where the present invention is applied to a NOR-type flash memory has been described. However, these structures can also be applied to semiconductor devices other than NOR-type flash memories. Hereinafter, as an eighth embodiment, an example in which a structure similar to that of the semiconductor memory device according to the first embodiment is applied to a product-sum operation device will be described.

[0146] The product-sum calculation device according to the eighth embodiment is basically configured in the same manner as the semiconductor memory device according to the first embodiment. However, the peripheral circuits of the product-sum calculation device according to the eighth embodiment are different from the peripheral circuits PC (FIG. 1) of the semiconductor memory device according to the first embodiment.

[0147] For example, when performing a sum-of-products operation, the peripheral circuit according to the eighth embodiment supplies a voltage corresponding to the magnitude of the weight to each of a plurality of word lines WL in a plurality of memory blocks BLK. Furthermore, a voltage corresponding to the input data to be subjected to the sum-of-products operation is supplied to a plurality of source lines SL. A current corresponding to the threshold voltage and the voltage (gate voltage) of the word line WL flows through each memory cell MC. A sum of the currents flowing through the plurality of memory cells MC in the corresponding memory pillar MP flows through each local bit line LBL. Furthermore, a sum of the currents flowing through the local bit lines LBL flows through each bit line BL. The peripheral circuit acquires the currents flowing through each bit line BL as the result of the sum-of-products operation.

[0148] [others] Although several embodiments of the present invention have been described, these embodiments are presented as examples and are not intended to limit the scope of the invention. These novel embodiments can be embodied in various other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their modifications are included within the scope and spirit of the invention, and are also included in the scope of the invention and its equivalents as defined in the claims. [Explanation of symbols]

[0149] 110...conductive layer, 120...conductor pillar, 130...semiconductor layer, 131...insulating pillar, 140...gate insulating film, 141...tunnel insulating film, 142...charge storage film, 143, 144...block insulating film.

Claims

1. A plurality of conductive layers stacked in a stacking direction; a first conductor column and a second conductor column extending in the stacking direction and aligned in a first direction intersecting the stacking direction; an insulating pillar extending in the stacking direction and provided between the first conductive pillar and the second conductive pillar; a semiconductor layer formed along an outer circumferential surface of the insulating pillar, connected to the first conductor pillar and the second conductor pillar, and facing the plurality of conductive layers; a memory film provided between the plurality of conductive layers and the semiconductor layer; Equipped with In a cross section intersecting the stacking direction, At least a part of the outer circumferential surface of the semiconductor layer is formed substantially along a circular, elliptical or oval shape, At least a portion of the first conductive rod and at least a portion of the second conductive rod are provided outside the shape of the circle, ellipse, or oval. Semiconductor device.

2. In the cross section intersecting the stacking direction, one of the plurality of conductive layers surrounds the first conductor pillar, the second conductor pillar, and the semiconductor layer. The semiconductor device according to claim 1.

3. The memory film includes silicon nitride, a floating gate, or a ferroelectric film. The semiconductor device according to claim 1.

4. A plurality of conductive layers stacked in a stacking direction; a first conductor column and a second conductor column extending in the stacking direction and aligned in a first direction intersecting the stacking direction; a semiconductor layer provided between the first conductor pillar and the second conductor pillar, connected to a surface of the first conductor pillar facing the second conductor pillar and a surface of the second conductor pillar facing the first conductor pillar, and facing the plurality of conductive layers; a memory film provided between the plurality of conductive layers and the semiconductor layer; Equipped with In a cross section intersecting the stacking direction, the lengths of the first conductor pillar and the second conductor pillar in a second direction intersecting the stacking direction and the first direction are smaller than the lengths of the semiconductor layer in the first direction and the second direction. Semiconductor device.

5. A plurality of conductive layers stacked in a stacking direction; a first conductor column and a second conductor column extending in the stacking direction and aligned in a first direction intersecting the stacking direction; an insulating pillar extending in the stacking direction, provided between the first conductor pillar and the second conductor pillar, and connected to a surface of the first conductor pillar facing the second conductor pillar and a surface of the second conductor pillar facing the first conductor pillar; a semiconductor layer connected to both surfaces of the first conductor column and the second conductor column in the stacking direction and a second direction intersecting the first direction, and to portions of the outer circumferential surface of the insulating column other than contact portions with the first conductor column and the second conductor column, and facing the plurality of conductive layers; a memory film provided between the plurality of conductive layers and the semiconductor layer; Equipped with In a cross section intersecting the stacking direction, the lengths of the first conductor column and the second conductor column in the second direction are smaller than the lengths of the insulating column in the first direction and the second direction. Semiconductor device.

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