Interconnect structure and integrated circuit device
By employing a ruthenium film with controlled grain boundaries and orientation, the resistance issues in miniaturized interconnect structures are addressed, ensuring effective electrical performance.
Patent Information
- Application Number
- JP2025103939
- Authority / Receiving Office
- JP · JP
- Patent Type
- Applications
- Current Assignee / Owner
- Priority Date
- 2025-04-28
- Filing Date
- 2025-06-19
- Publication Date
- 2026-01-07
AI Technical Summary
As the size of interconnect structures in integrated circuit devices decreases, the resistance increases due to material limitations, leading to degradation of electrical characteristics.
The use of a ruthenium film with specific crystal grain properties, including a texturing coefficient of 0.70 to 1, average grain size of 50 nm to 200 nm, and controlled grain boundaries, is employed to reduce resistance and prevent electrical degradation.
This approach allows for reducing the dimensions of interconnect structures while maintaining or improving electrical characteristics by enhancing crystal orientation and reducing electron scattering.
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Figure 2026001725000001_ABST
Abstract
Description
[Technical Field]
[0001] The present invention relates to interconnect structures and integrated circuit devices. [Background technology]
[0002] In order to provide highly integrated, high-performance integrated circuit devices, it is necessary to reduce the dimensions of the circuit elements that make up the integrated circuit device. To this end, methods for reducing the dimensions of interconnect structures that electrically connect the circuit elements are being studied. Summary of the Invention [Problem to be solved by the invention]
[0003] However, as the size of the interconnect structure is reduced, the resistance increases rapidly due to the material limitations of the metal, which can cause degradation of electrical characteristics.
[0004] An object of one embodiment is to provide an interconnect structure that can reduce or prevent degradation of electrical characteristics while reducing the size of the interconnect structure.
[0005] Another embodiment aims to provide an integrated circuit device that includes the interconnect structure. [Means for solving the problem]
[0006] According to one embodiment, a method for manufacturing a ruthenium film includes: a lower layer including a non-single crystalline material; and a ruthenium film located on the lower layer and including a plurality of crystal grains, wherein the ruthenium film <001> The texturing coefficient (F 001 ) is 0.70 to 1, and the average crystal grain size of the ruthenium film is 50 nm to 200 nm.
[0007] The non-single crystalline material may include an amorphous conductor, a polycrystalline conductor, an amorphous semiconductor, a polycrystalline semiconductor, an amorphous dielectric, or a polycrystalline dielectric, or a combination thereof.
[0008] The interconnect structure may further include a dielectric film surrounding the ruthenium film.
[0009] The ratio of the intensity of the (002) peak to the intensity of the (101) peak observed in the X-ray diffraction pattern of the ruthenium film may be 30:1 to 100:1.
[0010] The intensity of the (002) peak observed in the X-ray diffraction pattern of the ruthenium film may be 90% to 100% of the total intensity of the (100), (101) and (002) peaks.
[0011] The misorientation angle of the grain boundary between adjacent crystal grains of the ruthenium film may be 0 to 15 degrees based on the horizontal direction of the ruthenium film.
[0012] Each grain boundary between adjacent grains of the ruthenium film may have a coincidence site lattice.
[0013] The ruthenium film may have an average surface roughness of more than 0 and less than 1.0 nm.
[0014] The ruthenium film may contain carbon in an amount of 0.01 at % or more and less than 0.30 at %.
[0015] The carbon may be distributed along grain boundaries between adjacent grains of the ruthenium film.
[0016] The ruthenium film <001> The texturing coefficient (F 001 ) may be 0.95 to 1, and the average crystal grain size of the ruthenium film may be 80 nm to 200 nm.
[0017] The line width of the ruthenium film may be equal to or greater than 1 nm and less than 20 nm.
[0018] According to another embodiment, the method includes the steps of: supplying a ruthenium precursor onto a lower layer including a non-single crystalline material to form a ruthenium deposit; and additionally annealing the ruthenium deposit to form a ruthenium film, <001> The texturing coefficient (F 001 ) is about 0.70 to 1, and the average crystal grain size of the ruthenium film is about 50 nm to 200 nm.
[0019] The steps of forming the ruthenium deposit and additionally annealing the ruthenium deposit may be performed at a temperature of about 200°C to 550°C, respectively.
[0020] The ruthenium film may contain carbon in an amount of 0.01 at % or more and less than 0.30 at %.
[0021] The ruthenium deposit may contain more carbon than the ruthenium film, and the ruthenium deposit may contain about 0.10 to 1.50 at % carbon.
[0022] of the ruthenium deposit <001> The area ratio of the crystal grains aligned in the direction may be less than about 60%, and the average crystal grain size of the ruthenium deposit may be greater than or equal to about 1 nm and less than about 20 nm.
[0023] During or after the step of supplying the ruthenium precursor, at least one of an oxidizing agent and a reducing agent and an inert gas may be supplied.
[0024] The oxidizing agent may include oxygen, ozone, water, or plasma species derived therefrom, and the reducing agent may include hydrogen gas, ammonia gas, or plasma activated species derived therefrom, and the partial pressure ratio of at least one of the oxidizing agent and the reducing agent to the inert gas may be about 0.05 to 1.
[0025] The ruthenium precursor may be supplied discontinuously 1 to 10 times.
[0026] According to another embodiment, a semiconductor device includes a semiconductor substrate, a circuit element integrated in or located on the semiconductor substrate, and a wiring electrically connected to the circuit element and including a ruthenium film including a plurality of crystal grains, wherein the ruthenium film <001> The texturing coefficient (F 001 ) is 0.70 to 1, and the average crystal grain size of the ruthenium film is 50 nm to 200 nm.
[0027] The integrated circuit device may further include a lower film located below the wiring and including a non-single crystalline material, and the lower film may include an amorphous conductor, a polycrystalline conductor, an amorphous semiconductor, a polycrystalline semiconductor, an amorphous dielectric, a polycrystalline dielectric, or a combination thereof.
[0028] The ruthenium film may contain carbon in an amount of 0.01 at % or more and less than 0.30 at %.
[0029] The misorientation angle of the grain boundaries between adjacent grains of the ruthenium film may be 0 to 15 degrees with respect to the horizontal direction of the ruthenium film, or the grain boundaries between adjacent grains of the ruthenium film may have coincident position lattices.
[0030] The ruthenium film may have an average surface roughness of more than 0 and less than 1.0 nm.
[0031] The line width of the ruthenium film may be equal to or greater than 1 nm and less than 20 nm.
[0032] According to yet another embodiment, a method for manufacturing a semiconductor device includes: a semiconductor substrate; a circuit element integrated in or located on the semiconductor substrate; a dielectric film located on the circuit element and having a trench; and a ruthenium film located in the trench, the ruthenium film comprising: <001> The ruthenium film contains the most oriented crystal grains, and the misorientation angle of the crystal grain boundaries between adjacent crystal grains in the ruthenium film is 0 to 15 degrees with respect to the horizontal direction of the ruthenium film, or the crystal grain boundaries between adjacent crystal grains in the ruthenium film have a coincident position lattice.
[0033] The ruthenium film <001> The texturing coefficient (F 001 ) can be between 0.95 and 1.
[0034] The ruthenium film may have an average crystal grain size of 80 nm to 200 nm, and an average surface roughness of the ruthenium film may be greater than 0 and less than 1.0 nm. [Effects of the Invention]
[0035] The dimensions of the interconnect structure can be reduced while reducing or preventing degradation of electrical characteristics. [Brief explanation of the drawings]
[0036] [Figure 1] 1 is a cross-sectional view illustrating an example of an interconnect structure according to an embodiment. [Figure 2] 1A to 1C are schematic diagrams illustrating an example of a method for manufacturing an interconnect structure according to an embodiment. [Figure 3] 1A to 1C are schematic diagrams illustrating an example of a method for manufacturing an interconnect structure according to an embodiment. [Figure 4] 1A to 1C are schematic diagrams illustrating an example of a method for manufacturing an interconnect structure according to an embodiment. [Figure 5] 1A to 1C are schematic diagrams illustrating an example of a method for manufacturing an interconnect structure according to an embodiment. [Figure 6] 10A and 10B are schematic diagrams illustrating another example of a method for manufacturing an interconnect structure according to an embodiment. [Figure 7] 10A and 10B are schematic diagrams illustrating another example of a method for manufacturing an interconnect structure according to an embodiment. [Figure 8] 10A and 10B are schematic diagrams illustrating another example of a method for manufacturing an interconnect structure according to an embodiment. [Figure 9] 10A and 10B are schematic diagrams illustrating another example of a method for manufacturing an interconnect structure according to an embodiment. [Figure 10] 1 is a cross-sectional view showing a three-dimensional logic element, which is an example of an integrated circuit element according to an embodiment. [Figure 11] FIG. 1 is a conceptual diagram illustrating an example of an electronic device according to an embodiment. [Figure 12] 1 is an atom probe tomography (APT) image showing carbon distribution in a ruthenium deposition according to Example 2. [Figure 13] 13 is a graph showing carbon concentration depending on the position of the ruthenium deposit in the APT image of FIG. 12. [Figure 14] 10 is an APT image showing the carbon distribution in the ruthenium film according to Example 2. [Figure 15] 15 is a graph showing carbon concentrations depending on positions in the ruthenium film in the APT image of FIG. 14. [Figure 16a] 1 is a PED orientation map along the z-axis direction of a ruthenium deposit according to Example 1. [Figure 16b] 1 is a PED orientation map along the z-axis direction of a ruthenium film according to Example 1. [Figure 17a] 1 is a PED orientation map of the ruthenium deposition according to Example 2 in the z-axis direction (direction perpendicular to the substrate surface). [Figure 17b] 10 is a PED orientation map of the ruthenium film according to Example 2 in the z-axis direction (direction perpendicular to the substrate surface). [Figure 18a] 10 is a PED orientation map along the z-axis of a ruthenium deposit according to Example 3. [Figure 18b]10 is a PED orientation map along the z-axis direction of a ruthenium film according to Example 3. [Figure 19a] 10 is a PED orientation map along the z-axis of a ruthenium deposit according to Example 4. [Figure 19b] 10 is a PED orientation map along the z-axis direction of a ruthenium film according to Example 4. [Figure 20a] 1 is a PED orientation map along the z-axis direction of the ruthenium deposition product according to Reference Example 1. [Figure 20b] 1 is a PED orientation map of the ruthenium film according to Reference Example 1 along the z-axis direction. [Figure 21] 1 shows XRD patterns measured at a normal angle of a ruthenium deposit and a ruthenium film according to Example 2. [Figure 22] 1 shows XRD patterns measured at normal angles of a ruthenium deposition product and a ruthenium film according to Reference Example 1. [Figure 23] 1 shows glancing angle incidence XRD patterns at a low angle (glancing angle, 0.5 degrees relative to the substrate surface) of a ruthenium deposit and a ruthenium film according to Example 2. [Figure 24] 1 shows glancing angle incidence XRD patterns at a low angle (0.5 degrees relative to the substrate surface) of a ruthenium deposition product and a ruthenium film according to Reference Example 1. [Figure 25] 1 is a TEM photograph showing the grain boundaries of a ruthenium film according to Example 2. [Figure 26] 1 is a TEM photograph showing the crystal grain boundaries of a ruthenium film according to Reference Example 2. [Figure 27a] 10 is a PED orientation map of the ruthenium film according to Example 2 in the z-axis direction (direction perpendicular to the substrate surface). [Figure 27b] 10 is a PED orientation map of the ruthenium film according to Example 2 in the x-axis direction (direction parallel to the substrate surface). [Figure 28a] 1 is a PED orientation map of the ruthenium film according to Reference Example 1 along the z-axis direction. [Figure 28b]1 is a PED orientation map along the x-axis direction of a ruthenium film according to Reference Example 1. [Figure 29a] 10 is a PED orientation map along the z-axis direction of the ruthenium film according to Reference Example 2. [Figure 29b] 10 is a PED orientation map along the x-axis direction of the ruthenium film according to Reference Example 2. [Figure 30] 1 is a graph showing the change in resistivity depending on the thickness (line width) of the ruthenium film according to Example 2 and Reference Examples 1 and 2. DETAILED DESCRIPTION OF THE INVENTION
[0037] Although the following detailed description of the embodiments will be given so that those skilled in the art can easily implement the present invention, the actual structure may be embodied in various different forms and is not limited to the embodiments described herein.
[0038] The terms used herein are merely used to describe exemplary embodiments and are not intended to limit the present invention. The singular expressions include the plural expressions unless the context clearly indicates otherwise.
[0039] It should be understood that the terms "comprise," "comprise," or "have" are intended to specify the presence of embodied features, numbers, steps, components, or combinations thereof, but do not preclude the possible presence or addition of one or more other features, numbers, steps, components, or combinations thereof.
[0040] In the drawings, thicknesses are exaggerated to clearly show multiple layers and regions, and similar parts are designated by the same reference numerals throughout the specification. When a part such as a layer, film, region, or plate is said to be "on" another part, this includes not only the case where it is "directly on" the other part, but also the case where there is another part between them. Conversely, when a part is said to be "directly on" the other part, it means that there is no other part between them.
[0041] In the drawings, in order to clearly explain the present embodiment, parts unnecessary for the explanation are omitted, and the same or similar components are designated by the same reference numerals throughout the specification.
[0042] Hereinafter, the term "top" or "above" may refer not only to something directly adjacent and immediately above, below, left, or right of something, but also to something not directly adjacent and above, below, left, or right of something. Furthermore, when a part is said to "comprise" a certain element, this means that it may further include other elements, unless otherwise specified.
[0043] Furthermore, the term "layer" or "film" as used herein includes not only shapes formed on the entire surface when observed in a plan view, but also shapes formed on a portion of the surface.
[0044] Use of the term "said" and similar directives can refer to both the singular and the plural. Unless a method step is expressly stated or stated to the contrary, such steps may be performed in any suitable order and are not necessarily limited to the order described.
[0045] As used herein, "combinations thereof" refers to mixtures, laminates, composites, alloys, blends, and the like of compositions.
[0046] Unless otherwise defined below, "substantially" or "nearly" or "about" includes not only the stated value but also the average within an acceptable range of variation, taking into account the error associated with the measurement and measurement of the measurand. For example, "substantially" or "nearly" can mean within ±10%, ±5%, ±3%, or ±1% or within the standard deviation of the stated value. Hereinafter, "metal" can include metals and metalloids.
[0047] An interconnect structure according to an embodiment will now be described. The interconnect structure may be a structure that provides a path that electrically connects two or more circuit elements in a semiconductor device, such as an integrated circuit device, and may include a via or wiring.
[0048] FIG. 1 is a cross-sectional view showing an example of an interconnect structure according to an embodiment.
[0049] Referring to FIG. 1, an interconnect structure 100 according to one embodiment includes a lower film 10, a dielectric film 20, and a ruthenium film 30.
[0050] The lower film 10 may be located below the ruthenium film 30 and may face the lower surface of the ruthenium film 30. For example, the lower film 10 may abut the lower surface of the ruthenium film 30.
[0051] The lower film 10 may include a non-monocrystalline material, such as a non-monocrystalline conductor, a non-monocrystalline semiconductor, or a non-monocrystalline dielectric, or a combination thereof. For example, the lower film 10 may include an amorphous conductor, a polycrystalline conductor, an amorphous semiconductor, a polycrystalline semiconductor, an amorphous dielectric, or a polycrystalline dielectric, or a combination thereof.
[0052] When the lower film 10 includes an amorphous conductor, a polycrystalline conductor, an amorphous semiconductor, or a polycrystalline semiconductor, the lower film 10 may be a contact conductive film or a contact semiconductor film electrically connected to the ruthenium film 30. The contact conductive film may be, for example, a contact metal film including a metal such as copper (Cu), aluminum (Al), cobalt (Co), tungsten (W), molybdenum (Mo), or an alloy or combination thereof, or may include, but is not limited to, a contact semimetal film such as an impurity-doped semimetal (e.g., silicon).
[0053] If the lower film 10 comprises an amorphous dielectric or a polycrystalline dielectric, the lower film 10 may be an interlayer dielectric (ILD) or an intermetal dielectric (IMD) and may comprise the same or a different dielectric material as the dielectric film 20. If the lower film 10 and the dielectric film 20 comprise the same dielectric material, the lower film 10 and the dielectric film 20 may be a continuous single film.
[0054] Dielectric film 20 can include, for example, a dielectric material having a dielectric constant of about 4.0 or less, such as a metal oxide, a metalloid oxide, a carbon-doped metal oxide, a carbon-doped metalloid oxide, a metal carbide, a metalloid carbide, a metal hydride, a metal hydride, a metalloid carbide, a metal nitride, a metalloid nitride, a carbon-doped metal nitride, a carbon-doped metalloid nitride, a metal oxynitride, a metalloid oxynitride, a carbon-doped metal oxynitride, or a carbon-doped metalloid oxynitride, or a combination thereof.
[0055] Dielectric film 20 may include, but is not limited to, for example, silicon oxide, silicon nitride, silicon oxynitride, silicon carbonate, silicon carbonitride, silicon carbonate nitride, aluminum oxide, aluminum nitride, aluminum silicon oxide, aluminum silicon nitride, zirconium oxide, hafnium oxide, or boron nitride, or combinations thereof.
[0056] The dielectric film 20 may have one or more trenches or via holes 21 (hereinafter referred to as "trench"). The trench 21 may be a space filled with a ruthenium film 30 (described later), and the internal shape of the trench 21 may be substantially the same as the shape of the ruthenium film 30. The trench 21 may have a relatively narrow width (W), and the width of the trench 21 may be substantially the same as the line width (W) of the ruthenium film 30 (described later). The width (W) of trench 21 may be, for example, less than about 20 nm, and may be within the above range of about 18 nm or less, about 15 nm or less, about 12 nm or less, about 10 nm or less, for example, about 9 nm or less, about 8 nm or less, about 7 nm or less, about 6 nm or less, about 5 nm or less, about 4 nm or less, or about 3 nm or less, and within the above range of about 1 nm or more but less than 20 nm, about 1 nm to 18 nm, about 1 nm to 15 nm, about 1 nm to 12 nm, about 1 nm to 10 nm, about 1 nm to 9 nm, about 1 nm to 8 nm, about 1 nm to 7 nm, about 1 nm to 6 nm, about 1 nm to 5 nm, about 1 nm to 4 nm, or about 1 nm to 3 nm.
[0057] The trench 21 may have a high aspect ratio, and the aspect ratio of the trench 21 may be substantially the same as the aspect ratio of the ruthenium film 30. Here, the aspect ratio may be the ratio of depth or thickness to width. The aspect ratio of the trench 21 may be about 3 or more, about 5 or more, about 7 or more, or about 10 or more. Within this range, the aspect ratio may be about 3 to 50, about 3 to 45, about 3 to 40, about 3 to 35, about 3 to 30, about 5 to 50, about 5 to 45, about 5 to 40, about 5 to 35, about 5 to 30, about 7 to 50, about 7 to 45, about 7 to 40, about 7 to 35, about 7 to 30, about 10 to 50, about 10 to 45, about 10 to 40, about 10 to 35, or about 10 to 30. The trench 21 can be narrow and deep by having a high aspect ratio in the range mentioned above.
[0058] The ruthenium film 30 may be filled in the trench 21 of the dielectric film 20 and may be used as wiring or vias (hereinafter, may be referred to as "wiring") in semiconductor devices (e.g., integrated circuit devices). The ruthenium film 30 may be a three-dimensional structure having a width (W), length, and thickness, where the length direction (e.g., Y direction) of the ruthenium film 30 may be the direction in which electrons move, the width direction (e.g., X direction) may be a direction perpendicular to the length direction within the plane, and the thickness direction (e.g., Z direction) may be perpendicular to the surface of the lower film 10 and perpendicular to the length direction and width direction, respectively.
[0059] The ruthenium film 30 can have a narrow linewidth (W) of less than about 20 nm, and within the above range can have a linewidth of about 18 nm or less, about 15 nm or less, about 12 nm or less, about 10 nm or less, for example, about 9 nm or less, about 8 nm or less, about 7 nm or less, about 6 nm or less, about 5 nm or less, about 4 nm or less, about 3 nm or less, about 1 nm or more but less than 20 nm, about 1 nm to 18 nm, about 1 nm to 15 nm, about 1 nm to 12 nm, about 1 nm to 10 nm, about 1 nm to 9 nm, about 1 nm to 8 nm, about 1 nm to 7 nm, about 1 nm to 6 nm, about 1 nm to 5 nm, about 1 nm to 4 nm, or about 1 nm to 3 nm.
[0060] The ruthenium film 30 may include ruthenium or a ruthenium alloy and may be, for example, a polycrystalline conductive film having a hexagonal close-packed (HCP) crystal structure. The ruthenium film 30 may be formed by, for example, atomic layer deposition (ALD) or chemical vapor deposition (CVD), and therefore may be effectively formed with the narrow linewidths described above.
[0061] The ruthenium film 30 may include ruthenium or a ruthenium alloy obtained by additionally annealing a ruthenium or ruthenium alloy deposit (hereinafter referred to as "ruthenium deposit") formed by atomic layer deposition or chemical vapor deposition at a relatively low temperature.
[0062] Atomic layer deposition or chemical vapor deposition is a process for nucleating crystals within the ruthenium deposit, which can induce a preferred crystallographic orientation. Additional annealing can be a recrystallization process that rearranges and grows atoms within the ruthenium deposit, enhancing crystallinity and orientation. The annealed ruthenium film 30 can have improved film quality compared to unannealed ruthenium deposits. The improved film quality is due to the crystalline orientation of the grains, a reduced number of grain boundaries, and a smooth surface. This improved film quality can effectively reduce electron scattering at the surface and / or grain boundaries in ruthenium films 30 with narrow linewidths of less than about 20 nm (e.g., about 15 nm or less, or about 10 nm or less), thereby exhibiting improved electrical properties.
[0063] A ruthenium precursor for atomic layer deposition or chemical vapor deposition may be a ruthenium-containing organometallic compound, and the ruthenium deposit and ruthenium film 30 may contain carbon derived from the ruthenium precursor. Alternatively, a carbon promoter may be additionally provided during the atomic layer deposition or chemical vapor deposition step, and the ruthenium deposit and ruthenium film 30 may contain carbon derived from the carbon promoter.
[0064] The carbon remaining in the ruthenium deposit and / or the final carbon remaining in the ruthenium film 30 after additional annealing may be mostly distributed along the grain boundaries between adjacent grains.
[0065] For example, carbon distributed at the grain boundaries of a ruthenium deposit during the deposition stage can effectively control the crystal orientation of the grains in the ruthenium deposit to induce a preferred crystal orientation, and can provide a basis for strengthening the crystal orientation during the subsequent annealing stage (recrystallization process). This is expected to be because, without being limited to a particular theory, a certain amount of carbon distributed at the grain boundaries of a ruthenium deposit controls the surface energy of the crystal grains, capturing more atoms in a preferred direction and diffusing them to the surface to control the crystal orientation.
[0066] For example, during the annealing step (recrystallization process), some of the carbon distributed along the grain boundaries of the ruthenium deposit can be expelled, promoting atomic migration and coalescence, thereby expanding the grains and increasing their size, while also further strengthening the crystallographic orientation of the ruthenium film 30.
[0067] The control of the grain size and crystal orientation of the ruthenium film 30 can be determined by the amount of residual carbon in the ruthenium deposit and / or the ruthenium film 30 .
[0068] The amount of residual carbon in the ruthenium deposit may be, for example, about 1.50 at% or less, and within this range, it may be about 0.10-1.50 at%, about 0.10-1.40 at%, about 0.10-1.30 at%, about 0.10-1.20 at%, about 0.20-1.50 at%, about 0.20-1.40 at%, about 0.20-1.30 at%, or about 0.20-1.20 at%. By including carbon in the ruthenium deposit in this range, the crystal orientation of the crystal grains in the ruthenium deposit can be effectively controlled. The amount of residual carbon in the ruthenium deposit can be controlled by adjusting the substrate temperature (process temperature), deposition pressure, and / or co-reactant partial pressure (e.g., oxygen partial pressure) during deposition. For example, the amount of residual carbon can be effectively reduced by increasing the substrate temperature (process temperature), decreasing the deposition pressure, and / or decreasing the co-reactant partial pressure (e.g., oxygen partial pressure).
[0069] The amount of carbon remaining in the ruthenium film 30 after annealing may be less than the amount of carbon in the ruthenium deposit, for example, less than about 0.30 at% carbon, and may be within the range of about 0.28 at% or less, about 0.25 at% or less, about 0.22 at% or less, about 0.20 at% or less, or about 0.19 at% or less, and within the range of about 0.01 to less than about 0.30 at%, about 0.01 to about 0.28 at%, about 0.01 to about 0.25 at%, about 0.01 to about 0.2 ... The carbon content may be 1 to about 0.20 at%, about 0.01 to 0.19 at%, about 0.05 or more but less than about 0.30 at%, about 0.05 to about 0.28 at%, about 0.05 to about 0.25 at%, about 0.05 to about 0.22 at%, about 0.05 to about 0.20 at%, about 0.05 to 0.19 at%, about 0.10 or more but less than about 0.30 at%, about 0.10 to about 0.28 at%, about 0.10 to about 0.25 at%, about 0.10 to about 0.22 at%, about 0.10 to about 0.20 at%, or about 0.10 to 0.19 at%. The carbon content in the above range in the ruthenium film 30 effectively increases the size of the crystal grains and further strengthens the crystal orientation of the ruthenium film 30.
[0070] For example, by including carbon in the above range, the majority of the crystal grains constituting the ruthenium film 30 can be oriented in a direction perpendicular to the surface (horizontal surface of the crystal grains) of the underlying film 10 (hereinafter referred to as the "vertical direction"). For example, most of the crystal grains of the ruthenium film 30 are <001> oriented in a direction <001> The direction of the ruthenium film 30 may be the c-axis direction. <001> The area ratio of crystal grains aligned in the direction may be about 70% to 100%, and within this range may be about 75% to 100%, about 80% to 100%, about 85% to 100%, about 90% to 100%, about 95% to 100%, about 97% to 100%, about 98% to 100%, or about 99% to 100%.
[0071] The degree to which the crystal grains are oriented in one direction can be expressed as a grain texturing factor (F) (or Lotgering degree of orientation), which can be the ratio of the area of the crystal grains aligned in a given direction to the area occupied by the crystal grains. <001> The grain texturing coefficient, F, is the ratio of the area of grains aligned in the direction. 001 may be about 0.70 to 1, about 0.75 to 1, about 0.80 to 1, about 0.85 to 1, about 0.90 to 1, about 0.95 to 1, about 0.97 to 1, about 0.98 to 1, or about 0.99 to 1.
[0072] Here, the grain texturing coefficient is the percentage of the total area observed in a photograph of a portion of the ruthenium film 30 (for example, a transmission electron microscopy (TEM) photograph and a precession electron diffraction orientation map (PED) map). <001> It can be measured from the ratio of the area occupied by the oriented crystal grains, for example, in a photograph of about 500nm x about 500nm size or a photograph of an area equivalent thereto. <001> It can be measured from the ratio of the area occupied by the oriented crystal grains.
[0073] Furthermore, as will be described later, when the ruthenium film 30 is included in the wiring or via of an element such as an integrated circuit element, the grain texturing coefficient (F 001 ) is a photograph of an area corresponding to a predetermined area (for example, about 500 nm (line width) x about 500 nm (length)) of the cross section of the ruthenium film 30 (for example, wiring or via). <001> It can be measured from the ratio of the area occupied by the oriented grains. For example, when the line width of a wiring or via is about 10 nm, the grain texturing coefficient (F 001 ) is a photograph of a line width of approximately 10 nm and a length of approximately 25 μm (corresponding to an area defined by a line width of approximately 500 nm and a length of approximately 500 nm). <001> It can be measured from the ratio of the area occupied by the oriented crystal grains.
[0074] The orientation of the crystal grains constituting the ruthenium film 30 can be confirmed by an X-ray diffraction (XRD) pattern. <001> The (002) peak (2θ = 42.3 degrees) corresponding to the direction is predominantly observed. <001> The intensity of the (002) peak corresponding to the direction can account for about 90% or more, about 92% or more, about 95% or more, about 97% or more, about 98% or more, about 99% or more, about 99.5% or more, or 100% of the total intensity of the (100) (2θ=38.5 degrees), (101) (2θ=44.2 degrees), and (002) peaks. For example, the (100) and (101) peaks may be substantially absent from the XRD pattern of the ruthenium film 30.
[0075] For example, the ratio of the intensity of the (002) peak to the intensity of the (101) peak observed in the XRD pattern of the ruthenium film 30 may be about 30 or greater (about 30:1 or greater), and may be about 33 or greater (about 33:1 or greater), about 35 or greater (about 35:1 or greater), about 37 or greater (about 37:1 or greater), or about 40 or greater (about 40:1 or greater) within the aforementioned range, and may be about 30 to 100 (about 30:1 to 100:1), about 33 to 100 (about 33:1 to 100:1), about 35 to 100 (about 35:1 to 100:1), about 37 to 100 (about 37:1 to 100:1), or about 40 to 100 (about 40:1 to 100:1) within the aforementioned range.
[0076] For example, no peaks may be observed in the grazing incidence (or glancing angle incidence) XRD pattern of the ruthenium film 30 at an incidence angle of about 0.5 degrees. The grazing incidence XRD pattern is a method for analyzing the crystalline structure of a surface by irradiating light at an angle of less than about 10 degrees with respect to the horizontal direction. The reason why no peaks are observed is that most of the crystal grains in the ruthenium film 30 are perpendicular to the surface (horizontal plane of the crystal grains) of the underlying film 10. <001> It can mean arranged in a direction.
[0077] For example, by including carbon in this range, the ruthenium film 30 can effectively control the orientation of horizontal grain boundaries by reducing the misorientation between adjacent grains arranged in a direction (hereinafter referred to as the "horizontal direction" or "in-plane direction") parallel to the surface (the horizontal plane of the grains) of the underlying film 10. The orientation of such horizontal grain boundaries can be confirmed from the misorientation angle (or tilt angle) of the grain boundaries between adjacent grains, where the misorientation angle of the grain boundaries can be the angle of change required to align adjacent grains.
[0078] The misorientation angle of the grain boundaries between adjacent crystal grains in the ruthenium film 30 may be about 15 degrees or less based on the horizontal direction of the ruthenium film 30 (or the in-plane direction of the ruthenium film 30). The misorientation angle of the grain boundaries in the ruthenium film 30 can be evaluated through transmission electron microscopy (TEM) analysis. The misorientation angle of the grain boundaries between adjacent crystal grains within the above range may be 0 degrees to about 15 degrees, 0 degrees to about 13 degrees, 0 degrees to about 10 degrees, 0 degrees to about 7 degrees, or 0 degrees to about 5 degrees. The misorientation angle of the grain boundaries between adjacent crystal grains within the above range may be about 0.2 degrees to about 15 degrees, about 0.2 degrees to about 13 degrees, about 0.2 degrees to about 10 degrees, about 0.2 degrees to about 7 degrees, or about 0.2 degrees to about 5 degrees.
[0079] When the ruthenium film 30 has a grain boundary misorientation angle within this range, electron scattering at the grain boundaries can be effectively reduced, and therefore, a sudden increase in resistance due to electron scattering at the grain boundaries of a ruthenium film 30 having a fine linewidth of about 20 nm or less (e.g., about 15 nm or less or about 10 nm or less) can be effectively reduced or prevented.
[0080] Each grain boundary in the ruthenium film 30 may have a coincidence site lattice (CSL). The coincidence site lattice refers to a lattice structure in which some lattice points coincide when the crystal lattices of two adjacent crystal grains are rotated by a predetermined angle, and may indicate the symmetry of the crystal grains in the ruthenium film 30. For example, when adjacent crystal grains have different crystal orientations (e.g., when crystal grains having (001), (110), and (011) orientations are arranged adjacent to each other), the crystal grains do not have symmetry and therefore may not have a coincidence site lattice. Most of the crystal grain boundaries in the ruthenium film 30 may have a coincidence site lattice. The coincidence site lattice is expressed as sigma (ΣX, where X is a natural number), where ΣX is the ratio of the number of lattice points in a unit cell of the coincidence site lattice to the number of lattice points in a unit cell of the base lattice. For example, Σ3 may indicate that three lattice points coincide when two crystal lattices are rotated. The ruthenium film 30 can have a coincident lattice, such as, for example, Σ7, Σ13, Σ19, and / or Σ31, where the coincident lattice of the ruthenium film 30 can be evaluated through transmission electron microscope (TEM) analysis.
[0081] As mentioned above, most of the crystal grains in the ruthenium film 30 are vertical. <001> The ruthenium film 30 has a predominantly oriented crystal grain direction, and the orientation of the grain boundaries between horizontally adjacent crystal grains is effectively controlled, resulting in a relatively low surface roughness. The average surface roughness of the ruthenium film 30 may be less than about 1.0 nm, and may be within the range of about 0.9 nm or less, about 0.8 nm or less, about 0.7 nm or less, about 0.6 nm or less, or about 0.5 nm or less, and within the range of more than 0 and less than about 1 nm, more than 0 and less than about 0.9 nm, more than 0 and less than about 0.8 nm, more than 0 and less than about 0.7 nm, more than 0 and less than about 0.6 nm, more than 0 and less than about 0.5 nm, about 0.01 nm or more and less than about 1 nm, about 0.01 nm to about 0.9 nm, about 0.01 nm to 0.8 nm, about 0.01 nm to 0.7 nm, about 0.01 nm to 0.7 nm, or about 0.01 nm to 0.1 nm. The average surface roughness may be about 0.2 nm to about 0.9 nm, about 0.2 nm to about 0.8 nm, about 0.2 nm to about 0.7 nm, about 0.2 nm to about 0.6 nm, about 0.01 nm to 0.5 nm, about 0.1 nm to about 0.9 nm, about 0.1 nm to 0.8 nm, about 0.1 nm to 0.7 nm, about 0.1 nm to 0.6 nm, about 0.1 nm to 0.5 nm, about 0.2 nm to about 0.9 nm, about 0.2 nm to 0.8 nm, about 0.2 nm to 0.7 nm, about 0.2 nm to 0.6 nm, about 0.2 nm to 0.5 nm, about 0.3 nm to about 0.9 nm, about 0.3 nm to 0.8 nm, about 0.3 nm to 0.7 nm, about 0.3 nm to 0.6 nm, or about 0.3 nm to 0.5 nm. Here, the average surface roughness may be Arithmetic Average Roughness (Ra).
[0082] For example, the ruthenium film 30 can grow with relatively uniformly large crystal grains by including carbon in the above range. As described above, during the annealing step (recrystallization process), some of the carbon in the ruthenium deposit is released, which can move the grain boundaries and expand the grains, resulting in an increase in the size of the crystal grains.
[0083] The average crystal grain size of the ruthenium film 30 may be about 50 nm or more, and may be within the range of about 55 nm or more, about 60 nm or more, about 70 nm or more, about 80 nm or more, about 90 nm or more, or about 100 nm or more, and may be within the range of about 50 nm to 200 nm, about 55 nm to 200 nm, about 60 nm to 200 nm, about 70 nm to 200 nm, about 80 nm to 200 nm, about 90 nm to 200 nm, or about 100 nm. nm~200nm, approx. 50nm~180nm, approx. 55nm~180nm, approx. 60nm~180nm, approx. 70nm~180nm, approx. 80nm~180nm, approx. 90nm~180nm, approx. 100nm ~180nm, approx. 50nm ~ 160nm, approx. 55nm ~ 160nm, approx. 60nm ~ 160nm, approx. 70nm ~ 160nm, approx. 80nm ~ 160nm, approx. 90nm ~ 160nm, approx. 100nm ~ 16 0nm, approx. 50nm~150nm, approx. 55nm~150nm, approx. 60nm~150nm, approx. 70nm~150nm, approx. 80nm~150nm, approx. 90nm~150nm, approx. 100nm~150n m, approximately 50nm~140nm, approximately 55nm~140nm, approximately 60nm~140nm, approximately 70nm~140nm, approximately 80nm~140nm, approximately 90nm~140nm, approximately 100nm~140nm, approx. It can be 50 nm to 130 nm, about 55 nm to 130 nm, about 60 nm to 130 nm, about 70 nm to 130 nm, about 80 nm to 130 nm, about 90 nm to 130 nm, about 100 nm to 130 nm, about 50 nm to 115 nm, about 55 nm to 115 nm, about 60 nm to 115 nm, about 70 nm to 115 nm, about 80 nm to 115 nm, about 90 nm to 115 nm, or about 100 nm to 115 nm.
[0084] Here, the average crystal grain size of the ruthenium film 30 can be determined by averaging the crystal grain sizes observed in a photograph (e.g., a transmission electron microscope (TEM) photograph and / or a PED orientation map) of a portion of the ruthenium film 30. Furthermore, within an element such as an integrated circuit device, the average crystal grain size of the ruthenium film 30 can be determined by observing an area range corresponding to a predetermined area (e.g., about 500 nm x about 500 nm) of the cross section of the ruthenium film 30 and averaging the crystal grain sizes. For example, if the integrated circuit device includes wiring with a fine line width (e.g., about 10 nm), as will be described later, the average crystal grain size can be determined by averaging the crystal grain sizes observed in an area corresponding to a line width of about 10 nm and a length of about 25 μm, which corresponds to about 500 nm x about 500 nm.
[0085] Thus, the ruthenium deposit and the ruthenium film 30 are vertically oriented due to the inclusion of carbon in the range described above. <001> The grains are predominantly oriented in the vertical and horizontal directions, and the horizontal orientation of the grain boundaries between adjacent grains is stably controlled, while the grain size can be increased. As a result, the ruthenium film 30 has relatively large grains, yet has uniform and stable orientation in both the vertical and horizontal directions, which effectively reduces electron scattering at the grain boundaries. Unlike bulk metals such as copper, this effectively reduces or prevents a sudden increase in resistance even at narrow line widths of less than about 20 nm (about 15 nm or less, or about 10 nm or less).
[0086] For example, in a ruthenium film 30 having a narrow linewidth of less than about 20 nm, the change in resistivity due to a 10% reduction in linewidth may be less than about 2 times. Within this range, the change in resistivity of the ruthenium film 30 due to a 10% reduction in linewidth may be about 1 to 1.8 times, about 1 to 1.6 times, or about 1 to 1.4 times. For example, in a ruthenium film 30 having a narrow linewidth of less than about 20 nm, the change in resistivity due to a 20%, 30%, 40%, 50%, 60%, or 70% reduction in linewidth may be less than about 2 times, and within the above range, may be about 1 to 1.8 times, about 1 to 1.6 times, or about 1 to 1.4 times.
[0087] As an example, for a ruthenium film 30 having a narrow linewidth of less than about 20 nm, the resistivity of the ruthenium film 30 may be about 15 μΩ·cm or less, and within the range may be about 13 μΩ·cm or less, about 12 μΩ·cm or less, or about 10 μΩ·cm or less, and within the range may be about 3 μΩ·cm to 15 μΩ·cm, about 3 μΩ·cm to 13 μΩ·cm, about 3 μΩ·cm to 12 μΩ·cm, about 3 μΩ·cm to 10 μΩ·cm, about 5 μΩ·cm to 15 μΩ·cm, about 5 μΩ·cm to 13 μΩ·cm, about 5 μΩ·cm to 12 μΩ·cm, or about 5 μΩ·cm to 10 μΩ·cm.
[0088] The ruthenium film 30 described above can have stable vertical and horizontal orientation, reduced grain boundaries, and relatively large grains, even without using a single-crystal substrate (e.g., a sapphire substrate) or a physical vapor deposition method (e.g., sputtering) that requires high temperatures of about 1000°C or higher. Therefore, even with a narrow linewidth of less than about 20 nm (about 15 nm or less or about 10 nm or less), electron scattering at the surface and grain boundaries can be effectively reduced, maintaining stable electrical characteristics without abrupt changes in resistivity. Therefore, the ruthenium film 30 described above and the interconnect structure 100 including the same can be effectively applied to semiconductor devices in which multiple circuit elements are stacked, overcoming limitations such as the lower layer (non-single-crystal film) and process temperature.
[0089] An example of a method for manufacturing an interconnect structure according to an embodiment will be described below.
[0090] 2 to 5 are schematic diagrams showing an example of a method for manufacturing an interconnect structure according to an embodiment.
[0091] An example of a method for manufacturing an interconnect structure according to one embodiment includes forming a dielectric film 20 on a lower film 10, forming a trench or via 21 (hereinafter referred to as a "trench") in the dielectric film 20, forming a ruthenium deposit 30a in the trench 21, and further annealing the ruthenium deposit 30a to form a ruthenium film 30.
[0092] Referring to FIG. 2, a dielectric film 20 is formed on a lower film 10 .
[0093] The lower film 10 may include a non-single-crystalline material, such as an amorphous conductor, a polycrystalline conductor, an amorphous semiconductor, a polycrystalline semiconductor, an amorphous dielectric, a polycrystalline dielectric, or a combination thereof. For example, the lower film 10 may include a contact metal film including a metal such as copper (Cu), aluminum (Al), cobalt (Co), tungsten (W), molybdenum (Mo), an alloy thereof, or a combination thereof; a contact semimetal film such as an impurity-doped semimetal (e.g., silicon); or a dielectric including silicon oxide, silicon nitride, silicon oxynitride, silicon carbonate, silicon carbonitride, silicon carbonate nitride, aluminum oxide, aluminum nitride, aluminum silicon oxide, aluminum silicon nitride, zirconium oxide, hafnium oxide, or boron nitride, or a combination thereof.
[0094] 3, the dielectric film 20 is patterned to form a trench 21. The trench 21 may be narrow and deep, for example, having a width of less than about 20 nm and an aspect ratio of about 3 or greater. The width of the trench 21 may be within the above ranges of about 18 nm or less, about 15 nm or less, about 12 nm or less, about 10 nm or less, for example, about 9 nm or less, about 8 nm or less, about 7 nm or less, about 6 nm or less, about 5 nm or less, about 4 nm or less, or about 1 nm or more but less than 20 nm, about 1 nm to 18 nm, about 1 nm to 15 nm, about 1 nm to 12 nm, about 1 nm to 10 nm, about 1 nm to 9 nm, about 1 nm to 8 nm, about 1 nm to 7 nm, about 1 nm to 6 nm, about 1 nm to 5 nm, about 1 nm to 4 nm, or about 1 nm to 3 nm. The aspect ratio of trench 21 may be within the above ranges, for example, about 3 to 50, about 3 to 45, about 3 to 40, about 3 to 35, about 3 to 30, about 5 to 50, about 5 to 45, about 5 to 40, about 5 to 35, or about 5 to 30. Patterning can be performed by, for example, a photoetching process, but is not limited to this.
[0095] Optionally, a deposition suppression layer (not shown), a barrier layer (not shown), and / or a liner (not shown) may be additionally formed on the inner wall of the dielectric film 20 in the trench 21. The deposition suppression layer may include, but is not limited to, a silane compound, a siloxane compound, a silazane compound, or a combination thereof. The barrier layer and / or liner may include, but is not limited to, a metal, a semi-metal, a metal alloy, a metal nitride, a semi-metal nitride, or a combination thereof, such as tantalum (Ta), titanium (Ti), cobalt (Co), tungsten (W), silicon (Si), or a nitride thereof, or a combination thereof.
[0096] 4, a ruthenium deposit 30a is formed inside the trench 21 and on the dielectric film 20. The ruthenium deposit 30a can be formed by, for example, atomic layer deposition or chemical vapor deposition. Here, a method for forming the ruthenium deposit 30a will be described focusing on atomic layer deposition as an example, but is not limited thereto.
[0097] Deposition can be performed by placing a substrate including the lower film 10 in a deposition chamber (not shown) and supplying a ruthenium precursor as a reactant. Deposition can be performed at a process pressure (deposition pressure or chamber pressure) of about 10 Torr or less and a temperature of about 550°C or less, or at about 500°C or less or about 450°C or less within the above range. Deposition can be performed at about 220°C to 550°C, about 220°C to 500°C, about 220°C to 450°C, about 250°C to 550°C, about 250°C to 500°C, about 250°C to 450°C, about 300°C to 550°C, about 300°C to 500°C, about 300°C to 450°C, about 350°C to 550°C, about 350°C to 500°C, or about 350°C to 450°C within the above range.
[0098] Ruthenium precursors can include, for example, organometallic compounds, such as (arene)(diene)Ru(0) such as (ethylbenzene)(1-ethyl-1,4-cyclohexadiene)Ru(0), (1-isopropyl-4-methylbenzene)(1,3-cyclohexadiene)Ru(0); (arene)(triene)Ru(0) such as (benzene)(1,3,5-cycloheptatriene)Ru(0); (2,3-dimethyl-1,3-butadiene)Ru(0) tricarbonyl (diene)(CO)3Ru(0) such as (1,3-cyclohexadiene)Ru(0) tricarbonyl; (triene)(CO)3Ru(0) such as (1,3,5-cycloheptatriene)Ru(0) tricarbonyl; (cyclopentadienyl)(CO)2(R)Ru(II) such as (cyclopentadienyl)(ethyl)Ru(II) dicarbonyl; (cyclopentadienyl)2Ru(II) such as bis(ethylcyclopentadienyl)Ru(II); (2,4-di (pentadienyl)(η5-cyclopentadienyl)Ru(II) such as (methylpentadienyl)(ethylcyclopentadienyl)Ru(II); bis(ethylcyclopentadienyl)ruthenium(II) (bis(ethylcyclopentadienyl)ruthenium(II), RuEtCP2); (pentadienyl)2Ru(II) such as bis(2,4-dimethylpentadienyl)Ru(II); bis(2,4-pentanediketonate)Ru(II) The dicarbonyl(diketonate)Ru(II); (N,N'-di-isopropylacetamidinate)Ru(II); dicarbonyl(amidinate)Ru(CO)Ru(II); tricarbonyl(trimethylenemethane)ruthenium, or Ru(TMM)(CO), or combinations thereof.
[0099] The ruthenium precursor may be discontinuously supplied in several portions, discontinuously supplied in 1 to 10 portions, or discontinuously supplied in 1 to 8 portions, 1 to 6 portions, or 1 to 4 portions within the above range.
[0100] Next, a purge gas may be supplied into the deposition chamber to perform a primary purge. The purge gas may include, for example, argon gas, helium gas, nitrogen gas, neon gas, or a mixture thereof, and may be supplied at a flow rate of, for example, about 10 sccm to 2000 sccm. Impurities in the deposition chamber may be removed by evacuating diffusing unreacted materials and / or reaction by-products.
[0101] Next, at least one of an oxidant and a reductant and an inert gas can be supplied as co-reactants into the chamber. The oxidant can include, for example, oxygen, ozone, water, or plasma species derived therefrom. The reductant can include, for example, hydrogen gas, ammonia gas, or plasma-activated species derived therefrom. The inert gas can be, for example, argon gas, helium gas, nitrogen gas, neon gas, or a mixture thereof. The partial pressure ratio of at least one of the oxidant and the reductant to the inert gas (volume ratio of inert gas to at least one of the oxidant and the reductant) can be about 0.05 to 1 (about 95:5 to about 50:50), and within this range, it can be about 0.1 to 0.8, about 0.1 to 0.6, or about 0.1 to 0.5. The at least one of the oxidant and the reductant and the inert gas can be supplied after the purging step or simultaneously with the ruthenium precursor.
[0102] Next, a second purge can be performed by supplying a purge gas into the deposition chamber. The purge gas can include, for example, N2, Ne, Ar, He, or a mixture thereof, and can be supplied at a flow rate of, for example, about 10 sccm to 2000 sccm.
[0103] The deposition may be performed in one to multiple cycles to form a ruthenium deposit 30a of a desired thickness. For example, the cycle may be performed 1 to 300 times, but is not limited to this.
[0104] The ruthenium deposit 30a may be a polycrystalline conductor, and the film quality of the ruthenium deposit 30a may be different from the film quality of the ruthenium film 30 that is the final structure.
[0105] For example, the ruthenium deposit 30a may contain carbon derived from the ruthenium precursor, and the carbon may be distributed primarily at the grain boundaries of the ruthenium deposit 30a. The amount of carbon in the ruthenium deposit 30a may be, for example, about 1.50 at% or less, and within this range may be about 0.10-1.50 at%, about 0.10-1.40 at%, about 0.10-1.30 at%, about 0.10-1.20 at%, about 0.20-1.50 at%, about 0.20-1.40 at%, about 0.20-1.30 at%, or about 0.20-1.20 at%. As described above, the carbon content in the ruthenium deposit 30a can be controlled by adjusting the substrate temperature, deposition pressure, and / or partial pressure of the co-reactant (e.g., oxygen partial pressure) during deposition. For example, the carbon content can be reduced by increasing the substrate temperature, decreasing the deposition pressure, and / or decreasing the partial pressure of the co-reactant (e.g., oxygen partial pressure).
[0106] For example, some of the crystal grains of the ruthenium deposit 30a may be oriented in a predetermined direction. <001> The area ratio of crystal grains aligned in the direction may be less than about 60%, and may be within the above ranges of about 55% or less, about 50% or less, or about 40% or less, and within the above ranges of about 1% to less than about 60%, about 1% to 55%, about 1% to 50%, about 1% to 40%, about 5% to less than about 60%, about 5% to 55%, about 5% to 50%, or about 5% to 40%.
[0107] For example, the average grain size of the ruthenium deposit 30a can be less than about 20 nm, and can be within the range of about 18 nm or less, about 16 nm or less, about 14 nm or less, about 12 nm or less, or about 10 nm or less, and can be within the range of about 1 nm or more but less than 20 nm, about 1 nm to 18 nm, about 1 nm to 16 nm, about 1 nm to 14 nm, about 1 nm to 12 nm, or about 1 nm to 10 nm.
[0108] 5, the ruthenium deposit 30a is then annealed to form a ruthenium film 30. Annealing can be performed, for example, under vacuum or vacuum-like conditions. Annealing can be performed at a temperature of about 550°C or less, and within the above range, about 500°C or less, or about 450°C or less. Annealing can be performed at a temperature of about 220°C to 550°C, about 220°C to 500°C, about 200°C to 450°C, about 250°C to 550°C, about 250°C to 500°C, about 250°C to 450°C, about 300°C to 550°C, about 300°C to 500°C, about 300°C to 450°C, about 350°C to 550°C, about 350°C to 500°C, or about 350°C to 450°C.
[0109] Annealing may remove some of the carbon distributed along the grain boundaries of the ruthenium deposit 30a, so that the carbon content of the ruthenium film 30 may be less than that of the ruthenium deposit 30a. The carbon content of the ruthenium film 30 may be, for example, less than about 0.30 at%, and within the range, may be about 0.01 to less than about 0.30 at%, about 0.01 to about 0.28 at%, about 0.01 to about 0.25 at%, about 0.01 to about 0.22 at%, about 0.01 to about 0.20 at%, about 0.01 to about 0.18 at%, about 0.05 to less than about 0.30 at%, about 0.05 to about 0.2 8 at%, about 0.05 to about 0.25 at%, about 0.05 to about 0.22 at%, about 0.05 to about 0.20 at%, about 0.05 to 0.18 at%, about 0.10 or more but less than about 0.30 at%, about 0.10 to about 0.28 at%, about 0.10 to about 0.25 at%, about 0.10 to about 0.22 at%, about 0.10 to about 0.20 at%, or about 0.10 to 0.18 at%.
[0110] Annealing can rearrange the grains of the ruthenium film 30, with most of the grains in the ruthenium film 30 being vertically oriented. <001> The ruthenium film 30 can be oriented preferentially in the direction <001> The area ratio of the crystal grains aligned in the direction is, for example, about 70% to 100% (F 001 can be about 0.70 to 1), and within that range, about 75% to 100% (F 001 is about 0.75 to 1), about 80% to 100% (F 001is approximately 0.80 to 1), approximately 85% to 100% (F 001 is about 0.85 to 1), about 90% to 100% (F 001 is approximately 0.90 to 1), approximately 95% to 100% (F 001 is approximately 0.95 to 1), approximately 97% to 100% (F 001 is approximately 0.97 to 1), approximately 98% to 100% (F 001 is approximately 0.98 to 1) or approximately 99% to 100% (F 001 can be about 0.99 to 1).
[0111] Annealing can cause the ruthenium film 30 to exhibit a reduced misorientation angle of the grain boundaries between horizontally adjacent grains or a coincident lattice, for example, the misorientation angle of the grain boundaries between adjacent grains is about 15 degrees or less relative to the horizontal direction of the ruthenium film 30, or the film can have a coincident lattice, such as Σ7, Σ13, Σ19, and / or Σ31.
[0112] Annealing may cause the grain size in the ruthenium film 30 to be larger than the grain size of the ruthenium deposit 30a, and the average grain size in the ruthenium film 30 may be about 50 nm or greater, and may be within the range of about 60 nm or greater, about 70 nm or greater, about 80 nm or greater, about 90 nm or greater, or about 100 nm or greater, and may be within the range of about 50 nm to 200 nm, about 60 nm to 200 nm, about 70 nm to 200 nm, about 80 nm to 200 nm, about 90 nm to 200 nm, or about 100 nm to 200 nm.
[0113] 1, the top surface of the ruthenium film 30 is planarized to form the ruthenium film 30 buried in the trench 21. The top surface of the ruthenium film 30 may be planarized by, for example, chemical mechanical polishing (CMP), but is not limited to this.
[0114] Another example of the method for manufacturing an interconnect structure according to an embodiment will be described below.
[0115] 6 to 9 are schematic views showing another example of a method for manufacturing an interconnect structure according to an embodiment.
[0116] An example of a method for manufacturing an interconnect structure according to one embodiment includes forming a ruthenium deposit 30a on the lower film 10, further annealing the ruthenium deposit 30a to form a ruthenium film 30, and patterning the ruthenium film 30.
[0117] 6, a ruthenium deposit 30a is formed on the lower film 10. The ruthenium deposit 30a can be formed by, for example, atomic layer deposition or chemical vapor deposition.
[0118] As described above, atomic layer deposition or chemical vapor deposition can be carried out at a temperature of about 550°C or less at about 10 Torr or less, or at about 500°C or less or about 450°C or less within the above range, and can be carried out at about 220°C to 550°C, about 220°C to 500°C, about 220°C to 450°C, about 250°C to 550°C, about 250°C to 500°C, about 250°C to 450°C, about 300°C to 550°C, about 300°C to 500°C, about 300°C to 450°C, about 350°C to 550°C, about 350°C to 500°C, or about 350°C to 450°C within the above range.
[0119] Atomic layer deposition or chemical vapor deposition can form a ruthenium deposit 30a of a desired thickness by performing one or more cycles of supplying a ruthenium precursor, performing a first purge, supplying at least one of an oxidizing agent and a reducing agent as co-reactants and an inert gas, and performing a second purge. As described above, the carbon content in the ruthenium deposit 30a can be controlled by adjusting the substrate temperature, pressure, and / or co-reactant partial pressure (e.g., oxygen partial pressure) during deposition. For example, the carbon content can be reduced by increasing the substrate temperature, decreasing the deposition pressure, and / or decreasing the co-reactant partial pressure (e.g., oxygen partial pressure). Details of this process are as described above.
[0120] 7, the ruthenium deposit 30a is further annealed to form a ruthenium film 30. Annealing can be performed at a temperature of about 550°C or less, and within the above range, can be about 500°C or less or about 450°C or less, and within the above range, can be performed at about 220°C to 550°C, about 220°C to 500°C, about 220°C to 450°C, about 250°C to 550°C, about 250°C to 500°C, about 250°C to 450°C, about 300°C to 550°C, about 300°C to 500°C, about 300°C to 450°C, about 350°C to 550°C, about 350°C to 500°C, or about 350°C to 450°C. As described above, annealing can cause the carbon content in the ruthenium film 30 to be lower than the carbon content in the ruthenium deposit 30a, the ruthenium film 30 to have stronger vertical and horizontal crystal orientation than the ruthenium deposit 30a, and the crystal grain size of the ruthenium film 30 to be larger than the crystal grain size of the ruthenium deposit 30a, as detailed above.
[0121] Referring to FIG. 8, an etching mask (EM) is placed on the ruthenium film 30 .
[0122] 9, the ruthenium film 30 is etched and patterned using an etching mask (EM). The etching may be, for example, but is not limited to, dry etching using plasma. The etching mask (EM) is then removed.
[0123] The line width of the patterned ruthenium film 30 may be less than about 20 nm, for example, about 18 nm or less, about 15 nm or less, about 12 nm or less, about 10 nm or less, for example, about 9 nm or less, about 8 nm or less, about 7 nm or less, about 6 nm or less, about 5 nm or less, about 4 nm or less, or about 3 nm or less, and within the above range, it may be about 1 nm or more but less than 20 nm, about 1 nm to 18 nm, about 1 nm to 15 nm, about 1 nm to 12 nm, about 1 nm to 10 nm, about 1 nm to 9 nm, about 1 nm to 8 nm, about 1 nm to 7 nm, about 1 nm to 6 nm, about 1 nm to 5 nm, about 1 nm to 4 nm, or about 1 nm to 3 nm.
[0124] Referring to FIG. 1, a dielectric layer 20 can be formed to surround the patterned ruthenium layer 30, for example, by a gapfill method that fills the gap between adjacent patterned ruthenium layers 20, but is not limited thereto.
[0125] An example of an integrated circuit device including the above-described interconnect structure will now be described, which may be, but is not limited to, a DRAM or a 3D logic device.
[0126] An integrated circuit device according to one embodiment includes a semiconductor substrate, circuit elements integrated into or located above the semiconductor substrate, and vias or interconnects electrically coupled to the circuit elements.
[0127] The semiconductor substrate may include, for example, a Group IV semiconductor material, a Group III-V semiconductor compound, or a Group II-VI semiconductor compound, such as a Group IV semiconductor material containing at least one of Si, Ge, Sn, and C, a Group III-V compound semiconductor material in which at least one of B, Ga, In, and Al is combined with at least one of N, P, As, and Sb, or a Group II-VI compound semiconductor material in which at least one of Be, Mg, Cd, and Zn is combined with at least one of O, S, Se, and Te. For example, the semiconductor substrate may include, but is not limited to, Si, Ge, SiC, SiGe, SiGeC, a Ge alloy, GaAs, InAs, and InP.
[0128] The circuit elements may include transistors, capacitors, diodes, or resistors, or combinations thereof, and the ruthenium film 30 of the interconnect structure 100 described above may be applied to wiring (e.g., bit lines, word lines, etc.) electrically connected to one or more of these circuit elements and / or wiring or vias of a BEOL (back end of line) structure.
[0129] For example, the transistor may have a variety of structures, such as, but not limited to, a FinFET, a GAAFET, an MBCFET, a CFET, or a VFET. For example, the transistor may be, but not limited to, a complementary field effect transistor (C-FET), a multi-bridge channel field effect transistor (MBC-FET), or a carbon nanotube field effect transistor (CNT-FET).
[0130] FIG. 10 is a cross-sectional view showing a three-dimensional logic element, which is an example of an integrated circuit element according to an embodiment.
[0131] In FIG. 10, the upper dielectric film 120, upper via 111, and upper wiring 112 shown by dotted lines may be a BEOL structure, and the BEOL structure will be described as an example of a structure electrically connected to a circuit element (e.g., a transistor) of a 3D logic device shown by solid lines below it.
[0132] The upper via 111 and / or upper interconnection 112 in the BEOL structure may be the above-described ruthenium film 30, and the upper dielectric film 120 may be the above-described dielectric film 20 surrounding the upper via 111 and / or upper interconnection 112. The ruthenium film 30 and the dielectric film 20 have been described above. The upper via 111 and / or upper interconnection 112 in the BEOL structure may be electrically connected to an upper contact layer 221 (active region) formed in the intermediate dielectric film 220, and the upper contact layer 221 may be the above-described lower film 10. Another interconnection (not shown) electrically connected to the upper interconnection 112 may be disposed on the upper interconnection 112.
[0133] An upper source or drain electrode 222 is disposed below the upper contact layer 221 in the intermediate dielectric film 220, and a lower source or drain electrode 223 is disposed facing the upper source or drain electrode 222 with the intermediate dielectric film 220 interposed therebetween. A lower contact layer 224 (active region) is disposed below the lower source or drain electrode 223, and the lower contact layer 224 is electrically connected to a lower via 231 and / or a lower wiring 232 formed in the lower dielectric film 230. A through contact 225 is formed in the intermediate dielectric film 220.
[0134] Although the above description has been given using a 3D logic device as an example of an integrated circuit device, the present invention is not limited thereto and may be applied to any integrated circuit device including narrow vias and / or wiring, such as an integrated circuit device that can be used for arithmetic operations, program execution, and / or temporary data storage.
[0135] The above-described interconnect structures and / or integrated circuit elements may be included in a variety of electronic devices, including, but not limited to, mobile devices, computers, laptops, tablet PCs, smart watches, sensors, digital cameras, e-books, network devices, vehicle navigation systems, Internet of Things devices (IoT), Internet of Everything devices (IoE), drones, door locks, safes, automated teller machines (ATMs), security devices, medical devices, or automotive electronics components.
[0136] FIG. 11 is a conceptual diagram illustrating an example of an electronic device according to an embodiment.
[0137] 11 , an electronic device 3100 according to an embodiment may include a memory unit 3110, an arithmetic logic unit 3120, and a control unit 3130, which may be electrically connected to one another. For example, the memory unit 3110, the arithmetic logic unit 3120, and the control unit 3130 may be implemented as a single integrated circuit device, e.g., monolithically integrated on a single substrate and implemented as a single semiconductor chip. The memory unit 3110, the arithmetic logic unit 3120, and the control unit 3130 may each independently include transistors, capacitors, diodes, or resistors, or a combination thereof. The electronic device 3100 may be connected to one or more input / output devices 3200.
[0138] The above-described embodiments will be described in more detail with reference to the following examples, which are provided for illustrative purposes only and are not intended to limit the scope of the present invention.
[0139] <Ruthenium film formation I> [Example 1] A silicon wafer coated with a 100 nm thick amorphous silicon oxide film was placed in the chamber (1 Torr or less) of a showerhead atomic layer deposition system as a substrate (substrate temperature: 270°C). Ruthenium precursors, tricarbonyl(trimethylenemethane)ruthenium (Ru(TMM)(CO)3) and bis(ethylcyclopentadienyl)ruthenium(II) (RuEtCP2), were injected. Argon gas was then introduced into the chamber for the first purge. Argon gas and oxygen gas (O2) were then introduced at a volume ratio of 9:1 (partial pressure ratio of oxygen gas to argon gas: 0.1). Argon gas was then introduced for the second purge. This process is repeated once to form a monolayer of ruthenium deposit with a thickness of about 1 to 2 Å. This process is repeated several times to form a monolayer of ruthenium deposit with a thickness of about 10 nm.
[0140] Next, the silicon wafer on which the ruthenium deposition was formed is removed from the chamber and placed in a rapid thermal process (RTP) device where it is annealed at 450° C. for 20 minutes in a vacuum atmosphere to form a ruthenium film.
[0141] [Example 2] A ruthenium film is formed in the same manner as in Example 1, except that the substrate temperature is changed to 300°C.
[0142] [Example 3] A ruthenium film is formed in the same manner as in Example 1, except that the substrate temperature is changed to 325°C.
[0143] [Example 4] A ruthenium film is formed in the same manner as in Example 1, except that the substrate temperature is changed to 365°C.
[0144] [Reference example 1] A ruthenium film is formed in the same manner as in Example 1, except that the substrate temperature is changed to 210°C.
[0145] [Reference example 2] An amorphous silicon oxide-coated silicon wafer (substrate temperature: 300°C) is placed in a sputtering chamber (1 Torr or less) facing a ruthenium target (pure Ru target), and sputtering is performed for approximately 60 seconds to form a ruthenium deposit approximately 10 nm thick. The silicon wafer with the ruthenium deposit formed is then removed from the chamber and placed in rapid thermal processing (RTP) equipment, where it is annealed at 450°C for 20 minutes in a vacuum atmosphere to form a ruthenium film.
[0146] <Rating I> The carbon contents in the ruthenium deposits (before annealing) and the ruthenium films (after annealing) of the Examples and Reference Examples are evaluated.
[0147] The carbon content in the ruthenium deposit and the ruthenium film is analyzed using a quad secondary ion mass spectroscopy (SIMS) device with Ru as the standard reference material.
[0148] The results are shown in Table 1.
[0149] [Table 1]
[0150] <Evaluation II> The carbon distribution in the ruthenium deposit (before annealing) and the ruthenium film (after annealing) according to the example will be confirmed.
[0151] The carbon distribution in the ruthenium film is evaluated from atom probe tomography (APT) images.
[0152] FIG. 12 is an atom probe tomography (APT) image showing the carbon distribution in the ruthenium deposit (before annealing) according to Example 2, FIG. 13 is a graph showing the carbon concentration at different positions in the ruthenium deposit in the APT image of FIG. 12, FIG. 14 is an APT image showing the carbon distribution in the ruthenium film (after annealing) according to Example 2, and FIG. 15 is a graph showing the carbon concentration at different positions in the ruthenium deposit in the APT image of FIG. 14.
[0153] In Figures 12 and 14, dotted lines indicate grain boundaries.
[0154] 12 to 15, it can be seen that carbon is distributed mainly along the grain boundaries of the ruthenium deposit and the ruthenium film, and that a considerable amount of carbon is released from the ruthenium deposit during the annealing step, resulting in a decrease in the carbon content after annealing. Furthermore, it can be seen that the grain boundaries move along with the release of carbon distributed along the grain boundaries during the annealing step, thereby expanding the grains and increasing their size.
[0155] <Evaluation III> The crystal orientation of the ruthenium deposit (before annealing) and the ruthenium film (after annealing) in the examples and reference examples will be confirmed.
[0156] The crystal orientation is evaluated from transmission electron microscopy (TEM) and precession electron diffraction (PED) orientation maps obtained using PED orientation microscopy.
[0157] The results are shown in Figures 16a to 20b and Table 2.
[0158] Figures 16a and 16b are PED orientation maps along the z-axis direction of the ruthenium deposit and ruthenium film, respectively, according to Example 1. Figures 17a and 17b are PED orientation maps along the z-axis direction (the direction perpendicular to the substrate surface) of the ruthenium deposit and ruthenium film, respectively, according to Example 2. Figures 18a and 18b are PED orientation maps along the z-axis direction of the ruthenium deposit and ruthenium film, respectively, according to Example 3. Figures 19a and 19b are PED orientation maps along the z-axis direction of the ruthenium deposit and ruthenium film, respectively, according to Example 4. Figures 20a and 20b are PED orientation maps along the z-axis direction of the ruthenium deposit and ruthenium film, respectively, according to Reference Example 1. The size of each PED orientation map in Figures 16a to 20b is approximately 500 nm by approximately 500 nm.
[0159] In Figures 16a to 20b, the colors correspond to crystallographic orientations, e.g. <001> Orientation is red, <100> Orientation is blue, <210> The orientation is shown in green. The scale bar for the PED orientation map of the ruthenium deposit is 30 nm, and the scale bar for the PED orientation map of the ruthenium film is 100 nm.
[0160] [Table 2]
[0161] Referring to Table 2 and FIGS. 16a to 19b, in the ruthenium film according to the embodiment, most of the crystal grains are aligned in the direction perpendicular to the substrate surface (c-axis direction, <001> ) is strongly oriented to F 001 It can be confirmed that the percentage is about 70% or more (for example, about 80% or more or about 85% or more), and that there is a large change in the crystal orientation before and after annealing.
[0162] In contrast, referring to Table 2 and Figures 20a and 20b, it can be seen that the crystal grains of the ruthenium film according to Reference Example 1 have various crystal orientations, i.e., are randomly oriented, even after annealing, and that there is no significant change in the crystal orientation before and after annealing.
[0163] This confirms that the crystal orientation of the ruthenium film is affected by the initial carbon content and the final carbon content. For example, when the initial carbon content is about 1.50 at% or less and the final carbon content is less than about 0.30 at%, <001> It can be seen that the orientation appears predominant.
[0164] <Rating IV> The average crystal grain size of the ruthenium deposition (before annealing) and the ruthenium film (after annealing) in the examples and reference examples was confirmed.
[0165] The average grain size is estimated through the ASTAR™ orientation mapping methodology.
[0166] The results are shown in Table 3.
[0167] [Table 3]
[0168] Referring to Table 3, it can be seen that the ruthenium films according to the examples have an average crystal grain size that is about three times larger than that of the films according to the examples, and in particular, the ruthenium film according to Example 2 has large crystal grains of about 100 nm or larger, and shows the largest change in average crystal grain size before and after annealing. In contrast, it can be seen that the ruthenium film according to Reference Example 1 does not show a large change in average crystal grain size before and after annealing.
[0169] This confirms that the grain size of the ruthenium film is affected by the initial carbon content and the final carbon content. For example, when the initial carbon content is about 1.50 at% or less and the final carbon content is less than about 0.30 at%, it is confirmed that relatively large grains of about 50 nm or more are formed.
[0170] <Rating V> The X-ray diffraction patterns (XRD) of the ruthenium deposits (before annealing) and the ruthenium films (after annealing) of the examples and reference examples are evaluated.
[0171] FIG. 21 shows XRD patterns of the ruthenium deposit and ruthenium film according to Example 2, measured at a normal angle. FIG. 22 shows XRD patterns of the ruthenium deposit and ruthenium film according to Reference Example 1, measured at a normal angle. FIG. 23 shows glancing angle incidence XRD patterns of the ruthenium deposit and ruthenium film according to Example 2, measured at a low glancing angle (0.5 degrees relative to the substrate surface). FIG. 24 shows glancing angle incidence XRD patterns of the ruthenium deposit and ruthenium film according to Reference Example 1, measured at a low glancing angle (0.5 degrees relative to the substrate surface).
[0172] In FIGS. 21 to 24, the gray lines are XRD patterns of the ruthenium deposit, and the red or green lines are XRD patterns of the ruthenium film.
[0173] 21 and 22, the ruthenium film according to Example 2 <001> The (002) peak (2θ = 42.3 degrees) corresponding to the ruthenium film orientation is predominantly observed, with the (100) peak (2θ = 38.5 degrees) and the (101) peak (2θ = 44.2 degrees) being substantially absent. However, the ruthenium film of Reference Example 1 exhibits significant amounts of (100) and (101) peaks in addition to the (002) peak. For example, in the XRD pattern of the ruthenium film of Example 2, the ratio of the (002) peak intensity to the (101) peak intensity may be greater than about 30:1. Furthermore, the ruthenium film of Example 2 (red line) exhibits a significantly increased (002) peak compared to the ruthenium deposit (gray line).
[0174] 23 and 24, the ruthenium film according to Example 2 shows no peaks in the range of approximately 30° to 70°, whereas the ruthenium film according to Reference Example 1 shows a considerable amount of (100), (110), and (102) peaks in addition to the (002) peak. For example, in the XRD pattern of the ruthenium film according to Example 2, the ratio of the intensity of the (002) peak to the total intensity of the (100), (110), and (102) peaks may be approximately 90% or more. It can also be seen that the ruthenium film according to Example 2 (red line) shows fewer peaks than the ruthenium deposit (gray line).
[0175] As a result, unlike the random orientation of the ruthenium film of Reference Example 1, the majority of the crystal grains (approximately 99% or more) of the ruthenium film of Example 2 <001> It can be seen that the orientation of the ruthenium film according to Example 2 was predominantly aligned in the direction of the ruthenium atoms. It can also be seen that the orientation of the ruthenium film according to Example 2 was further strengthened by annealing.
[0176] <Evaluation VI> The grain boundaries of the ruthenium films according to the example and comparative example will be evaluated.
[0177] The grain boundaries of the ruthenium film are evaluated using a transmission electron microscopy (TEM).
[0178] FIG. 25 is a TEM photograph showing the grain boundaries of the ruthenium film according to Example 2, and FIG. 26 is a TEM photograph showing the grain boundaries of the ruthenium film according to Reference Example 2.
[0179] 25, it can be seen that coincident lattice (CSL) grain boundaries such as Σ7, Σ19, and Σ31 and low angle CSL grain boundaries are predominantly present in the ruthenium film according to Example 2. In contrast, referring to FIG. 26, it can be seen that the ruthenium film according to Reference Example 2 has a considerable number of non-CSL grain boundaries, along with CSL grain boundaries including Σ13 boundaries.
[0180] Since the specific resistivity that occurs when current passes through the boundary between non-CSL grain boundaries is greater than that of CSL grain boundaries, it is expected that the resistance of ruthenium films made of CSL grain boundaries or wiring / vias containing them will be lower.
[0181] Therefore, it can be predicted that the ruthenium film according to Example 2 promotes the formation of base angle CSL lattice grain boundaries with lower grain boundary energy due to the release of carbon from the grain boundaries during the annealing process, thereby making it possible to achieve lower resistance.
[0182] <Evaluation VII> The vertical and horizontal crystal orientations of the ruthenium films in the examples and reference examples are confirmed.
[0183] The results are shown in Figures 27a to 29b.
[0184] Figures 27a and 27b are PED orientation maps of the ruthenium film according to Example 2 in the z-axis direction (direction perpendicular to the substrate surface) and the x-axis direction (direction parallel to the substrate surface), respectively; Figures 28a and 28b are PED orientation maps of the ruthenium film according to Reference Example 1 along the z-axis direction and the x-axis direction, respectively; and Figures 29a and 29b are PED orientation maps of the ruthenium film according to Reference Example 2 along the z-axis direction and the x-axis direction, respectively.
[0185] In Figures 27a to 29b, the colors correspond to the crystal orientation, e.g. <001> Orientation is red, <100> Orientation is blue, <210> The orientation is shown in green. The scale bar for the PED orientation map of the ruthenium film is 100 nm.
[0186] 27a and 27b, the ruthenium film according to Example 2 has a crystal grain structure in which most of the crystal grains are aligned in a direction perpendicular to the substrate surface (c-axis direction, <001> ) (Fig. 27a), while there is little misorientation between adjacent crystal grains aligned parallel to the substrate surface (Fig. 27b).
[0187] In contrast, referring to Figures 28a and 28b, it can be seen that the crystal grains of the ruthenium film according to Reference Example 1 have various crystal orientations, i.e., are randomly oriented. Also, referring to Figures 29a and 29b, it can be seen that the ruthenium film according to Reference Example 2 has a large misorientation between adjacent crystal grains aligned parallel to the substrate surface, and many very small crystal grains are distributed between the larger crystal grains, resulting in a large deviation in the size of the crystal grains.
[0188] <Rating VIII> The surface roughness of the ruthenium deposit and the ruthenium film in the examples and reference examples is evaluated.
[0189] The surface roughness is measured using an atomic force microscopy (AFM, Dimension Icon XR, Bruker Corporation) instrument in tapping mode.
[0190] The results are shown in Table 4.
[0191] [Table 4]
[0192] Referring to Table 4, it can be seen that the ruthenium films according to the Examples have smoother surfaces than the ruthenium films according to the Reference Examples, which suggests that the ruthenium films according to the Examples can effectively reduce electron surface scattering compared to the ruthenium films according to the Reference Examples.
[0193] <Rating IX> Ruthenium films according to the examples and reference examples are formed in various thicknesses (line widths) of 6 nm to 20 nm, and electrical characteristics depending on the thickness (line width) of the ruthenium film are evaluated.
[0194] The electrical properties of the ruthenium film are determined by measuring the sheet resistance using a four-point probe and the resistivity value using the film thickness measured by the TEM method.
[0195] The results are shown in Figure 30.
[0196] FIG. 30 is a graph showing the change in resistivity depending on the thickness (line width) of the ruthenium film in Example 2 and Reference Examples 1 and 2.
[0197] 30, it can be seen that the ruthenium film according to Example 2 has a smaller change in resistivity due to a decrease in line width compared to the ruthenium films according to Reference Examples 1 and 2. In particular, it can be seen that the resistivity of the ruthenium film according to Example 2 is significantly lower than that of the ruthenium films according to Reference Examples 1 and 2 at line widths of 10 nm or less.
[0198] This suggests that the ruthenium film according to Example 2 can prevent degradation of electrical characteristics without a sudden increase in resistance even when the line width is as fine as less than about 20 nm (about 15 nm or less or about 10 nm or less).
[0199] Although the embodiments have been described in detail above, the scope of the invention is not limited to these examples, and various modifications and improvements made by those skilled in the art using the basic concepts defined in the following claims also fall within the scope of the invention. (1) A method for manufacturing a ruthenium film, comprising: a lower film including a non-single-crystal material; and a ruthenium film located on the lower film and including a plurality of crystal grains, wherein the ruthenium film <001> The texturing coefficient (F 001 ) is about 0.70 to 1, and the average crystal grain size of the ruthenium film is about 50 nm to 200 nm. (2) The non-single crystalline material includes an amorphous conductor, a polycrystalline conductor, an amorphous semiconductor, a polycrystalline semiconductor, an amorphous dielectric, or a polycrystalline dielectric, or a combination thereof. (3) The interconnect structure may further include a dielectric film surrounding the ruthenium film. (4) The ratio of the intensity of the (002) peak to the intensity of the (101) peak observed in the X-ray diffraction pattern of the ruthenium film may be about 30:1 to 100:1. (5) The intensity of the (002) peak observed in the X-ray diffraction pattern of the ruthenium film may be about 90% to 100% of the total intensity of the (100), (101) and (002) peaks. (6) The misorientation angle of the grain boundaries between adjacent crystal grains of the ruthenium film may be 0 to 15 degrees with respect to the horizontal direction of the ruthenium film. (7) Each grain boundary between adjacent grains of the ruthenium film may have a coincident position lattice. (8) The ruthenium film may have an average surface roughness of more than 0 and less than about 1.0 nm. (9) The ruthenium film may contain carbon in an amount of about 0.01 to less than 0.30 at %. (10) The carbon may be distributed along grain boundaries between adjacent grains. (11) The ruthenium film <001> The texturing coefficient (F 001 ) can be about 0.95 to 1. (12) The average crystal grain size of the ruthenium film may be about 80 nm to 200 nm. (13) The average crystal grain size of the ruthenium film may be approximately 55 nm to 115 nm. (14) The line width of the ruthenium film may be greater than or equal to about 1 nm and less than 20 nm. (15) A method for manufacturing a ruthenium film, comprising: supplying a ruthenium precursor onto a lower film including a non-single crystalline material to form a ruthenium deposit; and further annealing the ruthenium deposit to form a ruthenium film, <001> The texturing coefficient (F 001 ) is 0.70 to 1, and the average crystal grain size of the ruthenium film is about 50 nm to 200 nm. (16) The steps of forming the ruthenium deposit and additionally annealing the ruthenium deposit may be performed at about 200°C to 550°C, respectively. (17) The ruthenium film may contain carbon in an amount of about 0.01 to less than 0.30 at %. (18) The ruthenium deposit may contain more carbon than the ruthenium film. (19) The ruthenium deposit may contain about 0.10 to 1.50 at % carbon. (20) The ruthenium deposition <001> The area percentage of the grains aligned in the direction may be less than about 60%. (21) The average grain size of the ruthenium deposit may be greater than or equal to about 1 nm and less than 20 nm. (22) At least one of an oxidizing agent and a reducing agent and an inert gas may be supplied during or after the step of supplying the ruthenium precursor. (23) The oxidizing agent may include oxygen, ozone, water, or plasma species derived therefrom, and the reducing agent may include hydrogen gas, ammonia gas, or plasma activated species derived therefrom. (24) The partial pressure ratio of at least one of the oxidizing agent and the reducing agent to the inert gas may be about 0.05 to 1. (25) The step of supplying the ruthenium precursor may be discontinuously supplied 1 to 10 times. (26) A semiconductor device comprising: a semiconductor substrate; a circuit element integrated in or located on the semiconductor substrate; and wiring electrically connected to the circuit element and including a ruthenium film including a plurality of crystal grains, wherein the ruthenium film <001> The texturing coefficient (F 001 ) is 0.70 to 1, and the average crystal grain size of the ruthenium film is about 50 nm to 200 nm. (27) The integrated circuit device may further include a lower film located below the wiring and including a non-single-crystalline material, and the lower film may include an amorphous conductor, a polycrystalline conductor, an amorphous semiconductor, a polycrystalline semiconductor, an amorphous dielectric, a polycrystalline dielectric, or a combination thereof. (28) The integrated circuit element may further include a dielectric film surrounding the wiring. (29) The ruthenium film may contain carbon in an amount of about 0.01 at % or more and less than 0.30 at %. (30) The misorientation angle of the grain boundaries between adjacent grains of the ruthenium film may be 0 degrees to about 15 degrees with respect to the horizontal direction of the ruthenium film, or the grain boundaries between adjacent grains of the ruthenium film may have a coincidence site lattice. (31) The ruthenium film may have an average surface roughness of more than 0 and less than about 1.0 nm. (32) The line width of the ruthenium film may be equal to or greater than 1 nm and less than 20 nm. (33) A method for fabricating a semiconductor device comprising: a semiconductor substrate; a circuit element integrated in or located on the semiconductor substrate; a dielectric film located on the circuit element and having a trench; and a ruthenium film located in the trench, wherein the ruthenium film comprises: <001> The ruthenium film includes a majority of oriented crystal grains, and the misorientation angle of the grain boundaries between adjacent crystal grains in the ruthenium film is 0 to 15 degrees based on the horizontal direction of the ruthenium film, or the grain boundaries between adjacent crystal grains in the ruthenium film have a coincidence site lattice. (34) The ruthenium film <001> The texturing coefficient (F 001 ) can be about 0.95 to 1. (35) The average crystal grain size of the ruthenium film may be about 80 nm to 200 nm. (36) The ruthenium film may have an average surface roughness of more than 0 and less than about 1.0 nm. (37) The average crystal grain size of the ruthenium film may be about 80 nm to 200 nm. (38) The average crystal grain size of the ruthenium film may be about 80 nm to 200 nm. (39) The linewidth of the ruthenium film may be less than about 20 nm. (40) The ruthenium film may have a depth to linewidth ratio of about 3 to 50. (41) The resistivity of the ruthenium film may be about 15 μΩ·cm or less. (42) The ruthenium film may be located on an underlying film exposed through the via hole, and the underlying film may include an amorphous conductor, a polycrystalline conductor, an amorphous semiconductor, a polycrystalline semiconductor, an amorphous dielectric, or a polycrystalline dielectric, or a combination thereof. [Explanation of symbols]
[0200] 10: Lower membrane 20: Dielectric film 30: Ruthenium film 30a: Ruthenium deposit 111: Top via 112: Upper wiring 120: Upper dielectric film 220: Intermediate dielectric film 221: Upper contact layer 222: Upper source or drain electrode 223: Lower source or drain electrode 224: Lower contact layer 230: Lower dielectric film 231: Bottom via 232: Lower wiring
Claims
1. a lower film including a non-single crystalline material; a ruthenium film disposed on the lower film and including a plurality of crystal grains; Including, The texturing coefficient (F 001 ) is 0.70 to 1, the average crystal grain size of the ruthenium film is 50 nm to 200 nm; Interconnect structures.
2. 10. The interconnect structure of claim 1, wherein the non-single crystalline material comprises an amorphous conductor, a polycrystalline conductor, an amorphous semiconductor, a polycrystalline semiconductor, an amorphous dielectric, or a polycrystalline dielectric, or a combination thereof.
3. 10. The interconnect structure of claim 1, further comprising a dielectric film surrounding said ruthenium film.
4. 4. The interconnect structure according to claim 1, wherein the ratio of the intensity of the (002) peak to the intensity of the (101) peak observed in the X-ray diffraction pattern of the ruthenium film is 30:1 to 100:
1.
5. 4. The interconnect structure according to claim 1, wherein the intensity of the (002) peak observed in the X-ray diffraction pattern of the ruthenium film is 90% to 100% of the sum of the intensities of the (100), (101) and (002) peaks.
6. 4. The interconnect structure according to claim 1, wherein a misorientation angle of a grain boundary between adjacent crystal grains of the ruthenium film is 0 to 15 degrees with respect to a horizontal direction of the ruthenium film.
7. 4. The interconnect structure of claim 1, wherein each grain boundary between adjacent grains of the ruthenium film has a coincidence site lattice.
8. 4. The interconnect structure according to claim 1, wherein the average surface roughness of the ruthenium film is greater than 0 and less than 1.0 nm.
9. 4. The interconnect structure according to claim 1, wherein the ruthenium film contains 0.01 at % or more and less than 0.30 at % of carbon.
10. 10. The interconnect structure of claim 9, wherein the carbon is distributed along grain boundaries between adjacent grains of the ruthenium film.
11. the texturing coefficient (F001) of the crystal grains having a <001> orientation in the ruthenium film is 0.95 to 1; the average crystal grain size of the ruthenium film is 80 nm to 200 nm; The interconnect structure according to any one of claims 1 to 3.
12. 4. The interconnect structure according to claim 1, wherein the line width of the ruthenium film is equal to or greater than 1 nm and less than 20 nm.
13. a semiconductor substrate; circuit elements integrated into or located on said semiconductor substrate; a wiring electrically connected to the circuit element and including a ruthenium film including a plurality of crystal grains; Including, the texturing coefficient (F001) of the crystal grains having a <001> orientation in the ruthenium film is 0.70 to 1; the average crystal grain size of the ruthenium film is 50 nm to 200 nm; Integrated circuit element.
14. The wiring further includes a lower layer including a non-single crystalline material, the lower layer being located under the wiring, 14. The integrated circuit device of claim 13, wherein the underlying film comprises an amorphous conductor, a polycrystalline conductor, an amorphous semiconductor, a polycrystalline semiconductor, an amorphous dielectric, or a polycrystalline dielectric, or a combination thereof.
15. 14. The integrated circuit element according to claim 13, wherein the ruthenium film contains 0.01 to less than 0.30 atomic percent carbon.
16. 16. The integrated circuit device according to claim 13, wherein a misorientation angle of a grain boundary between adjacent crystal grains of the ruthenium film is 0 to 15 degrees with respect to a horizontal direction of the ruthenium film, or each grain boundary between adjacent crystal grains of the ruthenium film has a coincidence site lattice.
17. 16. The integrated circuit element according to claim 13, wherein the average surface roughness of the ruthenium film is greater than 0 and less than 1.0 nm.
18. 16. The integrated circuit element according to claim 13, wherein the line width of the ruthenium film is equal to or greater than 1 nm and less than 20 nm.
19. a semiconductor substrate; circuit elements integrated into or located on said semiconductor substrate; a dielectric film overlying the circuit element and having a trench; a ruthenium film located in the trench; Including, the ruthenium film contains the most crystal grains having a <001> orientation; An integrated circuit device, wherein a misorientation angle of a grain boundary between adjacent crystal grains of the ruthenium film is 0 degrees to 15 degrees based on a horizontal direction of the ruthenium film, or each grain boundary between adjacent crystal grains of the ruthenium film has a coincidence site lattice.
20. the texturing coefficient (F001) of the crystal grains having a <001> orientation in the ruthenium film is 0.95 to 1; the average crystal grain size of the ruthenium film is 80 nm to 200 nm; The average surface roughness of the ruthenium film is greater than 0 and less than 1.0 nm.
20. The integrated circuit device of claim 19.