Ceramic electronic component and method of manufacturing the same

Abstract

To provide a ceramic electronic component capable of improving moisture resistance while suppressing ESR, and to provide a method of manufacturing the same.SOLUTION: A ceramic electronic component includes a multilayer structure in which a plurality of dielectric layers mainly composed of ceramic and a plurality of internal electrode layers are alternately stacked in a stacking direction. The plurality of internal electrode layers include a first internal electrode layer at one end in the laminating direction, a second internal electrode layer at a center in the laminating direction, and a third internal electrode layer between the first internal electrode layer and the second internal electrode layer. The first internal electrode layer, the second internal electrode layer, and the third internal electrode layer include Ni and Sn. The first internal electrode layer, the second internal electrode layer, and the third internal electrode layer include Sn at a center in a first direction orthogonal or substantially orthogonal to the lamination direction. The Sn concentration of the third internal electrode layer is higher than that of the second internal electrode layer.SELECTED DRAWING: Figure 4

Description

[Technical Field]

[0001] The present invention relates to a ceramic electronic component and a method for manufacturing the same. [Background technology]

[0002] As electronic devices become smaller, further miniaturization is also required for ceramic electronic components such as multilayer ceramic capacitors used in electronic devices. To increase the capacitance, which is a basic characteristic, there are three possible methods: (1) increasing the dielectric constant of the dielectric layer, (2) increasing the capacitance-specified area, or (3) making the dielectric layer thinner. When the dielectric constant and element size are fixed, thinner dielectric layers can increase the capacitance per layer. In addition, by making the dielectric layers and internal electrode layers thinner, it is possible to increase the number of layers to be stacked within a given thickness, which is advantageous. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Laid-Open No. 2007-258646 Summary of the Invention [Problem to be solved by the invention]

[0004] However, thinning the internal electrode layers makes them more susceptible to fracture during the firing process. When moisture from the external environment penetrates into the fractured areas and reaches the functional area, problems such as poor insulation occur. Thinner dielectric layers further accelerate these problems. Patent Document 1 describes a method for making the internal electrode layers less susceptible to fracture by adjusting the proportions of nickel (Ni) paste and co-materials added to form the internal electrode layers, as well as the particle size. By placing the fracture-resistant internal electrode layers as the outermost layers in the stacking direction, moisture penetration from the outside is prevented, improving moisture resistance. However, as the internal electrode layers become thinner, the above method becomes insufficient, and other measures become necessary.

[0005] One solution is to add tin (Sn) to the internal electrode layers. However, although adding Sn to the internal electrode layers improves moisture resistance, it also increases the ESR (equivalent series resistance).

[0006] The present invention has been made in view of the above-mentioned problems, and has an object to provide a ceramic electronic component that can improve moisture resistance while suppressing ESR, and a method for manufacturing the same. [Means for solving the problem]

[0007] A ceramic electronic component according to the present invention has a laminated structure in which a plurality of dielectric layers containing ceramic as a main component and three or more internal electrode layers are alternately laminated, the three or more internal electrode layers containing Ni and Sn, and at least two of the three or more internal electrode layers have a higher Sn concentration in the internal electrode layer at an end of the stacking direction than in the internal electrode layer at a center of the stacking direction.

[0008] The ceramic electronic component may have an inner electrode layer at the center in the lamination direction to an inner electrode layer at the outermost end in the lamination direction, the inner electrode layer at the outermost end having the highest Sn concentration.

[0009] In the ceramic electronic component, the Sn concentration of each of the plurality of internal electrode layers from the outermost end toward the center in the stacking direction may be higher than the Sn concentration of each of the remaining internal electrode layers toward the center in the stacking direction.

[0010] In the ceramic electronic component, the Sn concentration of each internal electrode layer from the internal electrode layer at the center in the stacking direction to the internal electrode layer at the end of the stacking direction may increase stepwise or gradually from the internal electrode layer at the center in the stacking direction to the internal electrode layer at the end of the stacking direction.

[0011] In the ceramic electronic component, the three or more internal electrode layers may have a thickness of 1 μm or less.

[0012] In the three or more internal electrode layers of the ceramic electronic component, the Sn concentration may be 10 at % or less.

[0013] In the three or more internal electrode layers of the ceramic electronic component, the Sn concentration may be 0.1 at % or more.

[0014] In the ceramic electronic component, the ratio of the maximum Sn concentration to the minimum Sn concentration in each of the three or more internal electrode layers may be greater than 1 and 100 or less.

[0015] In the internal electrode layer of the ceramic electronic component, the concentration of Sn may be higher in the vicinity of the interface with the dielectric layer than in the center in the thickness direction.

[0016] A method for manufacturing a ceramic electronic component according to the present invention includes the steps of forming a laminate unit by forming an internal electrode pattern containing Ni and Sn on a dielectric green sheet, forming a laminate by stacking three or more of the laminate units, and firing the laminate, and is characterized in that, in at least two layers of the internal electrode patterns before firing, the Sn concentration of the internal electrode patterns on the ends of the lamination direction is made higher than that of the internal electrode patterns on the center side of the lamination direction. [Effects of the Invention]

[0017] According to the present invention, it is possible to provide a ceramic electronic component that can suppress ESR while improving moisture resistance, and a method for manufacturing the same. [Brief explanation of the drawings]

[0018] [Figure 1] FIG. 2 is a partial cross-sectional perspective view of a multilayer ceramic capacitor. [Figure 2] FIG. 2 is a cross-sectional view taken along line AA in FIG. [Figure 3] FIG. 2 is a cross-sectional view taken along line BB in FIG. [Figure 4] 10(a) and 10(b) are diagrams illustrating the Sn concentration. [Figure 5] FIG. 10 is a diagram illustrating an example of Sn concentration. [Figure 6] FIG. 10 is a diagram illustrating an example of the Sn concentration in an internal electrode layer. [Figure 7] 1A to 1C are diagrams illustrating a flow of a method for manufacturing a multilayer ceramic capacitor. [Figure 8] 1(a) and 1(b) are diagrams illustrating the lamination process. DETAILED DESCRIPTION OF THE INVENTION

[0019] Hereinafter, embodiments will be described with reference to the drawings.

[0020] (Embodiment) FIG. 1 is a partial cross-sectional perspective view of a multilayer ceramic capacitor 100 according to an embodiment. FIG. 2 is a cross-sectional view taken along line AA in FIG. 1. FIG. 3 is a cross-sectional view taken along line BB in FIG. 1. As illustrated in FIGS. 1 to 3, the multilayer ceramic capacitor 100 includes a laminated chip 10 having a substantially rectangular parallelepiped shape and external electrodes 20a, 20b provided on two opposing end faces of the laminated chip 10. Of the four faces of the laminated chip 10 other than the two end faces, the two faces other than the top and bottom faces in the stacking direction are referred to as side faces. The external electrodes 20a, 20b extend on the top, bottom and two side faces of the laminated chip 10 in the stacking direction. However, the external electrodes 20a, 20b are spaced apart from each other.

[0021] The multilayer chip 10 has a configuration in which dielectric layers 11 containing a ceramic material that functions as a dielectric and three or more internal electrode layers 12 containing a base metal material are alternately stacked. The edges of each internal electrode layer 12 are alternately exposed at the end face of the multilayer chip 10 where the external electrode 20a is provided and the end face where the external electrode 20b is provided. As a result, each internal electrode layer 12 is alternately electrically connected to the external electrode 20a and the external electrode 20b. As a result, the multilayer ceramic capacitor 100 has a configuration in which multiple dielectric layers 11 are stacked with the internal electrode layers 12 interposed therebetween. In addition, in the laminate of the dielectric layers 11 and the internal electrode layers 12, the internal electrode layer 12 is arranged as the outermost layer in the stacking direction, and the upper and lower surfaces of the laminate are covered by cover layers 13. The cover layers 13 are primarily composed of a ceramic material. For example, the material of the cover layers 13 may have the same primary ceramic component as the dielectric layers 11.

[0022] The size of the multilayer ceramic capacitor 100 is, for example, 0.25 mm in length, 0.125 mm in width, and 0.125 mm in height, or 0.4 mm in length, 0.2 mm in width, and 0.2 mm in height, or 0.6 mm in length, 0.3 mm in width, and 0.3 mm in height, or 1.0 mm in length, 0.5 mm in width, and 0.5 mm in height, or 3.2 mm in length, 1.6 mm in width, and 1.6 mm in height, or 4.5 mm in length, 3.2 mm in width, and 2.5 mm in height, but is not limited to these sizes.

[0023] The dielectric layer 11 is mainly composed of a ceramic material having a perovskite structure represented by the general formula ABO3. 3-α For example, the ceramic material includes BaTiO3 (barium titanate), CaZrO3 (calcium zirconate), CaTiO3 (calcium titanate), SrTiO3 (strontium titanate), BaTiO3 (barium titanate) which forms a perovskite structure, 1-x-y Ca x Sr y Ti 1-z Zr zO3 (0≦x≦1, 0≦y≦1, 0≦z≦1), etc., can be used. The thickness of each dielectric layer 11 is, for example, 0.05 μm or more and 5 μm or less, or 0.1 μm or more and 3 μm or less, or 0.2 μm or more and 1 μm or less.

[0024] 2, the region where the internal electrode layer 12 connected to the external electrode 20a and the internal electrode layer 12 connected to the external electrode 20b face each other is a region where capacitance is generated in the multilayer ceramic capacitor 100. Therefore, this region where capacitance is generated is referred to as a capacitance region 14. In other words, the capacitance region 14 is a region where adjacent internal electrode layers 12 connected to different external electrodes face each other.

[0025] The region where the internal electrode layers 12 connected to the external electrode 20a face each other without an internal electrode layer 12 connected to the external electrode 20b interposed therebetween is called the end margin 15. The region where the internal electrode layers 12 connected to the external electrode 20b face each other without an internal electrode layer 12 connected to the external electrode 20a interposed therebetween is also the end margin 15. In other words, the end margin 15 is the region where the internal electrode layers 12 connected to the same external electrode face each other without an internal electrode layer 12 connected to a different external electrode interposed therebetween. The end margin 15 is a region where no capacitance is generated.

[0026] 3, in the laminated chip 10, the regions extending from the two side surfaces of the laminated chip 10 to the internal electrode layers 12 are referred to as side margins 16. In other words, the side margins 16 are regions provided so as to cover the ends of the multiple internal electrode layers 12 stacked in the above-mentioned laminated structure, which extend to the two side surfaces. The side margins 16 are also regions that do not generate electrical capacitance.

[0027] All the internal electrode layers 12 contain Ni and Sn. For example, each internal electrode layer 12 is mainly composed of Ni and also contains Sn. When the internal electrode layers 12 contain Ni and Sn, the moisture resistance of the multilayer ceramic capacitor 100 can be improved. For example, it is believed that alloying of Ni and Sn changes the state of the interface between the internal electrode layer 12 and the dielectric layer 11, thereby improving the moisture resistance of the multilayer ceramic capacitor 100.

[0028] However, if the internal electrode layers 12 contain Sn in addition to Ni, the electrical resistance of the internal electrode layers 12 may increase. As a result, the ESR of the entire multilayer ceramic capacitor 100 may increase. Therefore, the multilayer ceramic capacitor 100 according to this embodiment has a configuration that improves moisture resistance while suppressing the ESR.

[0029] Through extensive research, the inventors have found that the shorter the distance from the external environment to the multilayer ceramic capacitor 100, the more easily moisture penetrates. Therefore, the multilayer ceramic capacitor 100 according to this embodiment has a configuration in which, for at least two layers in the range from the central internal electrode layer 12 in the stacking direction to the internal electrode layer 12 at the end of the stacking direction, the internal electrode layer 12 with a higher Sn concentration is arranged closer to the end of the stacking direction than the internal electrode layer 12 with a lower Sn concentration. This configuration increases the Sn concentration of the internal electrode layer 12, which is closer to the external environment and thus more susceptible to moisture penetration. This enhances the effect of improving the moisture resistance of the multilayer ceramic capacitor 100. Furthermore, since the Sn concentration of the internal electrode layer 12, which is farther from the external environment and thus less susceptible to moisture penetration, is low, the ESR can be suppressed while suppressing a decrease in the moisture resistance of the multilayer ceramic capacitor 100. From the above, the moisture resistance of the multilayer ceramic capacitor 100 can be improved while suppressing the ESR. Note that if the number of stacked internal electrode layers 12 is even, the central internal electrode layer in the stacking direction refers to the two central internal electrode layers in the stacking direction. If the number of stacked internal electrode layers 12 is odd, the internal electrode layer at the center in the stacking direction refers to one internal electrode layer at the center in the stacking direction.

[0030] For example, as illustrated in Fig. 4(a), it is preferable that the Sn concentration of the inner electrode layer 12 at the end of the stacking direction is the highest from the inner electrode layer 12 at the center of the stacking direction to the inner electrode layer 12 at the outermost end of the stacking direction. In this configuration, the Sn concentration of the inner electrode layer 12 that is closest to the external environment is the highest, which enhances the effect of improving the moisture resistance of the multilayer ceramic capacitor 100. In Fig. 4(a), the inner electrode layer 12 at the outermost end of the stacking direction is depicted in black to indicate that the Sn concentration of the inner electrode layer 12 at the outermost end is the highest.

[0031] For example, as illustrated in Fig. 4(b), it is preferable that the Sn concentration of each of the multiple internal electrode layers 12 (internal electrode layers 12 in the outer layer region) extending from the outermost layer toward the center in the stacking direction is higher than the Sn concentration of each of the remaining internal electrode layers 12 toward the center in the stacking direction (internal electrode layers 12 in the central region). In this configuration, the Sn concentration of each internal electrode layer 12 in the outer layer region, which is closer to the external environment, is higher, thereby enhancing the effect of improving the moisture resistance of the multilayer ceramic capacitor 100. In Fig. 4(b), the internal electrode layers 12 are shaded from white to black to indicate the magnitude relationship of the Sn concentration.

[0032] In the configuration of Fig. 4(b), if the outer layer region where the Sn concentration is high is too narrow, the ESR may be low but sufficient moisture resistance may not be obtained. Therefore, it is preferable to set a lower limit for the range of the outer layer region. For example, the outer layer region is more than 0% and preferably 5% or more, more preferably 10% or more, of all the internal electrode layers 12 from the upper and lower ends to the center in the stacking direction.

[0033] On the other hand, if the outer layer region where the Sn concentration is high is too wide, sufficient moisture resistance can be obtained, but the ESR may become large. Therefore, it is preferable to set an upper limit to the range of the outer layer region. For example, the outer layer region is preferably 45% or less, more preferably 30% or less, and even more preferably 20% or less, of all the internal electrode layers 12, from the upper and lower ends to the center in the stacking direction.

[0034] 5, it is preferable that the Sn concentration of each internal electrode layer 12 from the central internal electrode layer 12 in the stacking direction to the end internal electrode layer 12 in the stacking direction increases stepwise or gradually from the central internal electrode layer 12 to the end internal electrode layer 12. In this configuration, the Sn concentration of the internal electrode layer 12, which is close to the external environment and thus easily penetrates moisture, is high, thereby enhancing the effect of improving the moisture resistance of the multilayer ceramic capacitor 100. Furthermore, the Sn concentration of the internal electrode layer 12, which is close to the external environment and thus less likely to penetrate moisture, is low, thereby suppressing the ESR while suppressing a decrease in the moisture resistance of the multilayer ceramic capacitor 100. Note that "gradually increasing" includes a continuous increase (monotonous increase) as well as an overall increase with repeated ups and downs when the Sn concentration is measured at multiple sample points from the central internal electrode layer 12 in the stacking direction to the end internal electrode layer 12.

[0035] The thickness of each internal electrode layer 12 is, for example, 0.01 μm to 5 μm, or 0.05 μm to 3 μm, or 0.1 μm to 1 μm. For example, if the thickness of the internal electrode layer 12 is 1 μm or less, the continuity rate is likely to decrease due to fracture during firing, so the effect of the configuration according to this embodiment is significantly exhibited. In the multilayer ceramic capacitor 100, the number of stacked internal electrode layers 12 is, for example, 10 to 5,000, 50 to 4,000, or 100 to 3,000.

[0036] If the Sn concentration of each internal electrode layer 12 is too high, the ESR of the multilayer ceramic capacitor 100 may become high, or the internal electrode layer 12 may dissolve during firing. Therefore, it is preferable to set an upper limit for each Sn concentration. For example, the Sn concentration of each internal electrode layer 12 is preferably 10 at% or less, more preferably 5 at% or less, and even more preferably 1 at% or less. Note that the at% of Sn refers to the atomic concentration ratio of Sn when the total amount of Ni and Sn is 100 at%.

[0037] On the other hand, if the Sn concentration of each internal electrode layer 12 is too low, sufficient moisture resistance may not be obtained in the multilayer ceramic capacitor 100. Therefore, it is preferable to set a lower limit for each Sn concentration. For example, the Sn concentration of each internal electrode layer 12 is preferably 0.01 at% or more, more preferably 0.05 at% or more, and even more preferably 0.1 at% or more.

[0038] For example, for each Sn concentration in each internal electrode layer 12, the ratio of the maximum Sn concentration to the minimum Sn concentration is preferably greater than 1 and not greater than 1000, more preferably 1.5 to 100, and even more preferably 2 to 50.

[0039] It is preferable that the Sn concentration is high in the internal electrode layer 12 near the interface with the dielectric layer 11. This is because reliability is determined not by the entire internal electrode layer, but only by the vicinity of the interface between the dielectric layer 11 and the internal electrode layer 12. Therefore, as illustrated in Fig. 6, it is preferable that the internal electrode layer 12 has a concentration gradient such that the Sn concentration is low in the center in the thickness direction and high near the interface with the dielectric layer 11.

[0040] Incidentally, since the internal electrode layers 12 contain Sn in addition to Ni, the mechanical strength of each internal electrode layer 12 is improved. Since all the internal electrode layers 12 contain Sn in addition to Ni, the mechanical strength of the multilayer ceramic capacitor 100 is improved.

[0041] Next, a description will be given of a method for manufacturing the multilayer ceramic capacitor 100. FIG.

[0042] (raw powder production process) First, a dielectric material for forming the dielectric layer 11 is prepared. The A-site elements and B-site elements contained in the dielectric layer 11 are typically contained in the dielectric layer 11 in the form of a sintered compact of ABO3 particles. For example, BaTiO3 is a tetragonal compound with a perovskite structure and exhibits a high dielectric constant. This BaTiO3 can generally be obtained by synthesizing barium titanate by reacting a titanium raw material such as titanium dioxide with a barium raw material such as barium carbonate. Various methods have been known for synthesizing the ceramic that is the main component of the dielectric layer 11, including the solid-phase method, the sol-gel method, and the hydrothermal method. Any of these methods can be used in this embodiment.

[0043] The resulting ceramic powder is then doped with a predetermined additive compound depending on the purpose, such as oxides of magnesium (Mg), manganese (Mn), vanadium (V), chromium (Cr), rare earth elements (yttrium (Y), samarium (Sm), europium (Eu), gadolinium (Gd), terbium (Tb), dysprosium (Dy), holmium (Ho), erbium (Er), thulium (Tm), and ytterbium (Yb)), oxides containing cobalt (Co), nickel (Ni), lithium (Li), boron (B), sodium (Na), potassium (K), or silicon (Si), or glasses containing cobalt, nickel, lithium, boron, sodium, potassium, or silicon.

[0044] For example, a ceramic material is prepared by wet-mixing a ceramic raw material powder with a compound containing an additive compound, followed by drying and pulverization. For example, the ceramic material obtained as described above may be pulverized as necessary to adjust the particle size, or may be combined with a classification process to adjust the particle size. A dielectric material is obtained by the above process.

[0045] (Lamination process) Next, a binder such as polyvinyl butyral (PVB) resin, an organic solvent such as ethanol or toluene, and a plasticizer are added to the obtained dielectric material and wet mixed. The obtained slurry is used to coat a dielectric green sheet 52 on a substrate 51 by, for example, a die coater method or a doctor blade method, and then dried. The substrate 51 is, for example, a PET (polyethylene terephthalate) film.

[0046] Next, as illustrated in FIG. 8(a), an internal electrode pattern 53 is formed on a dielectric green sheet 52. In FIG. 8(a), as an example, four layers of internal electrode patterns 53 are formed on the dielectric green sheet 52 at predetermined intervals. The film formation method is not particularly limited, but for example, an electrode paste containing NiSn alloy powder or a mixture of Ni powder and Sn powder is used. Alternatively, vacuum film formation such as sputtering using a NiSn alloy target, or simultaneous sputtering using separate Ni and Sn targets may be used. The dielectric green sheet 52 on which the internal electrode pattern 53 is formed is used as a lamination unit.

[0047] Next, while peeling the dielectric green sheet 52 from the substrate 51, three or more lamination units are laminated as shown in Fig. 8(b). In this case, in at least two layers of each internal electrode pattern, the Sn concentration of the internal electrode pattern on the end side in the lamination direction is made higher than that of the internal electrode pattern on the center side in the lamination direction. The Sn concentration of each internal electrode pattern may be adjusted so as to obtain the Sn concentration distributions shown in Figs. 4(a) to 5.

[0048] Next, a predetermined number of cover sheets (e.g., 2 to 10 layers) are laminated on top and bottom of the laminate obtained by laminating the lamination units, and are thermocompression bonded, and then cut to predetermined chip dimensions (e.g., 1.0 mm x 0.5 mm). In the example of FIG. 8(b), cutting is performed along the dotted lines. The cover sheets may have the same components as the dielectric green sheets 52, or may contain different additive compounds.

[0049] (Firing process) The ceramic laminate thus obtained was subjected to binder removal treatment in an N2 atmosphere, after which a metal paste that would become the base layer of the external electrodes 20a, 20b was applied by dipping, and the ceramic laminate was heated in an atmosphere with an oxygen partial pressure of 10 -5 ~10 -8 The mixture is then fired in a reducing atmosphere at 1100 to 1300° C. for 10 minutes to 2 hours at 1 atm. In this way, the multilayer ceramic capacitor 100 is obtained.

[0050] (Reoxidation treatment process) Thereafter, a re-oxidation treatment may be performed at 600°C to 1000°C in an N2 gas atmosphere.

[0051] (Plating process) Thereafter, the external electrodes 20a, 20b may be coated with a metal such as Cu, Ni, or Sn by plating.

[0052] According to the manufacturing method of this embodiment, in at least two layers ranging from the central internal electrode layer 12 in the stacking direction to the endmost internal electrode layer 12 in the stacking direction, the internal electrode layer 12 with a high Sn concentration is arranged closer to the end in the stacking direction than the internal electrode layer 12 with a low Sn concentration. This makes it possible to improve the moisture resistance while suppressing the ESR of the multilayer ceramic capacitor 100.

[0053] In the above embodiments, a multilayer ceramic capacitor has been described as an example of a ceramic electronic component, but the present invention is not limited to this. For example, other electronic components such as a varistor or a thermistor may also be used. [Example]

[0054] The multilayer ceramic capacitor according to the embodiment was fabricated and its characteristics were examined.

[0055] Example 1 Additives were added to barium titanate powder, and the mixture was thoroughly wet mixed and pulverized in a ball mill to obtain a dielectric material. A butyral-based organic binder, toluene, and ethyl alcohol were added to the dielectric material, and a dielectric green sheet was applied to a PET substrate using the doctor blade method. The thickness of the dielectric green sheet was 1 μm.

[0056] Next, an internal electrode pattern was formed on the dielectric green sheet using a paste containing a Ni—Sn alloy.

[0057] Next, the dielectric green sheet was peeled off from the substrate, and the lamination units were stacked. The number of stacks was 1,000. Next, a predetermined number of cover sheets were stacked on the top and bottom of the laminate obtained by stacking the lamination units, and they were thermocompression bonded. After that, it was cut to the predetermined chip dimensions (1.0 mm × 0.5 mm × 0.5 mm).

[0058] The ceramic laminate thus obtained was subjected to a binder removal treatment in an N2 atmosphere, after which a metal paste that would become the base layer of the external electrodes was applied by dipping, and then fired in a reducing atmosphere.

[0059] The thickness of each internal electrode layer 12 after firing was 0.5 μm. In the laminated chip 10, the Sn concentration of the internal electrode layers 12 in the outer layer region 20 μm from the end in the stacking direction was 3 at%. The outer layer region 20 μm from the end in the stacking direction includes nine internal electrode layers 12. The Sn concentration of the internal electrode layers 12 in the central region excluding the outer layer regions was 0.2 at%.

[0060] Example 2 In Example 2, the Sn concentration of the internal electrode layers 12 in the central region of the laminated chip 10, excluding the outer layer regions 10 μm from the outermost end in the lamination direction, was set to 0.05 at %. Other conditions were the same as in Example 1.

[0061] Example 3 In Example 3, the Sn concentration of the internal electrode layers 12 in the outer layer region 10 μm from the outermost end in the stacking direction of the laminated chip 10 was set to 10 at %. The Sn concentration of the internal electrode layers 12 in the central region excluding the outer layer region was set to 0.1 at %. Other conditions were the same as in Example 1.

[0062] (Comparative Example 1) In Comparative Example 1, Sn was not added to any of the internal electrode layers 12. Other conditions were the same as in Example 1.

[0063] (Comparative Example 2) In Comparative Example 2, the Sn concentration was set to 3 at% in both the internal electrode layers 12 in the outer layer region 10 μm from the end of the stacking direction and the internal electrode layers 12 in the central region excluding the outer layer region in the laminated chip 10. Other conditions were the same as in Example 1.

[0064] (Comparative Example 3) In Comparative Example 3, the Sn concentration of the internal electrode layers 12 in the outer layer region 10 μm from the outermost end in the stacking direction of the laminated chip 10 was set to 0.2 at %. The Sn concentration of the internal electrode layers 12 in the central region excluding the outer layer region was set to 3 at %. Other conditions were the same as in Example 1.

[0065] (analysis) For each of Examples 1 to 3 and Comparative Examples 1 to 3, the humidity load life (min), flexural strength (N), and ESR (mΩ) were measured. The humidity load life was measured at a temperature of 85°C and a humidity of 85%. The flexural strength (N) was measured by placing both ends of the element on a bridge, pressing the center from above with a blade having a specified tip diameter, and measuring the load at the moment when the element broke. The ESR was calculated from the frequency characteristics of the impedance. The results are shown in Table 1. Table 1 also lists the ratio of the Sn concentration in the outer layer region to the Sn concentration in the center region. [Table 1]

[0066] For the humidity load life, if it exceeded 1000 min, it was judged to be acceptable. For the ESR, if it was less than 15 mΩ, it was judged to be acceptable. In all of Examples 1 to 3, both the humidity load life and ESR were judged to be acceptable. This is thought to be because the Sn concentration in the internal electrode layer that is close to the external environment was increased and the Sn concentration in the internal electrode layer that is far from the external environment was decreased. Note that in all of Examples 1 to 3, high bending strength was obtained. This is thought to be because the mechanical strength was improved by adding Sn together with Ni to the internal electrode layer.

[0067] The humidity resistance load life was judged to be unacceptable for Comparative Example 1. This is thought to be because sufficient humidity resistance was not obtained due to the lack of Sn added to the internal electrode layers.

[0068] The ESR of Comparative Example 2 was judged to be unacceptable, which is thought to be because the Sn concentration in the internal electrode layer, which is far from the external environment, was also increased.

[0069] The humidity resistance load life was judged to be unacceptable for Comparative Example 3. This is thought to be because sufficient humidity resistance was not obtained due to the small amount of Sn in the internal electrode layer, which is close to the external environment.

[0070] Example 4 In Example 4, the Sn concentration of the inner electrode layer at the end of the lamination direction was 3 at %, and the Sn concentration of the inner electrode layer at the center of the lamination direction was 0.2 at %, with the Sn concentration gradually increasing from the center to the outermost end in the lamination direction. Specifically, the Sn concentration of the inner electrode layer was gradually increased in 10-layer increments from the center to the outermost end, resulting in 50 Sn concentration levels. For Example 4, the humidity load life (min), flexural strength (N), and ESR (mΩ) were also measured. The results are shown in Table 2. As shown in Table 2, both the humidity load life and ESR were judged to be acceptable. This is thought to be because the Sn concentration was increased in the inner electrode layer that was closer to the external environment and decreased in the inner electrode layer that was farther from the external environment. Furthermore, a high flexural strength was obtained. This is thought to be due to the addition of Sn together with Ni to the inner electrode layer, which improved mechanical strength. [Table 2]

[0071] Although the embodiments of the present invention have been described in detail above, the present invention is not limited to such specific embodiments, and various modifications and variations are possible within the scope of the gist of the present invention as defined in the claims.

[0072] The inventions described in the claims of the original application of this application are as follows: [1] The capacitor has a laminated structure in which a plurality of dielectric layers mainly made of ceramic and a plurality of internal electrode layers are alternately laminated, the plurality of internal electrode layers contain Ni and Sn, the plurality of internal electrode layers include a first portion having a plurality of internal electrode layers from an upper end to a center side in the stacking direction, a second portion having a plurality of internal electrode layers from a lower end to a center side in the stacking direction, and a third portion located closer to the center side in the stacking direction than the first portion and the second portion, the first portion and the second portion occupy 5% or more of the total number of stacked layers of the internal electrode layers in the stacked structure, A ceramic electronic component, characterized in that the Sn concentration of the internal electrode layers included in the first portion and the second portion is higher than the Sn concentration of the internal electrode layers included in the third portion. [2] The ceramic electronic component according to [1], wherein the first portion and the second portion occupy 10% or more of the total number of stacked layers of the internal electrode layers in the stacked structure. [3] The ceramic electronic component according to [1] or [2], wherein the first portion and the second portion comprise 45% or less of the total number of stacked layers of the internal electrode layers in the stacked structure. [4] The ceramic electronic component according to [1] or [2], wherein the first portion and the second portion comprise 30% or less of the total number of stacked layers of the internal electrode layers in the stacked structure. [5] The ceramic electronic component according to [1] or [2], wherein the first portion and the second portion comprise 20% or less of the total number of stacked layers of the internal electrode layers in the stacked structure. [6] [1] to [5], characterized in that the Sn concentration of the inner electrode layer at the end is the highest from the inner electrode layer at the center in the stacking direction to the inner electrode layer at the end in the stacking direction. [7] The ceramic electronic component according to any one of [1] to [6], characterized in that the Sn concentration of each of the plurality of internal electrode layers from the outermost end toward the center in the stacking direction is higher than the Sn concentration of each of the remaining internal electrode layers toward the center in the stacking direction. [8] [1] to [7], characterized in that the Sn concentration of each internal electrode layer from the center internal electrode layer in the stacking direction to the end internal electrode layer in the stacking direction increases stepwise or gradually from the center internal electrode layer in the stacking direction to the end internal electrode layer in the stacking direction. [9] The ceramic electronic component according to any one of [1] to [8], wherein the thickness of the plurality of internal electrode layers of the laminated structure is 1 μm or less.

[10] The ceramic electronic component according to any one of [1] to [9], wherein the Sn concentration in at least some of the plurality of internal electrode layers of the laminated structure is 10 at % or less.

[11] The ceramic electronic component according to any one of [1] to

[10] , wherein the Sn concentration in at least some of the plurality of internal electrode layers of the laminated structure is 0.1 at% or more.

[12]

[12] The ceramic electronic component according to any one of [1] to

[11] , characterized in that the ratio of the maximum Sn concentration to the minimum Sn concentration in each of the plurality of internal electrode layers of the laminated structure is greater than 1 and is 100 or less.

[13]

[13] The ceramic electronic component according to any one of [1] to

[12] , characterized in that in at least some of the plurality of internal electrode layers of the laminated structure, the concentration of Sn is higher near the interface with the dielectric layer than in the center in the thickness direction.

[14] forming an internal electrode pattern containing Ni and Sn on a dielectric green sheet to form a laminate unit; forming a laminate by stacking a plurality of the lamination units; and firing the laminate, a first portion having a plurality of internal electrode patterns extending from an upper end to a center in the stacking direction, a second portion having a plurality of internal electrode patterns extending from a lower end to a center in the stacking direction, and a third portion located closer to the center in the stacking direction than the first portion and the second portion, wherein the first portion and the second portion account for 5% or more of the total number of layers of the internal electrode patterns in the laminate, and the Sn concentration of the internal electrode patterns included in the first portion and the second portion is set higher than the Sn concentration of the internal electrode patterns included in the third portion. [Explanation of symbols]

[0073] 10 stacked chips 11 Dielectric layer 12 Internal electrode layer 13 Cover Layer 14 capacity area 15 End Margin 16 Side Margin 20a,20b external electrode 51 Base material 52 Dielectric green sheet 53 Internal electrode pattern 100 Multilayer ceramic capacitors

Claims

1. The laminated structure has a plurality of dielectric layers mainly made of ceramic and a plurality of internal electrode layers alternately stacked in a stacking direction, the plurality of internal electrode layers include a first internal electrode layer at one end in the stacking direction, a second internal electrode layer at the center in the stacking direction, and a third internal electrode layer between the first internal electrode layer and the second internal electrode layer, the first internal electrode layer, the second internal electrode layer, and the third internal electrode layer contain Ni and Sn, the first internal electrode layer, the second internal electrode layer, and the third internal electrode layer contain Sn at the center in a first direction perpendicular to the stacking direction, A ceramic electronic component, characterized in that the third internal electrode layer has a higher Sn concentration than the second internal electrode layer.

2. 2. The ceramic electronic component according to claim 1, wherein the first internal electrode layers have a higher Sn concentration than the third internal electrode layers.

3. 2. The ceramic electronic component according to claim 1, wherein the Sn concentration of the first internal electrode layer is the highest among the second internal electrode layers to the first internal electrode layers.

4. the laminated structure has five or more layers of internal electrodes, 2. The ceramic electronic component according to claim 1, wherein the Sn concentration of each of the plurality of internal electrode layers from the outermost end toward the center in the stacking direction is higher than the Sn concentration of each of the remaining internal electrode layers toward the center in the stacking direction.

5. the laminated structure has five or more layers of internal electrodes, 2. The ceramic electronic component according to claim 1, wherein the Sn concentration of each of the internal electrode layers from the center internal electrode layer in the stacking direction to the end internal electrode layer in the stacking direction increases stepwise or gradually from the center internal electrode layer in the stacking direction to the end internal electrode layer in the stacking direction.

6. 6. The ceramic electronic component according to claim 1, wherein the first internal electrode layer, the second internal electrode layer, and the third internal electrode layer all have a thickness of 1 [mu]m or less.

7. 7. The ceramic electronic component according to claim 1, wherein the first internal electrode layer, the second internal electrode layer, and the third internal electrode layer each have an Sn concentration of 10 at % or less.

8. 8. The ceramic electronic component according to claim 1, wherein the first internal electrode layer, the second internal electrode layer, and the third internal electrode layer each have an Sn concentration of 0.01 at% or more.

9. 9. The ceramic electronic component according to claim 1, wherein a ratio of the Sn concentration of the first internal electrode layers to the Sn concentration of the second internal electrode layers is greater than 1 and 100 or less.

10. 10. The ceramic electronic component according to claim 1, wherein the internal electrode layer has a higher Sn concentration in the vicinity of the interface with the dielectric layer than in the center portion in the thickness direction.

11. The ceramic electronic component according to claim 1 , wherein the laminated structure has ten or more layers of internal electrodes.

12. the plurality of internal electrode layers further include a fourth internal electrode layer located between the first internal electrode layer and the third internal electrode layer, 2. The ceramic electronic component according to claim 1, wherein the fourth internal electrode layer has a higher Sn concentration than the third internal electrode layer.

13. the plurality of internal electrode layers further include a fourth internal electrode layer located between the first internal electrode layer and the third internal electrode layer, 2. The ceramic electronic component according to claim 1, wherein the fourth internal electrode layer has a lower Sn concentration than the third internal electrode layer.

14. 8. The ceramic electronic component according to claim 7, wherein the Sn concentration in each of the first internal electrode layer, the second internal electrode layer, and the third internal electrode layer is 5 at % or less.

15. 15. The ceramic electronic component according to claim 14, wherein the Sn concentration in each of the first internal electrode layer, the second internal electrode layer, and the third internal electrode layer is 1 at % or less.

16. 9. The ceramic electronic component according to claim 8, wherein the Sn concentration in each of the first internal electrode layer, the second internal electrode layer, and the third internal electrode layer is 0.05 at % or more.

17. 17. The ceramic electronic component according to claim 16, wherein the Sn concentration in each of the first internal electrode layer, the second internal electrode layer, and the third internal electrode layer is 0.1 at % or more.

18. 2. The ceramic electronic component according to claim 1, wherein the ceramic electronic component has an equivalent series resistance of 13 mΩ or less.

19. 2. The ceramic electronic component according to claim 1, wherein the ceramic electronic component has a flexural strength of 12 N or more.

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