Ceramic electronic component and method of manufacturing the same

Abstract

To provide a ceramic electronic component capable of achieving both high insulation resistance and high capacitance, and to provide a method of manufacturing the same.SOLUTION: A ceramic electronic component includes a multi-layer chip, and a first external electrode and a second external electrode respectively provided on a first end surface and a second end surface of the multi-layer chip. The multilayer chip includes a plurality of internal electrode layers and a plurality of dielectric layers alternately stacked with the internal electrode layers in a stacking direction. The plurality of internal electrode layers include a plurality of first internal electrode layers connected to the first external electrode and a plurality of second internal electrode layers connected to the second external electrode. The multi-layer chip includes a first outer layer region and a second outer layer region extending along a stacking direction from an upper surface and a lower surface of the multi-layer chip, respectively, and a center region provided between the first outer layer region and the second outer layer region. A Sn concentration of a first outer dielectric layer in a first outer region among the plurality of dielectric layers is lower than a Sn concentration of a center dielectric layer in a center region among the plurality of dielectric layers.SELECTED DRAWING: Figure 4

Description

[Technical Field]

[0001] The present invention relates to a ceramic electronic component and a method for manufacturing the same. [Background technology]

[0002] Multilayer ceramic electronic components such as multilayer ceramic capacitors have a structure in which internal electrode layers are stacked with dielectric layers sandwiched between them. The ferroelectric properties of the dielectric layer regions sandwiched between the internal electrode layers enable ceramic electronic components to achieve a high capacitance density (see, for example, Patent Document 1). [Prior art documents] [Patent documents]

[0003] [Patent Document 1] International Publication No. 2014 / 024538 Summary of the Invention [Problem to be solved by the invention]

[0004] The metal contained in the internal electrode layers may diffuse into the main ceramic component of the dielectric layer during the firing process and form a solid solution. If the metal contained in the internal electrode layers forms a solid solution in the main ceramic component of the dielectric layer, oxygen defects may form in the main ceramic component of the dielectric layer, reducing the insulating properties of the dielectric layer and potentially shortening the life of the ceramic electronic component.

[0005] Therefore, by dissolving Sn in the main component ceramic of the dielectric layer, it is possible to prevent the main component metal of the internal electrode layer from dissolving in the main component ceramic of the dielectric layer, thereby improving the insulation properties of the dielectric layer and extending its lifespan.

[0006] However, Sn has the effect of promoting sintering of the dielectric layers and spheroidization of the internal electrode layers. Therefore, while adding Sn can improve the insulation properties of the dielectric layers, it also causes a problem of reduced capacitance due to disruption of the laminated structure caused by spheroidization of the internal electrode layers.

[0007] The present invention has been made in view of the above-mentioned problems, and has as its object to provide a ceramic electronic component that can achieve both high insulation resistance and high capacitance, and a method for manufacturing the same. [Means for solving the problem]

[0008] A ceramic electronic component according to the present invention has a laminated structure in which a plurality of internal electrode layers and three or more dielectric layers whose main component is ceramic are alternately stacked, the three or more dielectric layers containing Sn, and at least two of the three or more dielectric layers have a lower Sn concentration in the dielectric layers at the ends in the stacking direction than in the dielectric layers at the center in the stacking direction.

[0009] In the ceramic electronic component, the Sn concentration of the outermost dielectric layer may be the lowest from the central dielectric layer in the stacking direction to the outermost dielectric layer in the stacking direction.

[0010] In the ceramic electronic component, the Sn concentration of each of the plurality of dielectric layers from the outermost end toward the center in the stacking direction may be lower than the Sn concentration of each of the remaining dielectric layers toward the center in the stacking direction.

[0011] In the ceramic electronic component, the Sn concentration of each dielectric layer from the central dielectric layer in the stacking direction to the endmost dielectric layer in the stacking direction may increase stepwise or gradually from the central dielectric layer in the stacking direction to the endmost dielectric layer in the stacking direction.

[0012] In the ceramic electronic component, the ratio of the minimum Sn concentration to the maximum Sn concentration in each of the three or more dielectric layers may be 2:3 or less.

[0013] In the ceramic electronic component, the main component ceramic of the three or more dielectric layers may have a perovskite structure, and the difference between the minimum Sn / B site element ratio and the maximum Sn / B site element ratio for the Sn concentration in each of the three or more dielectric layers may be 0.001 or more.

[0014] In the ceramic electronic component, the three or more dielectric layers may contain barium titanate as a main component ceramic, and the internal electrode layers may contain nickel as a main component metal.

[0015] In the ceramic electronic component, the three or more dielectric layers may have a thickness of 5 μm or less.

[0016] In the ceramic electronic component, the three or more dielectric layers may have an Sn concentration of 5 at % or less.

[0017] In the ceramic electronic component, the three or more internal electrode layers may have an Sn concentration of 0.1 at % or more.

[0018] A method for manufacturing a ceramic electronic component according to the present invention includes the steps of forming a laminate unit by forming an internal electrode pattern containing metal powder on a dielectric green sheet containing ceramic powder and an Sn source, forming a laminate by stacking three or more of the laminate units, and firing the laminate, wherein the method is characterized in that, in at least two layers of the dielectric green sheets before firing, the Sn concentration relative to the main component ceramic is lower in the dielectric green sheets at the ends of the lamination direction than in the dielectric green sheets at the center of the lamination direction. [Effects of the Invention]

[0019] According to the present invention, it is possible to provide a ceramic electronic component that can achieve both high insulation resistance and high capacitance, and a method for manufacturing the same. [Brief explanation of the drawings]

[0020] [Figure 1] FIG. 2 is a partial cross-sectional perspective view of a multilayer ceramic capacitor. [Figure 2] FIG. 2 is a cross-sectional view taken along line AA in FIG. [Figure 3] FIG. 2 is a cross-sectional view taken along line BB in FIG. [Figure 4] 10(a) and 10(b) are diagrams illustrating the Sn concentration. [Figure 5] FIG. 10 is a diagram illustrating an example of Sn concentration. [Figure 6] 1A to 1C are diagrams illustrating a flow of a method for manufacturing a multilayer ceramic capacitor. [Figure 7] 1(a) and 1(b) are diagrams illustrating the lamination process. DETAILED DESCRIPTION OF THE INVENTION

[0021] Hereinafter, embodiments will be described with reference to the drawings.

[0022] (Embodiment) FIG. 1 is a partial cross-sectional perspective view of a multilayer ceramic capacitor 100 according to an embodiment. FIG. 2 is a cross-sectional view taken along line AA in FIG. 1. FIG. 3 is a cross-sectional view taken along line BB in FIG. 1. As illustrated in FIGS. 1 to 3, the multilayer ceramic capacitor 100 includes a laminated chip 10 having a substantially rectangular parallelepiped shape and external electrodes 20a, 20b provided on two opposing end faces of the laminated chip 10. Of the four faces of the laminated chip 10 other than the two end faces, the two faces other than the top and bottom faces in the stacking direction are referred to as side faces. The external electrodes 20a, 20b extend on the top, bottom and two side faces of the laminated chip 10 in the stacking direction. However, the external electrodes 20a, 20b are spaced apart from each other.

[0023] The multilayer chip 10 has a configuration in which dielectric layers 11 containing a ceramic material that functions as a dielectric and three or more internal electrode layers 12 containing a base metal material are alternately stacked. The edges of each internal electrode layer 12 are alternately exposed at the end face of the multilayer chip 10 where the external electrode 20a is provided and the end face where the external electrode 20b is provided. As a result, each internal electrode layer 12 is alternately electrically connected to the external electrode 20a and the external electrode 20b. As a result, the multilayer ceramic capacitor 100 has a configuration in which multiple dielectric layers 11 are stacked with the internal electrode layers 12 interposed therebetween. In addition, in the laminate of the dielectric layers 11 and the internal electrode layers 12, the internal electrode layer 12 is arranged as the outermost layer in the stacking direction, and the upper and lower surfaces of the laminate are covered by cover layers 13. The cover layers 13 are primarily composed of a ceramic material. For example, the material of the cover layers 13 may have the same primary ceramic component as the dielectric layers 11.

[0024] The size of the multilayer ceramic capacitor 100 is, for example, 0.25 mm in length, 0.125 mm in width, and 0.125 mm in height, or 0.4 mm in length, 0.2 mm in width, and 0.2 mm in height, or 0.6 mm in length, 0.3 mm in width, and 0.3 mm in height, or 1.0 mm in length, 0.5 mm in width, and 0.5 mm in height, or 3.2 mm in length, 1.6 mm in width, and 1.6 mm in height, or 4.5 mm in length, 3.2 mm in width, and 2.5 mm in height, but is not limited to these sizes.

[0025] The internal electrode layers 12 are mainly composed of base metals such as Ni (nickel), Cu (copper), Sn (tin), etc. The internal electrode layers 12 may also be made of precious metals such as Pt (platinum), Pd (palladium), Ag (silver), Au (gold), etc., or alloys containing these metals.

[0026] The dielectric layer 11 is mainly composed of a ceramic material having a perovskite structure represented by the general formula ABO3. 3-αFor example, the ceramic material includes BaTiO3 (barium titanate), CaZrO3 (calcium zirconate), CaTiO3 (calcium titanate), SrTiO3 (strontium titanate), BaTiO3 (barium titanate) which forms a perovskite structure, 1-x-y Ca x Sr y Ti 1-z Zr z O3 (0≦x≦1, 0≦y≦1, 0≦z≦1), etc., can be used. The thickness of each dielectric layer 11 is, for example, 0.05 μm or more and 5 μm or less, or 0.1 μm or more and 3 μm or less, or 0.2 μm or more and 1 μm or less.

[0027] 2, the region where the internal electrode layer 12 connected to the external electrode 20a and the internal electrode layer 12 connected to the external electrode 20b face each other is a region where capacitance is generated in the multilayer ceramic capacitor 100. Therefore, this region where capacitance is generated is referred to as a capacitance region 14. In other words, the capacitance region 14 is a region where adjacent internal electrode layers 12 connected to different external electrodes face each other.

[0028] The region where the internal electrode layers 12 connected to the external electrode 20a face each other without an internal electrode layer 12 connected to the external electrode 20b interposed therebetween is called the end margin 15. The region where the internal electrode layers 12 connected to the external electrode 20b face each other without an internal electrode layer 12 connected to the external electrode 20a interposed therebetween is also the end margin 15. In other words, the end margin 15 is the region where the internal electrode layers 12 connected to the same external electrode face each other without an internal electrode layer 12 connected to a different external electrode interposed therebetween. The end margin 15 is a region where no capacitance is generated.

[0029] 3, in the laminated chip 10, the regions extending from the two side surfaces of the laminated chip 10 to the internal electrode layers 12 are referred to as side margins 16. In other words, the side margins 16 are regions provided so as to cover the ends of the multiple internal electrode layers 12 stacked in the above-mentioned laminated structure, which extend to the two side surfaces. The side margins 16 are also regions that do not generate electrical capacitance.

[0030] The multilayer chip 10 can be obtained by stacking and firing layers formed from powdered materials. However, the main component metal of the internal electrode layer 12 may dissolve into the main component ceramic of the dielectric layer 11 during the firing process. For example, if the internal electrode layer 12 contains Ni, some of the Ni oxidizes during the firing process, and the ionized Ni dissolves into the main component ceramic of the dielectric layer 11. If the main component metal of the internal electrode layer 12 dissolves into the main component ceramic of the dielectric layer 11, oxygen defects will form in the main component ceramic of the dielectric layer 11, which may reduce the insulating properties of the dielectric layer 11 and shorten the life of the multilayer ceramic capacitor 100.

[0031] Therefore, by dissolving Sn in the main component ceramic of the dielectric layer 11, the main component metal of the internal electrode layer 12 is prevented from dissolving in the main component ceramic of the dielectric layer 11, thereby improving the insulation of the dielectric layer 11 and extending the life of the multilayer ceramic capacitor 100.

[0032] However, Sn promotes sintering of the dielectric layers 11 and spheroidization of the internal electrode layers 12. Therefore, while adding Sn can improve the insulating properties of the dielectric layers 11, the addition of Sn also leads to a problem of reduced capacitance of the multilayer ceramic capacitor 100 due to disruption of the laminated structure caused by spheroidization of the internal electrode layers 12. In particular, a thermal gradient is likely to occur because heat from the sintering furnace is transferred from the outside to the inside of the laminated chip before sintering. For example, a rapid temperature increase of 100°C / min or more tends to cause a significant thermal gradient. This thermal gradient tends to facilitate sintering of the outer side more rapidly than the inner side, leading to spheroidization of the outer internal electrode layers. Furthermore, residual carbon in the binder, which inhibits sintering, gasifies from the outside and escapes into the sintering furnace atmosphere, making the outer side sintering more likely than the inner side. Sintering promotion is particularly pronounced in the outermost internal electrode layers. Therefore, the multilayer ceramic capacitor 100 according to this embodiment has a configuration that can achieve both high insulation resistance and high capacitance.

[0033] In the multilayer ceramic capacitor 100 according to this embodiment, each dielectric layer 11 contains Sn. For example, Sn is dissolved in the main ceramic of each dielectric layer 11. This prevents the main metal of the internal electrode layers 12 from dissolving in the main ceramic of the dielectric layers 11 during firing. As a result, the insulating properties of the dielectric layers 11 can be improved, and the life of the multilayer ceramic capacitor 100 can be extended. Next, for at least two of the three or more dielectric layers 11, the Sn concentration of the dielectric layers 11 at the ends in the stacking direction is lower than that of the dielectric layers 11 at the center in the stacking direction. The dielectric layers 11 at the center in the stacking direction effectively improve the life, while the dielectric layers 11 at the ends in the stacking direction prevent the internal electrode layers 12 from becoming spheroidized, effectively suppressing a decrease in the continuity ratio and preventing disruption of the stacked structure, thereby effectively improving the capacitance. These factors enable both high insulating properties and high capacitance to be achieved. If the number of dielectric layers 11 stacked is an even number, the central dielectric layer in the stacking direction refers to the two central dielectric layers in the stacking direction. If the number of dielectric layers 11 stacked is an odd number, the central dielectric layer in the stacking direction refers to the single central dielectric layer in the stacking direction.

[0034] For example, as illustrated in Fig. 4(a), it is preferable that the Sn concentration of the dielectric layer 11 at the end of the stacking direction from the central dielectric layer 11 to the outermost dielectric layer 11 in the stacking direction is the lowest. This configuration significantly suppresses sintering. In Fig. 4(a), the outermost dielectric layer 11 in the stacking direction is depicted in black to indicate that the Sn concentration of the outermost dielectric layer 11 is the lowest.

[0035] For example, as illustrated in FIG. 4(b), it is preferable that the Sn concentration of each of the dielectric layers 11 (dielectric layers 11 in the outer layer region) extending from the outermost layer toward the center in the stacking direction be lower than the Sn concentration of each of the remaining dielectric layers 11 toward the center in the stacking direction (dielectric layers 11 in the central region). For example, when a total of 400 dielectric layers 11 are stacked, the Sn concentration is high in the 200 dielectric layers 11 at the center in the stacking direction, and the Sn concentration is low in the 100 dielectric layers 11 at each end in the stacking direction. This configuration significantly suppresses sintering. Note that in FIG. 4(b), the dielectric layers 11 with low Sn concentrations are depicted in black.

[0036] In the configuration of Fig. 4(b), if the outer layer region where the Sn concentration is low is too narrow, the sintering suppression effect may not be sufficient. Therefore, it is preferable to set a lower limit for the range of the outer layer region. For example, the outer layer region is preferably more than 0% but not less than 5%, and more preferably not less than 10%, of the entire dielectric layer 11 from the top and bottom ends toward the center in the stacking direction.

[0037] On the other hand, if the outer layer region where the Sn concentration is low is too large, the effect of improving the lifespan may not be sufficiently obtained. Therefore, it is preferable to set an upper limit to the range of the outer layer region. For example, the outer layer region is preferably 40% or less, more preferably 30% or less, and even more preferably 20% or less of the total dielectric layer 11 from the top and bottom ends toward the center in the stacking direction.

[0038] For example, as illustrated in FIG. 5, it is preferable that the Sn concentration of each dielectric layer 11 from the central dielectric layer 11 in the stacking direction to the outermost dielectric layer 11 in the stacking direction decreases stepwise or gradually from the central internal electrode layer 12 in the stacking direction to the outermost internal electrode layer 12. In this configuration, the Sn concentration of the dielectric layers 11 at the ends in the stacking direction decreases, thereby significantly suppressing sintering. Furthermore, the Sn concentration of the dielectric layers 11 at the center in the stacking direction increases, thereby significantly improving the lifespan. Note that "gradually decreasing" includes a continuous decrease (monotonous decrease) as well as an overall decrease with repeated ups and downs when the Sn concentration is measured at multiple sample points from the central dielectric layer 11 in the stacking direction to the outermost dielectric layer 11.

[0039] The thickness of each internal electrode layer 12 is, for example, 0.01 μm to 5 μm, or 0.05 μm to 3 μm, or 0.1 μm to 1 μm. For example, if the thickness of the internal electrode layer 12 is 1 μm or less, the continuity rate is likely to decrease due to fracture during firing, so the effect of the configuration according to this embodiment is significantly exhibited. In the multilayer ceramic capacitor 100, the number of stacked internal electrode layers 12 is, for example, 10 to 5,000, 50 to 4,000, or 100 to 3,000.

[0040] If the Sn concentration in each dielectric layer 11 is too high, the internal electrode layers 12 may become more spherical, which may result in a decrease in the capacitance of the multilayer ceramic capacitor 100. Therefore, it is preferable to set an upper limit to the Sn concentration in each dielectric layer 11. For example, the Sn concentration in each dielectric layer 11 is preferably 5 at% or less, more preferably 3 at% or less, and even more preferably 2 at% or less. Note that the at% of Sn refers to the atomic ratio of Sn when the main component ceramic is taken as 100 at%. When the main component ceramic of the dielectric layer 11 has a perovskite structure, the at% of Sn refers to the atomic ratio of Sn when the B-site elements of the main component ceramic are taken as 100 at%.

[0041] On the other hand, if the Sn concentration in each dielectric layer 11 is too low, there is a risk that the diffusion of metal components contained in the internal electrode layers 12 into the dielectric layers 11 may not be sufficiently suppressed. Therefore, it is preferable to set a lower limit for each Sn concentration. For example, the Sn concentration in each dielectric layer 11 is preferably 0.1 at% or more, more preferably 0.5 at% or more, and even more preferably 1 at% or more.

[0042] For example, with regard to the Sn concentration in each dielectric layer 11, the ratio of the minimum Sn concentration to the maximum Sn concentration is preferably 2:3 or less, more preferably 1:3 or less, and even more preferably 1:5 or less. Furthermore, with regard to the Sn concentration in each dielectric layer 11, the difference between the minimum Sn / B site element ratio and the maximum Sn / B site element ratio is preferably 0.001 or more, more preferably 0.005 or more, and even more preferably 0.01 or more.

[0043] Next, a description will be given of a method for manufacturing the multilayer ceramic capacitor 100. FIG.

[0044] (raw powder production process) First, a dielectric material for forming the dielectric layer 11 is prepared. The A-site elements and B-site elements contained in the dielectric layer 11 are typically contained in the dielectric layer 11 in the form of a sintered compact of ABO3 particles. For example, BaTiO3 is a tetragonal compound with a perovskite structure and exhibits a high dielectric constant. This BaTiO3 can generally be obtained by synthesizing barium titanate by reacting a titanium raw material such as titanium dioxide with a barium raw material such as barium carbonate. Various methods have been known for synthesizing the ceramic that is the main component of the dielectric layer 11, including the solid-phase method, the sol-gel method, and the hydrothermal method. Any of these methods can be used in this embodiment.

[0045] The resulting ceramic powder is then doped with a predetermined additive compound depending on the purpose, such as oxides of tin (Sn), magnesium (Mg), manganese (Mn), vanadium (V), chromium (Cr), rare earth elements (yttrium (Y), samarium (Sm), europium (Eu), gadolinium (Gd), terbium (Tb), dysprosium (Dy), holmium (Ho), erbium (Er), thulium (Tm), and ytterbium (Yb)), or oxides containing cobalt (Co), nickel (Ni), lithium (Li), boron (B), sodium (Na), potassium (K), or silicon (Si), or glasses containing cobalt, nickel, lithium, boron, sodium, potassium, or silicon.

[0046] For example, a ceramic material is prepared by wet-mixing a ceramic raw material powder with a compound containing an additive compound, followed by drying and pulverization. For example, the ceramic material obtained as described above may be pulverized as necessary to adjust the particle size, or may be combined with a classification process to adjust the particle size. A dielectric material is obtained by the above process.

[0047] (Lamination process) Next, a binder such as polyvinyl butyral (PVB) resin, an organic solvent such as ethanol or toluene, and a plasticizer are added to the obtained dielectric material and wet mixed. The obtained slurry is used to coat a dielectric green sheet 52 on a substrate 51 by, for example, a die coater method or a doctor blade method, and then dried. The substrate 51 is, for example, a PET (polyethylene terephthalate) film.

[0048] Next, as illustrated in Fig. 7(a), an internal electrode pattern 53 is formed on a dielectric green sheet 52. In Fig. 7(a), as an example, four layers of internal electrode patterns 53 are formed on the dielectric green sheet 52 at predetermined intervals. The film formation method is not particularly limited, but for example, an electrode paste containing the main component metal of the internal electrode layer 12 is used. Alternatively, vacuum film formation such as sputtering using a target of the main component metal of the internal electrode layer 12 may be used. The dielectric green sheet 52 on which the internal electrode pattern 53 is formed is defined as a lamination unit.

[0049] Next, while peeling the dielectric green sheet 52 from the substrate 51, three or more lamination units are laminated as shown in Fig. 7(b). In this case, in at least two of the dielectric green sheets, the Sn concentration relative to the main component ceramic is made lower in the dielectric green sheets closer to the end of the lamination direction than in the dielectric green sheets closer to the center of the lamination direction. The Sn concentration of each dielectric green sheet may be adjusted so as to obtain the Sn concentration distributions shown in Figs. 4(a) to 5.

[0050] Next, a predetermined number of cover sheets (e.g., 2 to 10 layers) are laminated on top and bottom of the laminate obtained by laminating the lamination units, and are thermocompression bonded, and then cut to predetermined chip dimensions (e.g., 1.0 mm x 0.5 mm). In the example of FIG. 7(b), cutting is performed along the dotted lines. The cover sheets may have the same components as the dielectric green sheets 52, or may contain different additive compounds.

[0051] (Firing process) The ceramic laminate thus obtained was subjected to binder removal treatment in an N2 atmosphere, and then a metal paste that would become the base layer of the external electrodes 20a, 20b was applied by dipping. -5 ~10 -8 The mixture is then fired in a reducing atmosphere at 1100 to 1300° C. for 10 minutes to 2 hours at 1 atm. In this way, the multilayer ceramic capacitor 100 is obtained.

[0052] (Reoxidation treatment process) Thereafter, a re-oxidation treatment may be performed at 600°C to 1000°C in an N2 gas atmosphere.

[0053] (Plating process) Thereafter, the external electrodes 20a, 20b may be coated with a metal such as Cu, Ni, or Sn by plating.

[0054] According to the manufacturing method of this embodiment, for at least two layers ranging from the central dielectric layer 11 in the stacking direction to the endmost dielectric layer 11 in the stacking direction, the dielectric layer 11 with a low Sn concentration is disposed closer to the end in the stacking direction than the dielectric layer 11 with a high Sn concentration. This allows the multilayer ceramic capacitor 100 to achieve both high insulation properties and high capacitance.

[0055] In the above embodiments, a multilayer ceramic capacitor has been described as an example of a ceramic electronic component, but the present invention is not limited to this. For example, other electronic components such as a varistor or a thermistor may also be used. [Example]

[0056] The multilayer ceramic capacitor according to the embodiment was fabricated and its characteristics were examined.

[0057] Example 1 Additives were added to barium titanate powder, and the mixture was thoroughly wet mixed and pulverized in a ball mill to obtain a dielectric material. A butyral-based organic binder, toluene, and ethyl alcohol were added to the dielectric material, and a dielectric green sheet was applied to a PET substrate using the doctor blade method. Next, an internal electrode pattern was formed on the dielectric green sheet using a paste containing Ni powder.

[0058] Next, the dielectric green sheets were peeled off from the substrate and the laminated units were stacked. The number of layers was 400. Next, a predetermined number of cover sheets were stacked on the top and bottom of the laminate obtained by stacking the laminated units and thermocompression bonded. After that, it was cut to the predetermined chip dimensions (1.0 mm x 0.5 mm x 0.5 mm). In the dielectric green sheets of the 200th layer (central region) in the center of the stacking direction, the Sn content relative to Ti was 0.50 at%. In the dielectric green sheets of the 100th layer (outer layer) on the top side of the stacking direction and the 100th layer (outer layer) on the bottom side of the stacking direction, the Sn content relative to Ti was 0.25 at%.

[0059] The ceramic laminate thus obtained was subjected to a binder removal treatment in an N2 atmosphere, after which a metal paste that would become the base layer of the external electrodes was applied by dipping, and then fired in a reducing atmosphere.

[0060] After firing, the atomic concentration ratio, which is the ratio of the Sn atomic concentration to the Ti atomic concentration, was 0.004 in the dielectric layer of the 200th layer (central region) in the stacking direction. The atomic concentration ratio of Sn to Ti was 0.001 in the dielectric layer of the top 100th layer (outer layer) in the stacking direction and the dielectric layer of the bottom 100th layer (outer layer) in the stacking direction. To determine the elemental concentration ratio of Sn to Ti, the chip was cut near the center with a slicer and the cross section was polished using an ion milling device until it became clean. Laser ablation ICP mass spectrometry was performed on the target region of the chip cross section to quantify the elements. The spot diameter of the heating laser was 3 μm.

[0061] Example 2 In Example 2, the Sn content relative to Ti was 1.00 at% in the dielectric green sheets of the 200th layer (central region) in the stacking direction. The Sn content relative to Ti was 0.50 at% in the dielectric green sheets of the 100th layer (outer layer) on the top side in the stacking direction and the 100th layer (outer layer) on the bottom side in the stacking direction. Other conditions were the same as in Example 1.

[0062] After firing, the atomic concentration ratio of Sn to Ti was 0.009 in the dielectric layer of the 200th layer (central region) at the center of the stacking direction. The atomic concentration ratio of Sn to Ti was 0.004 in the dielectric layer of the 100th layer (outer layer) at the top and the 100th layer (outer layer) at the bottom of the stacking direction.

[0063] Example 3 In Example 3, the Sn content relative to Ti was 2.00 at% in the dielectric green sheets of the 200th layer (central region) in the stacking direction. The Sn content relative to Ti was 1.00 at% in the dielectric green sheets of the top 100th layer (outer layers) in the stacking direction and the bottom 100th layer (outer layers) in the stacking direction. Other conditions were the same as in Example 1.

[0064] After firing, the atomic concentration ratio of Sn to Ti was 0.019 in the dielectric layer of the 200th layer (central region) at the center of the stacking direction. The atomic concentration ratio of Sn to Ti was 0.010 in the dielectric layer of the 100th layer (outer layer) at the top and the 100th layer (outer layer) at the bottom of the stacking direction.

[0065] Example 4 In Example 4, the Sn content relative to Ti was 2.00 at% in the dielectric green sheets of the 200th layer (central region) in the stacking direction. The Sn content relative to Ti was 1.50 at% in the dielectric green sheets of the 100th layer (outer layer) on the top side in the stacking direction and the 100th layer (outer layer) on the bottom side in the stacking direction. Other conditions were the same as in Example 1.

[0066] After firing, the atomic concentration ratio of Sn to Ti was 0.020 in the dielectric layer of the 200th layer (central region) at the center of the stacking direction. The atomic concentration ratio of Sn to Ti was 0.016 in the dielectric layer of the 100th layer (outer layer) at the top and the 100th layer (outer layer) at the bottom of the stacking direction.

[0067] (Comparative Example 1) In Comparative Example 1, the Sn content relative to Ti was 0.00 at% in the dielectric green sheets of the 200th layer (central region) in the stacking direction. The Sn content relative to Ti was 0.00 at% in the dielectric green sheets of the upper 100th layer (outer layer) in the stacking direction and the lower 100th layer (outer layer) in the stacking direction. In other words, no Sn was added to any of the dielectric green sheets. The other conditions were the same as in Example 1.

[0068] After firing, the atomic concentration ratio of Sn to Ti was 0.000 in the dielectric layer of the 200th layer (central region) at the center of the stacking direction. The atomic concentration ratio of Sn to Ti was 0.000 in the dielectric layer of the 100th layer (outer layer) at the top of the stacking direction and the dielectric layer of the 100th layer (outer layer) at the bottom of the stacking direction.

[0069] (Comparative Example 2) In Comparative Example 2, the Sn content relative to Ti was 0.50 at% in the dielectric green sheets of the 200th layer (central region) in the stacking direction. The Sn content relative to Ti was 1.00 at% in the dielectric green sheets of the upper 100th layer (outer layer) in the stacking direction and the lower 100th layer (outer layer) in the stacking direction. Other conditions were the same as in Example 1.

[0070] After firing, the atomic concentration ratio of Sn to Ti was 0.005 in the dielectric layer of the 200th layer (central region) at the center of the stacking direction. The atomic concentration ratio of Sn to Ti was 0.010 in the dielectric layer of the 100th layer (outer layer) at the top and the 100th layer (outer layer) at the bottom of the stacking direction.

[0071] (Comparative Example 3) In Comparative Example 3, the Sn content relative to Ti was 1.00 at% in the dielectric green sheets of the 200th layer (central region) in the stacking direction. The Sn content relative to Ti was 1.00 at% in the dielectric green sheets of the upper 100th layer (outer layer) in the stacking direction and the lower 100th layer (outer layer) in the stacking direction. Other conditions were the same as in Example 1.

[0072] After firing, the atomic concentration ratio of Sn to Ti was 0.009 in the dielectric layer of the 200th layer (central region) at the center of the stacking direction. The atomic concentration ratio of Sn to Ti was 0.010 in the dielectric layer of the 100th layer (outer layer) at the top and the 100th layer (outer layer) at the bottom of the stacking direction.

[0073] Comparative Example 4 In Comparative Example 4, the Sn content relative to Ti was 1.00 at% in the dielectric green sheets of the 200th layer (central region) in the stacking direction. The Sn content relative to Ti was 2.00 at% in the dielectric green sheets of the upper 100th layer (outer layer) in the stacking direction and the lower 100th layer (outer layer) in the stacking direction. Other conditions were the same as in Example 1.

[0074] After firing, the atomic concentration ratio of Sn to Ti was 0.011 in the dielectric layer of the 200th layer (central region) at the center of the stacking direction. The atomic concentration ratio of Sn to Ti was 0.018 in the dielectric layer of the 100th layer (outer layer) at the top and the 100th layer (outer layer) at the bottom of the stacking direction.

[0075] (Comparative Example 5) In Comparative Example 5, the Sn content relative to Ti was 2.00 at% in the dielectric green sheets of the 200th layer (central region) in the stacking direction. The Sn content relative to Ti was 2.00 at% in the dielectric green sheets of the upper 100th layer (outer layer) in the stacking direction and the lower 100th layer (outer layer) in the stacking direction. Other conditions were the same as in Example 1.

[0076] After firing, the atomic concentration ratio of Sn to Ti was 0.020 in the dielectric layer of the 200th layer (central region) at the center of the stacking direction. The atomic concentration ratio of Sn to Ti was 0.020 in the dielectric layer of the 100th layer (outer layer) at the top of the stacking direction and the dielectric layer of the 100th layer (outer layer) at the bottom of the stacking direction.

[0077] (Comparative Example 6) In Comparative Example 6, the Sn content relative to Ti was 2.00 at% in the dielectric green sheets of the 200th layer (central region) in the stacking direction. The Sn content relative to Ti was 4.00 at% in the dielectric green sheets of the 100th layer (outer layer) on the top side in the stacking direction and the 100th layer (outer layer) on the bottom side in the stacking direction. Other conditions were the same as in Example 1.

[0078] After firing, the atomic concentration ratio of Sn to Ti was 0.021 in the dielectric layer of the 200th layer (central region) at the center of the stacking direction. The atomic concentration ratio of Sn to Ti was 0.037 in the dielectric layer of the 100th layer (outer layer) at the top and the 100th layer (outer layer) at the bottom of the stacking direction.

[0079] The lifespan (50% value) was measured for each of Examples 1 to 4 and Comparative Examples 1 to 6. The measurement was performed by applying DC 8 V in a thermostatic chamber at 120°C and measuring the time when the current value exceeded 2 mA as the lifespan of each chip. Measurements were performed on 100 chips of each type.

[0080] The capacitance was measured for each of Examples 1 to 4 and Comparative Examples 1 to 6. The measurement was performed using an LCR meter at 120 Hz and 0.5 Vrms. The measurement was performed after keeping the sample in a thermostatic chamber at 150°C for 1 hour, then returning it to room temperature and 24 hours later.

[0081] For each of Examples 1 to 4 and Comparative Examples 1 to 6, the continuity ratio of the internal electrode layers in the central region in the stacking direction was measured, and the continuity of the internal electrode layers in the outer layers was measured. The measurement method involved cutting the chip near the center with a slicer, and polishing the cross section with an ion milling device until it became a clean cross section. A region of interest in the chip cross section was imaged with an SEM, and the sum of the electrode lengths in each electrode layer was divided by the width of the SEM image to calculate the continuity ratio. Images were taken with the SEM at 5k magnification, at three locations shifted in the in-plane direction of the stacking, and the average value of 15 SEM images was used, with n being 5.

[0082] The measurement results are shown in Table 1. A test piece with a 10% or greater improvement in lifespan and a capacity decline rate of 10% or less compared to the results of Comparative Example 1, in which no Sn was added, was judged as passing (good). Comparative Examples 2 to 6 had a longer lifespan than Comparative Example 1. This is believed to be due to the addition of Sn to the dielectric layers. However, Comparative Examples 2 to 6 had a capacity decline rate of more than 10% compared to Comparative Example 1, and were judged as failing (bad). This is believed to be due to the fact that the Sn concentration in the outer layers was higher than that in the central region, which promoted spheroidization of the outer internal electrode layers and increased the disorder of the laminated structure. In contrast, Examples 1 to 4 had a longer lifespan than Comparative Example 1, and a capacity decline rate of 10% or less, and were judged as passing (good). This is believed to be due to the fact that the Sn concentration in the outer layers was lower than that in the central region, which suppressed spheroidization of the outer internal electrode layers. Comparative Example 1 did not achieve a sufficient lifespan and was therefore judged as failing (bad). [Table 1]

[0083] Although the embodiments of the present invention have been described in detail above, the present invention is not limited to such specific embodiments, and various modifications and variations are possible within the scope of the gist of the present invention as defined in the claims.

[0084] The inventions described in the claims of the original application of this application are as follows: [1] It has a laminated structure in which multiple internal electrode layers and three or more dielectric layers whose main component is ceramic are alternately laminated, the three or more dielectric layers contain Sn, A ceramic electronic component characterized in that, in at least two of the three or more dielectric layers, the Sn concentration of the dielectric layers at the ends of the stacking direction is lower than that of the dielectric layers at the center of the stacking direction. [2] The ceramic electronic component according to [1], characterized in that, from the dielectric layer at the center in the stacking direction to the dielectric layer at the outermost end in the stacking direction, the Sn concentration in the outermost dielectric layer is the lowest. [3] The ceramic electronic component according to [1], characterized in that the Sn concentration of each of the plurality of dielectric layers extending from the outermost end to the center in the stacking direction is lower than the Sn concentration of each of the remaining dielectric layers in the center in the stacking direction. [4] The ceramic electronic component according to [1], characterized in that the Sn concentration of each dielectric layer from the central dielectric layer in the stacking direction to the outermost dielectric layer in the stacking direction increases stepwise or gradually from the central dielectric layer in the stacking direction to the outermost dielectric layer in the stacking direction. [5] The ceramic electronic component according to any one of [1] to [4], characterized in that the ratio of the minimum Sn concentration to the maximum Sn concentration in each of the three or more dielectric layers is 2:3 or less. [6] the main component ceramic of the three or more dielectric layers has a perovskite structure, The ceramic electronic component according to any one of [1] to [5], characterized in that, for the Sn concentration in each of the three or more dielectric layers, the difference between the minimum Sn / B site element ratio and the maximum Sn / B site element ratio is 0.001 or more. [7] the three or more dielectric layers contain barium titanate as a main component ceramic; The ceramic electronic component according to any one of [1] to [6], wherein the main component metal of the plurality of internal electrode layers is nickel. [8] The ceramic electronic component according to any one of [1] to [7], wherein the thickness of the three or more dielectric layers is 5 μm or less. [9] The ceramic electronic component according to any one of [1] to [8], wherein the Sn concentration in the three or more dielectric layers is 5 at % or less.

[10] The ceramic electronic component according to any one of [1] to [9], wherein the Sn concentration in the three or more internal electrode layers is 0.1 at % or more.

[11] forming an internal electrode pattern containing a metal powder on a dielectric green sheet containing a ceramic powder and an Sn source to form a lamination unit; forming a laminate by stacking three or more of the lamination units; and firing the laminate, A method for manufacturing a ceramic electronic component, characterized in that, in at least two layers of the dielectric green sheets before firing, the Sn concentration relative to the main component ceramic is made lower in the dielectric green sheets closer to the ends in the stacking direction than in the dielectric green sheets closer to the center in the stacking direction. [Explanation of symbols]

[0085] 10 stacked chips 11 Dielectric layer 12 Internal electrode layer 13 Cover Layer 14 capacity area 15 End Margin 16 Side Margin 20a,20b external electrode 51 Base material 52 Dielectric green sheet 53 Internal electrode pattern 100 Multilayer ceramic capacitors

Claims

1. a laminated chip including a plurality of internal electrode layers and a plurality of dielectric layers alternately stacked with the plurality of internal electrode layers in a stacking direction; a first external electrode provided on a first end surface of the laminated chip; a second external electrode provided on a second end surface of the laminated chip that faces the first end surface; Equipped with the plurality of internal electrode layers include a plurality of first internal electrode layers and a plurality of second internal electrode layers, each of the plurality of first internal electrode layers is connected to the first external electrode; each of the plurality of second internal electrode layers is connected to the second external electrode; the laminated chip includes a first outer layer region extending from an upper surface of the laminated chip along the stacking direction, a second outer layer region extending from a lower surface of the laminated chip along the stacking direction, and a central region provided between the first outer layer region and the second outer layer region in the stacking direction, a first outer dielectric layer in the first outer region among the plurality of dielectric layers has a lower Sn concentration than a central dielectric layer in the central region among the plurality of dielectric layers; Ceramic electronic components.

2. a second outer dielectric layer in the second outer layer region among the plurality of dielectric layers has a lower Sn concentration than the central dielectric layer; The ceramic electronic component according to claim 1 .

3. the stacked chip has the top surface, the bottom surface, the first end surface, the second end surface, a first side surface, and a second side surface; the first side surface and the second side surface face each other and are connected to the top surface, the bottom surface, the first end surface, and the second end surface, respectively; a capacitance region where the plurality of first internal electrode layers and the plurality of second internal electrode layers overlap when viewed from the stacking direction, a first side margin between the first side surface of the laminated chip and the capacitance region, and a second side margin between the second side surface of the laminated chip and the capacitance region, the Sn concentration of the first outer dielectric layer in a region where the first side margin and the first outer region overlap is lower than the Sn concentration of the central dielectric layer in the central region; The ceramic electronic component according to claim 1 .

4. the Sn concentration of the second outer dielectric layer in a region where the first side margin and the second outer region overlap is lower than the Sn concentration of the central dielectric layer in the central region; The ceramic electronic component according to claim 3 .

5. the first outer layer region occupies 5% or more of the stacked chip in the stacking direction; The ceramic electronic component according to claim 1 .

6. the first outer layer region occupies 10% or more of the stacked chip in the stacking direction; The ceramic electronic component according to claim 1 .

7. the first outer layer region occupies 40% or less of the stacked chip in the stacking direction; The ceramic electronic component according to claim 1 .

8. the first outer layer region occupies 30% or less of the stacked chip in the stacking direction; The ceramic electronic component according to claim 1 .

9. the first outer layer region occupies 20% or less of the stacked chip in the stacking direction; The ceramic electronic component according to claim 1 .

10. a continuity ratio of the plurality of internal electrode layers in the first outer layer region is greater than a continuity ratio of the plurality of internal electrode layers in the central region; The ceramic electronic component according to claim 1 .

11. a continuity ratio of the plurality of internal electrode layers in the second outer layer region is greater than a continuity ratio of the plurality of internal electrode layers in the central region; The ceramic electronic component according to claim 10.

12. a continuity rate of the plurality of internal electrode layers in the first outer layer region is 90% or more; The ceramic electronic component according to claim 10.

13. The thickness of each of the plurality of internal electrode layers is 0.01 μm or more and 5 μm or less. The ceramic electronic component according to claim 1 .

14. The thickness of each of the plurality of internal electrode layers is 0.03 μm or more and 3 μm or less. The ceramic electronic component according to claim 13.

15. The thickness of each of the plurality of internal electrode layers is 0.1 μm or more and 1 μm or less. The ceramic electronic component according to claim 14.

16. Sn is solid-solved in the main component ceramic of the plurality of dielectric layers. The ceramic electronic component according to claim 1 .

17. further comprising an upper cover layer covering the upper surface of the laminated chip; The ceramic electronic component according to claim 1 .

18. a lower cover layer covering the lower surface of the laminated chip; The ceramic electronic component according to claim 1 .

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