Display device

Abstract

To prevent disconnection caused by electrostatic discharge in a display area.SOLUTION: The display apparatus 10 includes the display area AA, the non-display area NAA, the first lines 24 extending in the first direction across the display area AA and the non-display area NAA, and the second lines 29A extending in the second direction intersecting the first direction in the non-display area NAA, and the first lines 24 and the second lines 29A are formed of different parts of the first conductive film. The first lines 24 include the first wiring portions 24A in the display region AA and the second wiring portions 24B in the non-display region NAA. Each of the second wiring portions 24B includes a first end portion 29A spaced apart from the second wiring portion 24B1 in the first direction, a first line width portion 24B1 closer to the first wiring portion 24A than the first end portion 24B2 in the first direction, and a second line width portion 24B2 continuous with the first line width portion 24B2 and narrower than the first line width portion 24B3.SELECTED DRAWING: Figure 3

Description

[Technical Field]

[0001] The technology disclosed in this specification relates to a display device that is less susceptible to disconnections caused by electrostatic discharge within the display area. [Background technology]

[0002] One example of a conventionally known display device is that described in Patent Document 1. The display device described in Patent Document 1 comprises a first electrode substrate including a plurality of first electrode wirings arranged substantially parallel to one another on a first insulating substrate and a plurality of pixel electrodes arranged in a matrix and electrically coupled to the first electrode wirings via switch elements, a second electrode substrate arranged on a second insulating substrate and including counter electrodes facing the pixel electrodes, and a light modulation layer held between the pixel electrodes and the counter electrode, and at least one of the adjacent first electrode wirings has at least one discharge protrusion facing the other. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Publication No. 8-234227 Summary of the Invention [Problem to be solved by the invention]

[0004] In the above-mentioned Patent Document 1, a protrusion is formed on a wiring portion as the above-mentioned "discharge protrusion," and the protrusion is positioned at a location where no conductive pattern such as a signal line on another layer is formed, thereby preventing a short circuit between a conductive pattern on another layer, such as a signal line, and a scanning line or auxiliary capacitance line due to damage to the insulating film caused by discharge. However, in Patent Document 1, the protrusion is formed on each of adjacent scanning line inspection pads and auxiliary capacitance line connection / inspection pads. Therefore, the technology described in Patent Document 1 cannot be applied to display devices that do not have a "configuration in which two inspection pads are arranged adjacent to each other." If the technology described in Patent Document 1 could not be applied, there was a risk of wire breakage due to electrostatic discharge in the display area where an image is displayed.

[0005] The technology described in this specification was developed based on the above circumstances, and aims to make it difficult for disconnections caused by electrostatic discharge to occur within the display area. [Means for solving the problem]

[0006] (1) A display device related to the technology described in this specification includes a display area where an image is displayed, a non-display area where the image is not displayed, a first wiring arranged across the display area and the non-display area and extending along a first direction, and a second wiring arranged in the non-display area and extending along a second direction intersecting the first direction, wherein the first wiring and the second wiring are each made of different parts of a first conductive film, and the first wiring is formed by connecting a first wiring configuration portion arranged in the display area and a second wiring configuration portion arranged in the non-display area, and the second wiring configuration portion has a first end portion arranged at a distance from the second wiring in the first direction, a first line width portion located closer to the first wiring configuration portion in the first direction than the first end portion, and a second line width portion connected to the first line width portion and narrower than the first line width portion.

[0007] (2) In addition to the above (1), the display device may further include a third wiring arranged in the display area and extending along the second direction, and a first insulating film arranged on the upper side of the first conductive film, the third wiring being made of a second conductive film arranged on the upper side of the first insulating film and intersecting with the first wiring configuration via the first insulating film, and a first contact hole connecting the third wiring and the first wiring configuration may be provided in the first insulating film at a position overlapping both the third wiring and the first wiring configuration.

[0008] (3) Furthermore, in addition to (1) or (2), the display device may further include an inspection wiring arranged in the non-display area, extending along the first direction and transmitting an inspection signal, and a first insulating film arranged on the upper side of the first conductive film, wherein the second wiring, the inspection wiring and the second wiring configuration are arranged in pairs on either side of the display area in the first direction, and the paired inspection wirings are each made of a second conductive film arranged on the upper side of the first insulating film, and have a second end that intersects with the second wiring via the first insulating film and overlaps with the first end, and a second contact hole that connects the first end and the second end may be provided in the first insulating film at a position that overlaps with both the first end and the second end.

[0009] (4) In addition to any one of (1) to (3) above, the display device may further include a fourth line width portion connected to the third line width portion and narrower than the third line width portion, wherein the first wiring configuration portion has a third line width portion.

[0010] (5) In addition to (4), the display device may further include a fourth wiring arranged in the display area and extending along the second direction, and a first insulating film arranged on the upper side of the first conductive film, and the fourth wiring may be made of a second conductive film arranged on the upper side of the first insulating film and may intersect with the fourth line width portion via the first insulating film.

[0011] (6) Furthermore, in addition to any one of (1) to (5), the display device may be configured such that the second wiring configuration has a plurality of the first line width portions and the second line width portions, and the first line width portions and the second line width portions are alternately arranged in the first direction. [Effects of the Invention]

[0012] According to the technology described in this specification, it is possible to make it difficult for disconnections to occur in the display area due to electrostatic discharge. [Brief explanation of the drawings]

[0013] [Figure 1] 1 is a plan view of an electronic paper display according to a first embodiment; [Figure 2] FIG. 1 is a circuit diagram showing the electrical configuration of an array substrate that constitutes an electronic paper display according to a first embodiment. [Figure 3] FIG. 1 is a plan view showing a pixel arrangement of an array substrate according to a first embodiment; [Figure 4] 4 is a cross-sectional view of the array substrate according to the first embodiment taken along line iv-iv in FIG. 3. [Figure 5] 4 is a cross-sectional view of the array substrate according to the first embodiment taken along line vv in FIG. 3. [Figure 6] 4 is a cross-sectional view of the array substrate according to the first embodiment taken along line vi-vi in ​​FIG. 3 . [Figure 7] 7 is a cross-sectional view of the array substrate according to the first embodiment taken along line vii-vii in FIG. 3. [Figure 8] FIG. 1 is a plan view showing a pixel array of an array substrate according to a first embodiment, in which a configuration made of a first metal film is extracted. [Figure 9] FIG. 1 is a plan view showing a pixel arrangement of an array substrate according to the first embodiment, in which a configuration made of a second metal film is extracted. [Figure 10] FIG. 1 is a plan view showing a pixel array of an array substrate according to the first embodiment, in which a configuration made of a third metal film is extracted. DETAILED DESCRIPTION OF THE INVENTION

[0014] <Embodiment 1> A first embodiment will be described with reference to Figs. 1 to 10. In this embodiment, an electronic paper display (display device, EPD: Electronic Paper Display) 10 will be illustrated. Note that X-axis, Y-axis, and Z-axis are shown in a portion of each drawing, and each axis direction is depicted as being the direction shown in each drawing. Also, the upper side of Figs. 4 to 7 is the front side, and the lower side of the drawings is the back side.

[0015] As shown in Fig. 1, the electronic paper display 10 has a vertically long rectangular shape. In this embodiment, the electronic paper display 10 operates using a microcapsule electrophoresis method. The central portion of the main surface of the electronic paper display 10 is a display area AA where an image is displayed. In contrast, the frame-shaped outer peripheral portion of the main surface of the electronic paper display 10 surrounding the display area AA is a non-display area NAA where no image is displayed.

[0016] As shown in FIG. 1, the electronic paper display 10 includes an array substrate 21 serving as a backplane and a counter substrate 20 bonded to the front side of the array substrate 21, facing the array substrate 21. Both the counter substrate 20 and the array substrate 21 are made of, for example, a substantially transparent synthetic resin substrate (resin substrate). A microcapsule layer (not shown) containing a large number of microcapsules encapsulating charged particles is interposed between the counter substrate 20 and the array substrate 21. The microcapsules contain at least positively charged particles (e.g., titanium oxide particles) that are white pigments and negatively charged particles (e.g., carbon black particles) that are black pigments. A counter electrode (not shown) is provided on the inner surface of the counter substrate 20 (the surface facing the array substrate 21). The counter electrode is made of a transparent electrode material and is formed solidly on the inner surface of the counter substrate 20, extending across at least the entire display area AA.

[0017] As shown in FIG. 1, the short and long sides of the counter substrate 20 are shorter than those of the array substrate 21. The counter substrate 20 is disposed at a position offset to one side (upper side in FIG. 1) in the Y-axis direction relative to the array substrate 21. Therefore, the array substrate 21 has a frame-shaped portion 21A that is not covered by the counter substrate 20 and is exposed. The other side (lower side in FIG. 1) of the frame-shaped portion 21A in the Y-axis direction is wider than the other side. As described below, a driver 11 and a flexible substrate 12 for supplying various signals are mounted on the wider side of the frame-shaped portion 21A of the array substrate 21. The non-display area NAA includes at least the entire frame-shaped portion 21A of the array substrate 21 and a portion of the counter substrate 20 that surrounds the display area AA. The display area AA is rectangular and slightly smaller than the counter substrate 20. A frame-shaped capacitance trunk wiring (common trunk wiring) 29 that is slightly larger than the display area AA and slightly smaller than the counter substrate 20 is provided in a portion of the array substrate 21 that is covered by the counter substrate 20. The capacitance trunk wiring 29 includes a pair of first trunk wiring components (second wiring) 29A extending along the Y-axis direction and a pair of second trunk wiring components 29B extending along the X-axis direction, and each end of each first trunk wiring component 29A and each end of each second trunk wiring component 29B are connected to each other.

[0018] The driver 11 is an LSI chip with an internal drive circuit. The driver 11 processes various signals transmitted by the flexible substrate 12. The driver 11 is disposed adjacent to one side of the display area AA in the Y-axis direction (the lower side in FIG. 1) on a wide side of the frame portion 21A of the array substrate 21, and is sandwiched between the flexible substrate 12 and the display area AA in the Y-axis direction. The driver 11 has a horizontally elongated rectangular shape in plan view. The driver 11 can supply various signals to various wirings and the like provided on the array substrate 21. The flexible substrate 12 is configured by forming multiple wiring patterns on a base material made of an insulating and flexible synthetic resin material (e.g., polyimide resin). One end of the flexible substrate 12 is connected to the wide side of the frame portion 21A of the array substrate 21, and the other end is connected to an external circuit board (e.g., a control board) (not shown).

[0019] Next, the electrical configuration of the array substrate 21 will be described with reference to FIG. 2. As shown in FIG. 2, at least TFTs (thin film transistors, switching elements) 22 and pixel electrodes 23 are provided on the inner surface of the array substrate 21 in the display area AA. The TFTs 22 and pixel electrodes 23 are arranged in a matrix (rows and columns) with multiple TFTs 22 and multiple pixel electrodes 23 spaced apart along the X-axis and Y-axis directions. Gate wiring (first wiring, scanning wiring) 24, source wiring (fourth wiring, image wiring, signal wiring) 25, capacitor branch wiring 26, and gate connection wiring (third wiring) 27 are arranged around the TFTs 22 and pixel electrodes 23, intersecting each other at right angles. The TFT 22 includes a gate electrode 22A connected to the gate wiring 24, a source electrode 22B connected to the source wiring 25, a drain electrode 22C connected to the pixel electrode 23, and a semiconductor portion 22D connected to the source electrode 22B and the drain electrode 22C. The TFT 22 is driven based on a scanning signal supplied to the gate electrode 22A by the gate wiring 24. This scanning signal includes a potential higher than the threshold voltage of the TFT 22. Then, a potential related to the image signal supplied to the source electrode 22B by the source line 25 is supplied to the drain electrode 22C via the semiconductor portion 22D. As a result, the pixel electrode 23 is charged to the potential related to the image signal. In addition, a capacitance electrode 28 that forms a capacitance with the pixel electrode 23 is provided on the inner surface of the array substrate 21 in the display area AA. In addition, a capacitance main line 29 and an inspection line 30 are provided on the inner surface of the array substrate 21 in the non-display area NAA.

[0020] As shown in FIG. 2, the gate lines 24 and the capacitive branch lines 26 both extend along the X-axis direction (first direction). The gate lines 24 and the capacitive branch lines 26 are arranged alternately and repeatedly at intervals in the Y-axis direction (second direction intersecting the first direction). One TFT 22 and one pixel electrode 23 are sandwiched between adjacent gate lines 24 and capacitive branch lines 26 at intervals in the Y-axis direction. The number of gate lines 24 and capacitive branch lines 26 installed is approximately half the number of pixel electrodes 23 arranged in the Y-axis direction. The gate lines 24 are arranged across the display area AA and the non-display area NAA, and are connected to the gate electrodes 22A of the TFTs 22 in the display area AA. The gate wiring 24 is connected to the gate electrode 22A of the TFT 22 connected to the pixel electrode 23 located above the gate wiring 24 (upper side in FIG. 2), and to the gate electrode 22A of the TFT 22 connected to the pixel electrode 23 located below the gate wiring 24 (lower side in FIG. 2). In other words, a scanning signal is supplied to the gate electrodes 22A of the TFTs 22 connected to the pixel electrodes 23 in two rows adjacent to each other in the Y-axis direction by one gate wiring 24. The end of the gate wiring 24 that is drawn out to the non-display area NAA is connected to the test wiring 30.

[0021] The inspection wiring 30 is routed from the connection point with the gate wiring 24 in the non-display area NAA to an inspection terminal (not shown) provided at a predetermined position in the non-display area NAA and is connected to the inspection terminal. An inspection signal is input to the inspection terminal from an inspection pad provided on an external inspection device. The inspection signal input to the inspection terminal is supplied to the gate wiring 24 via the inspection wiring 30. Whether or not a break has occurred in the gate wiring 24 can be inspected based on this inspection signal. The inspection wirings 30 are arranged in pairs on either side of the display area AA in the X-axis direction, and the paired inspection wirings 30 are connected to both ends of the gate wiring 24 in the X-axis direction. Therefore, an inspection signal can be supplied to the gate wiring 24 from each of the paired inspection wirings 30. The number of inspection wirings 30 installed is twice the number of gate wirings 24 installed.

[0022] As shown in FIG. 2 , the capacitive branch line 26 is disposed across the display area AA and the non-display area NAA and is connected to the capacitive electrode 28 in the display area AA. The end of the capacitive branch line 26 extending into the non-display area NAA is connected to a first trunk line component 29A of the capacitive trunk line 29. The first trunk line component 29A extends along the Y-axis direction and connects all of the capacitive branch lines 26 spaced apart along the Y-axis. A predetermined reference potential signal is supplied to the capacitive branch line 26 from the first trunk line component 29A. Therefore, the reference potential signal from the first trunk line component 29A is supplied to the capacitive electrode 28 via the capacitive branch line 26. The capacitive trunk line 29 is connected to the driver 11 or the flexible substrate 12, and the reference potential signal is supplied from the driver 11 or an external circuit board. The capacitive electrode 28, to which the reference potential signal from the capacitive branch line 26 is supplied, forms electrostatic capacitance with the pixel electrode 23, thereby maintaining the potential of the charged pixel electrode 23. The first trunk wiring components 29A are arranged in pairs on either side of the display area AA in the X-axis direction, and the paired first trunk wiring components 29A are connected to both ends in the X-axis direction of the capacitive branch wiring 26. Therefore, it is possible to supply a reference potential signal to the capacitive branch wiring 26 from each of the paired first trunk wiring components 29A.

[0023] As shown in FIG. 2, the source lines 25 and the gate connection lines 27 both extend along the Y-axis direction. Two source lines 25 are arranged between adjacent pixel electrodes 23 in the X-axis direction. Source lines 25 are also arranged at positions spaced apart on the non-display area NAA side from pixel electrodes 23 located at the ends of the display area AA in the X-axis direction. Therefore, the number of source lines 25 is approximately twice the number of pixel electrodes 23 arranged in the X-axis direction. The source lines 25 are arranged across the display area AA and the non-display area NAA, and the ends of the lines extending into the non-display area NAA are connected to the driver 11. Image signals are supplied to the source lines 25 from the driver 11.

[0024] As shown in FIG. 2 , the gate connection lines 27 are arranged one by one between adjacent pixel electrodes 23 in the X-axis direction. Furthermore, the gate connection lines 27 are also arranged at positions spaced apart from the source lines 25 located at the ends of the display area AA in the X-axis direction toward the non-display area NAA. The number of gate connection lines 27 is approximately the same as the number of pixel electrodes 23 arranged in the X-axis direction, and is at least equal to or greater than the number of gate lines 24. The gate connection lines 27 are arranged across the display area AA and the non-display area NAA and are connected to the gate lines 24 in the display area AA. One or more gate connection lines 27 are connected to each of the gate lines 24 arranged in the display area AA. The ends of the gate connection lines 27 extending into the non-display area NAA are connected to the driver 11. Scanning signals are supplied to the gate connection lines 27 from the driver 11. Therefore, scanning signals from the driver 11 are supplied to the gate lines 24 via the gate connection lines 27.

[0025] The detailed planar configuration of the array substrate 21 will be described with reference to Fig. 3. The gate electrode 22A of the TFT 22 arranged in the display area AA of the array substrate 21 is provided so as to extend along the Y-axis direction from a portion of the gate line 24 near the intersection with the source line 25, as shown in Fig. 3. The source electrode 22B of the TFT 22 is provided so as to extend along the X-axis direction from a portion of the source line 25 near the intersection with the gate line 24. The source electrode 22B is arranged at one end of the TFT 22 in the X-axis direction. The source electrode 22B overlaps a portion of the gate electrode 22A and is connected to the semiconductor portion 22D.

[0026] 3, the drain electrode 22C of the TFT 22 is disposed at a position spaced apart from the source electrode 22B in the X-axis direction, i.e., at the other end of the TFT 22 in the X-axis direction. The drain electrode 22C extends along the X-axis direction, and an end of the drain electrode 22C on the source electrode 22B side is disposed so as to overlap with a portion of the gate electrode 22A and is connected to the semiconductor portion 22D. The end of the drain electrode 22C opposite to the source electrode 22B side is connected to the pixel electrode 23. The semiconductor portion 22D of the TFT 22 has a horizontally elongated shape extending along the X-axis direction. The semiconductor portion 22D is disposed so as to overlap with the gate electrode 22A in a plan view. One end portion of the semiconductor portion 22D in the X-axis direction is connected to the source electrode 22B, and the other end portion in the X-axis direction is connected to the drain electrode 22C. The TFTs 22 include a TFT 22 adjacent to the gate line 24 on the upper side of FIG. 3 and a TFT 22 adjacent to the gate line 24 on the lower side of FIG. 3, and these TFTs 22 are configured inverted vertically and horizontally in FIG. 3.

[0027] As shown in FIG. 3, the pixel electrodes 23 arranged in the display area AA of the array substrate 21 are located in an area surrounded by gate lines 24, capacitive branch lines 26, and two source lines 25. The pixel electrodes 23 are generally rectangular and vertically elongated. The pixel electrodes 23 have excellent light reflectivity and are arranged opposite a counter electrode provided on the counter substrate 20 (see FIG. 1) via a microcapsule layer. When the pixel electrodes 23 are charged, charged particles within the microcapsules move according to the polarity and potential of the pixel electrodes 23. Light incident on the microcapsule layer from outside the electronic paper display 10 through the counter substrate 20 is either transmitted or absorbed by the charged particles located on the counter substrate 20 side in the Z-axis direction within the microcapsules. This controls the amount of reflected light for each pixel electrode 23, allowing a predetermined image to be displayed in the display area AA. Incidentally, a color filter can be installed on the counter substrate 20 to display a color image.

[0028] As shown in FIG. 3 , the capacitance electrode 28 extends along the Y-axis direction and overlaps the pixel electrodes 23 aligned along the Y-axis direction in a plan view. The capacitance electrode 28 extends across substantially the entire length of the display area AA in the Y-axis direction and overlaps all of the pixel electrodes 23 in one column. Specifically, the capacitance electrode 28 includes a capacitance electrode main body 28A that overlaps two pixel electrodes 23 sandwiched between two adjacent gate lines 24 spaced apart in the Y-axis direction, a connecting portion 28B connected to the capacitance electrode main body 28A, and a covering portion 28C connected to the capacitance electrode main body 28A and covering a portion of the TFT 22. The capacitance electrode main body 28A extends along the Y-axis direction to straddle the two pixel electrodes 23 and cross the capacitance branch lines 26 extending along the X-axis. A plurality of capacitance electrode main bodies 28A are arranged side by side in the Y-axis direction at intervals equal to the connecting portions 28B. The connecting portions 28B are arranged in a row at intervals equal to the capacitance electrode main body 28A in the Y-axis direction, connecting two adjacent capacitance electrode main bodies 28A with a gap in the Y-axis direction. The connecting portions 28B are connected to the approximate center of the capacitance electrode main body 28A in the X-axis direction. The covering portions 28C extend along the Y-axis direction from the connection points with the capacitance electrode main body 28A toward the TFT 22 and cover at least the semiconductor portion 22D of the TFT 22. The covering portions 28C have a light-blocking property, which can prevent light from being directly incident on the semiconductor portion 22D. This reduces the degradation of the characteristics of the TFT 22. A plurality of capacitance electrodes 28 having such a configuration are arranged in a row at intervals in the X-axis direction. The number of capacitance electrodes 28 is the same as the number of pixel electrodes 23 arranged in the X-axis direction (the number of columns).

[0029] As shown in FIG. 3 , in the display area AA, the capacitive branch wiring 26 extends substantially straight along the X-axis direction and is arranged to cross all of the capacitive electrodes 28 aligned along the X-axis direction. The capacitive branch wiring 26 is connected to all of the capacitive electrodes 28 aligned along the X-axis direction. In the non-display area NAA, the capacitive branch wiring 26 is bent in a crank shape and reaches a first trunk wiring portion 29A of the capacitive trunk wiring 29, where it is connected to the first trunk wiring portion 29A. The first trunk wiring portion 29A of the capacitive trunk wiring 29 extends substantially straight along the Y-axis direction and is connected to an end (connection portion 26A, described later) of the capacitive branch wiring 26 extending along the X-axis direction. The first trunk wiring portion 29A intersects with the test wiring 30 extending along the X-axis direction.

[0030] 3, in the display area AA, the source lines 25 and the gate connection lines 27 both extend substantially straight along the Y-axis direction and intersect with all of the gate lines 24 and capacitance branch lines 26 aligned along the Y-axis direction. The source lines 25 are arranged at a predetermined distance from the pixel electrodes 23 and capacitance electrodes 28 in the X-axis direction. The gate connection lines 27 are arranged at a distance from the source lines 25 in the X-axis direction that is wider than the distance between the source lines 25 and the pixel electrodes 23 and capacitance electrodes 28. The gate connection lines 27 have a wider line width than the source lines 25. The detailed configuration of the gate lines 24 will be explained again later.

[0031] Here, various films laminated on the inner surface side of the array substrate 21 will be described with reference to Fig. 4. Fig. 4 is a cross-sectional view of the vicinity of the TFT 22 on the array substrate 21. As shown in Fig. 4, the array substrate 21 has at least a first metal film (first conductive film), a gate insulating film (first insulating film) 31, a semiconductor film, a second metal film (second conductive film), a first interlayer insulating film (second insulating film) 32, a third metal film (third conductive film), and a second interlayer insulating film 33 laminated thereon in this order from the lower layer side (resin substrate side).

[0032] The first metal film, the second metal film, and the third metal film each have electrical conductivity and light-blocking properties by being a single layer film made of one type of metal material selected from copper, titanium, aluminum, molybdenum, tungsten, etc., or a laminated film or alloy made of different types of metal materials. The first metal film constitutes part of the pixel electrode 23, part of the gate line 24, the gate electrode 22A of the TFT 22, part of the gate connection line 27, part of the capacitor trunk line 29, etc. The second metal film constitutes part of the gate line 24, the source line 25, the source electrode 22B and drain electrode 22C of the TFT 22, part of the gate connection line 27, part of the capacitor electrode 28, part of the capacitor trunk line 29, the inspection line 30, etc. The third metal film constitutes part of the pixel electrode 23, the capacitor branch line 26, part of the capacitor electrode 28, etc.

[0033] The semiconductor film is made of an oxide semiconductor material and constitutes the semiconductor portion 22D of the TFT 22. The semiconductor film may contain at least one metal element selected from the group consisting of In, Ga, and Zn, and may be, for example, an In-Ga-Zn-O-based semiconductor (e.g., indium gallium zinc oxide). The In-Ga-Zn-O-based semiconductor is a ternary oxide of In (indium), Ga (gallium), and Zn (zinc). The ratio (composition ratio) of In, Ga, and Zn is not particularly limited, and examples include In:Ga:Zn=2:2:1, In:Ga:Zn=1:1:1, and In:Ga:Zn=1:1:2. The In-Ga-Zn-O-based semiconductor used in the semiconductor film may be amorphous or crystalline. Instead of the In-Ga-Zn-O-based semiconductor, the semiconductor film may contain other oxide semiconductors. For example, it may contain an In-Sn-Zn-O-based semiconductor (e.g., In2O3-SnO2-ZnO; InSnZnO). The In-Sn-Zn-O-based semiconductor is a ternary oxide of In (indium), Sn (tin), and Zn (zinc). Alternatively, the oxide semiconductor layer may include an In-W-Zn-O-based semiconductor containing W (tungsten), an In-W-Sn-Zn-O-based semiconductor, an In-Al-Zn-O-based semiconductor, an In-Al-Sn-Zn-O-based semiconductor, a Zn-O-based semiconductor, an In-Zn-O-based semiconductor, a Zn-Ti-O-based semiconductor, a Cd-Ge-O-based semiconductor, a Cd-Pb-O-based semiconductor, CdO (cadmium oxide), an Mg-Zn-O-based semiconductor, an In-Ga-Sn-O-based semiconductor, an In-Ga-O-based semiconductor, a Zr-In-Zn-O-based semiconductor, an Hf-In-Zn-O-based semiconductor, an Al-Ga-Zn-O-based semiconductor, a Ga-Zn-O-based semiconductor, or an In-Ga-Zn-Sn-O-based semiconductor. The oxide semiconductor material of the semiconductor film has a higher resistance value when no voltage is applied (off state) than polysilicon semiconductor material, and also has a higher electron mobility than amorphous silicon semiconductor material.

[0034] The gate insulating film 31, the first interlayer insulating film 32, and the second interlayer insulating film 33 are each made of silicon nitride (SiN xThe gate insulating film 31 is made of an inorganic material such as silicon dioxide (SiO2). The gate insulating film 31 keeps the first metal film on the lower layer insulated from the semiconductor film and second metal film on the upper layer. The first interlayer insulating film 32 keeps the semiconductor film and second metal film on the lower layer insulated from the third metal film on the upper layer. The second interlayer insulating film 33 covers the third metal film and the like from the upper layer side.

[0035] Next, the cross-sectional structure of the TFT 22 will be described. As shown in FIG. 4, the gate electrode 22A of the TFT 22 is made of a part of the first metal film. The semiconductor portion 22D of the TFT 22 is made of a part of the semiconductor film and is disposed above the gate electrode 22A with a gate insulating film 31 interposed therebetween. The source electrode 22B of the TFT 22 is made of a part of the second metal film and is in direct contact with one end portion of the semiconductor portion 22D in the X-axis direction from above. The drain electrode 22C of the TFT 22 is made of a part of the second metal film and is in direct contact with the other end portion of the semiconductor portion 22D in the X-axis direction from above.

[0036] The cross-sectional structure of the pixel electrode 23 will be described with reference to FIG. 4 and other figures. As shown in FIGS. 4, 8, and 10, the pixel electrode 23 has a lower electrode portion 23A made of a part of the first metal film and an upper electrode portion 23B made of a part of the third metal film. FIG. 8 is a plan view showing the pixel arrangement of the array substrate, illustrating the structure made of the first metal film. FIG. 10 is a plan view showing the pixel arrangement of the array substrate, illustrating the structure made of the third metal film. The lower electrode portion 23A and the upper electrode portion 23B are arranged so that their major portions overlap each other. As shown in FIGS. 4 and 8, a portion of the lower electrode portion 23A overlaps a portion of the end of the drain electrode 22C opposite the source electrode 22B. A first pixel contact hole CH1 is opened in the gate insulating film 31 interposed between the lower electrode portion 23A and the drain electrode 22C at a position overlapping both the lower electrode portion 23A and the drain electrode 22C. The lower electrode portion 23A and the drain electrode 22C are connected through the first pixel contact hole CH1. As shown in FIGS. 4 and 10 , a portion of the upper electrode portion 23B overlaps substantially the entire end of the drain electrode 22C opposite the source electrode 22B. A second pixel contact hole CH2 is opened in the first interlayer insulating film 32 interposed between the upper electrode portion 23B and the drain electrode 22C at a position overlapping both the upper electrode portion 23B and the drain electrode 22C but not overlapping the first pixel contact hole CH1. The upper electrode portion 23B and the drain electrode 22C are connected through the second pixel contact hole CH2. The first pixel contact hole CH1 and the second pixel contact hole CH2 are arranged side by side at an interval in the Y-axis direction.

[0037] The cross-sectional structure of the capacitance electrode main body 28A constituting the capacitance electrode 28 will be described. As shown in FIGS. 4 and 9, the capacitance electrode main body 28A is made of a part of the second metal film. FIG. 9 is a plan view showing the pixel array of the array substrate, illustrating the structure made of the second metal film. The capacitance electrode main body 28A overlaps the lower electrode portion 23A via the gate insulating film 31, and overlaps the upper electrode portion 23B via the first interlayer insulating film 32. That is, the capacitance electrode main body 28A is sandwiched between the lower electrode portion 23A and the upper electrode portion 23B in the Z-axis direction. Because electrostatic capacitance is formed between the capacitance electrode main body 28A and the lower electrode portion 23A, and between the capacitance electrode main body 28A and the upper electrode portion 23B, the potential of the charged pixel electrode 23 can be maintained well. 4 and 10, covering portion 28C constituting capacitive electrode 28 is made of a part of the third metal film. Covering portion 28C is arranged to overlap source electrode 22B, drain electrode 22C, and semiconductor portion 22D via first interlayer insulating film 32. Covering portion 28C can effectively block light that would otherwise be incident on semiconductor portion 22D (particularly the portion that constitutes the channel region).

[0038] The cross-sectional structures of the source wiring 25 and the gate connection wiring 27 will be described. As shown in FIGS. 4 and 9, the source wiring 25 is made of a part of the second metal film and is directly connected to the source electrode 22B. As shown in FIGS. 4, 8, and 9, the gate connection wiring 27 has a connection wiring main body 27A made of a part of the second metal film and an overlapping portion 27B made of a part of the first metal film and arranged to overlap the connection wiring main body 27A. As shown in FIGS. 4 and 9, the connection wiring main body 27A extends over almost the entire length of the display area AA in the Y-axis direction. In contrast, as shown in FIGS. 4 and 8, the overlapping portion 27B extends along the Y-axis direction and is arranged only in the area sandwiched between two adjacent gate wirings 24 spaced apart in the Y-axis direction. This prevents short-circuiting between the overlapping portion 27B and the gate wiring 24. A plurality of overlapping portions 27B are arranged side by side at intervals in the Y-axis direction, and the plurality of overlapping portions 27B are arranged to overlap one connection wiring main body 27A via the gate insulating film 31. Contact holes CH3 are opened and provided in the gate insulating film 31 at positions overlapping both ends of the overlapping portion 27B in the Y-axis direction. The overlapping portion 27B is connected to the connection wiring main body 27A at two positions spaced apart in the Y-axis direction through the two contact holes CH3. This ensures redundancy of the gate connection wiring 27.

[0039] Next, the cross-sectional configuration of the gate wiring 24 and the inspection wiring 30 will be described with reference to FIG. 5 and other figures. FIG. 5 is a cross-sectional view of the gate wiring 24, the inspection wiring 30, and the like on the array substrate 21. As shown in FIG. 5, the gate wiring 24 has a first wiring component 24A arranged in the display area AA and a second wiring component 24B arranged in the non-display area NAA. As shown in FIGS. 5, 8, and 9, the first wiring component 24A arranged in the display area AA has a gate wiring main body 24A1 made of a part of the first metal film and an overlapping portion 24A2 made of a part of the second metal film and arranged to overlap the gate wiring main body 24A1. As shown in FIGS. 5 and 8, the gate wiring main body 24A1 extends over substantially the entire length of the display area AA in the X-axis direction and intersects with the source wiring 25 and the connection wiring main body 27A of the gate connection wiring 27, each with a gate insulating film 31 interposed therebetween. A gate connection contact hole (first contact hole) CH4 is opened and provided in the gate insulating film 31 at a position overlapping both the gate wiring main body 24A1 and the connection wiring main body 27A, which are to be connected to each other. The gate wiring main body 24A1 of the gate wiring 24 is connected to the connection wiring main body 27A of the gate connection wiring 27, which is to be connected, through the gate connection contact hole CH4. The gate insulating film 31 is not provided with the gate connection contact hole CH4 at a position overlapping both the gate wiring main body 24A1 and the connection wiring main body 27A, which are not to be connected.

[0040] In contrast, as shown in FIGS. 5 and 9 , the overlapping portion 24A2 extends along the X-axis direction and is limited to the area sandwiched between the source wiring 25 and the connecting portion 28B of the capacitor electrode 28, which are adjacent to each other with a gap in the X-axis direction. The connecting portion 28B of the capacitor electrode 28 is made of a part of the second metal film and intersects with the gate wiring main body 24A1 via the gate insulating film 31. This prevents a short circuit between the overlapping portion 24A2 and the source wiring 25, and also prevents a short circuit between the overlapping portion 24A2 and the connecting portion 28B. The overlapping portions 24A2 are arranged two by two with the connecting portion 28B of the capacitor electrode 28 sandwiched between them in the X-axis direction, and the multiple overlapping portions 24A2 are overlapped with one gate wiring main body 24A1 via the gate insulating film 31. Contact holes CH5 are opened and provided in the gate insulating film 31 at positions overlapping both ends of the overlapping portion 24A2 in the X-axis direction. The overlapping portion 24A2 is connected to the gate wire main body 24A1 at two positions spaced apart in the X-axis direction through two contact holes CH5, thereby ensuring redundancy of the first wire component portion 24A.

[0041] The second wiring component 24B disposed in the non-display area NAA is made of a part of the first metal film, as shown in FIGS. 5 and 8. The second wiring component 24B extends along the X-axis direction in the non-display area NAA, and its end on the display area AA side in the X-axis direction is connected to an end of the gate wiring main body 24A1 of the first wiring component 24A. The end of the second wiring component 24B opposite the display area AA side in the X-axis direction is a first end 24B1 connected to the inspection wiring 30. The first end 24B1 is disposed at a position spaced apart from the capacitor trunk wiring 29 (first trunk wiring component 29A) in the X-axis direction. The first end 24B1 has a wider line width than other portions of the second wiring component 24B (first line width portion 24B2 and second line width portion 24B3, which will be described later). In contrast, the inspection wiring 30 is made of a part of the second metal film, as shown in FIGS. 5 and 9. The inspection wiring 30 extends along the X-axis direction, crosses the first trunk wiring component 29A of the capacitor trunk wiring 29, and has an end portion on the display region AA side in the X-axis direction that overlaps and is connected to the first end 24B1 of the second wiring component 24B as a second end 30A. The second end 30A has a wider line width than other portions of the inspection wiring 30. An inspection connection contact hole (second contact hole) CH6 is opened and provided in the gate insulating film 31 at a position overlapping both the first end 24B1 and the second end 30A. The first end 24B1 of the second wiring component 24B is connected to the second end 30A of the inspection wiring 30 through the inspection connection contact hole CH6. A plurality of inspection connection contact holes CH6 are arranged side by side at intervals in the X-axis direction.

[0042] The cross-sectional configuration of the capacitive branch line 26 in the display region AA will be described with reference to FIG. 6 and other figures. FIG. 6 is a cross-sectional view of the capacitive branch line 26 and other components on the array substrate 21. As shown in FIGS. 6 and 10, the capacitive branch line 26 is made of a part of the third metal film. In the display region AA, the capacitive branch line 26 extends along the X-axis direction and crosses the source line 25, the gate connecting line 27, and the capacitive electrode 28. The capacitive branch line 26 intersects the source line 25 and the connecting line main body 27A of the gate connecting line 27 via the first interlayer insulating film 32, and crosses the overlapping portion 27B of the gate connecting line 27 via the gate insulating film 31. The capacitive branch line 26 intersects the capacitive electrode main body 28A of the capacitive electrode 28 via the first interlayer insulating film 32. The portion of the capacitive branch line 26 that intersects with the capacitive electrode main body 28A has a wider line width than the portion that crosses the source line 25 and the gate connecting line 27. Contact holes CH7 are opened and provided in the first interlayer insulating film 32 at positions overlapping both the capacitive branch wiring 26 and the capacitive electrode main body 28A. The capacitive branch wiring 26 is connected to the capacitive electrode main body 28A through the contact holes CH7. Two contact holes CH7 are provided near each end of the capacitive electrode main body 28A in the X-axis direction.

[0043] The cross-sectional configurations of the capacitive branch wiring 26 and the capacitive main wiring 29 in the non-display area NAA will be described with reference to FIG. 7 and other figures. FIG. 7 is a cross-sectional view of the capacitive branch wiring 26, the capacitive electrode 28, and the like on the array substrate 21. As shown in FIGS. 7 to 9, the capacitive main wiring 29 has a main wiring body 29C made up of a part of the first metal film and a connection electrode portion 29D made up of a part of the second metal film. Note that while FIG. 7 shows the cross-sectional configuration of the first main wiring portion 29A of the capacitive main wiring 29 as a representative, the cross-sectional configuration of the second main wiring portion 29B (see FIG. 1) is also similar. The portion of the main wiring body 29C that constitutes the first main wiring portion 29A extends along the Y-axis direction and has a length greater than the dimension in the Y-axis direction in the display area AA. The portion of the main wiring body 29C that constitutes the first main wiring portion 29A intersects with the test wiring 30 via a gate insulating film 31. The connection electrode portion 29D extends along the Y-axis direction and is disposed only in the area sandwiched between two adjacent inspection wirings 30 spaced apart in the Y-axis direction. This prevents short-circuiting between the connection electrode portion 29D and the inspection wiring 30. A plurality of connection electrode portions 29D are arranged side by side at intervals in the Y-axis direction and overlap the main wiring body 29C via the gate insulating film 31. The gate insulating film 31 overlaps both the main wiring body 29C and the connection electrode portion 29D, and contact holes CH8 are opened near the center and both ends of the connection electrode portion 29D in the Y-axis direction. The connection electrode portion 29D is connected to the main wiring body 29C through the contact holes CH8. A plurality of contact holes CH8 are disposed at intervals in the X-axis direction.

[0044] As shown in FIGS. 7 and 10 , in the non-display area NAA, the capacitive branch line 26 made of the third metal film is bent in a crank shape in plan view and extends along the X-axis direction to reach the first trunk line component 29A of the capacitive trunk line 29. The capacitive branch line 26 has a connection portion 26A that overlaps the connection electrode portion 29D of the first trunk line component 29A via the first interlayer insulating film 32. The connection portion 26A is wider than other portions of the capacitive branch line 26. A contact hole CH9 is opened and provided in the first interlayer insulating film 32 at a position that overlaps both the connection portion 26A and the connection electrode portion 29D. The connection portion 26A is connected to the connection electrode portion 29D through the contact hole CH9. Two contact holes CH9 are provided at positions spaced apart in the Y-axis direction, and multiple contact holes CH9 are provided at positions spaced apart in the X-axis direction.

[0045] As shown in FIG. 8, the second wiring component 24B constituting the gate wiring 24 according to this embodiment is configured so that its line width (dimension in the Y-axis direction) varies from its end on the first wiring component 24A side to the first end 24B1. Specifically, the second wiring component 24B has a first line width portion 24B2 and a second line width portion 24B3 narrower than the first line width portion 24B2. Both the first line width portion 24B2 and the second line width portion 24B3 are located closer to the first wiring component 24A (toward the display area AA) in the X-axis direction than the first end 24B1. The first line width portion 24B2 has a line width smaller than that of the first end 24B1 and a line width larger than that of the second line width portion 24B3. The second line width portion 24B3 is continuous with the first line width portion 24B2 and has the smallest line width among the second wiring components 24B. Furthermore, the first line width portion 24B2 and the second line width portion 24B3 may have approximately the same dimensions in the X-axis direction.

[0046] On the other hand, as shown in FIG. 8 , the gate wiring main body 24A1 of the first wiring component 24A constituting the gate wiring 24 is configured so that its line width varies depending on its position in the X-axis direction. The first wiring component 24A has a third line width portion 24A1A, a fourth line width portion 24A1B narrower than the third line width portion 24A1A, and a fifth line width portion 24A1C narrower than the third line width portion 24A1A. The third line width portion 24A1A is a portion of the first wiring component 24A that does not intersect with the source wiring 25 and the connecting portion 28B of the capacitor electrode 28. A plurality of third line width portions 24A1A are arranged side by side at intervals in the X-axis direction. Specifically, the third line width portions 24A1A include portions of the first wiring component 24A that overlap with the overlapping portion 24A2 and portions that intersect with the gate connection wiring 27. The third line width portion 24A1A has substantially the same line width as the first line width portion 24B2. The fourth line width portion 24A1B is a portion of the first wiring component 24A that intersects with the source line 25 via the gate insulating film 31. The fifth line width portion 24A1C is a portion that intersects with the connecting portion 28B of the capacitor electrode 28 via the gate insulating film 31. The third line width portion 24A1A that overlaps with the overlapping portion 24A2 is disposed between the fourth line width portion 24A1B and the fifth line width portion 24A1C in the X-axis direction. The third line width portion 24A1A that intersects with the gate connection wiring 27 is disposed between two fourth line width portions 24A1B in the X-axis direction. The fourth line width portion 24A1B and the fifth line width portion 24A1C are both continuous with the third line width portion 24A1A. The fourth line width portion 24A1B and the fifth line width portion 24A1C have substantially the same line width as each other. The fourth line width portion 24A1B and the fifth line width portion 24A1C have substantially the same line width as the second line width portion 24B3.

[0047] As shown in FIG. 8 , the portion of the gate wiring main body 24A1 of the first wiring configuration portion 24A that intersects with the source wiring 25 via the gate insulating film 31 has a fourth line width portion 24A1B that is narrower than the third line width portion 24A1A. Therefore, compared to when the source wiring intersects with the third line width portion 24A1A, it is possible to reduce the parasitic capacitance that may occur between the gate wiring 24 and the source wiring 25. Furthermore, the portion of the gate wiring main body 24A1 of the first wiring configuration portion 24A that intersects with the connecting portion 28B of the capacitor electrode 28 via the gate insulating film 31 has a fifth line width portion 24A1C that is narrower than the third line width portion 24A1A. Therefore, compared to when the connecting portion of the capacitor electrode intersects with the third line width portion 24A1A, it is possible to reduce the parasitic capacitance that may occur between the gate wiring 24 and the capacitor electrode 28.

[0048] Incidentally, during the manufacturing process of the array substrate 21, when the first metal film formed on the resin substrate is patterned to provide the gate wiring main body 24A1, the second wiring portion 24B, and the first trunk wiring portion 29A of the capacitor trunk wiring 29 in the first wiring portion 24A of the gate wiring 24, there is a concern that electrostatic discharge may occur between the first trunk wiring portion 29A and the first end 24B1 of the second wiring portion 24B, which are adjacent to each other with a gap in the X-axis direction, as shown in Fig. 8. Meanwhile, in the display region AA, the fourth line width portion 24A1B and the fifth line width portion 24A1C of the first wiring portion 24A are both narrower than the third line width portion 24A1A, and therefore there is a concern that electrostatic breakdown may be more likely to occur in the fourth line width portion 24A1B and the fifth line width portion 24A1C if the above-mentioned electrostatic discharge occurs. If electrostatic breakdown occurs in the fourth line width portion 24A1B and the fifth line width portion 24A1C, there is a risk that the first wiring component 24A will be disconnected, the fourth line width portion 24A1B will be short-circuited with the source wiring 25, or the fifth line width portion 24A1C will be short-circuited with the capacitance electrode 28.

[0049] In this embodiment, as shown in FIG. 8 , the second line width portion 24B3 of the second wiring component 24B arranged in the non-display area NAA, which is connected to the first line width portion 24B2 located closer to the first wiring component 24A in the X-axis direction than the first end portion 24B1, is narrower than the first line width portion 24B2. This makes the second line width portion 24B3 more susceptible to electrostatic discharge damage. This reduces the likelihood of electrostatic discharge damage occurring in the fourth line width portion 24A1B and the fifth line width portion 24A1C of the first wiring component 24A arranged in the display area AA. This also reduces the likelihood of electrostatic discharge-induced disconnections in the first wiring component 24A. Furthermore, this reduces the likelihood of short-circuits between the fourth line width portion 24A1B and the source wiring 25 and between the fifth line width portion 24A1C and the capacitor electrode 28.

[0050] As shown in FIG. 8 , the second wiring component 24B according to this embodiment has a plurality of first line width portions 24B2 and a plurality of second line width portions 24B3. The plurality of first line width portions 24B2 and the plurality of second line width portions 24B3 are alternately arranged in the X-axis direction from the end of the first wiring component 24A to the first end 24B1. This allows electrostatic discharge damage to occur in the plurality of second line width portions 24B3. This reduces the likelihood of electrostatic damage occurring in the fourth line width portion 24A1B and the fifth line width portion 24A1C of the first wiring component 24A, which are arranged in the display area AA. This reduces the likelihood of breaks in the gate wiring 24 within the display area AA and of short-circuiting the gate wiring 24 with the source wiring 25 and the capacitor electrode 28.

[0051] 3 and 5, in this embodiment, the gate connection wiring 27 that transmits the scanning signal from the driver 11 is connected to the first wiring component 24A of the gate wiring 24 that is arranged in the display area AA through the gate connection contact hole CH4 in the gate insulating film 31, so that the scanning signal can be supplied to the first wiring component 24A via the gate connection wiring 27 without passing through the second wiring component 24B. Therefore, even if electrostatic breakdown occurs in the second line width portion 24B3 of the second wiring component 24B due to electrostatic discharge and the second wiring component 24B is broken, the supply of the scanning signal to the gate wiring 24 can be maintained.

[0052] In this embodiment, as shown in FIG. 2, the inspection wirings 30 transmitting inspection signals from an inspection device are arranged in pairs on either side of the display area AA in the X-axis direction, and the second wiring components 24B arranged in the non-display area NAA of the gate wiring 24 are also arranged in pairs on either side of the display area AA in the X-axis direction. As shown in FIGS. 2 and 5, each second end 30A of the paired inspection wirings 30 is connected to each first end 24B1 of the paired second wiring components 24B through the inspection connection contact hole CH6 in the gate insulating film 31. Therefore, even if electrostatic discharge causes electrostatic breakdown in the second line width portion 24B3 of one of the paired second wiring components 24B, causing the second wiring component 24B to break, the inspection signal can be supplied to the other second wiring component 24B from the connected inspection wiring 30. This allows the supply of inspection signals to the gate wiring 24 to be maintained.

[0053] As described above, the electronic paper display (display device) 10 of this embodiment includes a display area AA where an image is displayed, a non-display area NAA where no image is displayed, gate wiring (first wiring) 24 arranged across the display area AA and the non-display area NAA and extending along a first direction, and a first main wiring component (second wiring) 29A arranged in the non-display area NAA and extending along a second direction intersecting the first direction, and the gate wiring 24 and the first main wiring component 29A are each made of a first metal film (first conductive film) The gate wiring 24 is made up of different parts, and the gate wiring 24 is made up of a first wiring component 24A arranged in the display area AA and a second wiring component 24B arranged in the non-display area NAA, which are connected together. The second wiring component 24B has a first end 24B1 arranged at a distance in the first direction from the first main wiring component 29A, a first line width portion 24B2 located closer to the first wiring component 24A in the first direction than the first end 24B1, and a second line width portion 24B3 connected to the first line width portion 24B2 and narrower than the first line width portion 24B2.

[0054] The first end 24B1 of the second wiring component 24B constituting the gate wiring 24 extending along the first direction and the first main wiring component 29A extending along a second direction intersecting the first direction are spaced apart in the first direction in the non-display area NAA. Therefore, when the first metal film is patterned to provide the gate wiring 24 and the first main wiring component 29A, electrostatic discharge may occur between the first end 24B1 of the second wiring component 24B and the first main wiring component 29A. Even in this case, the second line width portion 24B3 of the second wiring component 24B, which is connected to the first line width portion 24B2 located closer to the first wiring component 24A in the first direction than the first end 24B1, is narrower than the first line width portion 24B2, making electrostatic breakdown due to electrostatic discharge more likely to occur in the second line width portion 24B3. As a result, electrostatic breakdown is less likely to occur in the first wiring component 24A of the gate wiring 24 arranged in the display area AA, and therefore disconnection due to electrostatic discharge is less likely to occur in the gate wiring 24 within the display area AA.

[0055] The display region AA also includes a gate connection wiring (third wiring) 27 extending in the second direction, and a gate insulating film (first insulating film) 31 disposed above the first metal film. The gate connection wiring 27 is made of a second metal film (second conductive film) disposed above the gate insulating film 31 and intersects with the first wiring component 24A via the gate insulating film 31. A gate connection contact hole (first contact hole) CH4 connecting the gate connection wiring 27 and the first wiring component 24A is provided in the gate insulating film 31 at a position overlapping both the gate connection wiring 27 and the first wiring component 24A. The gate connection wiring 27 extending in the second direction in the display region AA and the first wiring component 24A constituting the gate wiring 24 are connected through the gate connection contact hole CH4 in the gate insulating film 31, so that a signal can be supplied to the gate wiring 24 via the gate connection wiring 27. Therefore, even if electrostatic breakdown occurs in the second line width portion 24B3 of the second wiring component 24B that configures the gate wiring 24 due to electrostatic discharge, the supply of signals to the gate wiring 24 can be maintained.

[0056] The display element also includes an inspection wiring 30 arranged in the non-display area NAA, extending along the first direction and transmitting an inspection signal, and a gate insulating film 31 arranged on the upper side of the first metal film, and the first main wiring component 29A, the inspection wiring 30 and the second wiring component 24B are arranged in pairs on either side of the display area AA in the first direction, and each pair of inspection wiring 30 is made of a second metal film arranged on the upper side of the gate insulating film 31, and has a second end 30A that intersects with the first main wiring component 29A via the gate insulating film 31 and overlaps with the first end 24B1, and an inspection connection contact hole (second contact hole) CH6 that connects the first end 24B1 and the second end 30A is provided in the gate insulating film 31 at a position that overlaps both the first end 24B1 and the second end 30A. The inspection wiring 30 crosses the first main wiring component 29A via the gate insulating film 31, thereby avoiding short-circuiting with the first main wiring component 29A. The inspection wiring 30 extending along the first direction in the non-display area NAA is connected to the second wiring component 24B constituting the gate wiring 24 through the inspection connection contact hole CH6 in the gate insulating film 31, allowing an inspection signal to be supplied from the inspection wiring 30 to the gate wiring 24. The first main wiring component 29A, the inspection wiring 30, and the second wiring component 24B are arranged in pairs on either side of the display area AA in the first direction, allowing the gate wiring 24 to be inspected using the paired inspection wiring 30. Therefore, even if electrostatic breakdown occurs in the second line width portion 24B3 of one of the paired second wiring components 24B due to electrostatic discharge, the gate wiring 24 can be inspected using one of the paired inspection wirings 30.

[0057] The first wiring component 24A also has a third line width portion 24A1A and a fourth line width portion 24A1B that is continuous with the third line width portion 24A1A and narrower than the third line width portion 24A1A. In the display area AA, the fourth line width portion 24A1B of the first wiring component 24A is narrower than the third line width portion 24A1A, raising concerns that electrostatic discharge damage may be more likely to occur in the fourth line width portion 24A1B. In contrast, in the non-display area NAA, the second line width portion 24B3 of the second wiring component 24B, which has a first end portion 24B1 spaced apart from the first main wiring component 29A in the first direction, is narrower than the first line width portion 24B2, making the second line width portion 24B3 more likely to be electrostatic discharge damage. As a result, electrostatic breakdown is less likely to occur in the fourth line width portion 24A1B of the first wiring component 24A arranged in the display area AA, making it less likely that breaks will occur in the gate wiring 24 within the display area AA due to electrostatic discharge.

[0058] The display region AA also includes a source wiring (fourth wiring) 25 arranged in the second direction and extending in the second direction, and a gate insulating film 31 arranged above the first metal film. The source wiring 25 is made of a second metal film arranged above the gate insulating film 31, and intersects with the fourth line width portion 24A1B via the gate insulating film 31. In this way, the source wiring 25 extending in the second direction in the display region AA intersects with the fourth line width portion 24A1B, which is narrower than the third line width portion 24A1A of the first wiring-component 24A, via the gate insulating film 31. Therefore, compared to a case in which the source wiring intersects with the third line width portion 24A1A, it is possible to reduce parasitic capacitance that may occur between the gate wiring 24 and the source wiring 25. Furthermore, since electrostatic breakdown due to electrostatic discharge is more likely to occur in the second line width portion 24B3, electrostatic breakdown is less likely to occur in the fourth line width portion 24A1B, making it less likely that the source wiring 25 and the fourth line width portion 24A1B, which intersect with each other, will short-circuit due to electrostatic breakdown.

[0059] The second wiring component 24B has a plurality of first line width portions 24B2 and a plurality of second line width portions 24B3, and the first line width portions 24B2 and the second line width portions 24B3 are arranged alternately in the first direction. Because the plurality of first line width portions 24B2 and the plurality of second line width portions 24B3 are arranged alternately in the first direction, electrostatic breakdown due to electrostatic discharge can occur in the plurality of second line width portions 24B3. This makes it less likely that electrostatic breakdown will occur in the first wiring component 24A of the gate wiring 24 that is arranged in the display area AA, and therefore makes it less likely that breaks in the gate wiring 24 within the display area AA will occur due to electrostatic discharge.

[0060] <Other embodiments> The technology disclosed in this specification is not limited to the embodiments described above and illustrated in the drawings, and the following embodiments, for example, are also included in the technical scope.

[0061] (1) The specific number of first line width portions 24B2 and second line width portions 24B3 provided in the second wiring component 24B can be changed as appropriate to numbers other than those shown in the drawings.

[0062] (2) The dimensions of the first line width portion 24B2 and the second line width portion 24B3 in the X-axis direction may be changed as appropriate to those not shown in the drawings. For example, the dimension of the first line width portion 24B2 in the X-axis direction may be different from the dimension of the second line width portion 24B3 in the X-axis direction.

[0063] (3) The capacitive main wiring 29 may not have the connection electrode portion 29D. In this case, for example, the connection portion 26A of the capacitive branch wiring 26 may be directly connected to the main wiring body 29C of the capacitive main wiring 29 through a contact hole provided in communication with the gate insulating film 31 and the first interlayer insulating film 32.

[0064] (4) A gate wiring 24 may be provided for each row of pixel electrodes 23, each consisting of a plurality of pixel electrodes 23 aligned along the X-axis direction. In this case, the number of gate wirings 24 provided is equal to the number of rows of pixel electrodes 23. Accordingly, a source wiring 25 may be provided for each column of pixel electrodes 23, each consisting of a plurality of pixel electrodes 23 aligned along the Y-axis direction, so that the number of source wirings 25 provided is equal to the number of columns of pixel electrodes 23. Note that the capacitive branch wirings 26 are arranged to overlap certain gate wirings 24. The number of gate connection wirings 27 provided can also be changed depending on the number of gate wirings 24 provided.

[0065] (5) In the above (4), if the number of source wirings 25 and gate connection wirings 27 is changed, the number of third line width portions 24A1A, fourth line width portions 24A1B, and fifth line width portions 24A1C provided in the first wiring configuration portion 24A can also be changed.

[0066] (6) The array substrate 21 may be provided with a source driver that supplies image signals to the source lines 25 and a gate driver that supplies scanning signals to the gate connection lines 27.

[0067] (7) Instead of the gate connection wiring 27 provided longitudinally across the display area AA, gate connection wiring connected to the first end 24B1 of the second wiring component 24B can be provided in the non-display area NAA. In this case, a pair of gate drive circuits can be provided on the array substrate 21, sandwiching the display area AA in the X-axis direction, and a pair of gate connection wiring can be provided between the display area AA and the gate drive circuits. Each gate connection wiring can extend along the X-axis direction from each gate drive circuit to the first end 24B1 of each second wiring component 24B. In this case, by supplying a scanning signal from the gate drive circuit to the gate connection wiring, the scanning signal can be supplied to the gate wiring 24 via the gate connection wiring. Note that even if the second line width portion 24B3 of one of the pair of second wiring components 24B is disconnected due to electrostatic discharge, the other second wiring component 24B can supply the scanning signal from the gate connection wiring to the gate wiring 24.

[0068] (8) In the above (7), the inspection wiring 30 can be omitted, but it is also possible to connect the inspection wiring 30 and the gate connection wiring to the first end 24B1 of the second wiring component 24B.

[0069] (9) In the above (7), instead of the gate drive circuit, it is also possible to provide a pair of gate drivers sandwiching the display area AA in the X-axis direction.

[0070] (10) The material of the semiconductor film that constitutes the semiconductor portion 22D may be polysilicon (LTPS), amorphous silicon, or the like.

[0071] (11) In the counter substrate 20 and the array substrate 21, glass substrates may be used instead of resin substrates.

[0072] (12) On the counter substrate 20, the color filter may be omitted to provide a black and white display (gray scale display).

[0073] (13) The operating method of the electronic paper display 10 can be changed as appropriate to an electronic liquid powder method, an electrowetting method, a cholesteric liquid crystal method, or the like.

[0074] (14) Display devices other than the electronic paper display 10 (for example, a liquid crystal panel, an organic EL display panel, etc.) may also be used. [Explanation of symbols]

[0075] 10...electronic paper display (display device), 24...gate wiring (first wiring), 24A...first wiring configuration portion, 24A1A...third line width portion, 24A1B...fourth line width portion, 24B...second wiring configuration portion, 24B1...first end portion, 24B2...first line width portion, 24B3...second line width portion, 25...source wiring (fourth wiring), 27...gate connection wiring (third wiring), 29A...first main wiring configuration portion (second wiring), 30...inspection wiring, 30A...second end portion, 31...gate insulating film (first insulating film), AA...display area, CH4...gate connection contact hole (first contact hole), CH6...inspection connection contact hole (second contact hole), NAA...non-display area

Claims

1. a display area in which an image is displayed; a non-display area in which the image is not displayed; a first wiring disposed across the display area and the non-display area and extending along a first direction; a second wiring disposed in the non-display area and extending along a second direction intersecting the first direction; the first wiring and the second wiring are respectively formed from different portions of a first conductive film; the first wiring is formed by connecting a first wiring configuration portion arranged in the display area and a second wiring configuration portion arranged in the non-display area, The second wiring configuration portion has a first end portion arranged at a distance from the second wiring in the first direction, a first line width portion located closer to the first wiring configuration portion in the first direction than the first end portion, and a second line width portion connected to the first line width portion and narrower than the first line width portion.

2. a third wiring disposed in the display region and extending along the second direction; a first insulating film disposed on an upper layer side of the first conductive film, the third wiring is made of a second conductive film disposed on the upper layer side of the first insulating film, and intersects with the first wiring component via the first insulating film; 2. The display device according to claim 1, wherein a first contact hole connecting the third wiring and the first wiring component is provided in the first insulating film at a position where the first insulating film overlaps both the third wiring and the first wiring component.

3. an inspection line disposed in the non-display area, extending along the first direction, and transmitting an inspection signal; a first insulating film disposed on an upper layer side of the first conductive film, the second wiring, the inspection wiring, and the second wiring configuration portion are arranged in pairs on either side of the display area in the first direction, the pair of test wirings are each made of a second conductive film disposed on an upper layer side of the first insulating film, and have second ends that intersect with the second wirings via the first insulating film and overlap with the first ends; 3. A display device according to claim 1, wherein a second contact hole connecting the first end and the second end is provided in the first insulating film at a position where the first insulating film overlaps both the first end and the second end.

4. 3. The display device according to claim 1, wherein the first wiring configuration portion has a third line width portion and a fourth line width portion that is continuous with the third line width portion and is narrower than the third line width portion.

5. a fourth wiring arranged in the display region and extending along the second direction; a first insulating film disposed on an upper layer side of the first conductive film, 5. The display device according to claim 4, wherein the fourth wiring is made of a second conductive film disposed on the upper layer side of the first insulating film, and intersects with the fourth line width portion via the first insulating film.

6. 3. The display device according to claim 1, wherein the second wiring configuration has a plurality of the first line width portions and the second line width portions, and the first line width portions and the second line width portions are arranged alternately in the first direction.

Images