Semiconductor integrated circuit

Abstract

To provide a semiconductor integrated circuit capable of performing accurate conversion by an A / D converter.SOLUTION: The voltage adjustment circuit 300 generates the second reference voltage Vref1 based on the first reference voltage Vref2 generated by the reference voltage source. The non-inverting amplifier 200 includes an operational amplifier 210 and a first voltage divider circuit 220. The second voltage dividing circuit 310 divides the output voltage Vadj of the non-inverting amplifier 200. The second reference voltage Vref2 corresponds to the voltage outputted from the second voltage divider 310.SELECTED DRAWING: Figure 2

Description

[Technical Field]

[0001] The present disclosure relates to semiconductor integrated circuits. [Background technology]

[0002] A / D converters require a highly accurate reference voltage. As the resolution of A / D converters increases, the accuracy required for the reference voltage also increases.

[0003] The voltage level of the reference voltage generated by a reference voltage source such as a bandgap reference circuit does not necessarily match the reference voltage required by an A / D converter, so a voltage adjustment circuit is required to adjust the voltage level of the reference voltage.

[0004] Suppose the output voltage of a bandgap reference circuit is expected to have a variation of 3%. To use it as the reference voltage for a 12-bit A / D converter, the error must be reduced to about 0.1% using a voltage adjustment circuit. [Prior art documents] [Patent documents]

[0005] [Patent Document 1] Japanese Patent Application Publication No. 2017-188783

[0006] [overview] The present disclosure has been made in view of the above-mentioned problems, and one purpose of an embodiment thereof is to provide a semiconductor integrated circuit that enables accurate conversion by an A / D converter.

[0007] A semiconductor integrated circuit according to an embodiment of the present disclosure includes a reference voltage source that generates a first reference voltage, a voltage adjustment circuit that generates a second reference voltage based on the first reference voltage, and an A / D converter to which the second reference voltage is supplied. The voltage adjustment circuit includes a non-inverting amplifier including an operational amplifier and a first voltage divider circuit, and a second voltage divider circuit that divides the output voltage of the non-inverting amplifier. The second reference voltage corresponds to the output voltage of the second voltage divider circuit.

[0008] Any combination of the above elements, or mutual substitution of elements or expressions between methods, devices, systems, etc., are also valid aspects of the present invention or the present disclosure. Furthermore, the description in this section (Means for Solving the Problems) does not explain all essential features of the present invention, and therefore, subcombinations of the described features may also constitute the present invention. [Brief explanation of the drawings]

[0009] [Figure 1] FIG. 1 is a block diagram of a semiconductor integrated circuit according to an embodiment. [Figure 2] FIG. 2 is a circuit diagram of a voltage adjustment circuit according to an embodiment. [Figure 3] FIG. 3 is a circuit diagram of a semiconductor integrated circuit according to a comparative technique. [Figure 4] FIG. 4 is a circuit diagram of a voltage adjusting circuit according to the first modification. [Figure 5] FIG. 5 is a circuit diagram of a voltage adjusting circuit according to the second modification. [Figure 6] FIG. 6 is a circuit diagram of a voltage adjusting circuit according to the third modification. [Figure 7] FIG. 7 is a circuit diagram of a voltage adjusting circuit according to the fourth modification. [Figure 8] FIG. 8 is a circuit diagram of a non-inverting amplifier according to the fifth modification. [Figure 9] FIG. 9 is a circuit diagram showing an example of the configuration of the non-inverting amplifier of FIG. [Figure 10] FIG. 10 is a circuit diagram showing a specific example of the configuration of the voltage divider circuit. [Figure 11] FIG. 11 is a circuit diagram of a non-inverting amplifier according to the sixth modification.

[0010] [Detailed explanation] (Outline of the embodiment) A summary of some exemplary embodiments of the present disclosure is provided. This summary is intended to provide a simplified overview of some concepts of one or more embodiments in order to provide a basic understanding of the embodiments as a prelude to the more detailed description that follows. It is not intended to limit the scope of the invention or disclosure. Furthermore, this summary is not an exhaustive overview of all possible embodiments, nor does it limit essential elements of the embodiments. For convenience, the term "one embodiment" may refer to one embodiment (example or variant) or multiple embodiments (examples or variants) disclosed herein.

[0011] A semiconductor integrated circuit according to one embodiment includes a reference voltage source that generates a first reference voltage, a voltage adjustment circuit that generates a second reference voltage based on the first reference voltage, and an A / D converter to which the second reference voltage is supplied. The voltage adjustment circuit includes a non-inverting amplifier including an operational amplifier and a first voltage divider circuit, and a second voltage divider circuit that divides the output voltage of the non-inverting amplifier. The second reference voltage corresponds to the output voltage of the second voltage divider circuit.

[0012] According to this configuration, when the second reference voltage required by the A / D converter is lower than the first reference voltage, the error in the second reference voltage can be reduced.

[0013] In one embodiment, the voltage adjustment circuit may further include a buffer that receives the output voltage of the second voltage divider circuit and generates a second reference voltage. The second reference voltage may fluctuate as the A / D converter performs its conversion operation. In this case, the A / D converter cannot proceed to the next operation until the second reference voltage settles. By adding a buffer, the second reference voltage can be settled in a short time, enabling the A / D converter to operate at high speed.

[0014] In one embodiment, the gain of the buffer may be 0 dB, which allows for high-speed response while keeping the operating current low.

[0015] In one embodiment, the voltage adjustment circuit may further include a filter disposed between the operational amplifier and the buffer. Fluctuations in the second reference voltage due to the conversion operation of the A / D converter propagate to the non-inverting amplifier via the buffer. Inserting the filter can prevent voltage fluctuations from being transmitted to the non-inverting amplifier, enabling the supply of a more stable reference voltage.

[0016] In one embodiment, the filter may be an RC filter.

[0017] In one embodiment, the non-inverting amplifier may further include a P-type transistor, which can increase the driving capability (current supply capability) of the non-inverting amplifier and suppress fluctuations in the second reference voltage.

[0018] In one embodiment, the non-inverting amplifier may further include a first capacitor connected between the control terminal of the P-type transistor and the output terminal of the non-inverting amplifier. When the output voltage of the non-inverting amplifier increases, the first capacitor applies feedback to increase the voltage at the control terminal of the P-type transistor, thereby suppressing the increase in the output voltage of the non-inverting amplifier. Conversely, when the output voltage of the non-inverting amplifier decreases, the first capacitor applies feedback to decrease the voltage at the control terminal of the P-type transistor, thereby suppressing the decrease in the output voltage of the non-inverting amplifier. In this way, the first capacitor serves to suppress fluctuations in the output voltage of the non-inverting amplifier in addition to its function as phase compensation.

[0019] In one embodiment, the non-inverting amplifier may further include a second capacitor connected between the control terminal of the P-type transistor and the output terminal of the second voltage divider circuit. When the output voltage of the second voltage divider circuit increases, the second capacitor applies feedback to increase the voltage at the control terminal of the P-type transistor, thereby suppressing the increase in the output voltage of the second voltage divider circuit. When the output voltage of the second voltage divider circuit decreases, the second capacitor applies feedback to decrease the voltage at the control terminal of the P-type transistor, thereby suppressing the decrease in the output voltage of the second voltage divider circuit. In this way, the second capacitor helps to suppress fluctuations in the output voltage of the second voltage divider circuit.

[0020] In one embodiment, the first voltage divider circuit may have a variable voltage division ratio.

[0021] In one embodiment, the first voltage divider circuit may include a first resistor, a second resistor, and a third resistor connected in series between the output terminal of the non-inverting amplifier and ground, and a digital potentiometer connected in parallel with the second resistor.

[0022] With this configuration, the digital potentiometer can adjust the gain of the non-inverting amplifier with high precision. The analog switch included in the digital potentiometer is located in a path through which almost no current flows (a high-impedance path), so the on-resistance of the analog switch has almost no effect on the output voltage of the non-inverting amplifier. This makes it possible to increase the number of gradations (resolution) of the digital potentiometer, thereby enabling the second reference voltage to be adjusted with high precision.

[0023] In one embodiment, at least one of the first resistor and the third resistor may be a variable resistor, which allows the gain of the non-inverting amplifier to be adjusted with coarse precision.

[0024] In one embodiment, the variable resistor may include a plurality of first resistance elements connected in series and having binary-weighted resistance values, and a plurality of switches connected in parallel with the plurality of first resistance elements and capable of being independently controlled to be turned on and off.

[0025] In one embodiment, the second resistor may include a plurality of second resistive elements connected in parallel and having equal resistance values.

[0026] (Embodiment) Preferred embodiments will be described below with reference to the drawings. The same or equivalent components, parts, and processes shown in each drawing will be designated by the same reference numerals, and redundant descriptions will be omitted where appropriate. Furthermore, the embodiments are merely examples and do not limit the invention, and all features and combinations thereof described in the embodiments are not necessarily essential to the invention.

[0027] In this specification, "a state in which component A is connected to component B" includes not only a case in which component A and component B are directly physically connected to each other, but also a case in which component A and component B are indirectly connected to each other via other components that do not substantially affect the electrical connection between them or that do not impair the function or effect achieved by their connection.

[0028] Similarly, "a state in which component C is provided between component A and component B" includes not only cases in which components A and C, or components B and C, are directly connected, but also cases in which they are indirectly connected via other components that do not substantially affect the electrical connection state between them or impair the functions or effects achieved by their combination.

[0029] 1 is a block diagram of a semiconductor integrated circuit 100 according to an embodiment. The semiconductor integrated circuit 100 includes a reference voltage source 110, an A / D converter 120, and a voltage adjustment circuit 300. The reference voltage source 110 is a bandgap reference circuit or the like, and generates a first reference voltage Vref1 that is independent of the power supply voltage and temperature.

[0030] The A / D converter 120 converts an analog input voltage Vin into a digital output signal Dout.

[0031] The voltage adjustment circuit 300 generates a second reference voltage Vref2 based on the first reference voltage Vref1 and supplies the second reference voltage Vref2 to the A / D converter 120.

[0032] 2 is a circuit diagram of a voltage adjustment circuit 300 according to an embodiment. The voltage adjustment circuit 300 includes a non-inverting amplifier 200 and a second voltage divider circuit 310.

[0033] The non-inverting amplifier 200 includes an operational amplifier 210 and a first voltage divider circuit 220 .

[0034] The operational amplifier 210 receives a first reference voltage Vref1 at a first input terminal (non-inverting input terminal) +. The first voltage divider circuit 220 divides the output voltage Vadj of the non-inverting amplifier 200 and supplies the divided voltage (referred to as a feedback voltage) Vfb to a second input terminal (inverting input terminal) − of the operational amplifier 210. As will be described later, the voltage division ratio α (α<1) of the first voltage divider circuit 220 may be digitally controllable. Vfb=α×Vadj

[0035] In a steady state, an imaginary short (Vref1=Vfb) is established, so the output voltage Vadj of the non-inverting amplifier 200 is Vadj=1 / α×Vref1 The gain of the non-inverting amplifier 200 is 1 / α.

[0036] The second voltage divider circuit 310 divides the output voltage Vadj of the non-inverting amplifier 200 to generate a second reference voltage Vref2. When the voltage division ratio of the second voltage divider circuit 310 is β, Vref2=β×Vadj=β / α×Vref1 This becomes:

[0037] The above is the basic configuration of the voltage regulation circuit 300. The advantages of the voltage regulation circuit 300 become clear when compared with comparative techniques.

[0038] 3 is a circuit diagram of a semiconductor integrated circuit 100R according to a comparative technique. The voltage adjustment circuit 300R includes a buffer 392, a voltage divider circuit 394, and a non-inverting amplifier 396. The voltage divider circuit 394 has a voltage division ratio β equivalent to that of the second voltage divider circuit 310. The output voltage Vref3 of the voltage divider circuit 394 is expressed as follows: Vref3=β×Vref1 This becomes:

[0039] The non-inverting amplifier 396 has the same gain (1 / α) as the non-inverting amplifier 200. The second reference voltage Vref2, which is the output of the non-inverting amplifier 396, is expressed as follows: Vref2=1 / α×Vref3=β / α×Vref1 In other words, the voltage regulation circuit 300R in FIG. 3 and the voltage regulation circuit 300 in FIG.

[0040] The voltage adjustment circuit 300R in Fig. 3 has a larger circuit area and consumes more current due to the buffer 392. In contrast, the voltage adjustment circuit 300 in Fig. 2 does not have the buffer 392 in Fig. 3, and therefore has a smaller circuit area and consumes less current.

[0041] 3, the second reference voltage Vref2 is subject to noise generated by the operational amplifier of the added buffer 392. The voltage adjustment circuit 300 of FIG. 2 does not include the buffer 392, and therefore can reduce the noise contained in the second reference voltage Vref2.

[0042] It should be noted that, since the output impedance of the reference voltage source 110 is high, it is practically difficult to omit the buffer 392.

[0043] The present disclosure covers various devices and methods that can be understood from the block diagram and circuit diagram in Figure 2 or derived from the above description, and is not limited to a specific configuration. Below, more specific configuration examples and examples will be described not to narrow the scope of the present disclosure, but to aid in understanding and clarify the essence and operation of the present disclosure and the present invention.

[0044] (Variation 1) 1, the second reference voltage Vref2 may fluctuate as the A / D converter 120 performs a conversion operation. This fluctuation becomes noise. While the second reference voltage Vref2 is fluctuating, the A / D converter 120 cannot proceed to the next process, making it difficult to operate the A / D converter 120 at high speed.

[0045] 4 is a circuit diagram of a voltage adjustment circuit 300A according to Modification 1. The voltage adjustment circuit 300A includes a buffer 320 in addition to the configuration of FIG. 2. The buffer 320 may be a voltage follower with a gain of 0 dB (1x). Setting the gain to 0 dB enables a high-speed response while suppressing the operating current.

[0046] The second reference voltage Vref2 fluctuates as the A / D converter 120 performs conversion operations. The buffer 320 can suppress fluctuations in the second reference voltage Vref2 supplied to the A / D converter 120 and can settle the fluctuations in the second reference voltage Vref2 in a short time, thereby enabling the A / D converter 120 to operate at high speed.

[0047] (Variation 2) 5 is a circuit diagram of a voltage adjustment circuit 300B according to Modification 2. The voltage adjustment circuit 300B includes a filter 330 in addition to the components of the voltage adjustment circuit 300A in FIG. 4. The filter 330 is inserted between the voltage adjustment circuit 300 and the buffer 320. The filter 330 is a low-pass filter that removes noise traveling from the buffer 320 to the second voltage divider circuit 310, and may be, for example, an RC filter.

[0048] Fluctuations (noise N) in the second reference voltage Vref2 due to the conversion operation of the A / D converter 120 can propagate toward the voltage adjustment circuit 300 via the input capacitance C of the buffer 320. The filter 330 blocks this noise N propagating in the reverse direction, thereby suppressing fluctuations in the second reference voltage Vref2.

[0049] (Variation 3) 6 is a circuit diagram of a voltage adjustment circuit 300C according to Modification 3. The non-inverting amplifier 200C is a linear regulator, and further includes a P-type transistor M1 in addition to an operational amplifier 210 and a first voltage divider circuit 220. The P-type transistor M1 is a P-channel MOSFET (Metal Oxide Semiconductor Field Effect Transistor) or a PNP bipolar transistor.

[0050] By adding the P-type transistor M1, the output impedance of the non-inverting amplifier 200C can be reduced, in other words, the current supply capability can be increased, thereby suppressing fluctuations in the output voltage Vadj of the non-inverting amplifier 200C and fluctuations in the output voltage Vref2 of the second voltage divider circuit 310.

[0051] The non-inverting amplifier 200C further includes a first capacitor C1 and a second capacitor C2. The first capacitor C1 is connected between the control terminal (gate) of the P-type transistor M1 and the output terminal of the non-inverting amplifier 200C.

[0052] When the output voltage Vadj of the non-inverting amplifier 200C increases, the first capacitor C1 applies feedback to increase the voltage at the control terminal (gate) of the P-type transistor M1, reducing the voltage drop across the P-type transistor M1 and suppressing the increase in the output voltage Vadj of the non-inverting amplifier 200C. Conversely, when the output voltage Vadj of the non-inverting amplifier 200C decreases, the first capacitor C1 applies feedback to decrease the voltage at the control terminal (gate) of the P-type transistor M1, increasing the voltage drop across the P-type transistor M1 and suppressing the decrease in the output voltage Vadj of the non-inverting amplifier 200C. In this way, the first capacitor C1 not only functions as phase compensation, but also helps to suppress fluctuations in the output voltage Vadj of the non-inverting amplifier 200C and, ultimately, fluctuations in the second reference voltage Vref2.

[0053] The second capacitor C2 is connected between the control terminal (gate) of the P-type transistor M1 and the output terminal of the second voltage-divider circuit 310. When the output voltage Vref2 of the second voltage-divider circuit 310 increases, the second capacitor C2 applies feedback so that the voltage at the control terminal (gate) of the P-type transistor M1 increases. As a result, the increase in the output voltage Vref2 of the second voltage-divider circuit 310 is suppressed. When the output voltage Vref2 of the second voltage-divider circuit 310 decreases, the second capacitor C2 applies feedback so that the voltage at the control terminal (gate) of the P-type transistor M1 decreases. As a result, the decrease in the output voltage Vref2 of the second voltage-divider circuit 310 is suppressed. In this way, the second capacitor C2 helps to suppress fluctuations in the output voltage Vref2 of the second voltage-divider circuit 310.

[0054] (Variation 4) Fig. 7 is a circuit diagram of a voltage adjustment circuit 300D according to Modification 4. The voltage adjustment circuit 300D includes a buffer 320 and a filter 330, similar to Fig. 5. The non-inverting amplifier 200D is a linear regulator, similar to Fig. 6. Although the first capacitor C1 is omitted in Fig. 7, the first capacitor C1 may be left.

[0055] (Variation 5) 8 is a circuit diagram of a non-inverting amplifier 200E according to Modification 5. The first voltage dividing circuit 220E includes a resistor string 222 and a digital potentiometer 230.

[0056] The resistor string 222 includes a first resistor R1, a second resistor R2, and a third resistor R3 connected in series between the output terminal of the operational amplifier 210 and ground. At least one of the first resistor R1 and the third resistor R3 is a variable resistor. In this example, the first resistor R1 is a variable resistor, and its resistance value can be digitally controlled in response to a first control signal ADJ1.

[0057] The three-terminal digital potentiometer 230 is connected in parallel with the second resistor R2. The output terminal of the digital potentiometer 230 is connected to the second input terminal (−) of the operational amplifier 210.

[0058] Fig. 9 is a circuit diagram showing an example configuration of the non-inverting amplifier 200E of Fig. 8. The first resistor R1 includes resistors R1a and R1b connected in series, n resistors R11, R12, ... R1n (n≧2), and n switches SW11, SW12, ... SW1n. One of the resistors R1a and R1b may be omitted.

[0059] The resistance values ​​of n resistors R11 to R1n are weighted in binary. The resistance value of the i-th resistor R1i is expressed as follows, with R1u as the unit resistance: R1i=R1u / 2 i-1 It can be expressed as:

[0060] Among the plurality of resistors R11 to R1n, the n-th resistor R1n has the smallest resistance value, and its resistance value Rmin is expressed by the following formula. Rmin=R1u / 2 n-1

[0061] The n switches SW11 to SW1n correspond to the n resistors R11 to R1n. The j-th (j=1, 2, . . . n) switch SW1j is connected in parallel with the corresponding resistor R1j.

[0062] The n switches SW11 to SW1n are controlled to be on or off in response to a digital control signal ADJ1.

[0063] The on-resistance of the switches SW11 to SW1n is defined as Ron. This on-resistance Ron is the maximum value when process variations are taken into consideration. In this case, Rmin>Ron This makes it possible to reduce the influence of the on-resistance Ron of the switches SW11 to SW1n on the gain of the voltage adjustment circuit 300, and to adjust the second reference voltage Vref2 with high precision.

[0064] More preferably, Rmin>Ron×(n-2) It is preferable that the following relationship holds.

[0065] The digital potentiometer 230 includes a plurality of m resistors R41 to R4m connected in parallel with the second resistor R2, and a selector 232. The plurality of resistors R41 to R4m have the same resistance value. A tap is provided at one end of each of the plurality of resistors R41 to R4m. The selector 232 selects a voltage generated at one tap from the plurality of taps in response to the control signal ADJ2, and outputs the selected voltage as the feedback voltage Vfb.

[0066] When the adjustment accuracy (resolution) of the digital potentiometer 230 is V2d, the adjustment range is V2d × m. By setting Vd2 to about twice the adjustment accuracy Vd1 of R1, the on-resistance of the switches SW11 to SW1n on the first resistor R1 side can be tolerated to a certain extent. If the deviation of the trimming resistance of the first resistor R1 reaches Rmin, an error of 1 LSB will occur, but the digital potentiometer 230 can absorb this error of 1 LSB.

[0067] 10 is a circuit diagram showing a specific example of the configuration of the first voltage dividing circuit 220E. In this example, n=4, and the first resistor R1 includes four resistors R11 to R14 and four switches SW11 to SW14. The switches SW11 to SW14 are CMOS switches (also called analog switches or transfer gates). The control signal ADJ1 includes n bits b1 to bn corresponding to the multiple switches SW11 to SW1n, and the state of the corresponding switch SW1j is controlled according to each bit bj (j=1, 2...n).

[0068] The second resistor R2 may include k (k≧2) resistor elements R21 to R2k connected in parallel. The resistor elements R21 to R2k may have the same resistance value R2u. During the circuit design stage, the resolution of gain adjustment in the digital potentiometer 230 can be adjusted according to the number k.

[0069] The selector 232 includes m+1 switches SW41 to SW4m+1. The switches SW41 to SW4m+1 are analog switches. The control signal ADJ2 includes m+1 bits b1 to bm+1 corresponding to the switches SW41 to SW4m+1, and the state of the corresponding switch SW4j is controlled according to each bit bj (j=1, 2..., m+1).

[0070] (Variation 6) 11 is a circuit diagram of a non-inverting amplifier 200F according to Modification 6. In this modification, the third resistor R3 is configured as a variable resistor instead of or in addition to the first resistor R1. This configuration also provides the same effects.

[0071] The embodiments described using specific terms merely illustrate the principles and applications of the present invention, and many modifications and changes in arrangement are permitted to the embodiments as long as they do not deviate from the spirit of the present invention as defined in the claims.

[0072] (Addendum) One aspect of the technology disclosed in this specification can be understood as follows.

[0073] (Item 1) a reference voltage source that generates a first reference voltage; a voltage adjustment circuit that generates a second reference voltage based on the first reference voltage; an A / D converter to which the second reference voltage is supplied; Equipped with The voltage regulation circuit a non-inverting amplifier including an operational amplifier and a first voltage divider circuit; a second voltage dividing circuit that divides the output voltage of the non-inverting amplifier; wherein the second reference voltage is dependent on an output voltage of the second voltage divider circuit.

[0074] (Item 2) The voltage regulation circuit 2. The semiconductor integrated circuit according to claim 1, further comprising a buffer that receives the output voltage of the second voltage divider circuit and generates the second reference voltage.

[0075] (Item 3) The voltage regulation circuit 3. The semiconductor integrated circuit according to item 2, further comprising a filter provided between the operational amplifier and the buffer.

[0076] (Item 4) 4. The semiconductor integrated circuit according to item 3, wherein the filter is an RC filter.

[0077] (Item 5) 5. The semiconductor integrated circuit according to any one of items 1 to 4, wherein the non-inverting amplifier further includes a P-type transistor.

[0078] (Item 6) 6. The semiconductor integrated circuit according to item 5, wherein the non-inverting amplifier further includes a first capacitor connected between a control terminal of the P-type transistor and an output terminal of the non-inverting amplifier.

[0079] (Item 7) 7. The semiconductor integrated circuit according to item 5 or 6, wherein the non-inverting amplifier further includes a second capacitor connected between a control terminal of the P-type transistor and an output terminal of the second voltage divider circuit.

[0080] (Item 8) 8. The semiconductor integrated circuit according to any one of items 1 to 7, wherein the first voltage divider circuit has a variable voltage division ratio.

[0081] (Item 9) The first voltage dividing circuit is a first resistor, a second resistor, and a third resistor connected in series between an output terminal of the non-inverting amplifier and ground; a digital potentiometer connected in parallel with the second resistor; 9. The semiconductor integrated circuit according to item 8, comprising:

[0082] (Item 10) 10. The semiconductor integrated circuit according to item 9, wherein at least one of the first resistor and the third resistor is a variable resistor. [Explanation of symbols]

[0083] 100...semiconductor integrated circuit, 110...reference voltage source, 120...A / D converter, 300...voltage adjustment circuit, 200...non-inverting amplifier, 210...operational amplifier, 220...first voltage divider circuit, 222...resistor string, R1...first resistor, R2...second resistor, R3...third resistor, 230...digital potentiometer, 232...selector, 310...second voltage divider circuit, 320...buffer, 330...filter.

Claims

1. a reference voltage source that generates a first reference voltage; a voltage adjustment circuit that generates a second reference voltage based on the first reference voltage; an A / D converter to which the second reference voltage is supplied; Equipped with The voltage regulation circuit a non-inverting amplifier including an operational amplifier and a first voltage divider circuit; a second voltage dividing circuit that divides the output voltage of the non-inverting amplifier; wherein the second reference voltage corresponds to an output voltage of the second voltage divider circuit.

2. The voltage regulation circuit 2. The semiconductor integrated circuit according to claim 1, further comprising a buffer that receives the output voltage of said second voltage divider circuit and generates said second reference voltage.

3. The voltage regulation circuit 3. The semiconductor integrated circuit according to claim 2, further comprising a filter provided between said operational amplifier and said buffer.

4. 4. The semiconductor integrated circuit according to claim 3, wherein the filter is an RC filter.

5. 5. The semiconductor integrated circuit according to claim 1, wherein the non-inverting amplifier further includes a P-type transistor.

6. 6. The semiconductor integrated circuit according to claim 5, wherein the non-inverting amplifier further includes a first capacitor connected between a control terminal of the P-type transistor and an output terminal of the non-inverting amplifier.

7. 6. The semiconductor integrated circuit according to claim 5, wherein said non-inverting amplifier further includes a second capacitor connected between a control terminal of said P-type transistor and an output terminal of said second voltage divider circuit.

8. 5. The semiconductor integrated circuit according to claim 1, wherein said first voltage divider circuit has a variable voltage division ratio.

9. The first voltage dividing circuit is a first resistor, a second resistor, and a third resistor connected in series between an output terminal of the non-inverting amplifier and ground; a digital potentiometer connected in parallel with the second resistor; The semiconductor integrated circuit according to claim 8 , comprising:

10. 10. The semiconductor integrated circuit according to claim 9, wherein at least one of the first resistor and the third resistor is a variable resistor.

Images