Method for programming a non-volatile memory

Abstract

The present invention relates generally to a method of programming a non-volatile memory, and more particularly to a method of band-to-band tunneling programming of a non-volatile memory.SOLUTION: A method for programming a nonvolatile memory, wherein the memory comprises at least one storage unit, the storage unit comprises a P well and an N well which are adjacent to each other and located in a deep N well, a 1PMOS transistor and an NMOS capacitor are respectively located in the N well and the P well, a floating gate covers the PMOS transistor and the NMOS capacitor, and the 1PMOS transistor in the storage unit is programmed in a band-to-band tunneling manner. The programming method of the present invention does not require a high drive charge pump and is more competitive in low power, low capacity memory applications.SELECTED DRAWING: None

Description

[Technical Field]

[0001] The present invention relates generally to methods for programming non-volatile memories, and more particularly to band-to-band tunneling programming methods for non-volatile memories. [Background technology]

[0002] Non-volatile memories include a number of storage units arranged in rows and columns, which typically include PMOS and / or NMOS transistors and may also include MOS coupling capacitors.

[0003] Currently, most nonvolatile memory programming methods use channel hot electron tunneling in PMOS or NMOS transistors in the storage unit to inject negative charges into the floating gate of the transistor. The advantage of this programming method is that it can be applied to a relatively large programming voltage range, and programming can be achieved as long as the voltage difference between the source and drain of the MOS transistor device satisfies the turn-on condition and enters saturation. This method is also applicable to multiple types of transistor devices manufactured using different process platforms. The drawback of this programming method is that it requires a high-driving charge pump, which consumes high power during programming. The high-driving charge pump requires a relatively large area, which is disadvantageous in reducing the memory size.

[0004] In the channel hot electron tunneling programming method, the positive and negative voltages required for memory programming are usually generated by a Dickson charge pump circuit. Programming, which induces channel hot holes in a transistor in a storage unit to inject hot electrons into its floating gate, requires the creation of a high lateral electric field in the channel to accelerate carriers and generate the saturated hole current required for programming. The high lateral electric field in the channel and the large channel current require the charge pump to have high driving capabilities for the positive and negative voltages and consume a lot of power.

[0005] A charge pump is a voltage amplifier circuit that generates the required voltage and drive capability using multiple series-parallel connections of MOS tube capacitances. A high-drive charge pump requires a larger number of parallel-connected MOS tubes, resulting in a relatively large area. Charge pumps typically occupy a relatively large area in a memory, for example, in a single-layer polysilicon PMOS memory, especially in a small-capacity (e.g., 256x8-bit) memory, the area can exceed 50%. Therefore, a high-drive charge pump hinders the reduction of memory size.

[0006] Thus, there is a need in the industry for new programming methods that allow for further reduction in power consumption and are advantageous in reducing memory area. Summary of the Invention [Means for solving the problem]

[0007] The present invention relates to a programming method for a nonvolatile memory, the memory including at least one nonvolatile storage unit built on a P-type substrate, each nonvolatile storage unit including a deep N-well located in the P-type substrate, one P-well and one N-well located in the deep N-well, a first PMOS transistor located in the N-well, an NMOS capacitor located in the P-well, the NMOS capacitor including an N+ junction area located in the P-well, and a floating gate covering the PMOS transistor and the NMOS capacitor, the programming method comprising: programming the first PMOS transistor in the nonvolatile storage unit by band-to-band tunneling; The programming method includes the steps of: (a) making the potential of an N-well higher than the potential of one electrode terminal of a first PMOS transistor, and forming a reverse bias voltage on a PN junction at the interface between the N-well and the electrode terminal using a potential difference between the two, where the reverse bias voltage causes electrons in the PN junction to concentrate toward one side of the PN junction closer to the N-well; (b) making the potential on the floating gate of the first PMOS transistor higher than the potential of the electrode terminal, where the potential difference between the two allows a strong electric field to be formed between the floating gate and the electrode terminal, with an electric field strength greater than 8 MV / cm; and (c) injecting electrons from one side of the PN junction at the interface between the N-well and the electrode terminal closer to the N-well into the floating gate of the first PMOS transistor under the action of the strong electric field, thereby realizing programming.

[0008] In one preferred embodiment, the potential difference between the N well and the electrode terminal is smaller than the avalanche breakdown voltage of the PN junction at the interface between them, and more preferably, the potential difference is 0.1 to 1.0 V smaller than the avalanche breakdown voltage of the PN junction at the interface between them.

[0009] In another preferred embodiment, the potential on the floating gate of the first PMOS transistor is obtained by coupling a potential applied on an N+ coupling area of ​​an NMOS capacitor, the potential applied on the N+ coupling area being less than or equal to the potential of an N-well, more preferably the potential applied on the N+ coupling area being equal to the potential of an N-well.

[0010] In yet another preferred embodiment, the electrode terminal involved in programming of the first PMOS transistor is a source electrode of the transistor, which is at a potential of 0V during the programming process, and another electrode terminal of the first PMOS transistor is a drain electrode, which is in a floating state during the programming process.

[0011] In yet another preferred embodiment, the capacitance of the NMOS is greater than the PMOS gate capacitance.

[0012] In yet another preferred embodiment, the non-volatile storage unit further includes a second PMOS transistor located in the N-well, wherein the drain electrode of the first PMOS transistor is coupled to the source electrode of the second PMOS transistor, and the drain electrode of the second PMOS transistor is not involved in programming during the programming process. More preferably, during the programming process, the drain electrode of the second PMOS transistor is in a floating state, or the channel of the second PMOS transistor is not conductive. Even more preferably, during the programming process, the drain electrode of the second PMOS transistor is in a floating state, and at the same time, the potential of the gate electrode of the second PMOS transistor is the same as the potential of the N-well.

[0013] In yet another preferred embodiment, the floating gate in the storage unit is a single-layer polycrystalline silicon gate electrode.

[0014] In yet another preferred embodiment, the non-volatile memory is an electrically programmable erasable non-volatile memory. [Effects of the Invention]

[0015] In the prior art, when programming using channel hot electron tunneling, achieving a high lateral electric field in the channel requires a charge pump with high driving capability for positive and negative voltages, resulting in a large channel operating current, typically >5mA, and relatively high programming power consumption. In the present invention, when programming using band-to-band tunneling, only a single voltage is required, eliminating the need for a negative voltage, and reducing the driving capability requirements for the charge pump. This results in an extremely small programming current, typically <100μA, reaching nA levels per bit. This significantly reduces memory programming power consumption.

[0016] The programming method of the present invention does not require a high-drive charge pump and can significantly reduce the area of ​​the charge pump compared to the existing channel hot electron tunneling programming method. For example, a 5V transistor device in a 0.18 μm process platform was programmed using the band-to-band tunneling scheme of the present invention, and the required charge pump area was only 0.03 mm. 2 On the other hand, if programming is performed using the channel hot electron tunneling method, the required charge pump area is up to 0.15 mm 2 The programming method of the present invention can greatly reduce the area occupied by the charge pump in the memory, which is very advantageous in reducing the size of the memory.

[0017] Furthermore, the programming method of the present invention does not require a high-drive charge pump, simplifies memory design, and is more competitive in low-power, small-capacity memory applications.

[0018] Example embodiments are described by way of example and not by way of limitation in the examples illustrated in the figures of the accompanying drawings, in which like numbers indicate similar elements and in which: Other features of the embodiments of the present invention will become apparent from the accompanying drawings and the detailed description that follows. [Brief explanation of the drawings]

[0019] [Figure 1a] 1 shows a top view of one storage unit of a non-volatile memory employing the programming method of the present invention. [Figure 1b] 2 shows a cross-sectional view along section line AA of one storage unit of a non-volatile memory employing the programming method of the present invention. [Figure 1c] 1 shows a cross-sectional view along section line BB of one storage unit of a non-volatile memory employing the programming method of the present invention. [Figure 2] 2 illustrates the relationship between the reverse bias voltage on the PN junction between the electrode terminal of the first PMOS transistor and the N-well and the output current in one embodiment of the storage unit illustrated in FIG. 1. [Figure 3a] 2 shows the relationship between the programming voltage (VPP) and the read current after programming under different programming times (10 μs / 100 μs / 1 ms / 10 ms) of the first PMOS transistor in one embodiment of the storage unit shown in FIG. 1. [Figure 3b] 2A and 2B show the relationship between the control gate potential and the read current in a read operation after programming the first PMOS transistor of the storage unit shown in FIG. 1 for different time periods under programming voltages (VPP) of 9.5V and 10.5V, respectively. [Figure 3c] 2A and 2B show the relationship between the control gate potential and the read current in a read operation after programming the first PMOS transistor of the storage unit shown in FIG. 1 for different time periods under programming voltages (VPP) of 9.5V and 10.5V, respectively. [Figure 3d]1 shows the relationship between the control gate potential and the read current in a read operation after performing 1 / 10 / 100 / 1000 / 10K programming and erasing operations on the first PMOS transistor in the storage unit shown in FIG. 1, respectively. [Figure 4] 2 shows a 2-row by 2-column array of the storage units shown in FIG. [Figure 5] 5A-5C show bias voltage signals coupled to the array shown in FIG. 4 during different periods of operation of the array. [Figure 6] 1 shows a top view of one storage unit of another non-volatile memory employing the programming method of the present invention. [Figure 7] 7 shows a cross-sectional view of the storage unit shown in FIG. 6 along section line AA. [Figure 8] 7 illustrates a cross-sectional view of the storage unit shown in FIG. 6 along section line BB. [Figure 9] 7 shows a cross-sectional view of the storage unit shown in FIG. 6 along section line CC. [Figure 10] 7 shows a storage array arranged in 2 rows and 2 columns of storage units as shown in FIG. [Figure 11] 11A-11C show bias voltage signals coupled to the array shown in FIG. 10 during different periods of operation of the array. DETAILED DESCRIPTION OF THE INVENTION

[0020] The nonvolatile memory of the present invention includes one-time programming memory and multi-time programmable erasable memory, with electrically programmable erasable nonvolatile memory being preferred.

[0021] The memory of the present invention can be fabricated using processes commonly used in silicon chip factories with deep submicron technology, such as a 40 nm to 350 nm process platform, and is preferably fabricated using a BCD (bipolar transistor, CMOS, and DMOS device fabrication on the same chip) process platform.

[0022] The memory unit of the present invention has a deep N-well to isolate the memory unit from the substrate. The first PMOS transistor and the NMOS capacitor in the memory unit are located in an N-well and a P-well, respectively, adjacently arranged in the deep N-well. Here, the PMOS transistor includes a PMOS gate oxide and an overlying gate electrode, and the NMOS capacitor includes an N+ junction area, a gate oxide, and an overlying gate electrode located in the P-well. The N+ junction area is formed by N+ source / drain ion implantation. The gate electrode of the NMOS capacitor is extended and integrated with the PMOS gate to form a floating gate of the memory unit. The floating gate covers the PMOS transistor and the NMOS capacitor but does not cover the N+ junction area of ​​the NMOS capacitor. The floating gate is preferably a single-layer polysilicon gate. The N+ junction area connects a control word line (WL) to the control gate of the memory unit. The control gate is formed by the channel region of the NMOS capacitor. A potential is applied on the N+ coupling area, and the channel region of the NMOS capacitor allows the potential to be coupled to the floating gate. Thus, the coupling capacitance structure consists of the floating gate overlapping the active area in the P-well, the underlying gate oxide, and the NMOS channel. To improve the efficiency of the coupling gate, the coupling capacitance is made much larger than that of the PMOS gate.

[0023] The storage unit of the memory of the present invention may further include a second PMOS transistor connected in series with the first PMOS transistor and located in an N-well. The second PMOS transistor also includes a gate oxide and an overlying gate electrode, preferably a single-layer polysilicon gate, connected to an access word line (WL) signal. The N+ junction region of the NMOS capacitor connects a control gate signal (CG) to the control gate of the storage unit, which is formed by the channel region of the NMOS capacitor. The second PMOS transistor, as the gate tube of the programmable first PMOS transistor, does not participate in programming the storage unit.

[0024] The programming of the storage unit is performed in a first PMOS transistor, and the programming method is band-to-band tunneling. One electrode terminal (e.g., source electrode) of the first PMOS transistor is involved in the programming. Another electrode terminal (e.g., drain electrode) may or may not be involved in the programming. Preferably, the other electrode terminal is not involved in the programming, and more preferably, the electrode terminal not involved in the programming is in a floating state during the programming process.

[0025] When programming starts, for the electrode terminal involved in programming of the first PMOS transistor, step (a) is first performed: the potential of the N-well is made greater than the potential of the electrode terminal, and the potential difference between them forms a reverse bias voltage on the PN junction at the interface between the N-well and the electrode terminal, which causes electrons in the PN junction to concentrate toward one side of the PN junction that is closer to the N-well.

[0026] A larger potential difference between the N-well and the electrode terminal involved in programming the first PMOS transistor is advantageous in concentrating more electrons in the PN junction on one side closer to the N-well, and the upper limit of this potential difference must be smaller than the avalanche breakdown voltage of the PN junction. Preferably, this potential difference is 0.1 to 1.0 V smaller, more preferably 0.1 to 0.7 V smaller, and even more preferably 0.1 to 0.5 V smaller than the avalanche breakdown voltage of the PN junction at the interface between the N-well and the electrode terminal involved in programming the first PMOS transistor. The potential difference may be 5.0 to 10.5 V, preferably 7.0 to 10.5 V, and more preferably 9.0 to 10.5 V. When the potential difference is close to the avalanche breakdown voltage of the PN junction, electrons on one side closer to the N-well in the PN junction are more likely to be injected by the floating gate under the action of an electric field, resulting in a better programming effect, shorter programming time, better programming convergence, and higher programming efficiency.

[0027] In the prior art memory circuit design, when the potential difference is close to but does not exceed the avalanche breakdown voltage of the PN junction, programming can be successful while avoiding irreversible damage or destruction of the PN junction. Furthermore, the inventors have discovered that when programming is performed under a condition where the potential difference is less than the avalanche breakdown voltage of the PN junction, the memory can be programmed 10,000 times, which is sufficient to meet application needs.

[0028] Then, steps (b) and (c) are sequentially performed to make the potential on the floating gate of the first PMOS transistor greater than the potential of the electrode terminal involved in its programming, and the potential difference between them allows a strong electric field having an electric field strength greater than 8 MV / cm to be formed between the floating gate and the electrode terminal, such that electrons on one side approaching the N-well in the PN junction can be injected into the floating gate by band-to-band tunneling, thereby performing programming.

[0029] The electric field formed by the potential on the floating gate of the first PMOS transistor and the potential of the electrode terminal involved in programming is preferably >8 MV / cm. For example, the potential on the floating gate may be 6.5 to 10.5 V, more preferably 7.0 to 10.5 V, and even more preferably 9.0 to 10.5 V.

[0030] The potential on the floating gate of the first PMOS transistor is obtained by coupling the potential applied to the N+ coupling area of ​​the NMOS capacitor through the channel of the NMOS capacitor. To improve coupling efficiency, the NMOS capacitor is much larger than the capacitance of the PMOS gate. The gate capacitance value of the NMOS capacitor may be 1 to 10 times, preferably 1.5 to 7 times, and more preferably 2 to 5 times, the gate capacitance value of the first PMOS transistor.

[0031] During the programming process, preferably, the potential applied on the N+ coupling area is less than or equal to the potential of the N-well, thus avoiding leakage between the P-well and the N-well. More preferably, the potential applied on the N+ coupling area is the same as the potential of the N-well.

[0032] Preferably, the electrode terminal of the first PMOS transistor involved in programming has a potential of 0V during the programming process, and the other electrode terminal not involved in programming is in a floating state during the programming process, and the electrode terminal involved in programming can be called a source electrode, and the other electrode terminal not involved in programming is called a drain electrode.

[0033] In the programming method of the present invention, steps (a) and (b) may be performed in either order, in reverse order, or simultaneously. Regardless of the order of steps (a) and (b), step (c) always occurs after steps (a) and (b).

[0034] The above-mentioned nonvolatile storage unit of the present invention may further include a second PMOS transistor located in the N-well, one electrode terminal of which is coupled to an electrode terminal (e.g., a drain electrode) of the first PMOS transistor that is not involved in programming, and another electrode terminal of which is not involved in programming.

[0035] Under the circumstance where the source electrode of the first PMOS transistor is involved in programming, if the drain electrode of the first PMOS transistor is coupled to the source electrode of the second PMOS transistor, the drain electrode of the second PMOS transistor is not involved in programming and is preferably in a floating state when programming, or the channel of the second PMOS transistor is not made conductive during the programming process.

[0036] More preferably, during the programming process, the potential of the gate electrode of the second PMOS transistor is the same as the potential of the N-well, so as to avoid generating electrical stress on the gate oxide layer, which would affect the service life of the gate oxide layer and the transistor.

[0037] According to the actual application case, the first PMOS transistor and the second PMOS transistor may be the same or different, but preferably they are the same.

[0038] In a more preferred embodiment, for a memory unit that does not include a second PMOS transistor, when programming, the potential of the N-well is the same as the potential of the N+ junction area, the potential of the electrode terminal involved in programming of the first PMOS transistor is 0V, and the electrode terminal not involved in programming is in a floating state. For a memory unit that includes a second PMOS transistor, when programming, the potential of the N-well and the potential of the N+ junction area are the same as the potential of the gate electrode of the second PMOS transistor, the potential of the electrode terminal involved in programming of the first PMOS transistor is 0V, and the electrode terminal not involved in programming of the second PMOS transistor is in a floating state. Under this circumstance, the voltage need during programming is single, which is very convenient for operation.

[0039] The programming method for nonvolatile memory of the present invention will be described in more detail below in combination with specific examples. The following description will be made with reference to specific examples. Obviously, various adjustments and modifications can be made to these examples without departing from the spirit and relatively broad scope of various embodiments of the present invention. In addition, although specific voltage values ​​are provided in the examples and accompanying drawings, it should be clear that these values ​​are not necessarily exact values, but are used to express the general concept of bias means.

[0040] The memory in the embodiment is an electrically programmable erasable nonvolatile memory fabricated on a 180 nm BCD process platform, the first and second PMOS transistors in the storage unit are identical, the two transistors and the NMOS capacitor are all 5 V devices, the gate oxide thickness is 120 angstroms, and the floating gate of the transistor is single-layer polysilicon.

[0041] FIG. 1a shows a top view of one non-volatile storage unit 100 of the memory in this embodiment, and FIGS. 1b-1c show cross-sectional views of the storage unit along section lines AA and BB in FIG. 1a, respectively.

[0042] In this embodiment, the nonvolatile storage unit 100 is constructed in a P-type silicon substrate 101. A deep N-well 104 is disposed in the P-substrate 101 to electrically isolate the storage unit from the substrate. An N-well 102 and a P-well 103 are adjacent to each other and disposed in the N-deep well 104. A first PMOS transistor 110 is disposed in the N-well 102. The PMOS transistor 110 includes a P-type drain electrode 112 and a source electrode 111. The drain electrode 112 includes a lightly doped area 112A and a heavily doped P+ contact area 112B. The source electrode 111 includes a lightly doped area 111A and a heavily doped P+ contact area 111B.

[0043] The source electrode 111 is connected to a common line (COM), and the drain electrode 112 is connected to a bit line (BL). The transistor 110 is surrounded by a shallow trench filled with a thick field oxide 114. Between the source electrode 111 and the drain electrode 112 is a channel area 113. A gate oxide layer 115 covering the top surface of the channel 113 has a thickness of 120 Angstroms. A conductively doped polycrystalline silicon gate is disposed on top of the gate oxide 115, forming a floating gate 116 of the first PMOS transistor.

[0044] The floating gate 116 and gate oxide 115 extend into the P well 103 and overlap the active area 125, forming the upper plate and dielectric of the NMOS capacitor 120. The floating gate 116 also overlaps the charge injection element 122, which consists of a lightly doped N area 122A and a heavily doped N+ area 122B. The floating gate 116 is surrounded by a sidewall isolation layer 117, which is typically made of silicon nitride or silicon oxide.

[0045] When forming the N+ or P+ area, the sidewall isolation layer 117 prevents the N+ or P+ implant from entering the lightly doped N or P area. The charge injection member 122 is connected to the word line (WL), which is also connected to the P-well by a P+ contact area (not shown). During operation, if the potential of the floating gate 116 is less than the WL, the voltage difference becomes greater than the threshold voltage of the NMOS capacitor, and the P-well area 121 below the floating gate is inverted. Electrons emitted by the injection member 122 form an electron layer in region 121, thereby forming the bottom plate of the NMOS capacitor 120. The bottom plate 121 is connected to the WL by the injection member 122. The N+ coupling region connects the control word line (WL) to the control gate of the storage unit, which is formed by the channel region of the NMOS capacitor. A potential can be applied on the N+ coupling area and coupled to the floating gate by the channel region of the NMOS capacitor.

[0046] All processing steps required to form storage unit 100 are the same as those used to form other on-chip circuits in the logic fabrication process. No additional processing steps are required. The gate capacitance value of NMOS capacitor 120 is 3.4 times the gate capacitance value of first PMOS transistor 110.

[0047] When programming the memory unit 100, the source electrode 111 of the first PMOS transistor 110 participates in programming, while the drain electrode 112 is not involved and is in a floating state. First, the potentials of the N-well and deep N-well are set to VPP, COM is driven to 0V, and BL is floating. Then, WL is driven to VPP to perform programming. VPP is a positive value. Since COM is 0V, VPP can also be called the programming voltage.

[0048] The potential of the N-well is a positive value VPP, and the potential of the doped areas 111A and 111B of the source electrode 111 of the first PMOS transistor is 0V. A reverse bias voltage VPP is applied to the PN junction between the N-well and the doped area of ​​the source electrode of the first PMOS transistor, concentrating electrons in the PN junction toward one side of the PN junction closer to the N-well. The floating gate 116 then receives the potential VPP of the N+ junction area of ​​the NMOS capacitor, and a positive potential of 0.95 times VPP is applied. A strong electric field greater than 8 MV / cm is formed between the floating gate 116 and the doped area of ​​the source electrode 111 of the first PMOS transistor, causing band-to-band tunneling in the electrons on one side of the PN junction closer to the N-well, transferring them to the floating gate, completing programming.

[0049] FIG. 2 shows the relationship between the reverse bias voltage on the PN junction between the source electrode doped area and the N-well of the first PMOS transistor 110 in the memory unit 100 and its output current. In this diagram, the abscissa represents the source electrode potential, and the ordinate represents the output current (amperes), with the N-well potential at 0V. As can be seen from FIG. 2, when the reverse bias voltage of the PN junction is 10.2V or higher, the output current rapidly increases. At this time, a large number of electron-hole pairs are generated, and when the voltage exceeds approximately 10.6V, avalanche breakdown of the junction occurs. By programming close to the breakdown voltage before avalanche breakdown, a large number of electrons are concentrated toward one side of the PN junction closer to the N-well, contributing to improved programming efficiency, shorter programming time, and better convergence. Therefore, the most suitable VPP is a bias voltage value between 10.05V and 10.5V, which is the voltage before avalanche breakdown of the PN junction occurs. The programming voltage VPP does not affect the programming life of the memory when it approaches the avalanche breakdown of the PN junction (a large number of electron-hole pairs are generated). The inventors have experimentally demonstrated that the programming operation can reach 10,000 programming cycles by performing a programming operation under a voltage close to the avalanche breakdown voltage of the PN junction, for example, 10.5 V.

[0050] When VPP is set to 10.5V, an electric field with a strength of 8.3 MV / cm is formed between the floating gate 116 and the doped area of ​​the source electrode 111 of the first PMOS transistor, which is greater than 8 MV / cm and can realize band-to-band tunneling of electrons to the floating gate.

[0051] During programming, electrons are injected into the floating gate of the storage unit, reducing the threshold voltage of the first PMOS transistor and making the channel of the transistor more conductive, resulting in a higher read current during a read operation.

[0052] In a read operation after programming, a potential is applied to the control gate such that the difference between the potential of the floating gate of the first PMOS transistor and the potential of the N-well is greater than the threshold voltage of the transistor, thereby making the channel of the transistor conductive, and at the same time, a potential difference exists between the source and drain electrodes of the transistor, causing a channel read current to flow out of the bit line.

[0053] FIG. 3a shows the relationship between the programming voltage (VPP) and the unit read current after programming for different programming times (10 μs / 100 μs / 1 ms / 10 ms) of the first PMOS transistor 110 in the memory unit 100. As shown in FIG. 3a, when VPP is ≥ 9 V, the programming effect is relatively significant. When VPP is 9 V and the programming time is 10 ms, the channel read current after programming is > 10 μA, which is relatively significant. As VPP increases within the 9-10 V range, the channel read current increases sharply, significantly accelerating the programming speed. After VPP exceeds 10 V, the channel read current after 10 μs of programming reaches > 20 μA. At this time, programming approaches saturation, with good convergence. Increasing the programming time or voltage does not necessarily improve the programming effect.

[0054] 3b and 3c respectively show the relationship between the control gate potential and the read current during a read operation after programming the first PMOS transistor 110 in the memory unit 100 for different time periods using VPP of 9.5V and 10.5V. As can be seen from FIGS. 3b and 3c, when programming is performed using VPP of 9.5V, the channel read current flowing from the bit line has poor convergence at different programming times, while when programming is performed using VPP of 10.5V, the channel read current has very good convergence at different programming times.

[0055] 3d shows the relationship between the control gate potential and the read current during a read operation for the first PMOS transistor 110 in the memory unit 100 after 1 / 10 / 100 / 1000 / 10K programming and erasing operations, respectively. The programming and erasing conditions are the same as those of the unit 200 in FIG. 5, where VPP is 10.5V. As shown in FIG. 3d, after 10K programming and erasing cycles, the difference between the programming and erasing currents (read window) is still greater than 20 μA, which meets the needs of the circuit design (the difference between the programming and erasing currents needs to be >= 3 μA).

[0056] In most applications, multiple non-volatile units 100 can be arranged together to form a storage array. For illustrative purposes, the operation of one 2x2 storage array 250 is described and shown in Figure 4. The array includes four storage units, arranged in two rows and two columns. Arrays of different sizes can be formed by increasing and / or decreasing the number of rows and / or columns. Storage array 250 includes storage units 200, 210, 220, and 230. Storage array 250 further includes NMOS capacitors 201, 211, 221, and 231, and first PMOS transistors 202, 212, 222, and 232.

[0057] In one embodiment, the WLs of memory units 200 and 210 are connected to WL0 to form one memory row, and the WLs of memory units 220 and 230 are connected to WL1 to form another memory row. The common lines (COM) and bit lines (BL) of units 200 and 220 are connected to COM0 and BL0, respectively, to form one memory column. Similarly, the common lines (COM) and bit lines (BL) of units 210 and 230 are connected to COM1 and BL1, respectively, to form another memory column. The memory array is constructed in a P-type substrate. The deep N-wells of these memory units are all integrated to form a single deep N-well (e.g., deep N-well 254). The N-wells and P-wells of the memory units in one memory row are integrated, respectively. As a result, each memory row includes one N-well (e.g., NW252A, NW252B) and one P-well (e.g., PW253A, PW253B).

[0058] The individual N-wells are all connected to a deep N-well, which in turn connects to a single DNW. The P-well of the "m"th memory row is connected to word line WLm, where "m" represents the row number. Consolidating wells within a row allows for tighter encapsulation of memory units in the array, eliminating the space between multiple wells. The memory array is built in the same substrate as the rest of the on-chip logic, which requires the substrate to be grounded or at 0v.

[0059] 5 shows the bias voltages under programming and reading modes of the array. Each individual storage unit in array 250 can be independently programmed or erased. Therefore, storage array 250 can be used to form a single large electrically programmable erasable memory (EEPROM), unlike FLASH memory, in which all units within a page are erased together. Alternatively, storage array 250 can form a single FLASH memory by programming or erasing the units within array 250.

[0060] Designated storage units can be individually programmed. During programming, electrons are injected into the floating gate of the selected unit by band-to-band tunneling, thereby reducing the threshold voltage of the first PMOS transistor in the storage unit, making it more conductive and increasing the read current during a read operation.

[0061] For example, memory unit 200 can be programmed by driving WL0 to VPP, BL0 floating, and COM0 to 0V, and the potential of the N-well and deep N-well is VPP. VPP is 10.5V. The programming process of memory unit 200 is the same as that of memory unit 100 described above.

[0062] Because COM1 of storage unit 210 is floating, there is no reverse bias voltage on the PN junction between the N-well and the source electrode of the first PMOS transistor, and electrons capable of tunneling cannot be formed in the PN junction, and a strong electric field cannot be formed between the floating gate and the source electrode to stimulate electron tunneling, making unit 210 unprogrammable. WL1 of unit 220 is floating, and a strong electric field cannot be formed between the floating gate and the source electrode of the first PMOS transistor to stimulate electron tunneling, making unit 210 unprogrammable. COM1, BL1, and WL1 of unit 230 are all floating and unprogrammable.

[0063] During programming, the deep N-well is driven to VPP, ensuring that all junctions in the array 250 are all reverse biased.

[0064] In a read operation, data in a row of memory units can be read simultaneously. The PMOS transistors in the programmed and unprogrammed units have threshold voltages of approximately 0V and -1.5V, respectively. In one embodiment, the memory units in row 0 are selected for the read operation, with unit 200 in a programmed state and all other units unprogrammed. This causes all common lines (COM) to be driven to 1.2V, all bit lines (BL) to be precharged to 0V, and the N-well and deep N-well to be driven to 1.5V. The unselected word lines are driven to 1.5V, while the selected word line WL0 is driven to 0V.

[0065] As a result, PMOS transistor 202 in unit 200 is turned on, pulling BL0 to 1.2v, but because the negative threshold voltage of transistor 212 is lower than the floating gate bias voltage, PMOS transistor 212 in unit 210 remains off, and BL1 is still at 0v. The high voltage on BL0 is then detected by a sense amplifier, which drives it to output a data signal with one status "1". Similarly, the low status on BL1 is detected by another amplifier, which drives it to output another status "0". Note that the transistors of units in unselected rows are turned off and are not related to their programming status. This is because their word line voltages are high; therefore, they have no effect on the bit lines.

[0066] Designated storage units in the array can also be erased. Erasing can be accomplished by conventional techniques, such as Fowler-Nordheim tunneling. During an erase operation, electrons are pulled out of the floating gate of the selected unit, raising the threshold voltage of the PMOS transistor, making it more difficult to conduct, and reducing the read current during a read operation.

[0067] For example, storage unit 200 can be erased by driving WL0 to -5V and both BL0 and COM0 to 5V, with the N-well and deep N-well potentials at 5V. Under these bias conditions, the bottom plate of NMOS capacitor 201 forms an inversion layer, and the floating gate is coupled to a potential of approximately -4.7V. With the transistor's source and drain electrodes driven to 5V, an inversion layer also forms in the channel area of ​​PMOS transistor 202. The inverted channel, which connects the source and drain electrodes, receives a voltage of 5V. This results in a total voltage applied to the gate oxide of PMOS transistor 202 of approximately 9.7V, creating a high electric field sufficient to tunnel electrons trapped in the floating gate into the inversion channel, which is fully filled with positive carriers. The high electric field can exceed approximately 10 MeV, and the tunneling mechanism is Fowler-Nordheim tunneling.

[0068] In this embodiment, WL0 and P-well 253B, shared by units 200 and 210, can be driven to one negative potential value less than the substrate bias voltage (0v) because P-well 253B is separated from the substrate by deep N-well 254. Deep N-well 254 is driven to 5v during erase.

[0069] The storage unit 210 also receives the word line voltage of −5V, but the source and drain electrodes of its PMOS transistor 212 receive a bias voltage of 0V. As a result, the voltage across the gate oxide is only 4.7V, and even if the channels of both the read transistor 212 and the NMOS capacitor 211 all form inversion layers, the resulting electric field is not sufficient to trigger Fowler-Nordheim tunneling. Therefore, the storage unit 210 is not affected during the erase period.

[0070] In storage unit 220, the source and drain electrodes of transistor 222 are driven to 5V, while the word line connected to WL1 receives a bias voltage of 0V. As a result, the voltage across the gate oxide of transistor 222 is only 4.7V. Even though the channels of both read transistor 222 and NMOS capacitor 221 all form inversion layers, the electric field is not sufficient to trigger Fowler-Nordheim tunneling. Therefore, storage unit 220 is not affected during the erase period.

[0071] In storage unit 230, the bias voltages on the word line, source electrode, and drain electrode of transistor 232 are all 0V, which allows negligible electric fields through the gate oxide of read transistor 232, and the unit is unaffected during erase.

[0072] The read operation after erasing is the same as the read operation after programming. In the read operation, data in one row of memory units can be read simultaneously. The first PMOS transistor in the erased unit has a threshold voltage of about -1.5V.

[0073] In another embodiment, a second PMOS transistor 330 is added and connected in series with the first PMOS transistor 310 to form another storage unit 300, as shown in Figure 6. The first PMOS transistor 310 is similar to the first PMOS transistor 110 of the non-volatile storage unit 100 in Figure 1. Figure 6 shows a top view of the non-volatile storage unit 300 with the second PMOS transistor 330. According to different embodiments, cross-sectional views along cross-sectional lines AA, BB, and CC in Figure 6 are shown in Figures 7, 8, and 9, respectively.

[0074] The non-volatile storage unit 300 comprises an NMOS coupling capacitor 320, a first PMOS transistor 310, and a second PMOS transistor 330. The first PMOS transistor 310 includes a P-type drain area 312, which includes a lightly doped area 312A and a P+ contact area 312B. The drain electrode P+ contact area 312B of the transistor 310 is shared with the source electrode P+ contact area of ​​the transistor 330, thereby connecting the two PMOS transistors in series. The source electrode of the transistor 310 is connected to a common line (COM). The unit 300 also includes a thick field oxide 314. A channel area 313 is located between the source and drain electrodes of the transistor 310.

[0075] The bit line (BL) is connected to the drain electrode of transistor 330. The charge injection member 322 of NMOS coupling capacitor 320 is connected to a control gate signal CG, which is used to control the voltage of the floating gate during a storage operation. The charge injection member 322 includes a lightly doped N area 322A and a heavily doped N+ area 322B. The gate of transistor 330 is connected to a word line (WL). By controlling the gate voltage with WL, transistor 330 can be turned on or off, thereby connecting or disconnecting the transistor from the bit line BL. The source electrode of transistor 310 is connected to a common signal (COM), similar to that in memory unit 100. Similar to memory unit 100, NMOS coupling capacitor 320 is disposed in a P-well 303, and PMOS transistors 310 and 330 are disposed in an N-well 302 adjacent to the P-well. These two wells are all located within a deep N-well (DNW) 304, which is disposed within a P-type substrate 301.

[0076] When programming the memory unit 300, similar to the memory unit 100, the source electrode of the first PMOS transistor participates in programming, but the drain electrode does not. The drain electrode of the second PMOS transistor is floating, and this transistor does not participate in programming. When programming, the potentials of the N-well and deep N-well are first driven to VPP, COM is driven to 0V, and BL is floating. Then, CG and WL are driven to VPP for programming. VPP is 10.5V. The programming process and mechanism are the same as those of the memory unit 100.

[0077] 10 shows a storage array 450 including four storage units 300 arranged in two rows and two columns. Thus, units 420 and 430 form one storage row, with their WL and CG lines connected to WL1 and CG1, respectively. Similarly, units 400 and 410 form another storage row, with their WL and CG lines connected to WL0 and CG0, respectively. Units 400 and 420 form one column, with their common and bit lines connected to COM0 and BL0, respectively. Units 410 and 430 form another example, with their common and bit lines connected to COM1 and BL1, respectively.

[0078] The memory array 450 is constructed on a P-type substrate. The deep N-wells of the memory units are all integrated to form a single N-deep well 304. The N-wells and P-wells of the memory units in one memory row are integrated, respectively. Thus, each memory row includes one N-well (e.g., NW452A, NW452B) and one P-well (e.g., PW453A, PW453B).

[0079] The individual N-wells are all connected to a deep N-well, which in turn is connected to one DNW 454. The P-well of the "m"th memory row is connected to word line CGm, where "m" represents the row number. Consolidating wells within a row allows for tighter encapsulation of memory units in the array because the space between multiple wells is eliminated. The memory array is built in the same substrate as the rest of the on-chip logic, which requires the substrate to be grounded or at 0v.

[0080] 11 shows the bias voltages under programming and read modes of array 450. The individual storage units in array 450 can all be erased or programmed independently. Therefore, storage array 450 can be used to form one large electrically programmable erasable memory (EEPROM). The units in storage array 450 may be erased or programmed in blocks, much like a single FLASH memory.

[0081] A designated storage unit in the array 450 is available for programming. During programming, electrons are injected into the floating gate of the selected unit, reducing the threshold voltage of the read transistor, making it more conductive and thus causing an increase in read current during a read operation. During programming, the deep N-well is driven to VPP, ensuring that all PN junctions in the array are reverse biased.

[0082] Assuming that storage unit 400 in storage unit array 450 is selected, storage unit 400 is programmed as follows: drive the active N-well to VPP, COM0 to 0V, drive CG0 and WL0 to VPP, and leave BL0 floating. The programming process for storage unit 400 is the same as for storage unit 300 described above.

[0083] COM1 of storage unit 410 is floating, which means that in its first PMOS transistor 412, there is no reverse bias voltage on the PN junction between the N-well and the transistor's source electrode, so electrons capable of tunneling cannot be formed in the PN junction, and a strong electric field cannot be formed between the floating gate and the source electrode to stimulate electron tunneling, making unit 410 unprogrammable. CG1 of unit 420 is 0V, which means that a strong electric field cannot be formed between the floating gate and the source electrode of its first PMOS transistor 422 to stimulate electron tunneling, making it unprogrammable. COM1 of unit 430 is floating, which means that CG1 is 0V, making it unprogrammable.

[0084] After programming, a read operation of array 450 can simultaneously read data from a row of storage units. The PMOS read transistors in the programmed and unprogrammed units have threshold voltages of approximately 0V and -1.5V, respectively. In one embodiment, a read operation can be performed when unit 400 is in a programmed state, unit 410 is in an unprogrammed state, and row 0 is selected for a read operation. This causes all common lines (COM) to be driven to 1.2V, all bit lines (BL) to be precharged to 0V, the coupling gate line (CG0) to be driven to 0V, and the N-well and DNW to be driven to 1.5V. The unselected word lines are driven to 1.5V, while the selected word line WL0 is driven to 0V. As a result, both the second transistor 403 and the first transistor 402 in unit 400 are all conductive, and BL0 is pulled up to 1.2V.

[0085] In unit 410, the second transistor 413 is turned on, but the first transistor 412 is turned off. This is because transistor 412 is in an unprogrammed state, with a negative threshold voltage lower than the floating gate voltage. Therefore, BL1 is held at 0V. A high voltage at BL0 is then detected by a sense amplifier, which drives it to output a data signal with a status of "1." Similarly, a low status at BL1 is detected by another amplifier, which drives it to output a data signal with a status of "0." Note that the transistors of units in unselected rows are turned off, disconnecting them from the bit lines.

[0086] Designated storage units in the array can also be erased. Erasing can be accomplished by conventional techniques, such as Fowler-Nordheim tunneling. During an erase operation, electrons are pulled out of the floating gate of the selected unit, raising the threshold voltage of the PMOS transistor, making it more difficult to conduct, and reducing the read current during a read operation.

[0087] For example, the memory unit 400 can be erased as follows: CG0 is driven to -5V, WL0 is driven to 5V, BL0 is driven to 3.3V, and COM0 is driven to 5V. The potential of the N-well and deep N-well is 5V. As a result, the second transistor 403 is turned off, disconnecting the first transistor 402 from BL0. The NMOS capacitor 401 is in strong inversion, and an inversion layer is formed in the bottom plate. The floating gate is coupled to approximately -4.7V. When the source electrode of the first PMOS transistor 402 is driven to 5V, an inversion layer is also formed in the channel area of ​​the transistor 402. When the drain electrode of the transistor 402 is separated from BL0, the transistor 402 is in the linear region. The inverted channel, connecting the source and drain electrodes, receives the 5V voltage. This results in a total voltage applied to the gate and / or tunnel oxide of approximately 9.7V, creating a high electric field that can penetrate the tunnel oxide in excess of approximately 10 MeV. This allows many of the electrons trapped in the floating gate to gain sufficient energy to tunnel into the inverted channel and recombine with holes. The mechanism is Fowler-Nordheim tunneling.

[0088] In this embodiment, the CG0 and P-well shared by units 400 and 410 can be driven to a negative potential less than the substrate bias voltage (0V). This is because the P-well is separated from the substrate by the deep N-well. The deep N-well is driven to 5V during the erase period. Storage unit 410 also receives the CG0 voltage of -5V, but the source electrode of its first PMOS transistor 412 receives the bias voltage of 0V. As a result, the voltage across the gate oxide is only 4.7V, and even if inversion layers are formed in the channels of both transistor 412 and NMOS capacitor 411, the resulting electric field is not sufficient to trigger Fowler-Nordheim tunneling. Therefore, storage unit 410 is unaffected during the erase period.

[0089] In storage unit 420, the source electrode of the first PMOS transistor is driven to 5V, while the coupling gate connected to CG1 receives a bias voltage of 0V. As a result, the voltage across the gate oxide of the first PMOS transistor is only 4.7V. Even if the channels of both first PMOS transistor 422 and NMOS capacitor 421 all form inversion layers, the electric field is not sufficient to trigger Fowler-Nordheim tunneling. Therefore, the erasure interference on storage unit 420 is negligible.

[0090] In the storage unit 430, the bias voltages of the CG and source electrodes of the first PMOS transistor 432 are all 0V, which allows for negligible electric fields through the gate oxide of the transistor 432 and negligible tunneling current within the transistor 432. This results in no significant erase interference within the unit 430.

[0091] The read operation after erasing is the same as the read operation after programming the array. In the read operation, data in a row of memory units can be read simultaneously. The first PMOS transistor in the erased unit has a threshold voltage of about -1.5V.

[0092] It will be appreciated that the various operations, processes, and methods described herein may be embodied in, among other things, machine-readable and / or machine-accessible media compatible with a data processing system (e.g., a computer system), and may be performed in any order (including, for example, employing methods to achieve various different operations). Accordingly, the specification and its accompanying drawings should be considered illustrative only, and not restrictive.

Claims

1. 1. A method for programming a non-volatile memory, comprising: The memory includes: At least one non-volatile storage unit constructed on a P-type substrate, each non-volatile storage unit including a deep N-well located in the P-type substrate, one P-well and one N-well located in the deep N-well; a first PMOS transistor located in the N-well; an NMOS capacitor located in the P-well, the NMOS capacitor including an N+ tie area located in the P-well; a floating gate, the floating gate covering the PMOS transistor and the NMOS capacitor; The programming method programs a first PMOS transistor in the nonvolatile storage unit by band-to-band tunneling, and the programming method includes: (a) making the potential of the N-well greater than the potential of one electrode terminal of the first PMOS transistor, and creating a reverse bias voltage on the PN junction at the interface between the N-well and the electrode terminal, the reverse bias voltage concentrating electrons of the PN junction toward one side of the PN junction that is closer to the N-well; (b) making the potential on the floating gate of the first PMOS transistor greater than the potential of the electrode terminal thereof so that the potential difference between them can form a strong electric field between the floating gate and the electrode terminal, the electric field strength of which is greater than 8 MV / cm; (c) injecting electrons on one side of a PN junction at the interface between an N well and the electrode terminal, which electrons are closer to the N well, into the floating gate of the first PMOS transistor under the action of the strong electric field, thereby realizing programming.

2. 2. The programming method according to claim 1, wherein a potential difference between said N-well and said electrode terminal is smaller than an avalanche breakdown voltage of a PN junction at an interface between said N-well and said electrode terminal.

3. 3. The programming method according to claim 2, wherein the potential difference between said N-well and said electrode terminal is 0.1 to 1.0 V smaller than the avalanche breakdown voltage of the PN junction at the interface between them.

4. 5. The programming method of claim 1, wherein the potential on the floating gate of the first PMOS transistor is obtained by coupling a potential applied on an N+ coupling area of ​​an NMOS capacitor, the potential applied on the N+ coupling area being less than or equal to the potential of the N-well.

5. The programming method of claim 4 , wherein the potential applied on the N+ coupling area is equal to the potential of an N-well.

6. 5. The programming method according to claim 1, wherein the electrode terminal involved in programming of the first PMOS transistor is a source electrode of the transistor, and a potential thereof is 0V during the programming process; and another electrode terminal of the first PMOS transistor is a drain electrode, and is in a floating state during the programming process.

7. 2. The programming method of claim 1, wherein the capacitance of the NMOS is greater than the PMOS gate capacitance.

8. 5. The programming method of claim 1, wherein the non-volatile storage unit further includes a second PMOS transistor located in the N-well, a drain electrode of the first PMOS transistor is coupled to a source electrode of the second PMOS transistor, and a drain electrode of the second PMOS transistor does not participate in programming.

9. 9. The programming method of claim 8, wherein the drain electrode of the second PMOS transistor is in a floating state during the programming process.

10. 10. The programming method of claim 9, wherein the potential of the gate electrode of the second PMOS transistor is the same as the potential of an N-well during the programming process.

11. 9. The method of claim 8, wherein the channel of the second PMOS transistor is not made conductive during the programming process.

12. 2. The programming method of claim 1, wherein the floating gate in the storage unit is a single-layer polysilicon gate electrode.

13. 2. The programming method of claim 1, wherein the non-volatile memory is an electrically programmable erasable non-volatile memory.

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