Method of manufacturing semiconductor device

Abstract

To provide a method of manufacturing a semiconductor device capable of improving characteristics of a semiconductor layer.SOLUTION: A method of manufacturing a semiconductor device according to an embodiment includes modifying a surface of a semiconductor layer using a compound having an alkoxysilyl group or a silanol group at one end and a cation-capturing organic group at the other end, treating the modified surface of the semiconductor layer with a metal ion-containing solution, washing the surface of the semiconductor layer treated with the metal ion-containing solution, drying the washed surface of the semiconductor layer, and heating the dried surface of the semiconductor layer in a non-oxidizing atmosphere.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] SUMMARY OF THE INVENTION An embodiment of the present invention relates to a method for manufacturing a semiconductor device. [Background technology]

[0002] The characteristics of the channel (semiconductor layer) of semiconductor memory have a large impact on the performance of the memory cell. One method to increase the mobility of the channel is induced lateral crystallization (MILC). [Prior art documents] [Non-patent literature]

[0003] [Non-Patent Document 1] Haruki Matsuo et. al., Effects of crystallinity of silicon channels formed by two metal-induced lateral crystallization methods on the cell current distribution in NAND-type 3D flash memory, Japanese Journal of Applied Physics 63, 04SP19 (2024) [Patent documents]

[0004] [Patent Document 1] Patent Publication No. 2021-15868 [Patent Document 2] Japanese Patent Application Laid-Open No. 2017-31476 [Patent Document 3] International Publication No. 2010 / 143306 Summary of the Invention [Problem to be solved by the invention]

[0005] A method for manufacturing a semiconductor device that can improve the characteristics of a semiconductor layer is provided. [Means for solving the problem]

[0006] The method for manufacturing a semiconductor device according to the embodiment includes the steps of modifying the surface of a semiconductor layer using a compound having an alkoxysilyl group or a silanol group at one end and a cation-capturing organic group at the other end, treating the modified surface of the semiconductor layer with a metal ion-containing solution, cleaning the surface of the semiconductor layer that has been treated with the metal ion-containing solution, drying the cleaned surface of the semiconductor layer, and heating the dried surface of the semiconductor layer in a non-oxidizing atmosphere. [Brief explanation of the drawings]

[0007] [Figure 1] 1 is a schematic cross-sectional view of a semiconductor device according to an embodiment; [Figure 2] 3 is a flowchart of a method for manufacturing a semiconductor device according to an embodiment. [Figure 3] 1A to 1C are schematic views illustrating a semiconductor device manufacturing method according to an embodiment. [Figure 4] 1A to 1C are schematic views illustrating a semiconductor device manufacturing method according to an embodiment. [Figure 5] 1A to 1C are schematic views illustrating a semiconductor device manufacturing method according to an embodiment. [Figure 6] 1A to 1C are schematic views illustrating a semiconductor device manufacturing method according to an embodiment. [Figure 7] 1A to 1C are schematic views illustrating a semiconductor device manufacturing method according to an embodiment. [Figure 8] 1A to 1C are schematic views illustrating a semiconductor device manufacturing method according to an embodiment. [Figure 9] 1A to 1C are schematic views illustrating a semiconductor device manufacturing method according to an embodiment. [Figure 10] 1A to 1C are schematic views illustrating a semiconductor device manufacturing method according to an embodiment. [Figure 11] 1A to 1C are schematic views illustrating a semiconductor device manufacturing method according to an embodiment. [Figure 12] 1A to 1C are schematic views illustrating a semiconductor device manufacturing method according to an embodiment. [Figure 13] 1A to 1C are schematic views illustrating a semiconductor device manufacturing method according to an embodiment. [Figure 14] 1A to 1C are schematic views illustrating a semiconductor device manufacturing method according to an embodiment. [Figure 15] 1A to 1C are schematic views illustrating a semiconductor device manufacturing method according to an embodiment. [Figure 16] 1A to 1C are schematic views illustrating a semiconductor device manufacturing method according to an embodiment. [Figure 17] 1A to 1C are schematic views illustrating a semiconductor device manufacturing method according to an embodiment. [Figure 18] 1A to 1C are schematic views illustrating a semiconductor device manufacturing method according to an embodiment. [Figure 19] 1A to 1C are schematic views illustrating a semiconductor device manufacturing method according to an embodiment. [Figure 20] 1A to 1C are schematic views illustrating a semiconductor device manufacturing method according to an embodiment. [Figure 21] FIG. 1 is a schematic perspective view of a semiconductor device according to an embodiment. [Figure 22] 1 is a schematic cross-sectional view of a semiconductor device according to an embodiment; [Figure 23] 1 is a schematic cross-sectional view of a semiconductor device according to an embodiment; [Figure 24] 3 is a flowchart of a method for manufacturing a semiconductor device according to an embodiment. [Figure 25] 1A to 1C are schematic views illustrating a semiconductor device manufacturing method according to an embodiment. [Figure 26] 1A to 1C are schematic views illustrating a semiconductor device manufacturing method according to an embodiment. [Figure 27] 1A to 1C are schematic views illustrating a semiconductor device manufacturing method according to an embodiment. [Figure 28] 1A to 1C are schematic views illustrating a semiconductor device manufacturing method according to an embodiment. [Figure 29] 1A to 1C are schematic views illustrating a semiconductor device manufacturing method according to an embodiment. [Figure 30] 1A to 1C are schematic views illustrating a semiconductor device manufacturing method according to an embodiment. [Figure 31] 1A to 1C are schematic views illustrating a semiconductor device manufacturing method according to an embodiment. [Figure 32] 1A to 1C are schematic views illustrating a semiconductor device manufacturing method according to an embodiment. [Figure 33] 1A to 1C are schematic views illustrating a semiconductor device manufacturing method according to an embodiment. [Figure 34]1A to 1C are schematic views illustrating a semiconductor device manufacturing method according to an embodiment. [Figure 35] 1A to 1C are schematic views illustrating a semiconductor device manufacturing method according to an embodiment. [Figure 36] 1A to 1C are schematic views illustrating a semiconductor device manufacturing method according to an embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0008] Hereinafter, embodiments will be described with reference to the drawings.

[0009] In this specification, some elements are given multiple examples of expressions. Note that these examples are merely illustrative and do not deny that the elements may be expressed using other expressions. Furthermore, elements that do not have multiple expressions may also be expressed using other expressions.

[0010] The drawings are schematic, and the relationship between thickness and planar dimensions, the thickness ratio of each layer, etc. may differ from the actual ones. Also, the drawings may include parts where the relationship and ratio of dimensions differ from each other. Also, some reference numerals are omitted in the drawings.

[0011] The physical property values ​​shown in the embodiments are values ​​at atmospheric pressure and 25° C. Furthermore, the diameter values ​​are values ​​of the circumscribed circle diameter of the cross section.

[0012] In the embodiments, the hyphen and equal sign used to represent compounds represent bonds.

[0013] In this specification, a step includes not only an independent step but also a combination with other steps or other processes. When multiple numerical ranges are described in the numerical conditions in this specification, the upper limit or lower limit of one numerical range may be replaced with the upper limit or lower limit of another numerical range. When the upper limit and lower limit of a numerical condition in this specification are described, they may also be replaced with a numerical range condition that combines the upper limit and lower limit.

[0014] (First embodiment) The first embodiment relates to a method for manufacturing a semiconductor device. FIG. 1 shows a schematic cross-sectional view of a semiconductor device 100 according to the first embodiment as an example of a semiconductor device. The semiconductor device 100 in FIG. 1 has a three-dimensional semiconductor memory structure. The semiconductor device 100 shown in FIG. 1 is an example of a three-dimensional semiconductor memory, a portion of which is shown in FIG. 1. The method for manufacturing a semiconductor device according to the first embodiment is preferably applied to an opening such as a memory hole. After describing the semiconductor device 100, a method for manufacturing the semiconductor device will be described. The semiconductor device 100 according to the first embodiment has a structure in which NAND strings, each of which is made up of vertical transistors stacked in series in the vertical direction, are bundled together.

[0015] The semiconductor device 100 in Figure 1 includes a substrate 1, a lower insulating film 2, a source-side conductive layer 3, an upper insulating film 4, multiple electrode layers 5, multiple insulating layers 6, a cover insulating film 7, a drain-side conductive layer 8, a first interlayer insulating film 9, a second interlayer insulating film 10, multiple contact plugs 11, a block insulating film 12 which is an example of a second insulating film, a charge storage layer 13, a tunnel insulating film 14 which is an example of a first insulating film, a channel semiconductor layer 15, and a core insulator 16 which is an example of a third insulating film.

[0016] The substrate 1 is, for example, a semiconductor substrate such as a Si (silicon) substrate. FIG. 1 shows an X direction and a Y direction that are parallel to the surface of the substrate 1 and perpendicular to each other, and a Z direction that is perpendicular to the surface of the substrate 1. In this specification, the +Z direction is treated as the upward direction, and the −Z direction is treated as the downward direction. The −Z direction may or may not coincide with the direction of gravity. The Z direction is an example of a first direction.

[0017] A diffusion layer L is provided on the lower insulating film 2 side of the substrate 1. The diffusion layer L includes, for example, a p-well and an n-well.

[0018] The lower insulating film 2 is provided on a diffusion layer L formed in the substrate 1. The lower insulating film 2 is an insulator that extends in the XY plane direction. The lower insulating film 2 includes, for example, silicon oxide.

[0019] The source-side conductive layer 3 is formed on the lower insulating film 2. The source-side conductive layer 3 is a conductor that extends in the XY plane direction. The source-side conductive layer 3 includes silicon doped with, for example, phosphorus (P).

[0020] The upper insulating film 4 is formed on the source-side conductive layer 3. The upper insulating film 4 is an insulator that extends in the XY plane direction. The upper insulating film 4 includes, for example, silicon oxide.

[0021] A plurality of electrode layers 5 are alternately stacked with insulating layers 6 on the upper insulating film 4 in the Z direction. The electrode layers 5 are conductive layers, such as metal layers, that extend in the XY plane. The electrode layers 5 function as word lines and select lines. The electrode layers 5 contain, for example, tungsten. The number of electrode layers 5 is, for example, 64 or more.

[0022] A plurality of insulating layers 6 are alternately stacked with electrode layers 5 on the upper insulating film 4 in the Z direction. The insulating layers 6 are insulating layers that extend in the XY plane direction. The insulating layers 6 include, for example, silicon oxide. The number of insulating layers 6 is, for example, 64 or more.

[0023] FIG. 1 shows a memory hole M penetrating the electrode layer 5 and the insulating layer 6, and a contact hole H formed on the step region of the electrode layer 5 and the insulating layer 6. As shown in FIG.

[0024] The cover insulating film 7 is an insulator that extends mainly in the XY plane direction. The cover insulating film 7 is provided on a stack including the electrode layer 5 and the insulating layer 6. The cover insulating film 7 is provided in a stepped shape on the contact plug 11 side so as to follow the cross section of the stack of the stepped region of the electrode layer 5 and the insulating layer 6. The cover insulating film 7 includes, for example, silicon oxide.

[0025] The drain-side conductive layer 8 is a conductor that extends mainly in the XY plane direction. The drain-side conductive layer 8 is formed on the cover insulating film 7. The drain-side conductive layer 8 includes, for example, polysilicon.

[0026] The first interlayer insulating film 9 is an insulator. The first interlayer insulating film 9 is provided between the cover insulating film 7 and the second interlayer insulating film 10 in the Z direction. The first interlayer insulating film 9 is formed on the cover insulating film 7 so as to fill the space above the staircase region (for example, the gap between the contact plugs 11). The first interlayer insulating film 9 includes, for example, silicon nitride.

[0027] The second interlayer insulating film 10 is an insulator that extends in the XY plane direction. The second interlayer insulating film 10 is formed on the drain-side conductive layer 8 and the first interlayer insulating film 9. The second interlayer insulating film 10 is, for example, a silicon nitride film.

[0028] A plurality of contact plugs 11 are formed in contact holes H that penetrate the cover insulating film 7, the first interlayer insulating film 9, and the second interlayer insulating film 10. These contact plugs 11 are electrically connected to different electrode layers 5. Each contact plug 11 is formed of, for example, a barrier metal layer such as a Ti (titanium)-containing layer and a plug material layer such as a W (tungsten) layer.

[0029] The block insulating film 12 is provided in a cylindrical shape within the memory hole M. The outside of the block insulating film 12 covers the side surfaces of the alternately stacked electrode layers 5 and insulating layers 6. A charge storage layer 13 is provided inside the block insulating film 12. The block insulating film 12 is, for example, a SiO2 film.

[0030] The charge storage layer 13 is provided in a cylindrical shape within the memory hole M. The charge storage layer 13 is, for example, a silicon nitride film, but may also be a semiconductor layer such as a polysilicon layer or a polysilicon germanium layer.

[0031] The tunnel insulating film 14 is provided in a cylindrical shape in the memory hole M. The tunnel insulating film 14 is provided between the charge storage layer 13 and the channel semiconductor layer 15. The tunnel insulating film 14 is, for example, a silicon oxide film. The film thickness of the tunnel insulating film 14 is, for example, not less than 5 [nm] and not more than 10 [nm].

[0032] The channel semiconductor layer 15 is provided in the memory hole M. The channel semiconductor layer 15 covers, for example, the surface of the core insulator 16. It is, for example, a polysilicon layer or a polysilicon germanium layer, and is electrically connected to the substrate 1. The lower end of the channel semiconductor layer 15 is provided on the surface of the substrate 1 and is connected to Si formed on the diffusion layer L by, for example, epitaxial growth. The film thickness of the channel semiconductor layer 15 is, for example, 5 nm or more and 30 nm or less.

[0033] The channel semiconductor layer 15 may contain a compound (silicide) containing Si and one or more metal elements selected from the group consisting of Au, Al, Cu, Ag, Pd, Ni, Pt, Mn, Rh, Co, Fe, Cr, Ti, Nb, Ir, Ta, Re, Mo, V, Hf, Ru, Zr, and W. The channel semiconductor layer 15 may contain a compound (silicide) containing Si and one or more metal elements selected from the group consisting of Au, Al, Cu, Ag, Pd, Ni, Pt, Mn, Rh, Co, Fe, Cr, Ti, Nb, Ir, Ta, Re, Mo, V, Hf, Ru, Zr, and W in an amount of 4×10 atoms. 17 [atoms / cm 3 ]Includes the following.

[0034] The core insulator 16 is provided in the center of the memory hole M. The core insulator 16 includes, for example, silicon oxide.

[0035] The memory film 17 is a stacked film including a block insulating film 12, a charge storage layer 13, and a tunnel insulating film 14. The core insulator 16 has a generally cylindrical shape extending in the Z direction.

[0036] The block insulating film 12, the charge storage layer 13, the tunnel insulating film 14, the channel semiconductor layer 15, and the core insulator 16 are formed in this order on the side surface of the memory hole M which penetrates the lower insulating film 2, the source-side conductive layer 3, the upper insulating film 4, the electrode layer 5, the insulating layer 6, the cover insulating film 7, the drain-side conductive layer 8, and the second interlayer insulating film 10. The channel semiconductor layer 15, the tunnel insulating film 14, the charge storage layer 13, and the block insulating film 12 generally have a cylindrical shape extending in the Z direction, and surround the core insulator 16 in annular form in this order.

[0037] The block insulating film 12, the charge storage layer 13, the tunnel insulating film 14, the channel semiconductor layer 15, and the core insulator 16 are formed, for example, by the following procedure. First, the block insulating film 12, the charge storage layer 13, and the tunnel insulating film 14 are formed in this order on the side and bottom surfaces of the memory hole M. Next, the tunnel insulating film 14, the charge storage layer 13, and the block insulating film 12 are removed from the bottom surface of the memory hole M. After that, the channel semiconductor layer 15 and the core insulator 16 are buried in this order in the memory hole M.

[0038] In this embodiment, a metal element is contained in the channel semiconductor layer 15 (semiconductor layer 21, semiconductor layer 21A described below) before crystallization, and then the channel semiconductor layer 15 (semiconductor layer 21, semiconductor layer 21A) is crystallized. This allows the channel semiconductor layer 15 (semiconductor layer 21, semiconductor layer 21A) to be crystallized at a low temperature, and the grain size of the crystal grains in the channel semiconductor layer 15 (semiconductor layer 21, semiconductor layer 21A) to be increased. As a result, it is possible to increase the mobility of the channel semiconductor layer 15 and reduce the threshold voltage of the memory cell of the three-dimensional semiconductor memory. When the channel semiconductor layer 15 is crystallized, the metal element moves within the channel semiconductor layer 15 (semiconductor layer 21, semiconductor layer 21A) to grow the crystal grains.

[0039] According to this embodiment, by crystallizing the channel semiconductor layer 15 (semiconductor layer 21, semiconductor layer 21A) containing metal elements before crystallization, it is possible to set the grain size (circumscribed circle diameter) of the crystal grains in the channel semiconductor layer 15 to, for example, 80 nm or more and 1600 nm or less.

[0040] In this embodiment, after the channel semiconductor layer 15 (semiconductor layer 21, semiconductor layer 21A) is crystallized, some of the metal elements in the channel semiconductor layer 15 are removed. As a result, as described above, the metal elements in the channel semiconductor layer 15 are reduced to 4×10 atoms. 17 [atoms / cm 3 ] or less.

[0041] By removing a part of the metal elements in the channel semiconductor layer 15, it is possible to reduce, for example, the leakage current in the tunnel insulating film 14 compared to when the metal atoms are not removed.

[0042] The metal element in this embodiment is, for example, Ni, but may be other metal elements. The metal element in this embodiment is preferably at least one element selected from the group (first group) consisting of Au (gold), Al (aluminum), Cu (copper), Ag (silver), Pd (palladium), Ni (nickel), and Pt (platinum). The metal element in this embodiment may optionally further include at least one element selected from the group (second group) consisting of Mn (manganese), Rh (rhodium), Co (cobalt), Fe (iron), Cr (chromium), Ti (titanium), Nb (niobium), Ir (iridium), Ta (tantalum), Re (rhenium), Mo (molybdenum), V (vanadium), Hf (hafnium), Ru (ruthenium), Zr (zirconium), and W (tungsten). Both the metal elements of the first group and the metal atoms of the second group have the effect of lowering the crystallization temperature of the channel semiconductor layer 15, but the metal elements of the first group generally have a greater effect than the examples of the metal elements of the second group.

[0043] For example, when Al and / or Ti is used, there is an advantage that an insulating film can be formed on the surface of the channel semiconductor layer 15 by performing oxidation or nitridation after crystallization of the channel semiconductor layer 15 (semiconductor layer 21, semiconductor layer 21A). If Al and / or Ti are present in the channel semiconductor layer 15, there is a risk that the short channel characteristics of the tunnel insulating film 14 and the channel semiconductor layer 15 may deteriorate. However, if the channel semiconductor layer 15 containing Al is oxidized or nitrided, an insulating film of AlO X Similarly, if the channel semiconductor layer 15 containing Ti is oxidized, a TiO 2 film or an AlN film is formed on the surface of the channel semiconductor layer 15 as an insulating film. X The film is formed, and it becomes possible to suppress the deterioration of short channel characteristics.

[0044] The channel semiconductor layer 15 may contain, in addition to the metal element, one or more elements selected from the group consisting of B (boron), P (phosphorus), and As (arsenic). The channel semiconductor layer 15 of this embodiment has a conductivity of, for example, 1.0×10 16 [atoms / cm 3 ] or more than 1.0 x 10 19 [atoms / cm 3 ] or less. This makes it possible to adjust the threshold voltage of the memory cell of the three-dimensional semiconductor memory to an appropriate value.

[0045] Next, a method for manufacturing the semiconductor device 100 will be described. Fig. 2 shows a flowchart of the method for manufacturing the semiconductor device 100. Figs. 3 to 12 show schematic diagrams relating to the method for manufacturing the semiconductor device 100. The manufacturing method described below is a part of the steps in the method for manufacturing the semiconductor device 100.

[0046] The method for manufacturing the semiconductor device 100 includes a step (S00) of treating the surface of the semiconductor layer, a step (S01) of modifying the surface of the semiconductor layer using a compound having an alkoxysilyl group or a silanol group at one end and a cation-capturing organic group at the other end, a step (S02) of treating the modified surface of the semiconductor layer with a metal ion-containing solution, a step (S03) of cleaning the surface of the semiconductor layer treated with the metal ion-containing solution, a step (S04) of drying the cleaned surface of the semiconductor layer, and a step (S05) of heating the dried surface of the semiconductor layer in a non-oxidizing atmosphere.

[0047] First, a lower insulating film 2, a source-side conductive layer 3, and an upper insulating film 4 are formed in this order on a substrate 1 (see FIG. 1), and then multiple electrode layers 5 and multiple insulating layers 6 are alternately stacked on the upper insulating film 4 to obtain the component shown in FIG. 3.

[0048] Next, a memory hole M is formed that penetrates the electrode layer 5 and insulating layer 6 of the member of FIG. 3 and reaches the substrate 1, thereby obtaining the member shown in FIG.

[0049] Next, a memory film 17 (a block insulating film 12, a charge storage layer 13, and a tunnel insulating film 14) and a semiconductor layer 21 are formed in this order on the side surfaces of the electrode layer 5 and the insulating layer 6 in the memory hole M of the member of FIG. 4, thereby obtaining the member shown in FIG.

[0050] The semiconductor layer 21 is a precursor of the channel semiconductor layer 15 in FIG. 1. The semiconductor layer 21 is an amorphous semiconductor layer, for example, an amorphous silicon layer. The semiconductor layer 21 is formed by LPCVD (Low Pressure Chemical Vapor Deposition), for example, at a temperature of 350°C to 550°C, with a total pressure (or the total of the partial pressure of the source gas, the partial pressure of the additive gas, and the partial pressure of the carrier gas) of 50 Pa to 500 Pa. The source gas and the additive gas are introduced to form amorphous silicon on the tunnel insulating film 14 of the memory film 17.

[0051] The source gas used to form the semiconductor layer 21 is, for example, one or more selected from the group consisting of Si2H6 gas, SiH4 gas, SiH2Cl2 gas, Si2Cl6 gas, and an organic gas containing Si.

[0052] The additive gas used when forming the semiconductor layer 21 is, for example, one or more selected from the group consisting of PH3, BCl, B2H6, ethylene, propylene, GeH4, N2O, and NH3.

[0053] The carrier gas used when forming the semiconductor layer 21 is, for example, one or more selected from the group consisting of N2, H2, and Ar.

[0054] Instead of alternately stacking a plurality of electrode layers 5 and a plurality of insulating layers 6 on the upper insulating film 4, a plurality of sacrificial layers and a plurality of insulating layers 6 may be alternately stacked on the upper insulating film 4. The sacrificial layers are, for example, SiN films. In this case, the sacrificial layers are replaced with electrode layers 5 in a later process. Specifically, the sacrificial layers between the insulating layers 6 are removed to form a plurality of cavities between the insulating layers 6, and the electrode layers 5 are embedded in these cavities. The method of using sacrificial layers is not shown.

[0055] It is preferable to remove a native oxide film by treating the surface of the semiconductor layer 21 with a dilute hydrofluoric acid solution before the step (S01) of modifying the surface of the semiconductor layer 21 with a compound having an alkoxysilyl group or a silanol group at one end and a cation-capturing organic group at the other end, or before the optional step (S00) of treating the surface of the semiconductor layer 21. The treatment of removing the native oxide film is preferable but can be omitted.

[0056] Prior to step (S01) of modifying the surface of semiconductor layer 21 with a compound having an alkoxysilyl group or a silanol group at one end and a cation-capturing organic group at the other end, step (S00) of treating the surface of semiconductor layer 21 may be performed. It is preferable to increase the number of OH groups on the surface of semiconductor layer 21 by treating the surface of semiconductor layer 21 with a mixture of ammonia water and hydrogen peroxide, treatment with hydrochloric acid and hydrogen peroxide, treatment with sulfuric acid and hydrogen peroxide, treatment with a mixture of choline (trimethyl-2-hydroxyethylammonium hydroxide) and hydrogen peroxide, H2O2 treatment, treatment with a mixture of hydrochloric acid, ozone water, and ultrapure water, thermal oxidation treatment, or radical oxidation treatment. After each solution treatment, it is preferable to wash with ultrapure water at room temperature and dry the surface.

[0057] The step (S01) of modifying the surface of the semiconductor layer 21 using a compound having an alkoxysilyl group or a silanol group at one end and a cation-capturing organic group at the other end will be described with reference to the schematic diagrams of FIGS. 5 and 6.

[0058] The surface of the semiconductor layer 21 of the member shown in the schematic diagram of Figure 5 is chemically modified. The compound used for chemical modification is a compound having an alkoxysilyl group at one end and a cation-trapping organic group at the other end, or a compound having a silanol group at one end and a cation-trapping organic group at the other end. Silicon of the alkoxysilyl group or silanol group at one end bonds with the semiconductor layer 21 via oxygen, thereby obtaining the member shown in the schematic diagram of Figure 6.

[0059] A compound having an alkoxysilyl group at one end and a cation-trapping organic group at the other end is a silane coupling agent. When the silane coupling agent is used as the compound, a silanol group generated by hydrolysis of the alkoxysilyl group undergoes a condensation reaction with an OH group on the surface of the semiconductor layer 21, thereby modifying the surface of the semiconductor layer 21 with a molecule 30 containing a cation-trapping organic group. The molecule 30 includes a bonding portion 31 for bonding to the semiconductor layer 21, a spacer 32, and a cation-trapping organic group 33. For example, a solution containing a compound having an alkoxysilyl group at one end and a cation-trapping organic group at the other end is brought into contact with the semiconductor layer 21. Specifically, the solution containing the compound having an alkoxysilyl group at one end and a cation-trapping organic group at the other end is brought into contact with the surface of the semiconductor layer 21 by spraying, applying, or immersing.

[0060] A compound having a silanol group at one end and a cation-trapping organic group at the other end modifies the surface of the semiconductor layer 21 by chemical vapor deposition. The compound having a silanol group at one end and a cation-trapping organic group at the other end undergoes a condensation reaction between the silanol group and an OH group on the surface of the semiconductor layer 21 in the gas phase, modifying the surface of the semiconductor layer 21 with a molecule 30 containing the cation-trapping organic group. The molecule 30 includes a bonding portion 31 for bonding to the semiconductor layer 21, a spacer 32, and a cation-trapping organic group 33. In addition to chemical vapor deposition, for example, a solution containing a compound having an alkoxysilyl group at one end and a cation-trapping organic group at the other end is brought into contact with the surface of the semiconductor layer 21. Specifically, the solution containing the compound having an alkoxysilyl group at one end and a cation-trapping organic group at the other end is brought into contact with the surface of the semiconductor layer 21 by spraying, coating, or immersion.

[0061] The bonding portion 31 with the semiconductor layer 21 is —Si—O—. The Si side of the bonding portion 31 is bonded to the spacer 32. The oxygen side of the bonding portion 31 is bonded to the semiconductor layer 21, specifically to the Si of the semiconductor layer 21.

[0062] The number of carbon atoms contained in the spacer 32 is preferably 1 to 11, more preferably 1 to 5. When the number of carbon atoms in the spacer 32 is within the above range, the molecules 30 can be modified with high dispersibility even when the molecules 30 are modified inside the memory holes M. When the number of carbon atoms in the spacer 32 is within the above range, for example, when the step (S01) of modifying the surface of the semiconductor layer 21 is performed using a compound having an alkoxysilyl group or a silanol group at one end and a cation-capturing organic group 33 at the other end, on a semiconductor layer 21 having a hole shape (memory hole M) formed on the side surface of a laminate in which multiple electrode layers 5 and insulating layers 6 are alternately stacked, the molecules 30 can be modified with high dispersibility inside the hole shape even if the aspect ratio (depth / average hole diameter) of the hole shape is 60 or more. The spacer 32 contains a hydrocarbon chain, and includes a linear hydrocarbon chain and / or a cyclic hydrocarbon chain. The hydrocarbon chain may be saturated or unsaturated. The cyclic hydrocarbon chain of the spacer 32 preferably contains a benzene structure, a piperidine structure, a piperazine structure, a pyrrolidine structure, a triazine structure, or a thiophene structure. The spacer 32 may contain one or more elements selected from the group consisting of an aromatic ring structure, N, S, and O. The aromatic ring structure, N, S, and O contained in the spacer 32 are contained in the main chain and / or side chain. The N, S, and O contained in the spacer 32 may also be involved in bonding with a metal ion.

[0063] The cation-trapping organic group 33 is not particularly limited as long as it becomes negatively charged when treated with a metal ion-containing solution (specifically, an acidic solution, more specifically, an acidic aqueous solution). The cation-trapping organic group 33 contains one or more of S, O, and N. The cation-trapping organic group 33 contains one or more of S, O, and N, and becomes negatively charged when treated with a metal ion-containing solution, and forms an ionic bond and / or a coordinate bond with the metal ion contained in the metal ion-containing solution.

[0064] The cation-capturing organic group 33 is specifically —SH, —OH, —NH 2 , —COOH, —NHR 1 , -PH3, -R 2 -NH-R 3-, -R 4 -OR 5 -, -R 6 -SR 7 -,-COOR 8 The cation-capturing organic group 33 preferably contains one or more selected from the group consisting of -OH, -NH2, -COOH, -NHR-, and -CONH-. 1 , -R 2 -NH-R 3 -and-R 4 -OR 5 It is more preferable that the cation-trapping organic group 33 contains one or more selected from the group consisting of -. When treated with a metal ion-containing solution, the cation-trapping organic group 33 having such a structure becomes negatively charged and forms an ionic bond or / and a coordinate bond with the metal ions contained in the metal ion-containing solution. The cation-trapping organic group 33 has a chain structure, a cyclic structure, or a combination of a chain structure and a cyclic structure. The cation-trapping organic group 33 forms an ionic bond or / and a coordinate bond with ions of one or more metals selected from the group consisting of Au, Al, Cu, Ag, Pd, Ni, Pt, Mn, Rh, Co, Fe, Cr, Ti, Nb, Ir, Ta, Re, Mo, V, Hf, Ru, Zr, and W.

[0065] When the cation-trapping organic group 33 does not contain a cyclic structure, the number of carbon atoms in the cation-trapping organic group 33 is preferably 2 or more and 10 or less. When the cation-trapping organic group 33 contains a cyclic structure, the number of carbon atoms in the cation-trapping organic group 33 is preferably 10 or more and 16 or less.

[0066] From the viewpoint of stably capturing cations, the cation-capturing organic group 33 preferably has two or more (preferably three or more) amine structures, carbonyl structures, ester structures, ether structures, thiol structures, or sulfide structures.

[0067] R 1 is a hydrocarbon group having 1 to 2 carbon atoms. 1 R contains carbon and hydrogen, and optionally contains one or more members selected from the group consisting of N, S, and O. 1 Specifically, a methyl group or an ethyl group is preferred.

[0068] R 2 is a hydrocarbon chain with 1 to 2 carbon atoms. 2 R contains carbon and hydrogen, and optionally contains one or more members selected from the group consisting of N, S, and O. 2 R 3 The cyclic structure bonded to R is included in the cation-capturing organic group 33. The number of rings in the cyclic structure is 2 and R 3 R is not subject to the carbon number restriction, and is preferably a 5-membered ring or a 20-membered ring. 2 R 3 The cyclic structure bonded to R is preferably a piperidine structure, a piperazine structure, a pyrrolidine structure or a triazine structure. 2 When is a linear hydrocarbon chain, the number of carbon atoms is preferably 1 or more and 2 or less.

[0069] R 3 is a hydrocarbon chain with 1 to 2 carbon atoms. 3 R contains carbon and hydrogen, and optionally contains one or more members selected from the group consisting of N, S, and O. 3 -SH, -OH, -NH2, -COOH and -NHR 1 may be bonded to one or more selected from the group consisting of:

[0070] R 4 is a hydrocarbon chain with 1 to 2 carbon atoms. 4 R contains carbon and hydrogen, and optionally contains one or more members selected from the group consisting of N, S, and O. 4 R 5 The cyclic structure bonded to R is included in the cation-capturing organic group 33. The number of rings in the cyclic structure is 4 and R 5 R is not subject to the carbon number restriction, and is preferably a 5-membered ring or a 20-membered ring. 4 R 5 The cyclic structure bonded to R is preferably a crown ether structure. 4 When is a linear hydrocarbon chain, the number of carbon atoms is preferably 1 or more and 2 or less.

[0071] R 5 is a hydrocarbon chain with 1 to 2 carbon atoms.5 R contains carbon and hydrogen, and optionally contains one or more members selected from the group consisting of N, S, and O. 5 -SH, -OH, -NH2, -COOH and -NHR 1 may be bonded to one or more selected from the group consisting of:

[0072] R 6 is a hydrocarbon chain with 1 to 2 carbon atoms. 6 R contains carbon and hydrogen, and optionally contains one or more members selected from the group consisting of N, S, and O. 6 R 7 The cyclic structure bonded to R is included in the cation-capturing organic group 33. The number of rings in the cyclic structure is 6 and R 7 R is not subject to the carbon number restriction, and is preferably a 5-membered ring or a 20-membered ring. 6 R 7 The cyclic structure bonded to R is preferably a thiophene structure. 6 When is a linear hydrocarbon chain, the number of carbon atoms is preferably 1 or more and 2 or less.

[0073] R 7 is a hydrocarbon chain with 1 to 2 carbon atoms. 7 R contains carbon and hydrogen, and optionally contains one or more members selected from the group consisting of N, S, and O. 7 -SH, -OH, -NH2, -COOH and -NHR 1 may be bonded to one or more selected from the group consisting of:

[0074] R 8 is a hydrocarbon chain with 1 to 2 carbon atoms. 8 R contains carbon and hydrogen, and optionally contains one or more members selected from the group consisting of N, S, and O. 8 -SH, -OH, -NH2, -COOH and -NHR 1 may be bonded to one or more selected from the group consisting of:

[0075] From the viewpoint of density of chemical modification, it is preferable that a compound having an alkoxysilyl group or silanol group at one end and a cation-capturing organic group 33 at the other end contains an average of 1 or more and less than 2 alkoxysilane groups or silanol groups.

[0076] A specific example of a preferred structure of the cation-trapping organic group 33 is -(C2H4NH) n -C2H4NH2 (n is 0 or more and 5 or less), -(C3H6NH) n -C3H6NH2 (n is 0 or more and 4 or less), 18-crown-6-ether (18C6), 15-crown-5-ether (15C5), triazine thiol, -(C2H4NH)3-C2H4NH2, -(C2H4NH)2-C2H4NH2, or -(C2H4NH)1-C2H4NH2.

[0077] Next, the step (S02) of treating the surface of the modified semiconductor layer 21 with the metal ion-containing solution 34 will be described with reference to the schematic diagram of Fig. 7. The treatment is performed so that the surface of the semiconductor layer 21 of the member of Fig. 6 comes into contact with the metal ion-containing solution 34. The member of Fig. 6 is immersed in the metal ion-containing solution 34, the metal ion-containing solution 34 is applied to the member of Fig. 6, the metal ion-containing solution 34 is sprayed onto the member of Fig. 6, or the like, and the surface of the semiconductor layer 21 is brought into contact with the metal ion-containing solution 34.

[0078] When the surface of the semiconductor layer 21 modified with the metal ion-containing solution 34 is treated, the negatively charged cation-trapping organic groups 33 form ionic bonds and / or coordinate bonds with the metal ions 22. A plurality of cation-trapping organic groups 33 may trap the metal ions 22.

[0079] The metal ion-containing solution 34 preferably contains ions of one or more metals (metal ions 22) selected from the group consisting of Au, Al, Cu, Ag, Pd, Ni, Pt, Mn, Rh, Co, Fe, Cr, Ti, Nb, Ir, Ta, Re, Mo, V, Hf, Ru, Zr, and W. The metal ion-containing solution 34 preferably contains ions of one or more metals selected from the group (first group) consisting of Au, Al, Cu, Ag, Pd, Ni, and Pt, and optionally contains ions of one or more metals (metal ions 22) selected from the group (second group) consisting of Mn, Rh, Co, Fe, Cr, Ti, Nb, Ir, Ta, Re, Mo, V, Hf, Ru, Zr, and W.

[0080] The metal ion concentration of the metal ion-containing solution 34 is 1.0x10 -6 [mol / L] or more 1.0x10 0 [mol / L] or less is preferred.

[0081] The metal ion-containing solution 34 is preferably an acidic solution or an acidic aqueous solution. The pH of the metal ion-containing solution 34 is preferably 5 or less. The metal ion-containing solution 34 preferably contains an acid. The metal ion-containing solution 34 is preferably an aqueous nitric acid solution, an aqueous hydrochloric acid solution, an aqueous acetic acid solution, an aqueous formic acid solution, an aqueous sulfuric acid solution, an aqueous oxalic acid solution, an aqueous sulfamic acid solution, an aqueous carbonic acid solution, or a mixture of these aqueous solutions.

[0082] The environment in which the step (S02) of treating the surface of the modified semiconductor layer 21 with the metal ion-containing solution 34 is carried out is not particularly limited as long as it does not exceed the boiling point of the acid, but it is preferable to carry out the step in air at a temperature of 0°C or higher but lower than 100°C.

[0083] Next, the step (S03) of cleaning the surface of semiconductor layer 21 treated with metal ion-containing solution 34 will be described with reference to the process schematic diagram of Fig. 8. The member of Fig. 7 is cleaned with cleaning liquid 35.

[0084] 8, the metal ions 22 are partially removed from inside the memory holes M, and the acid in the metal ion-containing solution 34 is also removed. By washing the surface of the semiconductor layer 21, some of the metal ions 22 that have been bonded to the cation-capturing organic groups 33 may be removed. Specifically, the surface of the semiconductor layer 21 treated with the metal ion-containing solution 34 is washed multiple times with ultrapure water as a washing liquid 35.

[0085] The environment for carrying out the step (S03) of cleaning the surface of the semiconductor layer 21 treated with the metal ion-containing solution 34 is not particularly limited as long as it does not exceed the boiling point of the cleaning solution 35, but it is preferable to carry out the step in the atmosphere at a temperature of 0°C or higher and lower than 80°C.

[0086] Next, the step (S04) of drying the surface of the cleaned semiconductor layer 21 will be described with reference to the schematic diagram of Fig. 9. The surface of the cleaned semiconductor layer 21 of the member of Fig. 8 is washed with a solvent more volatile than water to volatilize it, or is subjected to spin-drying, to obtain the member of Fig. 9. As a solvent more volatile than water, IPA (isopropyl alcohol) or the like is preferred.

[0087] Next, the step (S05) of heating the surface of the dried semiconductor layer 21 in a non-oxidizing atmosphere will be described with reference to the schematic diagrams of Figures 10 to 12. The surface of the semiconductor layer 21 of the member of Figure 9 or the entire member is heated (annealed) to decompose the molecules 30, thereby obtaining the member shown in the schematic diagram of Figure 10. Note that the metal ions 22 of the member of Figure 9 are not reduced to form a metal layer, and metal plating is not formed on the reduced metal layer.

[0088] 9, the molecules 30 are decomposed, and the metal ions 22 move to the surface side of the semiconductor layer 21. When the metal ions 22 move to the surface side of the semiconductor layer 21, the metal ions 22 exist in the semiconductor layer 21 in a state where they are bonded to a ligand, or in the form of an oxide, hydroxide, or the like.

[0089] By continuing to heat the member shown in FIG. 10, the metal ions 22 bonded to the ligands, oxides, hydroxides, etc., gradually change into silicides 23. As the silicides 23 move due to heating, they become crystal nuclei, and crystals grow, resulting in the member shown in FIG. 11, which includes a semiconductor layer 21A in which crystals grow from amorphous silicon.

[0090] By continuing to heat the member shown in FIG. 11, the crystals of the semiconductor layer 21A grow further, and the member shown in FIG. 12 having the channel semiconductor layer 15 with sufficiently grown crystals is obtained.

[0091] After the step (S05) of heating in a non-oxidizing atmosphere, the channel semiconductor layer 15 (concentration of metal elements per surface area of ​​the channel semiconductor layer 15) contains at least one metal element selected from the group consisting of Au, Al, Cu, Ag, Pd, Ni, Pt, Mn, Rh, Co, Fe, Cr, Ti, Nb, Ir, Ta, Re, Mo, V, Hf, Ru, Zr, and W at a concentration of 7x10 atoms. 13 [atoms / cm 2 ] or more 1x10 15 [atoms / cm 2 ] It is preferable that the following be included.

[0092] Even when the semiconductor layer 21 in the memory hole M is subjected to the treatment of the embodiment, the channel semiconductor layer 15 after the step (S05) of heating in a non-oxidizing atmosphere (metal element concentration per surface area of ​​the channel semiconductor layer 15) contains at least one metal element selected from the group consisting of Au, Al, Cu, Ag, Pd, Ni, Pt, Mn, Rh, Co, Fe, Cr, Ti, Nb, Ir, Ta, Re, Mo, V, Hf, Ru, Zr, and W at a concentration of 7×10 atoms. 13 [atoms / cm 2 ] or more 1x10 15 [atoms / cm 2 ] It is preferable that the following be included.

[0093] A non-oxidizing atmosphere is preferred when heating the surface of the dried semiconductor layer 21. The treatment atmosphere preferably contains one or more gases selected from the group consisting of nitrogen, hydrogen, deuterium, and rare gases.

[0094] The total pressure during heating is preferably 10 [Pa] or more and 200,000 [Pa] or less, and more preferably 10 [Pa] or more and 110,000 [Pa] or less.

[0095] The treatment temperature during heating is preferably 500° C. or more and 1000° C. or less, and more preferably 550° C. or more and 950° C. or less.

[0096] The heating time is preferably 30 minutes or more and 2160 minutes or less, and more preferably 30 minutes or more and 1440 minutes or less.

[0097] After drying the surface of semiconductor layer 21 and before the step (S05) of heating in a non-oxidizing atmosphere, the method may further include a step (S06) of pre-heating the surface of semiconductor layer 21 or irradiating the surface of semiconductor layer 21 with UV light. By performing this step (S06), the member shown in Fig. 10 can be obtained. In this case, when the step (S05) of heating the dried surface of semiconductor layer 21 in a non-oxidizing atmosphere is performed, the member shown in Fig. 10 changes into the member shown in Fig. 12.

[0098] An oxidizing atmosphere is preferred for preheating the surface of the semiconductor layer 21. The preheating atmosphere preferably contains one or more species selected from the group consisting of oxygen, ozone, and H2O.

[0099] The treatment temperature during preheating is preferably 20° C. or higher and 600° C. or lower, and more preferably 20° C. or higher and 400° C. or lower.

[0100] The total pressure during preheating is preferably 100 [Pa] or more and 200,000 [Pa] or less, and more preferably 100 [Pa] or more and 10,000 [Pa] or less.

[0101] The treatment time during pre-heating is preferably 1 minute or more and 60 minutes or less, and more preferably 1 minute or more and 30 minutes or less.

[0102] The UV wavelength of the UV irradiation is preferably 100 nm or more and 400 nm or less. The entire inside of the memory hole M is preferably irradiated with UV.

[0103] The temperature of the atmosphere and the surface temperature of the semiconductor layer 21 during UV irradiation are preferably 20°C or higher and 600°C or lower, and more preferably 20°C or higher and 400°C or lower.

[0104] Both UV irradiation and pre-heating may be performed.

[0105] It is preferable to treat semiconductor layer 21 in the gas phase after the surface of semiconductor layer 21 is dried and before the step (S05) of heating in a non-oxidizing atmosphere. If the surface of semiconductor layer 21 is treated in the liquid phase after drying, there is a possibility that metal ions 22 may be released, so the treatment in the gas phase is preferable.

[0106] By performing a step (S06) of preheating the surface of the semiconductor layer 21 or irradiating the surface of the semiconductor layer 21 with UV light before the step (S05) of heating in a non-oxidizing atmosphere, a semiconductor layer 21 containing metal ions 22, a semiconductor layer 21 having metal ions 22 attached to its surface, or a semiconductor layer 21 containing metal ions 22 and having metal ions 22 attached to its surface can be obtained.

[0107] After the step (S05) of drying the surface of the semiconductor layer 21 and then heating it in a non-oxidizing atmosphere, it is preferable to form a getter layer such as amorphous silicon, move the silicide 23 to the getter layer, and remove or reduce metal elements resulting from the metal ions 22 containing the silicide 23 in the channel semiconductor layer 15.

[0108] Thereafter, steps such as forming the core insulator 16 are carried out, and the semiconductor device 100 can be obtained.

[0109] The step (S01) of modifying the surface of the semiconductor layer 21 with a compound having an alkoxysilyl group or a silanol group at one end and a cation-trapping organic group 33 at the other end can perform high-density surface modification on the bottom side of the memory hole M without blocking the opening of the memory hole M, even in a memory hole M with a high aspect ratio. Therefore, when treated with a metal ion-containing aqueous solution, high concentrations of metal ions 22 are captured by the cation-trapping organic group 33 on both the opening side and the deep side of the memory hole M. This reduces the unevenness in the concentration of metal ions 22 imparted to the entire semiconductor layer 21, and crystal growth of the channel semiconductor layer 15 occurs with little unevenness overall, even at relatively low temperatures. Therefore, in the step (S05) of heating in a non-oxidizing atmosphere, the crystal grain size of the channel semiconductor layer 15 grows similarly on both the substrate 1 side and the opposite side from the substrate 1 side, thereby reducing the variation in mobility of the channel semiconductor layer 15 in the Z direction. Not only are channel characteristics improved, but the manufacturing method of the embodiment is also useful from the viewpoint of multi-value even when the number of layers is large.

[0110] (Second embodiment) The second embodiment relates to a method for manufacturing a semiconductor device. The second embodiment is a modification of the first embodiment. Description of the common features between the first and second embodiments will be omitted.

[0111] The second embodiment is not a treatment for a semiconductor layer in a hole such as the memory hole M, but a treatment for a semiconductor layer 41 in a layered non-hole. The first and second embodiments are common except for the difference in the parts to be treated. The second and first embodiments use a similar phenomenon in which the amorphous silicon semiconductor layer 41 undergoes crystal growth, resulting in a polysilicon semiconductor layer 42.

[0112] The method for manufacturing a semiconductor device according to the second embodiment will be described with reference to the schematic diagrams of Figures 13 to 20. The flowchart of the method for manufacturing a semiconductor device according to the second embodiment is the same as the flowchart of Figure 2.

[0113] A component shown in the schematic diagram of FIG. 13 is provided with a semiconductor layer 41 corresponding to the semiconductor layer 21, and a step (S01) of modifying the surface of the semiconductor layer 41 is performed using a compound having an alkoxysilyl group or a silanol group at one end and a cation-capturing organic group 33 at the other end, to obtain a component shown in the schematic diagram of FIG. 14 in which molecules 30 are formed on the surface of the semiconductor layer 41.

[0114] A step (S02) is performed in which the surface of semiconductor layer 41 modified into the member shown in the schematic diagram of Fig. 14 is treated with metal ion-containing solution 34. The member shown in Fig. 14 is treated with metal ion-containing solution 34, and metal ions 22 are ionic-bonded or / and coordinate-bonded to cation-capable organic groups 33, thereby obtaining the member shown in the schematic diagram of Fig. 15.

[0115] 15 is subjected to a step (S03) of cleaning the surface of the semiconductor layer 41 treated with the metal ion-containing solution 34. The member of FIG. 15 is cleaned to remove unbonded metal ions 22 and acid, thereby obtaining the member shown in the schematic diagram of FIG.

[0116] The member shown in the schematic diagram of FIG. 16 is subjected to a step (S04) of drying the surface of the cleaned semiconductor layer 41 to obtain the member shown in the schematic diagram of FIG.

[0117] The member shown in the schematic diagram of FIG. 17 is subjected to a step (S05) of heating the surface of the dried semiconductor layer 41 in a non-oxidizing atmosphere. When heated, the molecules 30 decompose, resulting in the member shown in the schematic diagram of FIG. 18. Further heating causes crystal growth, resulting in the member shown in FIG. 19, which has a semiconductor layer 42 containing silicide 23. The member shown in FIG. 19 can be used as a semiconductor layer in a semiconductor device.

[0118] The silicide 23 of the member shown in the schematic diagram of Fig. 19 can be removed using a getter layer to obtain the member shown in the schematic diagram of Fig. 20. The semiconductor layer 42 in Fig. 20 may have some silicide 23 remaining. The semiconductor layer 42 in Fig. 20 can be used as a semiconductor layer of a semiconductor device.

[0119] By adopting the semiconductor device manufacturing method of the embodiment, amorphous silicon can be converted into polysilicon at a relatively low temperature. The same favorable crystallization process as in the first embodiment can be performed not only in holes such as memory holes but also on the ordinary layered semiconductor layer 41.

[0120] (Third embodiment) The third embodiment relates to a method for manufacturing a semiconductor device. The third embodiment relates to a memory device with a different configuration from the first embodiment. Descriptions of content common to the first to third embodiments will be omitted. The description of the third embodiment can also be applied to the descriptions of the first and second embodiments. A semiconductor device 200 shown in the schematic perspective view of FIG. 21 has a three-dimensional semiconductor memory structure. The semiconductor device 200 shown in FIG. 21 is an example of a three-dimensional semiconductor memory, a portion of which is shown in FIG. 21. The method for manufacturing a semiconductor device of the third embodiment is preferably applied to a stacked structure in which channel semiconductor layers and insulating films are alternately stacked. After describing the semiconductor device 200, the method for manufacturing the semiconductor device 200 will be described. More specifically, the method for manufacturing the semiconductor device of the second embodiment can be applied to the method for manufacturing a semiconductor device of the third embodiment. The semiconductor device 200 of the third embodiment has a VG (Vertical Gate) structure in which the channel semiconductor layer of the transistor is parallel to the silicon substrate and the gate electrode is arranged vertically. The gate electrodes are structured to sandwich the flat side surfaces of the channel semiconductor layer.

[0121] 21 includes a substrate 201, an insulating film 202, a channel semiconductor layer 203, an insulating layer 204, an insulating film 205, a stacked film 206, an electrode 207, an electrode 208, a layer selection transistor 209, and a selection transistor 220. It is preferable that a plurality of memory string structures shown in FIG. 21 are arranged in the X direction.

[0122] Fig. 22 shows a cross section taken along line AA of the semiconductor device 200 shown in Fig. 21. Fig. 23 shows a cross section taken along line BB of the semiconductor device 200 shown in Fig. 21.

[0123] A substrate (semiconductor substrate) 201 corresponds to the substrate 1 of the first embodiment. Channel semiconductor layers 203 and insulating layers 204 are alternately stacked on the main surface of the substrate 201 with an insulating film 202 interposed therebetween. The channel semiconductor layers 203 and insulating layers 204 are stacked in the order of channel semiconductor layer 203, insulating layer 204, channel semiconductor layer 203, insulating layer 204, channel semiconductor layer 203. An insulating film 205 is provided on the uppermost channel semiconductor layer 203.

[0124] The insulating film 202 is an insulator provided between the substrate 201 and the channel semiconductor layer 203. The insulating film 202 includes, for example, silicon oxide.

[0125] The channel semiconductor layer 203 is provided between the insulating film 202 and the insulating layer 204 , between the insulating layers 204 and 204 , and between the insulating layer 204 and the insulating film 205 .

[0126] The number of stacked channel semiconductor layers 203 and insulating layers 204 varies depending on the memory configuration. The memory capacity of the semiconductor device 200 increases as the number of stacked channel semiconductor layers 203 and insulating layers 204 increases.

[0127] The channel semiconductor layer 203 corresponds to the channel semiconductor layer 15 of the first embodiment, and includes, for example, polysilicon, and the channel semiconductor layer 203 may include silicide 23 .

[0128] The insulating layer 204 is an insulator provided between the channel semiconductor layers 203. The insulating layer 204 includes, for example, silicon oxide.

[0129] The insulating film 205 is an insulator provided on the uppermost channel semiconductor layer 203. The insulating film 205 includes, for example, silicon oxide.

[0130] The laminated structure consisting of the insulating film 202, the channel semiconductor layer 203, the insulating layer 204, and the insulating film 205 has a fin-like shape.

[0131] The stacked film 206 is formed so as to surround the periphery of the stacked structure consisting of the insulating film 202, the channel semiconductor layer 203, the insulating layer 204, and the insulating film 205. A plurality of stacked films 206 are provided in the Y direction. The plurality of stacked films 206 are spaced apart and electrically insulated from each other. Note that the stacked film 206 does not have to be formed so as to surround the periphery of the stacked structure consisting of the stacked insulating film 202, the channel semiconductor layer 203, the insulating layer 204, and the insulating film 205, for example. The stacked film 206 may be formed on both sides in the X direction of the stacked structure consisting of the stacked insulating film 202, the channel semiconductor layer 203, the insulating layer 204, and the insulating film 205. In other words, the stacked films 206 formed on both sides in the X direction of the stacked structure consisting of the stacked insulating film 202, the channel semiconductor layer 203, the insulating layer 204, and the insulating film 205 may not be connected to each other above the insulating film 205.

[0132] The laminated film 206 includes, for example, an insulating film 206a, a charge storage layer 206b, an insulating film 206c, and an electrode 206d. The insulating film 206a, the charge storage layer 206b, the insulating film 206c, and the electrode 206d are laminated in this order from the laminated structure side formed of the insulating film 202, the channel semiconductor layer 203, the insulating layer 204, and the insulating film 205.

[0133] The insulating film 206a is, for example, a memory cell tunnel insulating film. The insulating film 206a is provided between the stacked structure and the charge storage layer 206b. Examples of the insulating film 206a include a silicon oxynitride film and a combination of a silicon oxide film and a silicon nitride film. The insulating film 206a may also contain silicon nanoparticles and / or metal ions.

[0134] The charge storage layer 206b is provided between the insulating film 206a and the insulating film 206c. The charge storage layer 206b is made of, for example, the same material as that used for the charge storage layer 13. In addition to a silicon nitride film, the charge storage layer 206b may include materials such as hafnium oxide (HfO2) and silicon nitride (SiN) films, each having a different composition ratio of silicon and nitrogen, which are constituent elements of the charge storage layer 206b. The charge storage layer 206b may contain silicon nanoparticles and / or metal ions in these films. In addition to the insulating film, the charge storage layer 206b may be a semiconductor layer such as a silicon layer.

[0135] The insulating film 206c is provided between the charge storage layer 206b and the electrode 206d. The insulating film 206c is, for example, a memory cell block insulating film. The insulating film 206c is, for example, a silicon oxide film, an aluminum oxide film (Al2O3), a lanthanum aluminum oxide film (LaAlO3), a lanthanum aluminum silicon oxide film (LaAlSiO), or a film in which the composition ratio of the constituent elements of these insulating films is changed.

[0136] The electrode 206d is a memory cell control electrode. The electrode 206d is made of, for example, a metal or / and a metal compound.

[0137] The electrode 207 is a conductor exposed on the insulating film 205 and penetrating the channel semiconductor layer 203, the insulating layer 204, and the insulating film 205. The electrode 207 is made of, for example, tungsten or aluminum. The electrode 207 is, for example, a memory string independent contact.

[0138] The electrode 208 is a conductor exposed on the insulating film 205 and penetrating the channel semiconductor layer 203, the insulating layer 204, and the insulating film 205. The electrode 208 is made of, for example, tungsten or aluminum. The electrode 208 is, for example, a memory string common contact.

[0139] The layer selection transistor 209 controls a layer (channel semiconductor layer 203) to be selected during memory operation. For example, each channel semiconductor layer 203 includes a channel region such that the layer selection transistor 209a connects to the lower channel semiconductor layer 203, the layer selection transistor 209b connects to the middle channel semiconductor layer 203, and the layer selection transistor 209c connects to the upper channel semiconductor layer 203 and the channel semiconductor layer 203.

[0140] The selection transistor 220 controls which memory string is selected during memory operation.

[0141] The layer select transistor 209 and the select transistor 220 are depicted with the same structure as the laminated film 206. The layer select transistor 209 and the select transistor 220 are not limited to any structure as long as they operate as transistors with the channel semiconductor layer 203 as a channel.

[0142] The impurity material contained in the channel region may be an impurity that forms an N-type semiconductor, such as a pentavalent element such as arsenic (As) or phosphorus (P), or an impurity that forms a P-type semiconductor, such as a trivalent element such as boron (B) or indium (In), or a combination of these materials.

[0143] Next, several examples of the manufacturing method of the semiconductor device 200 will be described. The manufacturing method of the third embodiment shows an example in which processing is performed on a planar semiconductor layer, similar to the manufacturing method of the second embodiment. FIG. 24 shows a flowchart of the manufacturing method of the semiconductor device 200. FIGS. 25 to 35 show schematic diagrams related to the manufacturing method of the semiconductor device 200. The manufacturing method described below is a part of the steps of the manufacturing method of the semiconductor device 200.

[0144] In the manufacturing method of the semiconductor device 200 of the third embodiment, the steps of treating the surface of the semiconductor layer (S00), modifying the surface of the semiconductor layer with a compound having an alkoxysilyl group or a silanol group at one end and a cation-capturing organic group at the other end (S01), treating the modified surface of the semiconductor layer with a metal ion-containing solution (S02), cleaning the surface of the semiconductor layer treated with the metal ion-containing solution (S03), drying the cleaned surface of the semiconductor layer (S04), heating the dried surface of the semiconductor layer in a non-oxidizing atmosphere (S05), and preheating or irradiating the surface of the semiconductor layer with UV light (S06) are described below. The process of removing the native oxide film is preferably performed before the surface of the semiconductor layer (S00).

[0145] The first manufacturing method is a method in which the step (S05) of heating the surface of the dried semiconductor layer in a non-oxidizing atmosphere is performed on multiple semiconductor layers. The second manufacturing method is a method in which the step (S05) of heating the surface of the dried semiconductor layer in a non-oxidizing atmosphere is performed individually on each semiconductor layer. The semiconductor layer 210 corresponds to the semiconductor layer 21.

[0146] As a first manufacturing method, a method will be described in which a step (S05) of heating the surface of the dried semiconductor layer 210 in a non-oxidizing atmosphere is performed on a plurality of semiconductor layers 210. The semiconductor layer 210, which is a precursor of the channel semiconductor layer 203, is formed on a member in which an insulating film 202 is formed on a substrate 201 to obtain the member shown in the schematic diagram of FIG.

[0147] Next, the component shown in the schematic diagram of FIG. 25 is subjected to the following steps: a step (S00) of treating the surface of the semiconductor layer 210; a step (S01) of modifying the surface of the semiconductor layer 210 using a compound having an alkoxysilyl group or a silanol group at one end and a cation-trapping organic group 33 at the other end; a step (S02) of treating the modified surface of the semiconductor layer 210 with a metal ion-containing solution 34; a step (S03) of cleaning the surface of the semiconductor layer 210 treated with the metal ion-containing solution 34; and a step (S04) of drying the cleaned surface of the semiconductor layer 210, thereby obtaining the component shown in the schematic diagram of FIG. 26, in which molecules 30 are bonded to the surface of the semiconductor layer 210 and metal ions 22 are captured by the cation-trapping organic groups 33 of the molecules 30.

[0148] Next, the component shown in the schematic diagram of FIG. 26 is subjected to a step (S06) of preheating the surface of the semiconductor layer 210 or irradiating the surface of the semiconductor layer 210 with UV light to decompose the molecules 30, thereby obtaining a component shown in the schematic diagram of FIG. 27 having a semiconductor layer 210 containing metal ions 22, a semiconductor layer 210 having metal ions 22 attached to its surface, or a semiconductor layer 210 containing metal ions 22 and having metal ions 22 attached to its surface, etc.

[0149] Next, the component shown in FIG. 27 is subjected to the following steps: forming an insulating layer 204 and a semiconductor layer 210; treating the surface of the newly formed semiconductor layer 210 (S00); modifying the surface of the semiconductor layer 210 with a compound having an alkoxysilyl group or a silanol group at one end and a cation-trapping organic group 33 at the other end (S01); treating the modified surface of the semiconductor layer 210 with a metal ion-containing solution 34 (S02); cleaning the surface of the semiconductor layer 210 treated with the metal ion-containing solution 34 (S03); and drying the cleaned surface of the semiconductor layer 210 (S04). This set of steps is then repeated multiple times to obtain the component shown in FIG. 28, in which the desired number of semiconductor layers 210 have been formed. The component shown in FIG. 28 has three semiconductor layers 210.

[0150] Next, the component shown in the schematic diagram of Figure 28 is subjected to a step (S05) of heating the surface of the dried semiconductor layer 210 in a non-oxidizing atmosphere, thereby growing crystals of multiple semiconductor layers 210, and obtaining the component shown in the schematic diagram of Figure 29, in which the silicide 23 converted from the semiconductor layer 210 to the channel semiconductor layer 203 is contained in the channel semiconductor layer 203.

[0151] Note that, for example, when forming semiconductor layer 210 having 2n (n is a natural number) stacked layers, for example, after forming semiconductor layer 210 having n stacked layers, a step (S05) of heating the surface of dried semiconductor layer 210 in a non-oxidizing atmosphere can be performed, and further, after forming semiconductor layer 210 having n stacked layers, a step (S05) of heating the surface of semiconductor layer 210 a second time in a non-oxidizing atmosphere can be performed to obtain the component shown in the schematic diagram of Fig. 29. In other words, the processes from step S00 to step S05, plus the step of forming insulating layer 204 and semiconductor layer 210 before step S00, can be repeated.

[0152] Next, amorphous silicon is formed as a getter layer 211 so as to contact the surface of the channel semiconductor layer 203 of the component shown in the schematic diagram of Figure 29, and by heating, the silicide 23 is moved to the getter layer 211, thereby obtaining the component shown in the schematic diagram of Figure 30.

[0153] In addition, when the process of forming the getter layer 211 and removing the silicide 23 from the channel semiconductor layer 203 involves performing the step (S05) of heating the surface of the dried semiconductor layer 210 in a non-oxidizing atmosphere twice as described above, the getter layer 211 may be formed each time after the step (S05) of heating the surface of the dried semiconductor layer 210 in a non-oxidizing atmosphere and the process of removing the silicide 23 from the channel semiconductor layer 203, or the getter layer 211 may be formed once after the last step (S05) of heating the surface of the dried semiconductor layer 210 in a non-oxidizing atmosphere and the process of removing the silicide 23 from the channel semiconductor layer 203.

[0154] Furthermore, before processing the stacked structure into a fin shape in a later step, a slit S may be provided in the portion to be removed when processing into the fin shape, as shown in the schematic diagram of FIG. 31, and a getter layer 211 may be formed also in the slit S to remove the silicide 23 from the channel semiconductor layer 203.

[0155] The insulating film 205 may be formed before the getter layer 211 is formed, or may be formed after the step of removing the silicide 23 from the channel semiconductor layer 203 using the getter layer 211.

[0156] The step of removing the silicide 23 using the getter layer 211 may be further performed after the steps described herein.

[0157] After removing the getter layer 211, the stacked structure having the desired number of stacked channel semiconductor layers 203 is processed into a fin shape, and the electrodes 207, 208 and stacked film 206 are formed, thereby obtaining the semiconductor device 200.

[0158] As a second manufacturing method, a method will be described in which the step (S05) of heating the surface of the dried semiconductor layer 210 in a non-oxidizing atmosphere is performed individually for each semiconductor layer 210. The semiconductor layer 210, which is a precursor of the channel semiconductor layer 203, is formed on a member in which an insulating film 202 is formed on a substrate 201 to obtain the member shown in the schematic diagram of FIG.

[0159] Next, the component shown in the schematic diagram of FIG. 32 is subjected to the following steps: a step (S00) of treating the surface of the semiconductor layer 210; a step (S01) of modifying the surface of the semiconductor layer 210 using a compound having an alkoxysilyl group or a silanol group at one end and a cation-trapping organic group 33 at the other end; a step (S02) of treating the modified surface of the semiconductor layer 210 with a metal ion-containing solution 34; a step (S03) of cleaning the surface of the semiconductor layer 210 treated with the metal ion-containing solution 34; and a step (S04) of drying the cleaned surface of the semiconductor layer 210, thereby obtaining the component shown in the schematic diagram of FIG. 33, in which molecules 30 are bonded to the surface of the semiconductor layer 210 and metal ions 22 are captured by the cation-trapping organic groups 33 of the molecules 30.

[0160] Next, the component shown in the schematic diagram of Figure 33 is subjected to a step (S05) of heating the surface of the dried semiconductor layer 210 in a non-oxidizing atmosphere, thereby growing crystals of multiple semiconductor layers 210, and obtaining the component shown in the schematic diagram of Figure 34, in which the silicide 23 converted from the semiconductor layer 210 to the channel semiconductor layer 203 is contained in the channel semiconductor layer 203.

[0161] 33 may be subjected to a step (S06) of preheating the surface of the semiconductor layer 210 or irradiating the surface of the semiconductor layer 210 with UV light. When the step (S06) of preheating the surface of the semiconductor layer 210 or irradiating the surface of the semiconductor layer 210 with UV light is performed on the member shown in the schematic diagram of FIG. 31, the molecules 30 are decomposed to obtain a semiconductor layer 210 containing metal ions 22, a semiconductor layer 210 having metal ions 22 attached to its surface, or a member having a semiconductor layer 210 containing metal ions 22 and having metal ions 22 attached to its surface. Then, a step (S05) of heating the surface of the dried semiconductor layer 210 in a non-oxidizing atmosphere is performed to obtain a member shown in the schematic diagram of FIG. 34. That is, the second manufacturing method described in the third embodiment also corresponds to the flowchart of FIG. 2.

[0162] Next, an insulating layer 204 and a semiconductor layer 210 are formed on the component shown in the schematic diagram of FIG. 34, and the following steps are performed: a step (S00) of treating the surface of the second semiconductor layer 210; a step (S01) of modifying the surface of the semiconductor layer 210 using a compound having an alkoxysilyl group or a silanol group at one end and a cation-capturing organic group 33 at the other end; a step (S02) of treating the modified surface of the semiconductor layer 210 with a metal ion-containing solution 34; a step (S03) of cleaning the surface of the semiconductor layer 210 treated with the metal ion-containing solution 34; a step (S04) of drying the cleaned surface of the semiconductor layer 210 (optionally, a step (S06) of pre-heating the surface of the semiconductor layer 210 or irradiating the surface of the semiconductor layer 210 with UV); and a step (S05) of heating the dried surface of the semiconductor layer 210 in a non-oxidizing atmosphere. Then, a member shown in the schematic diagram of FIG. 35 is obtained in which the second semiconductor layer 210 to the second channel semiconductor layer 203 are formed.

[0163] Each step is performed until the desired number of layers of the channel semiconductor layer 203 is formed, and then the getter layer 211 is formed to remove the silicide 23 from the channel semiconductor layer 203. The process of forming the getter layer 211 and removing the silicide 23 may be performed after forming any number of layers of the channel semiconductor layer 203.

[0164] After removing the getter layer 211, the stacked structure having the desired number of stacked channel semiconductor layers 203 is processed into a fin shape, and the electrodes 207, 208 and stacked film 206 are formed, thereby obtaining the semiconductor device 200.

[0165] 36 shows a schematic diagram of a semiconductor device manufacturing method. The schematic diagram of FIG. 36 shows a member on a substrate 201, in which a stack (insulating film 202, semiconductor layer 210, insulating layer 204, semiconductor layer 210, insulating layer 204, semiconductor layer 210, insulating film 205) processed into a fin shape is modified with molecules 30 on the side surface. Metal ions 22 are captured in the molecules 30 of the member shown in the schematic diagram of FIG. 36. The above-described process of processing the semiconductor layer 210 of the member shown in the schematic diagram of FIG. 36 into a channel semiconductor layer 203 may be performed.

[0166] By employing the manufacturing method of the embodiment, it is possible to crystallize the channel semiconductor layer 203 of a memory device with a VG structure. The induced lateral crystallization of the embodiment can also be implemented in a memory device with a VG structure, and a memory device with excellent channel characteristics can be obtained, similar to the first embodiment.

[0167] The embodiments will be described in detail below using examples. The examples are examples that can be applied to any of the first, second, and third embodiments, and are phenomena that are common to all of the embodiments.

[0168] Example 1 A sample with a hole pattern similar to memory hole M is prepared, and amorphous silicon is deposited on the side of the hole pattern. After removing the surface native oxide film with a hydrofluoric acid solution, a chemical oxide film is deposited on the amorphous silicon surface using a surface-oxidizing chemical such as SC-1, SC-2, SPM, ozone water, or hydrogen peroxide water. n The sample is immersed in an aqueous solution containing a silane coupling agent having the formula -C2H4NH2 (n is 0 or more and 5 or less), and then in an aqueous solution containing metal ions. 2+ Examples of metal ion aqueous solutions include nitric acid aqueous solution, hydrochloric acid aqueous solution, acetic acid aqueous solution, formic acid aqueous solution, sulfuric acid aqueous solution, oxalic acid aqueous solution, sulfamic acid aqueous solution, and carbonate aqueous solution containing metal ions. After immersion in each chemical solution, the wafer is washed with ultrapure water, and finally dried by IPA drying or spin dry drying. These chemical solution treatments and drying can be performed by either a single wafer process or a batch process. As a result, the nickel attached to the hole pattern is 1x10 in terms of a blanket film. +14 [atoms / cm 2 Furthermore, when this hole pattern sample is annealed under the conditions of step (S05) of the embodiment, crystallization of the amorphous silicon occurs, and it is believed that crystallization can be achieved in an area of ​​90% or more.

[0169] Example 2 After removing the native oxide film on the surface of a blank film made of amorphous silicon without a hole pattern using a dilute hydrofluoric acid solution, a chemical oxide film is formed on the surface using a surface-oxidizing chemical such as SC-1, SC-2, SPM, ozone water, or hydrogen peroxide water, and a -(C2H4NH) nThe wafer is immersed in a diluted aqueous solution of a silane coupling agent containing -C2H4NH2 (n is 0 to 5), followed by an aqueous solution containing metal ions. After each immersion, the wafer is rinsed with ultrapure water and finally dried using IPA or spin-drying. The morphology of the nickel attached to this blanket film is found to consist of components other than NiSi2, such as oxides, hydroxides, and metal complexes formed with ligands similar to ammonia. Furthermore, annealing this blanket film under the conditions of step (S05) of the embodiment converts the attached nickel to NiSi2. This change in the bonding state of the nickel allows NiSi2, which serves as a crystal nucleus, to be supplied to the amorphous silicon. This allows for crystallization as in Example 1.

[0170] Similar crystallization can be achieved by using other compounds as silane coupling agents. Furthermore, similar crystallization can also be achieved by bonding a compound in which a silanol group and a cation-capturing organic group are linked via a spacer to the amorphous silicon surface in the gas phase, instead of using a silane coupling agent.

[0171] In the specification, some elements are shown only by their element symbols.

[0172] Although several embodiments of the present invention have been described above, these embodiments are presented as examples and are not intended to limit the scope of the invention. These novel embodiments can be embodied in various other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their modifications are included within the scope and spirit of the invention, and are also included in the inventions and their equivalents as defined in the claims. [Explanation of symbols]

[0173] 1: Circuit board 2: Lower insulating film 3: Source side conductive layer 4: Upper insulating film 5: Electrode layer 6: Insulating layer 7: Cover insulating film 8: Drain side conductive layer 9: First interlayer insulating film 10: Second interlayer insulating film 11: Contact plug 12: Block insulating film 13: Charge storage layer 14: Tunnel insulating film 15: Channel semiconductor layer 16: Core insulator 17: Memory film 21: Semiconductor layer 21A: Semiconductor layer 22: Metal ions 23: Silicide 30: Molecule 31:Joining part 32: Spacer 33: Cation-capturing organic group 34: Metal ion-containing solution 35: Cleaning liquid 41: Semiconductor layer 42: Semiconductor layer 100: Semiconductor device 200: Semiconductor device 201: Substrate 202: insulating film 203: Channel semiconductor layer 204: Insulating layer 205: insulating film 206: Laminated film 206a: insulating film 206b: Charge storage layer 206c: insulating film 206d: Electrode 207: Electrode 208: Electrode 209: Layer selection transistor 209a: Layer selection transistor 209b: Layer selection transistor 209c: Layer selection transistor 210: Semiconductor layer 211: Getter layer 220: Select transistor 100: Semiconductor device H: Contact hole L: Diffusion layer M: Memory hole S: Slit

Claims

1. modifying the surface of the semiconductor layer with a compound having an alkoxysilyl group or a silanol group at one end and a cation-capturing organic group at the other end; treating the surface of the modified semiconductor layer with a metal ion-containing solution; a step of cleaning the surface of the semiconductor layer treated with the metal ion-containing solution; drying the surface of the cleaned semiconductor layer; heating the surface of the dried semiconductor layer in a non-oxidizing atmosphere; A method for manufacturing a semiconductor device having the above structure.

2. The cation-capturing organic group is —SH, —OH, —NH ２ , -COOH, -NHR １ , -PH ３ , -R ２ -NH-R ３ -, -R ４ -O-R ５ -, -R ６ -S-R ７ -, COOR ８ 2. The method for manufacturing a semiconductor device according to claim 1, wherein the compound further comprises at least one selected from the group consisting of - and -CONH-.

3. 2. The method for manufacturing a semiconductor device according to claim 1, wherein the step of modifying the surface of the semiconductor layer with a compound having an alkoxysilyl group or a silanol group at one end and a cation-capturing organic group at the other end is performed on the surface of the semiconductor layer provided on the side surface within the hole shape.

4. 2. The method for manufacturing a semiconductor device according to claim 1, wherein the compound has a spacer containing a hydrocarbon between the one end and the other end.

5. the compound has a spacer containing a hydrocarbon between the one end and the other end, The method for manufacturing a semiconductor device according to claim 1 , wherein the number of carbon atoms contained in the spacer is 1 or more and 11 or less.

6. the compound has a spacer containing a hydrocarbon between the one end and the other end, the number of carbon atoms contained in the spacer is 1 or more and 11 or less, 2. The method for manufacturing a semiconductor device according to claim 1, wherein the spacer comprises at least one element selected from the group consisting of an aromatic ring structure, N, S, and O.

7. The metal ion concentration of the metal ion-containing solution is 1.0 x 10 －６ [mol / L] or more 1.0x10 ０ 2. The method for manufacturing a semiconductor device according to claim 1, wherein the concentration is 0.1 to 1.0 mol / L or less.

8. 2. The method for manufacturing a semiconductor device according to claim 1, wherein the metal ion-containing solution is an acidic solution having a pH of 5 or less.

9. 2. The method for manufacturing a semiconductor device according to claim 1, wherein the metal ion-containing solution contains ions of one or more metals selected from the group consisting of Au, Al, Cu, Ag, Pd, Ni, Pt, Mn, Rh, Co, Fe, Cr, Ti, Nb, Ir, Ta, Re, Mo, V, Hf, Ru, Zr, and W.

10. 2. The method for manufacturing a semiconductor device according to claim 1, wherein the compound contains an average of one or more but less than two alkoxysilyl groups or silanol groups.

11. 2. The method for manufacturing a semiconductor device according to claim 1, wherein in the step of modifying the surface of the semiconductor layer, silicon of the alkoxysilyl group or silanol group at one end is bonded to the semiconductor layer via oxygen.

12. 2. The method for manufacturing a semiconductor device according to claim 1, wherein the heating step in a non-oxidizing atmosphere comprises heating a member in which the cation-capturing organic group and the metal ion contained in the metal ion-containing solution are bonded.

13. The treatment temperature in the step of heating in a non-oxidizing atmosphere is 500°C or higher and 1000°C or lower, 2. The method for manufacturing a semiconductor device according to claim 1, wherein the treatment atmosphere in the step of heating in a non-oxidizing atmosphere contains at least one kind selected from the group consisting of nitrogen, hydrogen, deuterium, and rare gases.

14. The treatment temperature in the step of heating in a non-oxidizing atmosphere is 500°C or higher and 1000°C or lower, the treatment atmosphere in the step of heating in a non-oxidizing atmosphere contains one or more selected from the group consisting of nitrogen, hydrogen, deuterium, and a rare gas; The total pressure of the treatment atmosphere in the step of heating in a non-oxidizing atmosphere is 10 [Pa] or more and 200,000 [Pa] or less, 2. The method for manufacturing a semiconductor device according to claim 1, wherein the treatment time for the step of heating in a non-oxidizing atmosphere is 30 minutes or more and 2160 minutes or less.

15. 2. The method for manufacturing a semiconductor device according to claim 1, further comprising the step of pre-heating the surface of the semiconductor layer or irradiating the surface of the semiconductor layer with UV light after the step of drying the surface of the semiconductor layer and before the step of heating in the non-oxidizing atmosphere.

16. The preheating treatment atmosphere is an oxidizing atmosphere, The temperature of the pre-heating treatment atmosphere is 20°C or higher and 600°C or lower, 16. The method for manufacturing a semiconductor device according to claim 15, wherein the preheating step has a processing time of 1 minute or more and 60 minutes or less.

17. The UV wavelength of the UV irradiation is 100 nm or more and 400 nm or less, 16. The method for manufacturing a semiconductor device according to claim 15, wherein the temperature of the atmosphere and the temperature of the surface of the semiconductor layer during the UV irradiation are 20[°C] or more and 600[°C] or less.

18. After the step of heating in a non-oxidizing atmosphere, the semiconductor layer contains at least one metal element selected from the group consisting of Au, Al, Cu, Ag, Pd, Ni, Pt, Mn, Rh, Co, Fe, Cr, Ti, Nb, Ir, Ta, Re, Mo, V, Hf, Ru, Zr, and W in an amount of 7×10 atoms. １３ [atoms / cm ２ ] or more 1x10 １５ [atoms / cm ２ 2. The method for manufacturing a semiconductor device according to claim 1, further comprising the steps of:

19. 2. The method for manufacturing a semiconductor device according to claim 1, further comprising the step of oxidizing the surface of the semiconductor layer before the step of modifying the surface of the semiconductor layer.

20. 2. The method for manufacturing a semiconductor device according to claim 1, wherein the semiconductor layer is treated in a gas phase from the step of drying the surface of the semiconductor layer until the step of heating in a non-oxidizing atmosphere.

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