Flash memory writing method

Abstract

To provide a flash memory writing method capable of distributing the use rate of a central processing unit on an on-vehicle controller.SOLUTION: In a flash memory writing method, in an in-vehicle control device including a central processing unit (CPU), write data collected for each meaningful unit is temporarily stored in a RAM, the write data is divided into a plurality of pieces, and the divided data is written in a flash memory at each fixed time interval at which other processing can be executed. The write data collected for each meaningful unit is divided for each predetermined size and written to the flash memory.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present disclosure relates to a flash memory writing method, and more particularly to a flash memory writing method that can distribute the usage rate of a central processing unit (CPU) on an on-board control unit (ECU). [Background technology]

[0002] When data writing to flash memory is started, it is necessary to wait until the writing process is completed, and during this time, the resources of the central processing unit (CPU) are occupied by the writing process. Therefore, by allocating the write destination of the flash memory to areas distributed for each storage block and managing the writing or erasure of data for each storage block, the size of the data written at one time can be reduced, and the waiting time for the next write process can be shortened. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Publication No. 2019-53396 Summary of the Invention [Problem to be solved by the invention]

[0004] However, even if the write destination is managed for each storage block, there will be a time when other processes must wait until the write process to the flash memory is completed. Therefore, during the write process to the flash memory, CPU resources are occupied by the write process, which causes a problem of affecting the execution of other processes.

[0005] The present disclosure provides a flash memory writing method that can distribute the usage rate of the central processing unit of an on-board control device. Other objects and novel features will become apparent from the description of this specification and the accompanying drawings. [Means for solving the problem]

[0006] The flash memory writing method according to the present disclosure involves temporarily storing write data organized into meaningful units in RAM in an on-board control device including a central processing unit (CPU), dividing the write data into multiple pieces, and writing the divided pieces of data to flash memory at regular time intervals when other processes can be executed.

[0007] That is, the write data organized into meaningful units such as the setting values ​​and diagnostic information of the on-board control device is temporarily stored in RAM memory, and the write process to the flash memory is started based on the operating status and CPU operating rate of the on-board control device.When writing to the flash memory, it is determined whether the write data organized into meaningful units can be written at predetermined intervals (fixed time intervals), and if it is determined that the data can be written, it is written.

[0008] The data to be written is prepared in advance as data divided into sizes that do not make it impossible to execute other arithmetic processing periodically performed on the vehicle-mounted control device, and when it is determined that writing is possible, the data to be written is selected from the group of write data divided in advance and written. [Effects of the Invention]

[0009] According to the above-described flash memory writing method, by distributing the utilization rate of the central processing unit, the occupation of CPU processing time by writing to flash memory (occupation of CPU 111 resources by the write process) can be reduced, and the impact on other periodically performed calculation processes can be suppressed.

[0010] That is, whether or not to write to the flash memory is determined at regular intervals based on the operating status and CPU operating rate of the on-board control device, and if it is determined that writing is possible at the time of execution of this determination, the writing process to the flash memory is started. Also, the data to be written is prepared in advance as data divided into sizes that do not make it impossible to execute other arithmetic processes that are periodically performed on the on-board control device, and if it is determined that writing is possible, the data to be written is selected from the group of write data divided in advance and written, thereby suppressing temporary concentration of the load on the microcomputer (CPU resources). [Brief explanation of the drawings]

[0011] [Figure 1] 1 is a diagram illustrating an example of the overall configuration of a flash memory writing method according to an embodiment; [Figure 2] 10A and 10B are diagrams illustrating an example of the configuration of write data temporarily stored in a RAM memory and data divided and written to a flash memory. [Figure 3] FIG. 10 is a flowchart for determining the timing to start writing to a flash memory based on the operating status and CPU operating rate of the on-board control device. [Figure 4] FIG. 10 is a flowchart showing a determination as to whether or not to temporarily suspend the write process to the flash memory based on the operating status and CPU operating rate of the on-board control device. [Figure 5] FIG. 10 is a diagram showing a flow in which write data temporarily stored in RAM memory is divided into predetermined size chunks and written to flash memory. [Figure 6] FIG. 1 is a diagram illustrating a conceptual configuration example of an on-board control device according to an embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0012] Hereinafter, with reference to the accompanying drawings, embodiments for carrying out the present disclosure will be described in detail. However, in the following description, the same components may be designated by the same reference numerals, and repeated explanations may be omitted. Note that the drawings may be more schematic than the actual embodiment for the purpose of clarifying the description, but they are merely examples and do not limit the interpretation of the present disclosure. [Example]

[0013] First, a conceptual configuration example of an on-vehicle control unit (ECU) 110 according to an embodiment will be described with reference to Fig. 6. Fig. 6 is a diagram showing a conceptual configuration example of an on-vehicle control unit according to an embodiment. The on-vehicle control unit 110 is one of on-vehicle devices, and is configured to be mounted on a vehicle and to be able to control the vehicle. As shown in Fig. 6, the on-vehicle control unit 110 includes a CPU 111, a RAM memory 112, a peripheral device 113, a flash memory 114, and a bus 115.

[0014] The CPU 111 is configured to be able to control the vehicle by executing a control program stored in the flash memory 114 .

[0015] The RAM memory 112 is a volatile storage device and can be configured, for example, by a static random access memory (SRAM) or a dynamic random access memory (DRAM). The RAM memory 112 can be used as a temporary work area for the CPU 111.

[0016] The flash memory 114 is configured as a nonvolatile storage device that can be electrically written and erased, and is configured so that data (programs) can be written and erased electrically. A control program for controlling the vehicle is stored in a portion of the flash memory 114.

[0017] In this example, the peripheral device 113 includes a timer 1131, a communication module (CANM) 1132 for a CAN (Controller Area Network), etc. The communication module (CANM) 1132 is connected to a communication bus CANB for the CAN provided outside the ECU 110. The communication module (CANM) 1132 is configured to receive reception data addressed to its own ECU 110 from the communication bus CANB, and to transmit transmission data addressed to another ECU to the communication bus CANB. Data transmission and reception using the communication module (CANM) 1132 are sometimes referred to as CAN transmission and CAN reception.

[0018] The bus 115 is configured to electrically connect the CPU 111, RAM memory 112, peripheral device 113, and flash memory 114 so that they can communicate with each other.

[0019] Next, a method for writing to the flash memory 114 will be described with reference to Fig. 1. Fig. 1 is a diagram for explaining an example of the overall configuration of a method for writing to a flash memory according to an embodiment.

[0020] As shown in FIG. 1, in the in-vehicle control device 110, a CPU 111 that executes an application, which is a control program, temporarily stores in a RAM memory 112 write data 100 that is organized into meaningful units such as setting values ​​and diagnostic information of the in-vehicle control device 110.

[0021] Meanwhile, the CPU 111 also executes driver software (write application) for writing to the flash memory 114. The write driver software is configured to determine the state of the on-board control device 110 as either a Busy state in which writing to the flash memory 114 is inhibited or an Idle state in which writing to the flash memory 114 is permitted, based on the operating status of the on-board control device 110 and the operating rate of the CPU 111 (hereinafter referred to as CPU operating rate). The state of the on-board control device 110 can also be referred to as the state of the CPU 111.

[0022] Then, when the CPU 111 executing the write driver software switches from a Busy state, which inhibits writing to the flash memory 114, to an Idle state, which permits writing to the flash 114, based on the operating status of the on-board control device 110 and the operating rate of the CPU 111 (hereinafter referred to as the CPU operating rate), that is, when the state changes from the Busy state to the Idle state, the CPU 111 executing the write driver software activates the timer 1131 to start a counting operation (timer start). Then, the CPU 111 starts the write process of the data (101, 102, 103) to the flash memory 114. The write process to the flash memory using the timer 1131 will be described in detail with reference to FIG. 5, and will not be described here.

[0023] Here, the write data 100 temporarily stored in the RAM memory 112 is prepared in advance as a plurality of data 101, 102, 103 divided into sizes that do not make it impossible to execute other arithmetic processing periodically performed on the on-board control device 100. The division into the plurality of data (101, 102, 103) may be performed by an application or by write driver software.

[0024] If it is determined that writing is possible (if the device is in the idle state), the write driver software selects, for example, one piece of data (101, 102, or 103) from a group of data to be written to the flash memory 114 that has been divided in advance (101, 102, 103), and writes it.

[0025] When the write data 100 (all of 101, 102, and 103) temporarily stored in the RAM memory 112 is written to the flash memory 114 at once (all at once), this temporarily occupies CPU processing time. In other words, the resources of the CPU 111 are occupied by the write process, which may affect other processes.

[0026] However, in this embodiment, data 100 to be written to flash memory 114 is divided into data (101, 102, 103) of a size that will not prevent other periodically performed arithmetic processing on the on-board control device 110 from being impossible to execute, and the divided data is prepared in advance. Then, if it is determined that the data is writable, one piece of write data (101, 102, or 103) is selected from the previously divided write data group (101, 102, 103) and automatically written to flash memory 114. This reduces the occupation of CPU processing time due to writing to flash memory 114 (occupation of CPU 111 resources due to the write processing), and suppresses the impact on other periodically performed arithmetic processing.

[0027] Next, an example of the structure of write data temporarily stored in RAM memory 112 and an example of the structure of divided data (101, 102, 103) divided and written to flash memory 114 will be described with reference to Fig. 2. Fig. 2 is a diagram showing an example of the structure of write data temporarily stored in RAM memory and data divided and written to flash memory.

[0028] The write data 100, which is organized into meaningful units temporarily stored in the RAM memory 112, includes first information 200 at the beginning of the data 100 indicating the beginning of the data 100 and second information 201 at the end of the data 100 indicating the end of the data 100, making it easy to recognize as the write data 100, which is organized into meaningful units temporarily stored in the RAM memory 112.

[0029] Furthermore, data 100 to be written to flash memory 114 is divided into data 101, 102, and 103. Data 101 includes first information 200 indicating the beginning of data 100, and data 103 includes second information 201 indicating the end of data 100.

[0030] After all of the data 101, 102, and 103 have been written to the flash memory 114, it is also possible to determine whether all of the data 101, 102, and 103 have been written successfully, based on the first information 200 indicating the beginning and the second information 201 indicating the end. For example, checksum data calculated from the write data 100 temporarily stored in the RAM memory 112 can be included in advance in the first information 200 indicating the beginning or the second information 201 indicating the end. This makes it possible to calculate a checksum from the data 101, 102, and 103 after they have been written to the flash memory, and detect errors in the write data by checking whether the checksum matches the checksum data included in advance.

[0031] FIG. 3 is a flowchart showing a process for determining the timing to start writing to the flash memory based on the operating status and CPU operating rate of the on-board control device.

[0032] In order to determine the timing for writing the divided data 101, 102, and 103 to the flash memory 114, the write process (write driver software) for the flash memory 114 on the on-board control device 110 carries out the following steps 300-305.

[0033] First, in step 300, the CPU 111 executing the driver software for writing checks the operating status of the on-board control device 110. In branching step 301, it is determined whether a predetermined function, such as CAN transmission or a self-test of the memory (112), which places a high processing load on the CPU 111, has stopped. Predetermined functions such as CAN transmission and a self-test of the memory (112) can be considered examples of periodic processing. If it is determined that the predetermined function has not stopped (301: NO), the on-board control device 110 is set to a busy state, and writing processing to the flash memory 114 is inhibited. On the other hand, if it is determined that the predetermined function has stopped (301: YES), the process proceeds to branching step 302.

[0034] In branching step 302, the CPU 111 executing the writing driver software determines whether the rotation speed of the driving source of the engine or motor of the vehicle equipped with the on-board control device 110 is equal to or lower than a predetermined rotation speed. If it is determined that the rotation speed is not equal to or lower than the predetermined rotation speed (302: NO), the on-board control device 110 is set to a busy state and the writing process to the flash memory 114 is inhibited. If it is determined that the rotation speed of the driving source is equal to or lower than the predetermined rotation speed (302: YES), the process proceeds to the next step 303.

[0035] In step 303 , the CPU 111 that executes the driver software for writing checks the CPU operating rate of the in-vehicle control device 110 .

[0036] In branch step 304, it is determined whether the CPU operating rate is lower than a preset value. If it is determined that the CPU operating rate is not lower (higher) than the set value (304: NO), the state of the on-board control device 110 is set to Busy and writing processing to the flash memory 114 is inhibited. If it is determined that the CPU operating rate is lower than the set value (304: YES), the process proceeds to the next step 305.

[0037] In the next step 305, the CPU 111 executing the writing driver software sets the state of the in-vehicle control device 110 to the idle state, enabling the writing process to the flash memory 114. This starts the writing process of the data (101, 102, or 103) to the flash memory 114.

[0038] This reduces the CPU processing time occupied by the write process to the flash memory 114, and suppresses the impact on other periodically performed arithmetic processes.

[0039] Fig. 3 shows the determination of the timing to start writing to the flash memory based on the operating status and CPU operating rate of the on-board control device. Fig. 4 is a flowchart showing the determination of whether to temporarily suspend writing to the flash memory 114 based on the operating status and CPU operating rate of the on-board control device during writing to the flash memory 114.

[0040] In order to determine whether to temporarily suspend the write process while writing the divided data 101, 102, and 103 to the flash memory 114, the write process (write driver software) to the flash memory 114 on the vehicle control device 110 performs the following steps 400-402.

[0041] First, in step 400, the CPU 111 executing the driver software for writing checks the operating status and CPU operating rate of the on-board control device (vehicle control device) 110. If a predetermined function with a high processing load, such as CAN transmission or a self-test of the memory (112), is not stopped, or if the rotation speed of the drive source of the engine or motor is equal to or greater than a predetermined rotation speed, or if the CPU operating rate is higher than a preset value, the CPU 111 executing the driver software for writing changes the state of the on-board control device 110 from the Idle state to the Busy state.

[0042] Next, in branch step 401, CPU 111 executing the writing driver software determines whether the state has changed from Idle to Busy. If it is determined to be Idle (401: NO), it continues the writing process to flash memory 114. If it is determined to be Busy (401: YES), it proceeds to next step 402.

[0043] In step 402 , the CPU 111 executing the write driver software temporarily suspends the write process to the flash memory 114 .

[0044] After the temporary suspension, if the CPU 111 executing the writing driver software detects that the state of the in-vehicle control device 110 has changed again from the Busy state to the Idle state, the CPU 111 executing the writing driver software resumes the writing process to the flash memory 114 from the point where it was temporarily suspended. This reduces the occupation of CPU processing time by writing to the flash memory 114, and can suppress the impact on other periodically performed arithmetic processes.

[0045] FIG. 5 is a diagram showing the flow of dividing the write data 100 temporarily stored in the RAM memory 112 into pieces of a predetermined size and writing them to the flash memory 114.

[0046] Write data 100 temporarily stored in an address area (space) of RAM memory 112 is divided into data 101, 102, and 103 of a predetermined size, and written to flash memory 114 at regular time intervals 500 using a timer 1131.

[0047] In this example, when the state of the on-board control device 110 changes from Busy to Idle, the CPU 111 executing the writing driver software sets a predetermined count value in the register of the timer 1131 and starts the timer 1131. The timer 1131 is configured to measure the time interval 500 by counting the operation clock up to the count value. When the timer 1131 counts the operation clock up to the count value, for example, the timer 1131 generates a first overflow signal, and then the timer 1131 restarts counting the operation clock up to the count value. Meanwhile, the CPU 111 writes the data 101 to the flash memory 114 based on the first overflow signal. When the timer 1131 generates a second overflow signal, the CPU 111 writes the data 102 to the flash memory 114 based on the second overflow signal. Similarly, when the timer 1131 generates a third overflow signal, the CPU 111, based on the third overflow signal, writes the data 103 to the flash memory 114. In this manner, writing to the flash memory 114 is performed at regular time intervals 500.

[0048] The write time 501 for one piece of data divided into a predetermined size is set so that writing can be completed within a certain time interval 500, and the data can be stored (written) into the flash memory 114 at a certain interval with enough time to allow other periodically performed arithmetic processing by the on-board control device 110 to be executed. This makes it easy to determine whether the write processing can be completed without affecting other periodically performed arithmetic processing by the on-board control device 110.

[0049] Although not particularly limited, the size (predetermined size) of each of the divided data 101, 102, and 103 is, for example, 32 bytes. Furthermore, the fixed time interval 500 is, for example, 3 ms. The time required to write 32 bytes of data to the flash memory 114 is, for example, 600 us. The fixed time interval 500 (3 ms) - the write time (600 us) = 2.4 ms, and the on-board control device 110 can perform periodic arithmetic processing (for example, CAN transmission or a self-test of the memory (112)) within the time range of 2.4 ms.

[0050] The disclosure made by the present inventor has been specifically described above based on examples, but it goes without saying that the present disclosure is not limited to the above examples and can be modified in various ways. [Explanation of symbols]

[0051] 100: Write data temporarily saved in RAM memory 101: Data 1 divided from the writing data temporarily stored in RAM memory 102: Data 2 divided from the writing data temporarily stored in RAM memory 103: Data 3 divided from the writing data temporarily stored in RAM memory 200: Information indicating the beginning of data 201: Information indicating the end of data 500: Flash write interval by timer 501: Time from start to completion of flash writing of one divided piece of data 110: In-vehicle control device (vehicle control device) 111: Central processing unit 112:RAM memory 113: Peripheral devices 114: Flash memory 115: Bus 1131: Timer on peripheral device 1132: Communication module for CAN on peripheral devices

Claims

1. A flash memory writing method in an on-board control device including a central processing unit (CPU), characterized in that write data organized into meaningful units is temporarily stored in RAM, the write data is divided into multiple pieces, and the divided pieces of data are written to flash memory at regular time intervals when other processes can be executed.

2. 2. The flash memory write method according to claim 1, wherein the write data collected into each meaningful unit is divided into predetermined size units and written to the flash memory.

3. 2. The flash memory writing method according to claim 1, wherein the write data organized into meaningful units includes first information at the beginning of the data indicating the beginning of the data and second information at the end of the data indicating the end of the data.

4. 4. The flash memory writing method according to claim 3, further comprising determining whether the write data has been successfully written to the flash memory based on the first information and the second information after writing to the flash memory.

5. 2. The flash memory writing method according to claim 1, wherein the timing of writing the divided data into the flash memory is determined based on the operating status of the vehicle-mounted control device.

6. 6. The flash memory writing method according to claim 5, wherein the operating state of the vehicle-mounted control device is a state in which a predetermined function of the vehicle-mounted control device is stopped.

7. 6. The flash memory writing method according to claim 5, wherein the operating condition of the on-board control device is that the rotational speed of the drive source of the on-board control device is equal to or lower than a predetermined rotational speed.

8. 6. The flash memory write method according to claim 5, wherein the timing for writing the divided data into the flash memory is determined based on the operating rate of the CPU.

9. The flash memory writing method according to claim 8, characterized in that, when the operating status of the vehicle control device changes to a busy state or the operating rate of the CPU is high at the timing of writing the divided data to the flash memory, the writing process to the flash memory is temporarily suspended.

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