Semiconductor device, method of manufacturing semiconductor device, and power conversion device

Abstract

The technique disclosed herein is a technique for improving the breakdown voltage of a semiconductor device.SOLUTION: A semiconductor device relating to a technique disclosed in the present specification includes a semiconductor layer of a first conductivity type, a diffusion layer of a second conductivity type in an upper layer of the semiconductor layer, a source layer of the first conductivity type in an upper layer of the diffusion layer, and a trench formed to reach an inside of the semiconductor layer from an upper surface of the source layer, wherein a protruding portion having an acute angle shape protruding toward an inside of the trench is formed at an upper end portion of the trench.SELECTED DRAWING: Figure 2

Description

[Technical Field]

[0001] The technology disclosed in the present specification relates to a trench type semiconductor device. [Background technology]

[0002] In recent years, there has been a demand for semiconductor devices with higher breakdown voltage and smaller size, and as a result, much research has been conducted on trench-type metal-oxide-semiconductor field-effect transistors (MOSFETs).

[0003] A trench MOSFET is a semiconductor device in which a groove (trenches) of about several micrometers is formed to form a channel region in the depth direction in order to increase the current per unit area of ​​the MOSFET. Trench MOSFETs have many advantages, but they also have many concerns about their proper operation.

[0004] One of these problems is the occurrence of dielectric breakdown due to electric field concentration at the trench opening when a voltage is applied to the gate electrode. To address this problem, there is a technology that alleviates electric field concentration by thickening the gate oxide film in the electric field concentration area, thereby increasing the breakdown voltage (see, for example, Patent Document 1). Furthermore, silicon carbide (SiC) semiconductor substrates, which have superior voltage resistance and heat resistance compared to silicon (Si) semiconductor substrates, are used in applications such as MOSFETs and insulated gate bipolar transistors (IGBTs).

[0005] In high-voltage MOSFETs using SiC substrates, the band gap of SiC is larger than that of Si, so the critical electric field (for example, 4 MV / cm or more and 7 MV / cm or less) is high and the off-state breakdown voltage is also high, so it is necessary to thicken the insulating film and improve the gate breakdown voltage. [Prior art documents] [Patent documents]

[0006] [Patent Document 1] Japanese Patent Application Laid-Open No. 2000-269499 Summary of the Invention [Problem to be solved by the invention]

[0007] The gate insulating film at the upper edge (corner part) of the trench of a P-channel power MOSFET using a silicon (Si) semiconductor substrate is thinner than the flat part or the trench sidewall. Furthermore, the shape of the upper edge (corner part) of the trench causes electric field concentration, which can lead to gate dielectric breakdown.

[0008] To address this issue, for example, in Patent Document 1, the oxide film in the trench is made thicker than in other areas such as the inside of the trench due to the effect of accelerated oxidation caused by silicon doped with a high concentration of arsenic, thereby mitigating the electric field concentration at the edge of the upper part of the trench.

[0009] However, even with the above structure, electric field concentration occurs at the trench opening when a voltage is applied to the gate electrode, which causes the gate oxide film to break down and reduces the breakdown voltage of the semiconductor device.

[0010] The technology disclosed in the present specification has been made in consideration of the problems described above, and is a technology for improving the breakdown voltage of a semiconductor device. [Means for solving the problem]

[0011] The semiconductor device according to the present disclosure comprises a semiconductor layer of a first conductivity type, a diffusion layer of a second conductivity type above the semiconductor layer, a source layer of the first conductivity type above the diffusion layer, and a trench formed from an upper surface of the source layer to reach into the semiconductor layer, and an acute-angled protrusion formed at the upper end of the trench that protrudes into the inside of the trench. [Effects of the Invention]

[0012] According to the present disclosure, by forming an acute-angled protrusion that protrudes inward at the opening at the top end of the trench, the gate insulating film formed in that location can be made thicker than in other locations, thereby alleviating electric field concentration in that location and improving the breakdown voltage of the semiconductor device.

[0013] Furthermore, objects, features, aspects, and advantages associated with the technology disclosed herein will become more apparent from the detailed description and accompanying drawings set forth below. [Brief explanation of the drawings]

[0014] [Figure 1] 1 is a plan view showing an example of the structure of a trench MOSFET using SiC, which is a semiconductor device according to a first embodiment. [Figure 2] 1 is a cross-sectional view showing an example of the structure of a semiconductor device according to a first embodiment. [Figure 3] 1 is a cross-sectional view showing an example of the structure of a semiconductor device according to a first embodiment. [Figure 4] 1 is a cross-sectional view showing an example of a method for manufacturing a semiconductor device according to a first embodiment. [Figure 5] 1 is a cross-sectional view showing an example of a method for manufacturing a semiconductor device according to a first embodiment. [Figure 6] 1 is a cross-sectional view showing an example of a method for manufacturing a semiconductor device according to a first embodiment. [Figure 7] 1 is a cross-sectional view showing an example of a method for manufacturing a semiconductor device according to a first embodiment. [Figure 8] 1 is a cross-sectional view showing an example of a method for manufacturing a semiconductor device according to a first embodiment. [Figure 9] 1 is a cross-sectional view showing an example of a method for manufacturing a semiconductor device according to a first embodiment. [Figure 10] 1 is a cross-sectional view showing an example of a method for manufacturing a semiconductor device according to a first embodiment. [Figure 11] 1 is a cross-sectional view showing an example of a method for manufacturing a semiconductor device according to a first embodiment. [Figure 12] 1 is a cross-sectional view showing an example of a method for manufacturing a semiconductor device according to a first embodiment. [Figure 13] 1 is a cross-sectional view showing an example of a method for manufacturing a semiconductor device according to a first embodiment. [Figure 14] 1 is a cross-sectional view showing an example of a method for manufacturing a semiconductor device according to a first embodiment. [Figure 15] 1 is a cross-sectional view showing an example of a method for manufacturing a semiconductor device according to a first embodiment. [Figure 16] 10A and 10B are cross-sectional views showing an example of a method for manufacturing a semiconductor device according to a second embodiment. [Figure 17] 10A and 10B are cross-sectional views showing an example of a method for manufacturing a semiconductor device according to a second embodiment. [Figure 18] 10A and 10B are cross-sectional views showing an example of a method for manufacturing a semiconductor device according to a third embodiment. [Figure 19] 10A and 10B are cross-sectional views showing an example of a method for manufacturing a semiconductor device according to a third embodiment. [Figure 20] FIG. 10 is a diagram schematically illustrating a configuration of a power conversion system to which a power conversion device according to a fourth embodiment is applied. DETAILED DESCRIPTION OF THE INVENTION

[0015] Hereinafter, embodiments will be described with reference to the accompanying drawings. In the following embodiments, detailed features are shown for the purpose of explaining the technology, but these are merely examples and are not necessarily essential features for enabling the embodiments to be implemented.

[0016] The drawings are schematic, and for the sake of convenience, components may be omitted or simplified as appropriate. The relative sizes and positions of components shown in different drawings are not necessarily accurately depicted and may be changed as appropriate. Hatching may also be used in drawings such as plan views that are not cross-sectional views to facilitate understanding of the embodiments.

[0017] In the following description, the same components are denoted by the same reference numerals, and their names and functions are also the same. Therefore, detailed descriptions of them may be omitted to avoid duplication.

[0018] Furthermore, in the description given in this specification, when a certain component is described as "comprising," "including," or "having," unless otherwise specified, this is not an exclusive expression that excludes the presence of other components.

[0019] Furthermore, although ordinal numbers such as "first" or "second" may be used in the descriptions in this specification, these terms are used for convenience to facilitate understanding of the contents of the embodiments, and the contents of the embodiments are not limited to the order that may result from these ordinal numbers.

[0020] Furthermore, in the description provided in this specification, terms that indicate specific positions or directions, such as "top," "bottom," "left," "right," "side," "bottom," "front," or "back," may be used, but these terms are used for convenience to facilitate understanding of the contents of the embodiments and have no relation to the positions or directions when the embodiments are actually implemented.

[0021] Furthermore, in the description of the present specification, when "the upper surface of ..." or "the lower surface of ..." is used, it is intended to include not only the upper surface or lower surface of the target component itself, but also a state in which another component is formed on the upper surface or lower surface of the target component. For example, when it is described as "B provided on the upper surface of A," it does not preclude another component "C" from being interposed between A and B.

[0022] Embodiment 1 A semiconductor device and a method for manufacturing the semiconductor device according to this embodiment will be described below.

[0023] 1 is a plan view showing an example of the structure of a trench MOSFET using SiC, which is a semiconductor device according to the present embodiment 1. Note that the material used in the semiconductor device is not limited to silicon carbide, and a wide band gap semiconductor material such as GaN may also be used.

[0024] Here, a wide bandgap semiconductor generally refers to a semiconductor with a forbidden band width of approximately 2 eV or more, and known examples include Group 3 nitrides such as gallium nitride (GaN), Group 2 oxides such as zinc oxide (ZnO), Group 2 chalcogenides such as zinc selenide (ZnSe), diamond, and silicon carbide.

[0025] In Fig. 1, the source region, gate electrode, and back gate region are shown. + The P-type diffusion layer 5, a trench 6 of several μm, a P-type side diffusion layer 8, and a source region (N + P formed in the diffusion layer 5) + A type diffusion layer 9, a gate insulating film 10, a gate electrode 11 formed in the trench 6, and a P + The NiSi 14 has a width wider than that of the N-type diffusion layer 9. The NiSi 14 is the source region. + 1, the P-type side diffusion layer 8 overlaps with a part of the N-type diffusion layer 5. + The mold is shown through the diffusion layer 5 .

[0026] 2 and 3 are cross-sectional views showing an example of the structure of the semiconductor device according to the first embodiment. Fig. 2 corresponds to the cross section AB in Fig. 1. Fig. 3 corresponds to the cross section CD in Fig. 1.

[0027] In the AB cross section, as shown in the example of FIG. 2, an N-type buffer layer 2 is formed on the upper surface of an N-type SiC substrate 1. Furthermore, an N-type SiC epitaxial layer 3 is epitaxially grown on the upper surface of the N-type buffer layer 2. Furthermore, a P-type diffusion layer 4 is formed on the upper layer of the N-type SiC epitaxial layer 3 by implanting P-type ion species (aluminum, boron). The P-type diffusion layer 4 is the back gate region of a trench MOSFET.

[0028] In addition, an N-type source region (source layer) is formed on the upper layer of the P-type diffusion layer 4. + A diffusion layer 5 of N type is formed. + A trench 6 is formed from the upper surface of the N-type diffusion layer 5 to reach the inside of the N-type SiC epitaxial layer 3. A gate insulating film 10 is formed on the bottom surface and sidewalls of the trench 6, and a gate electrode 11 is formed surrounded by the gate insulating film 10. At the upper end (opening) of the trench 6, a protrusion 50 having an acute angle protruding into the inside of the trench 6 is formed.

[0029] Further, below the trench 6, a P-type bottom diffusion layer 7 is formed by implanting P-type ion species (aluminum, boron) into the bottom surface of the trench 6.

[0030] 2, the width of the P-type bottom diffusion layer 7 in a plan view is the same as the width W1 of the bottom of the trench 6. The width of the P-type bottom diffusion layer 7 is narrower at its lower part. In other words, the width of the lower part of the P-type bottom diffusion layer 7 is narrower than the width W1 of the trench 6.

[0031] Also, N + The P-type diffusion layer 5 is formed on the upper surface thereof and reaches the P-type diffusion layer 4. + A diffusion layer 9 of N type is formed. + Part of the diffusion layer 5 of the mold and P + NiSi 14 is formed over the diffusion layer 9 of the mold.

[0032] An interlayer insulating film 12 is formed to cover the gate insulating film 10 and the gate electrode 11. Ti / TiN 15 and further wiring 16 are formed to cover the interlayer insulating film 12 and NiSi 14.

[0033] On the other hand, in the CD cross section, as shown in the example of Fig. 3, an N-type buffer layer 2 is formed on the upper surface of an N-type SiC substrate 1. Furthermore, an N-type SiC epitaxial layer 3 is formed on the upper surface of the N-type buffer layer 2. Furthermore, a P-type diffusion layer 4 is formed on the N-type SiC epitaxial layer 3.

[0034] In addition, N + A diffusion layer 5 of N type is formed. + A trench 6 is formed from the upper surface of the N-type diffusion layer 5 to reach the inside of the N-type SiC epitaxial layer 3. A gate insulating film 10 is formed on the bottom surface and sidewalls of the trench 6, and a gate electrode 11 is formed surrounded by the gate insulating film 10. At the upper end (opening) of the trench 6, a protrusion 50 having an acute angle protruding into the inside of the trench 6 is formed.

[0035] A P-type bottom diffusion layer 7 is formed below the trench 6. In Fig. 3, the width of the P-type bottom diffusion layer 7 in a plan view is the same as the width W1 of the bottom of the trench 6. The width of the P-type bottom diffusion layer 7 is narrowed at its bottom.

[0036] Also, N + The P-type diffusion layer 5 is formed on the upper surface thereof and reaches the P-type diffusion layer 4. + A diffusion layer 9 of N type is formed. + Part of the diffusion layer 5 of the mold and P + NiSi 14 is formed over the diffusion layer 9 of the mold.

[0037] An interlayer insulating film 12 is formed to cover the gate insulating film 10 and the gate electrode 11. Ti / TiN 15 and further wiring 16 are formed to cover the interlayer insulating film 12 and NiSi 14.

[0038] Furthermore, a P-type side diffusion layer 8 is formed on one side of the trench 6 and on the side of the P-type bottom diffusion layer 7. The P-type side diffusion layer 8 is N + It is formed below the diffusion layer 5 of the mold.

[0039] Next, a method for manufacturing the semiconductor device according to the first embodiment will be described with reference to FIGS.

[0040] It should be noted that, as long as a semiconductor device having the configuration shown in FIGS. 2 and 3 can be manufactured, the manufacturing process does not necessarily have to be the same as that described below.

[0041] 4 and 5 are cross-sectional views showing an example of a method for constructing a semiconductor device according to the first embodiment. The formation of an N-type diffusion layer in the source region is mainly shown in FIGS. 4 and 5. FIG. 4 corresponds to the AB cross section in FIG. 1. FIG. 5 corresponds to the CD cross section in FIG. 1.

[0042] As shown in the examples of FIGS. 4 and 5, an N-type buffer layer 2 is formed on the upper surface of an N-type SiC substrate 1, and an N-type SiC epitaxial layer 3 is epitaxially grown on the upper surface of the N-type buffer layer 2. Then, P-type ion species (aluminum, boron) are implanted into the upper layer of the N-type SiC epitaxial layer 3 to form a P-type diffusion layer 4. Next, photolithography is performed to implant N-type ion species (nitrogen, phosphorus) several times into the upper layer of the P-type diffusion layer 4, forming an N-type diffusion layer 4 that will become a source region. + A mold diffusion layer 5 is formed, and then the resist formed by photolithography is removed.

[0043] 6 and 7 are cross-sectional views showing an example of a method for manufacturing a semiconductor device according to the first embodiment. Fig. 6 corresponds to the cross section AB in Fig. 1. Fig. 7 corresponds to the cross section CD in Fig. 1.

[0044] As shown in Figs. 6 and 7, + A TEOS oxide film 17 is deposited on the upper surface of the mold diffusion layer 5 to a thickness of, for example, 2.0 μm or more and 3.0 μm or less. Then, photolithography is performed, and the TEOS oxide film 17 corresponding to the trench formation region is etched by dry etching, and N + The upper surface of the diffusion layer 5 of the mold is exposed, and the resist formed by photolithography is then removed.

[0045] Next, the N-type SiC epitaxial layer 3 is etched by several μm using the TEOS oxide film 17 as a mask to separate the P-type diffusion layer 4 and the N + A trench 6 is formed through the N-type diffusion layer 5 to reach the N-type SiC epitaxial layer 3 .

[0046] Since the TEOS oxide film 17 is used as a mask for etching, the N + The upper surface of the N-type diffusion layer 5 is etched in the trench 6. + The surface of the diffusion layer 5 may protrude beyond the side of the diffusion layer 5 (in other words, N + The portion of the mold diffusion layer 5 in contact with the TEOS oxide film 17 protrudes, and the upper end (opening) of the trench 6 may be narrower than the interior of the trench 6. By this process, an acute-angled protrusion 50 that protrudes into the inside of the trench 6 is formed at the upper end of the trench 6. The protrusion 50 is a portion that protrudes toward the inside of the trench 6, and its end is pointed (forms an acute corner).

[0047] The width of the opening of the formed trench 6 due to the protruding portion 50 is wider than the width (width X) of the opening of the masking TEOS oxide film 17. On the other hand, the width of the opening of the formed trench 6 due to the protruding portion 50 is narrower than the width of the trench 6 (width W1).

[0048] The depth direction (cross-sectional shape) of the formed trench 6 is + The angle may be perpendicular to the upper surface of the diffusion layer 5 of the mold, or may be at an obtuse angle of several degrees.

[0049] The inner end of the protrusion 50 at the upper end of the formed trench 6 has an acute angle (for example, 60° or more and less than 90°), and the pointed end protrudes into the trench 6. The inner end of the protrusion 50 is N + The diffusion layer 5 of the mold.

[0050] 8 and 9 are cross-sectional views showing an example of a method for constructing a semiconductor device according to the first embodiment. 8 and 9 mainly show the formation of a P-type bottom diffusion layer 7 at the bottom of trench 6. Fig. 8 corresponds to the AB cross section in Fig. 1. Fig. 9 corresponds to the CD cross section in Fig. 1.

[0051] 8 and 9, the TEOS oxide film 17 formed when the trench 6 was formed is used as a mask to implant P-type ion species (aluminum, boron) into the trench 6 several times. Then, a P-type bottom diffusion layer 7 is formed on the bottom surface of the trench 6.

[0052] Since the width (width X) of the opening of the TEOS oxide film 17 is narrower than the width W1 of the trench 6, the bottom width of the P-type bottom diffusion layer 7 formed on the bottom surface of the trench 6 is narrower than the width W1 of the bottom surface of the trench 6.

[0053] 10 and 11 are cross-sectional views showing an example of a method for constructing a semiconductor device according to the first embodiment. 10 and 11 mainly show the formation of a P-type side diffusion layer 8 on the side of trench 6. 10 corresponds to the AB cross section in FIG. 1. 11 corresponds to the CD cross section in FIG. 1.

[0054] 10, photolithography is performed to cover the TEOS oxide film 17 and the inside of the trench 6 (including the P-type bottom diffusion layer 7 on the bottom surface) in the AB cross section with a resist 18. Then, as shown in the example in FIG. 11, in the CD cross section, P-type ion species (aluminum, boron) are implanted several times at an implantation angle of, for example, 20° or more and 40° or less to form a P-type side diffusion layer 8 that connects the P-type diffusion layer 4 and the P-type bottom diffusion layer 7.

[0055] 12 and 13 are cross-sectional views showing an example of a method for constructing a semiconductor device according to the first embodiment. + 12 shows the formation of a mold diffusion layer 9. FIG. 12 corresponds to the cross section AB in FIG. 1. FIG. 13 corresponds to the cross section CD in FIG.

[0056] 12 and 13, the resist formed by photolithography is removed, and the TEOS oxide film 17 is removed by wet etching. + A TEOS oxide film 19 is deposited to a thickness of, for example, 1.0 μm or more and 2.0 μm or less so as to cover the upper surface of the mold diffusion layer 5. Then, photolithography is performed, and the TEOS oxide film 19 is etched by dry etching, and N + The upper surface of the diffusion layer 5 of the mold is partially exposed.

[0057] Then, the resist (TEOS oxide film 19) formed by photolithography is removed, and P-type ion species (aluminum, boron, BF2) are implanted once or multiple times to form P-type ion species for obtaining ohmic contact in the back gate region. + A mold diffusion layer 9 is formed.

[0058] 14 and 15 are cross-sectional views showing an example of a method for manufacturing a semiconductor device according to the first embodiment. Fig. 14 corresponds to the cross section AB in Fig. 1. Fig. 15 corresponds to the cross section CD in Fig. 1.

[0059] 14 and 15, the TEOS oxide film 19 is removed by wet etching, and then annealing is performed at 1700° C. or higher to activate the formed diffusion layers (N-type, P-type).

[0060] Since annealing is performed at 1700°C or higher, a carbon-based film (such as a graphite film) is deposited first to prevent the silicon from being digested. The carbon-based film (such as a graphite film) is removed after annealing (not shown here).

[0061] Next, N including the inside of trench 6 + The upper surface of the diffusion layer 5 of the mold, P + A TEOS oxide film is deposited to a thickness of, for example, 800 nm or more and 1500 nm or less so as to cover the upper surface of the N-type diffusion layer 9, the side surface of the P-type lateral diffusion layer 8, the side surface of the N-type SiC epitaxial layer 3, and the side surface of the P-type diffusion layer 4.

[0062] Next, photolithography is performed to etch the TEOS oxide film to form a field oxide film (not shown). Next, an oxide film having a thickness of, for example, 30 nm or more and 70 nm or less is deposited. At this time, the N + Since the mold diffusion layer 5 protrudes slightly inward and the inner end has an acute-angled shape (protrusion 50), the oxide film deposited can be made thicker only at the upper end of the trench 6 than in other parts of the trench 6 (the upper surface between the trenches 6 or the side surface of the trench 6). This reduces the electric field at the opening at the upper end of the trench 6, which is an electric field concentration part, and improves the breakdown voltage of the semiconductor device.

[0063] Embodiment 2 A semiconductor device and a method for manufacturing the semiconductor device according to the present embodiment will be described. In the following description, components similar to those described in the above embodiments will be denoted by the same reference numerals, and detailed descriptions thereof will be omitted as appropriate.

[0064] After depositing the oxide film in the first embodiment, nitridation is performed at 1100°C to form a gate oxide film (gate insulating film 10). During nitridation, more oxygen is supplied to the protruding portion 50 of the trench 6 than to the side or bottom surface of the trench 6, and therefore more reaction occurs there than at these locations. Therefore, the gate oxide film (gate insulating film 10) is formed thicker at the protruding portion 50 of the trench 6. This reduces the electric field at the opening at the top end of the trench 6, which is an electric field concentration portion, and improves the breakdown voltage of the semiconductor device.

[0065] 16 and 17 are cross-sectional views showing an example of a method for constructing a semiconductor device according to the second embodiment. Deposition of polysilicon that will become a gate electrode is mainly shown in FIGS. 16 and 17. FIG. 16 corresponds to the AB cross section in FIG. 1. FIG. 17 corresponds to the CD cross section in FIG. 1.

[0066] Polysilicon containing N-type impurities is deposited in trench 6, and photolithography is performed. Then, the polysilicon containing N-type impurities is etched by dry etching to form gate electrode 11 in trench 6. Then, the resist formed by photolithography is removed.

[0067] Embodiment 3 A semiconductor device and a method for manufacturing the semiconductor device according to the present embodiment 3 will be described. In the following description, components similar to those described in the above embodiments will be denoted by the same reference numerals, and detailed description thereof will be omitted as appropriate.

[0068] 18 and 19 are cross-sectional views showing an example of a method for forming a semiconductor device according to the third embodiment. The formation of a gate electrode is mainly shown in FIGS. 18 and 19. FIG. 18 corresponds to the AB cross section in FIG. 1. FIG. 19 corresponds to the CD cross section in FIG. 1.

[0069] In the second embodiment, the height of the upper surface of the gate electrode 11 is equal to the height of the protruding portion 50 of the trench 6 (in other words, N + The upper surface of the diffusion layer 5 of the mold is formed at the same height as the upper surface of the diffusion layer 5 of the mold.

[0070] On the other hand, in FIGS. 2 and 3, the height of the upper surface of the gate electrode 11 is the same as the height of the protruding portion 50 of the trench 6 (in other words, N + The height of the upper surface of the gate electrode 11 is lower than the height of the upper surface of the N-type diffusion layer 5. + The height is formed to be lower than the height of the upper surface of the diffusion layer 5 of the mold by, for example, 0.015 μm or more and 0.045 μm or less.

[0071] 2, the positions where the corners of the gate electrode 11 come into contact become slopes of the gate insulating film 10, and the corners of the gate insulating film 10 and the gate electrode 11 do not come into contact with each other. In other words, the distance between the corners of the gate insulating film 10 and the gate electrode 11 increases, and the electric field at the opening at the top end of the trench 6, which is an electric field concentration portion, can be alleviated, thereby improving the breakdown voltage of the semiconductor device.

[0072] After depositing the gate electrode 11, a TEOS oxide film is deposited on the top surface of the gate electrode 11, and then a boron phosphor silicate glass (BPSG) film is deposited to a thickness of, for example, 300 nm or more and 1000 nm or less. Then, a TEOS oxide film is deposited again to form the interlayer insulating film 12.

[0073] Next, photolithography is performed and dry etching is performed to form contacts. The etching of the TEOS oxide film, BPSG film, and TEOS oxide film during contact formation may be performed by wet etching only, or by dry etching followed by wet etching.

[0074] Next, to reduce the contact resistance on the top surface, the exposed top surface of the SiC (N + Diffusion layer 5 of the mold, P + Ni is sputtered onto the diffusion layer 9) of the mold, heat treatment is performed to remove the Ni, and then heat treatment is performed again to form NiSi 14.

[0075] Next, Ti / TiN 15 for wiring is sputtered, then aluminum or AlSi is sputtered, photolithography is performed, and dry etching is performed to form wiring 16. The etching of aluminum and AlSi may be wet etching.

[0076] Next, a SiN film or conductive nitride film is deposited on the top surface, and finally, polyimide is deposited.

[0077] Embodiment 4 A power conversion device according to the present embodiment 4 will be described. In the following description, components similar to those described in the above-described embodiments 1 to 3 will be denoted by the same reference numerals, and detailed description thereof will be omitted as appropriate.

[0078] 20 is a diagram schematically showing the configuration of a power conversion system to which a power conversion device 200 according to the fourth embodiment is applied. The power conversion system includes a power supply 100, the power conversion device 200, and a load 300.

[0079] Power supply 100 is a DC power supply and supplies DC power to power conversion device 200. Power supply 100 can be configured from a variety of elements, such as a DC system, a solar cell, or a storage battery, or it may be configured from a rectifier circuit or an AC / DC converter connected to an AC system. Power supply 100 may also be configured from a DC / DC converter that converts DC power output from a DC system into a predetermined power.

[0080] The power conversion device 200 is a three-phase inverter connected between the power source 100 and the load 300. The power conversion device 200 converts DC power supplied from the power source 100 into AC power and supplies it to the load 300. The power conversion device 200 has a main conversion circuit 201 and a control circuit 203. The main conversion circuit 201 converts input DC power into AC power and outputs the AC power. The control circuit 203 outputs a control signal to the main conversion circuit 201 to control the main conversion circuit 201.

[0081] The load 300 is a three-phase electric motor driven by AC power supplied from the power conversion device 200. The load 300 is not limited to a specific application, but is an electric motor mounted on various electric devices, and is used as an electric motor for, for example, a hybrid vehicle, an electric vehicle, a railroad car, an elevator, or an air conditioning device.

[0082] The power conversion device 200 will be described in detail below. The main conversion circuit 201 includes switching elements and freewheel diodes (not shown). By switching the switching elements, the main conversion circuit 201 converts DC power supplied from the power supply 100 into AC power and supplies it to the load 300. There are various specific circuit configurations for the main conversion circuit 201. However, the main conversion circuit 201 according to the fourth embodiment is a two-level, three-phase full-bridge circuit that can be configured with six switching elements and six freewheel diodes connected in anti-parallel to each switching element. At least one of the switching elements and freewheel diodes of the main conversion circuit 201 is configured using the semiconductor device 202 according to any of the first to third embodiments and their modifications. Two of the six switching elements are connected in series to form upper and lower arms, and each upper and lower arm forms a respective phase (U phase, V phase, W phase) of the full-bridge circuit. The output terminals of each upper and lower arm, in other words, the three output terminals of the main conversion circuit 201, are connected to the load 300.

[0083] The main conversion circuit 201 also includes a drive circuit (not shown) that drives each switching element. The drive circuit generates drive signals that drive the switching elements of the main conversion circuit 201 and supplies them to the control electrodes of the switching elements of the main conversion circuit 201. Specifically, in accordance with control signals from a control circuit 203 (described later), the drive circuit outputs to the control electrodes of each switching element a drive signal that turns the switching element on and a drive signal that turns the switching element off. When maintaining a switching element in the on state, the drive signal is a voltage signal (on signal) that is equal to or higher than the threshold voltage of the switching element, and when maintaining a switching element in the off state, the drive signal is a voltage signal (off signal) that is equal to or lower than the threshold voltage of the switching element.

[0084] The control circuit 203 controls the switching elements of the main conversion circuit 201 so that the desired power is supplied to the load 300. Specifically, the control circuit 203 calculates the time (on time) that each switching element of the main conversion circuit 201 should be in the on state, based on the power to be supplied to the load 300. For example, the main conversion circuit 201 can be controlled by pulse width modulation (PWM), which modulates the on time of the switching elements according to the voltage to be output. The control circuit 203 then outputs a control command (control signal) to a drive circuit included in the main conversion circuit 201 so that, at each point in time, an on signal is output to a switching element that should be in the on state, and an off signal is output to a switching element that should be in the off state. In accordance with this control signal, the drive circuit outputs an on signal or an off signal as a drive signal to the control electrode of each switching element.

[0085] In this example, the main conversion circuit 201 includes a semiconductor device 202 having the same configuration as in the first embodiment, and a mounting substrate 210. The mounting substrate 210 has a back electrode layer of the semiconductor device 202 bonded thereto.

[0086] The manufacturing method of the power conversion device 200 includes the following steps. A semiconductor device 202 is manufactured by the manufacturing method described in the first to third embodiments or their modifications. A main conversion circuit 201 having this semiconductor device 202 is formed. A control circuit 203 is also formed. This results in the power conversion device 200. When the main conversion circuit 201 is formed, a back electrode layer of the semiconductor device 202 is bonded onto a mounting substrate 210.

[0087] According to the fourth embodiment, the above-described semiconductor device 202 is used as at least one of the semiconductor devices constituting the main conversion circuit 201. This makes it possible to suppress unexpected adverse effects on the characteristics of the semiconductor device, while also suppressing the occurrence of poor insulation between the gate electrode and the source electrode caused by stress changes due to current flow in the semiconductor device. This improves the reliability of the main conversion circuit 201. This in turn improves the reliability of the power conversion device 200.

[0088] In the fourth embodiment, an example in which the present disclosure is applied to a two-level three-phase inverter has been described, but the present disclosure is not limited to this and can be applied to various power conversion devices. In the fourth embodiment, the power conversion device is a two-level power conversion device, but it may be a multi-level power conversion device such as a three-level power conversion device. Furthermore, when power is supplied to a single-phase load, the present disclosure may be applied to a single-phase inverter. Furthermore, when power is supplied to a DC load or the like, the present disclosure may also be applied to a DC / DC converter or an AC / DC converter.

[0089] Furthermore, the power conversion device to which the present disclosure is applied is not limited to cases where the above-mentioned load is an electric motor, but can also be used, for example, as a power supply device for an electric discharge machine, a laser processing machine, an induction heating cooker, or a non-contact power supply system, and can also be used as a power conditioner for a solar power generation system or a power storage system.

[0090] In the present disclosure, it is possible to freely combine the respective embodiments, and to appropriately modify or omit the respective embodiments within the scope of the technology. Although the present technology has been described in detail, the above description is merely an example in all aspects and does not limit the present technology. It is understood that countless variations not illustrated can be envisioned without departing from the scope of the present technology.

[0091] Next, examples of effects obtained by the above-described embodiments will be described. Note that in the following description, the effects will be described based on the specific configurations exemplified in the above-described embodiments, but these may be replaced with other specific configurations exemplified in the present specification as long as the same effects are obtained. In other words, for convenience, only one of the associated specific configurations may be described as a representative below, but the representatively described specific configuration may be replaced with another associated specific configuration.

[0092] Furthermore, the replacement may be made across multiple embodiments, i.e., configurations illustrated in different embodiments may be combined to produce the same effect.

[0093] According to the embodiment described above, the semiconductor device comprises a semiconductor layer of a first conductivity type, a diffusion layer of a second conductivity type above the semiconductor layer, a source layer of the first conductivity type above the diffusion layer, and a trench 6 formed from the upper surface of the source layer to reach the interior of the semiconductor layer. Here, the semiconductor layer corresponds to, for example, an N-type SiC epitaxial layer 3. The diffusion layer corresponds to, for example, a P-type diffusion layer 4. The source layer corresponds to, for example, an N-type SiC epitaxial layer 3. + This corresponds to the mold diffusion layer 5. At the upper end of the trench 6, a protrusion 50 is formed that protrudes into the inside of the trench 6 and has an acute angle.

[0094] According to this configuration, by forming an acute-angled protrusion 50 that protrudes inward at the opening at the upper end of the trench 6, the gate insulating film 10 formed at this location can be easily made thicker than other locations. Specifically, even without adjusting the amount of oxide film deposited to form a thick gate insulating film at the upper end of the trench 6, the oxide film at this location reacts with more oxygen during heat treatment than other locations, and therefore becomes thicker. This reduces electric field concentration at this location, thereby improving the breakdown voltage of the semiconductor device.

[0095] Furthermore, even if other configurations shown as examples in this specification are appropriately added to the above configuration, that is, even if other configurations in this specification that were not mentioned as the above configuration are appropriately added, the same effect can be achieved.

[0096] Furthermore, according to the embodiment described above, the semiconductor device includes the gate electrode 11 surrounded by the gate insulating film 10 in the trench 6. The thickness of the gate insulating film 10 covering the protrusion 50 is thicker than the thickness of the gate insulating film 10 not covering the protrusion 50. With this configuration, electric field concentration in the gate insulating film 10 covering the protrusion 50 can be alleviated, thereby improving the breakdown voltage of the semiconductor device.

[0097] Furthermore, according to the embodiment described above, the height of the upper surface of the gate electrode 11 is N + The height of the gate insulating film 10 is lower than the height of the upper surface of the mold diffusion layer 5. With this configuration, the distance between the corner of the gate insulating film 10 and the corner of the gate electrode 11 is increased, and the electric field at the opening at the upper end of the trench 6, where the electric field is concentrated, is alleviated, thereby improving the breakdown voltage of the semiconductor device.

[0098] Furthermore, according to the embodiment described above, the semiconductor device includes a P-type bottom diffusion layer 7 in contact with the bottom surface of the trench 6 within the N-type SiC epitaxial layer 3. The width of the lower part of the bottom diffusion layer 7 is narrower than the width of the trench 6. With this configuration, electric field concentration at the upper end of the trench 6 can be alleviated, thereby improving the breakdown voltage of the semiconductor device.

[0099] According to the embodiment described above, in the method for manufacturing a semiconductor device, a P-type diffusion layer 4 is formed on an N-type SiC epitaxial layer 3. Then, an N + Then, etching is performed with the upper surface of the source layer covered with a mask (TEOS oxide film 17) having an opening, thereby forming an N +A trench 6 is formed from the upper surface of the N-type diffusion layer 5 to reach the inside of the N-type SiC epitaxial layer 3. Here, the width X of the opening of the TEOS oxide film 17 is narrower than the width of the trench 6. When the trench 6 is formed, an acute-angled protrusion 50 that protrudes into the inside of the trench 6 is formed at the upper end of the trench 6.

[0100] According to this configuration, the acute-angled protrusion 50 that protrudes inward is formed at the opening at the upper end of the trench 6, which makes it easy to make the gate insulating film 10 formed at that location thicker than other locations. This reduces the electric field concentration at that location, thereby improving the breakdown voltage of the semiconductor device.

[0101] Unless otherwise specified, the order in which the processes are performed can be changed.

[0102] Furthermore, even if other configurations shown as examples in this specification are appropriately added to the above configuration, that is, even if other configurations in this specification that were not mentioned as the above configuration are appropriately added, the same effect can be achieved.

[0103] Furthermore, according to the embodiment described above, the TEOS oxide film 17 is removed to expose the inside of the trench 6 and the N + After forming the gate insulating film 10 that covers the mold diffusion layer 5, the gate insulating film 10 is heat-treated. Here, the thickness of the gate insulating film 10 in the portion that covers the protrusion 50 is thicker than the thickness of the gate insulating film 10 in the portion that does not cover the protrusion 50. With this configuration, the portion of the gate insulating film 10 that covers the protrusion 50 reacts with more oxygen than other portions during heat treatment, and therefore becomes thicker. Therefore, electric field concentration in this portion can be alleviated, and the breakdown voltage of the semiconductor device can be improved.

[0104] Furthermore, according to the embodiment described above, ions are implanted into trench 6 while it is covered with TEOS oxide film 17, thereby forming P-type bottom diffusion layer 7 in N-type SiC epitaxial layer 3, which is in contact with the bottom surface of trench 6. Here, the width of the lower part of bottom diffusion layer 7 is narrower than the width of trench 6. With this configuration, electric field concentration at the upper end of trench 6 can be alleviated, thereby improving the breakdown voltage of the semiconductor device.

[0105] In the above-described first to fourth embodiments, the material, composition, dimensions, shape, relative positional relationship, or implementation conditions of each component may also be described, but these are merely examples in all aspects and are not limiting.

[0106] Therefore, countless modifications and equivalents not shown as examples are contemplated within the scope of the technology disclosed in the present specification, including, for example, modifying, adding, or omitting at least one component, and further, extracting at least one component in at least one embodiment and combining it with a component in another embodiment.

[0107] Furthermore, in at least one of the embodiments described above, when a material name or the like is stated without being specifically specified, unless a contradiction arises, it is assumed that the material in question includes other additives, such as alloys.

[0108] Furthermore, unless a contradiction arises, when it is stated in the above-described embodiments that "one" component is provided, "one or more" of that component may also be provided.

[0109] Furthermore, each component in the embodiments described above is a conceptual unit, and the scope of the technology disclosed in this specification includes cases where one component is made up of multiple structures, cases where one component corresponds to part of a structure, and even cases where multiple components are provided in one structure.

[0110] Furthermore, each of the components in the embodiments described above includes structures having other structures or shapes as long as they perform the same function.

[0111] Furthermore, the descriptions in this specification are incorporated by reference for all purposes related to the present technology, and none of them are admitted to be prior art.

[0112] Furthermore, although the semiconductor substrate is of n-type in the above-described embodiments, it may be of p-type. That is, although a MOSFET is described as an example of a silicon carbide semiconductor device in the above-described embodiments, examples of the silicon carbide semiconductor device may also be other field effect transistors such as a junction field effect transistor (JFET) or a high electron mobility transistor (HEMT), or an IGBT.

[0113] In the case where the example of the silicon carbide semiconductor device is an IGBT, the source electrode corresponds to the emitter electrode, and the drain electrode corresponds to the collector electrode. In the case where the example of the silicon carbide semiconductor device is an IGBT, a layer of the opposite conductivity type to the N-type SiC epitaxial layer 3 is located below the N-type SiC epitaxial layer 3, but the layer located below the N-type SiC epitaxial layer 3 may be a layer newly formed below the N-type SiC epitaxial layer 3, or may be a semiconductor substrate on which the N-type SiC epitaxial layer 3 is formed, as in the above-described embodiments.

[0114] Various aspects of the present disclosure are summarized below as appendices.

[0115] (Appendix 1) a semiconductor layer of a first conductivity type; a second conductivity type diffusion layer above the semiconductor layer; a source layer of a first conductivity type above the diffusion layer; a trench formed from an upper surface of the source layer to reach the semiconductor layer; an acute-angled protrusion protruding into the trench is formed at an upper end of the trench; Semiconductor device.

[0116] (Appendix 2) 10. The semiconductor device according to claim 1, a gate electrode surrounded by a gate insulating film in the trench; a thickness of the gate insulating film in a portion covering the protrusion is greater than a thickness of the gate insulating film in a portion not covering the protrusion; Semiconductor device.

[0117] (Appendix 3) 1. The semiconductor device according to claim 2, the height of the upper surface of the gate electrode is lower than the height of the upper surface of the source layer; Semiconductor device.

[0118] (Appendix 4) The semiconductor device according to any one of Supplementary Notes 1 to 3, a bottom diffusion layer of a second conductivity type in contact with a bottom surface of the trench in the semiconductor layer; a width of a lower portion of the bottom diffusion layer is narrower than a width of the trench; Semiconductor device.

[0119] (Appendix 5) a main conversion circuit including the semiconductor device according to any one of Supplementary Notes 1 to 4, which converts input power and outputs the converted power; a control circuit that outputs a control signal for controlling the semiconductor device; Power conversion device.

[0120] (Appendix 6) forming a diffusion layer of a second conductivity type on the semiconductor layer of the first conductivity type; forming a source layer of a first conductivity type above the diffusion layer; etching the source layer while the source layer is covered with a mask having an opening, thereby forming a trench extending from the source layer to the semiconductor layer; the width of the opening in the mask is narrower than the width of the trench; When the trench is formed, an acute-angled protrusion protruding into the trench is formed at the upper end of the trench. A method for manufacturing a semiconductor device.

[0121] (Appendix 7) A method for manufacturing a semiconductor device according to Supplementary Note 6, removing the mask to form a gate insulating film covering the inside of the trench and the source layer, and then heat-treating the gate insulating film; a thickness of the gate insulating film in a portion covering the protrusion is greater than a thickness of the gate insulating film in a portion not covering the protrusion; A method for manufacturing a semiconductor device.

[0122] (Appendix 8) A method for manufacturing a semiconductor device according to claim 6 or 7, implanting ions into the trench while the trench is covered with the mask to form a bottom diffusion layer of a second conductivity type in the semiconductor layer in contact with a bottom surface of the trench; a width of a lower portion of the bottom diffusion layer is narrower than a width of the trench; A method for manufacturing a semiconductor device. [Explanation of symbols]

[0123] 1 SiC substrate, 2 buffer layer, 3 SiC epitaxial layer, 4 diffusion layer, 5 diffusion layer, 6 trench, 7 bottom diffusion layer, 8 side diffusion layer, 9 diffusion layer, 10 gate insulating film, 11 gate electrode, 12 interlayer insulating film, 16 wiring, 17 TEOS oxide film, 18 resist, 19 TEOS oxide film, 50 protrusion, 100 power supply, 200 power conversion device, 201 main conversion circuit, 202 silicon carbide semiconductor device, 203 control circuit, 210 mounting substrate, 300 load.

Claims

1. a semiconductor layer of a first conductivity type; a second conductivity type diffusion layer above the semiconductor layer; a source layer of a first conductivity type above the diffusion layer; a trench formed from an upper surface of the source layer to reach the semiconductor layer; an acute-angled protrusion protruding into the trench is formed at an upper end of the trench; Semiconductor device.

2. 2. The semiconductor device according to claim 1, a gate electrode surrounded by a gate insulating film in the trench; a thickness of the gate insulating film in a portion covering the protrusion is greater than a thickness of the gate insulating film in a portion not covering the protrusion; Semiconductor device.

3. 3. The semiconductor device according to claim 2, the height of the upper surface of the gate electrode is lower than the height of the upper surface of the source layer; Semiconductor device.

4. 4. The semiconductor device according to claim 1, a bottom diffusion layer of a second conductivity type in the semiconductor layer, the bottom diffusion layer being in contact with a bottom surface of the trench; a width of a lower portion of the bottom diffusion layer is narrower than a width of the trench; Semiconductor device.

5. a main conversion circuit including the semiconductor device according to any one of claims 1 to 3, which converts input power and outputs the converted power; a control circuit that outputs a control signal for controlling the semiconductor device; Power conversion device.

6. forming a diffusion layer of a second conductivity type on the semiconductor layer of the first conductivity type; forming a source layer of a first conductivity type above the diffusion layer; etching the source layer while the source layer is covered with a mask having an opening, thereby forming a trench extending from the source layer to the semiconductor layer; the width of the opening in the mask is narrower than the width of the trench; When the trench is formed, an acute-angled protrusion protruding into the trench is formed at the upper end of the trench. A method for manufacturing a semiconductor device.

7. 7. A method for manufacturing a semiconductor device according to claim 6, removing the mask to form a gate insulating film covering the inside of the trench and the source layer, and then heat-treating the gate insulating film; a thickness of the gate insulating film in a portion covering the protrusion is greater than a thickness of the gate insulating film in a portion not covering the protrusion; A method for manufacturing a semiconductor device.

8. 8. The method for manufacturing a semiconductor device according to claim 6 or 7, implanting ions into the trench while the trench is covered with the mask to form a bottom diffusion layer of a second conductivity type in the semiconductor layer in contact with a bottom surface of the trench; a width of a lower portion of the bottom diffusion layer is narrower than a width of the trench; A method for manufacturing a semiconductor device.

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